JP2005078716A - Signal transmission circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal transmission circuit stably operated even in the case of the low voltage of a circuit power source and the high speed of circuit driving. <P>SOLUTION: This signal transmission circuit is constituted of plural stages of circuits, and pulse voltages are sequentially output from the circuits in accordance with driving pulses. Each of the plural stages of circuits is provided with an output transistor T12 for outputting a driving pulse as a pulse voltage, a capacity C1 connected between the gate and the source of the output transistor, a drain being connected to a power source or a ground line and a source being connected to the gate of the output transistor to charge the capacity in which a start pulse is supplied to the gate in the case of the first stage, and a logical circuit configured to output the voltage signal of an H level when the source voltage of the output transistor is at an H level, and the voltage signal of an L level in accordance with the gate voltage of the output transistor when the source voltage of the output transistor is an L level. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal transmission circuit, a so-called shift register, and more particularly to a shift register for driving a liquid crystal display, a MOS type imaging device, and the like.

FIG. 7 is a circuit diagram showing a configuration example of a conventional signal transmission circuit, and shows a four-stage portion of a multi-stage circuit. This signal transmission circuit includes output transistors T12, T22, T32, T42 to the next stage, bootstrap capacitors C1, C2, C3, C4, bootstrap capacitor charging transistors T11, T21, T31, T41, 1 discharge transistors T13, T23, T33, T43 and second discharge transistors T14, T24, T34, T44.
A power supply voltage VDD, drive pulses V1 and V2, and a start pulse VST are supplied to each element of the signal transmission circuit.

  Next, the operation of the conventional signal transmission circuit configured as described above will be described. When the start pulse VST becomes a logic “High” level, the bootstrap capacitive charging transistor T11 in the first stage is turned on. For this reason, the bootstrap capacitor C1 is charged to (power supply voltage VDD−threshold voltage Vt1 of the transistor T11).

  When the charging voltage of the bootstrap capacitor C1 exceeds the threshold voltage of the output transistor T12, the first-stage output transistor T12 is turned on. After that, when the drive pulse V1 having the logic “High” level is input to the drain of the output transistor T12, the voltage of the drive pulse V1 and the potential difference between both ends of the bootstrap capacitor C1 are added to the gate of the output transistor T12. Applied. When the gate potential (node N11) of the output transistor T12 rises higher than the potential of the drive pulse V1, the drive pulse V1 is output from the node N12 as the output pulse OUT1 and used.

  At the same time, the voltage of the node N12 is applied to the gate of the bootstrap capacitive charging transistor T21 in the second stage, so that the transistor T21 is turned on, and the bootstrap capacitor C2 is equal to the threshold voltage Vt2 of the transistor T21. It is charged to the power supply voltage VDD without a drop.

  When the charging voltage of the bootstrap capacitor C2 exceeds the threshold voltage of the output transistor T22, the second-stage output transistor T22 is turned on. Thereafter, when a drive pulse V2 having a logic “High” level is input to the drain of the output transistor T22, the potential of the drive pulse V2 and the potential difference between both ends of the bootstrap capacitor C2 are added to the gate of the output transistor T22. Will be applied. When the gate voltage (node N21) of the output transistor T22 rises above the potential of the drive pulse V2, the drive pulse V2 is output from the node N22 as the output pulse OUT2 and used.

At the same time, the voltage of the node N22 is applied to the gate of the bootstrap capacitive charging transistor T31 at the third stage, so that the transistor T31 is turned on, and the bootstrap capacitor C3 has the threshold voltage Vt3 of the transistor T31. It is charged to the power supply voltage VDD without a drop.
When the charging voltage of the bootstrap capacitor C3 exceeds the threshold voltage of the output transistor T32, the third-stage output transistor T32 is turned on.

  By repeating such an operation, the signal transmission circuit further outputs the output pulses OUT3 and OUT4 sequentially.

  FIG. 8 is a circuit diagram showing a configuration example of a conventional signal transmission circuit diagram with malfunction prevention. In the signal transmission circuit with malfunction prevention, in the conventional signal transmission circuit shown in FIG. 7, the charging voltage that can be applied only to the gate of the bootstrap capacitive charging transistor is lower than the power supply voltage VDD. This is an improved signal transmission circuit that can be applied. This malfunction-preventing signal transmission circuit prevents the voltages at the nodes N11, N21, N31, and N41 from gradually dropping and preventing an output pulse from being output several stages earlier.

  The signal transmission circuit with malfunction prevention shown in FIG. 8 differs from the signal transmission circuit shown in FIG. 7 in that first malfunction prevention transistors T35 and T45 are further provided in the third and fourth stage circuits, respectively. The transistor T35 has a gate connected to the source (node N12) of the output transistor T12, a drain connected to the source (node N31) of the bootstrap capacitive charging transistor T31, and a source grounded. The transistor T45 has a gate connected to the source (node N22) of the output transistor T22, a drain connected to the source (node N41) of the bootstrap capacitive charging transistor T41, and a source grounded.

  7 is different from the signal transmission circuit shown in FIG. 7 in that the gate of the second discharge transistor at each stage is connected to the source of the output transistor at the next stage. For example, the gate of the first-stage second discharge transistor T14 is connected to the source of the second-stage output transistor T22.

Next, the operation of this signal transmission circuit with malfunction prevention circuit will be described.
FIG. 9 is a timing chart showing pulse voltages at various parts in a conventional signal transmission circuit using only NMOS. This circuit is a 3V system circuit, and shows the case where the voltage amplitudes of the drive pulses V1 and V2 and the power supply voltage VDD are 3V.

  However, the voltage amplitude of the start pulse VST is 5V. Here, only the voltage amplitude of the start pulse VST is set to 5 V because the high voltage from the previous stage cannot be supplied only in the case of the first stage bootstrap capacitive charging transistor T11 to which the start pulse VST is input. Therefore, only the start pulse VST is driven by the transistor T11 at 5V, which is higher than 3V which is the voltage amplitude of the drive pulses V1 and V2, thereby preventing a voltage drop due to the transistor T11 and the bootstrap capacitor C1 being the power supply voltage VDD. This is to allow charging to 3V.

  In FIG. 9, when the start pulse VST rises to 5 V at time T0, the bootstrap capacitor charging transistor T11 in the first stage is turned on, and the bootstrap capacitor C1 is charged toward the power supply voltage VDD. Here, even when the bootstrap capacitive charging transistor T11 is an enhancement type NMOS, the voltage VN11 of the node N11 to which the gate of the output transistor T12 is connected is not affected by the threshold voltage Vt1 of the transistor T11. The output transistor T12 is turned on.

  Next, when a 3V drive pulse V1 is input to the drain of the output transistor T12 at time T1, the voltage 3V of the drive pulse V1 and both ends of the bootstrap capacitor C1 are applied to the gate (node N11) of the output transistor T12. The voltage HB1 added with the potential difference (3V−Vt1) is applied, and a pulse with the amplitude H1 is output from the node N12.

  At the same time, the voltage HB1 of the node N11 is applied to the gate of the second-stage bootstrap capacitor charging transistor T21, the transistor T21 is turned on, and the bootstrap capacitor C2 drops by the threshold voltage of the transistor T21. The battery is charged to the power supply voltage VDD. When the charging voltage (node N21) of the bootstrap capacitor C2 exceeds the threshold voltage of the output transistor T22, the second-stage output transistor T22 is turned on.

  At the same time, the voltage at the node N21 is also applied to the gate of the third-stage bootstrap capacitive charging transistor T31. Therefore, the transistor T31 is turned on, and the bootstrap capacitor C3 is charged to a voltage (3V−Vt3) that is lower by the threshold voltage Vt3 of the transistor T31. In this state, when the drive pulse V1 is 3V that is the logic “High” level, when the drive pulse V1 is output to the first-stage output node N12, the drive pulse V1 is also equal to or less than the drive pulse V1 at the third-stage output node N32. An amplitude pulse is output. Therefore, a malfunction occurs between the positive terminal side of the bootstrap capacitor C3 and the ground potential so that the positive terminal side of the bootstrap capacitor C3 is brought closer to the ground potential side and the third-stage output transistor T32 is turned off. A prevention transistor T35 is connected. That is, the drain of the malfunction preventing transistor T35 is connected to the plus side of the bootstrap capacitor C3, the source is connected to the ground potential, and the gate is connected to the first-stage output node N12. Further, when the drive pulse V1 is output to the first-stage output node N12, the malfunction prevention transistor T35 is turned on, the node N31 is brought closer to the ground potential side, and the drive pulse V1 is output to the third-stage output node N32. I am trying not to.

Similarly, the drain and source of the malfunction prevention transistor T45 are connected between the positive terminal side of the bootstrap capacitor C4 at the rear stage and the ground potential, respectively, and the output node N22 of the previous stage is connected to the gate. By doing so, malfunctions are prevented throughout the entire stage.
Japanese Examined Patent Publication No. 3-75960 (Fig. 3)

  However, in the process of low-voltage driving and high-speed operation of the circuit, it is necessary to set the threshold voltage of the output transistor such as the output transistor T32 low. For this reason, in the malfunction prevention method in which only the positive terminal side of the bootstrap capacitor C3 or the like is brought close to the ground potential side, the output transistor such as the output transistor T32 is turned on, and the node N32 or a subsequent stage corresponding to this node is turned on. At all nodes, voltages having amplitudes equal to or lower than the drive pulse voltages V1 and V2 are output. For this reason, a pulse output is generated other than the predetermined pulse output position, and the signal transmission circuit does not operate normally. For example, paying attention to time T1, the first malfunction prevention transistor T35 has an ON resistance, so that the potential of the node N31 is not completely zero and the output transistor T32 is turned on.

In the future of low voltage drive and high speed operation of circuits in the future, this malfunction appears remarkably.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a signal transmission circuit capable of stable operation even when the voltage of the circuit power supply is reduced and the circuit drive speed is increased. It is.

  In order to achieve the above object, a signal transmission circuit according to the present invention is a signal transmission circuit configured by a plurality of stage circuits, in which a pulse voltage according to a driving pulse is sequentially output from each stage circuit, The circuit outputs an output transistor that outputs the drive pulse as the pulse voltage to a source, a bootstrap capacitor connected between a gate and a source of the output transistor, and a capacitor for charging the bootstrap capacitor. The drain is connected to the power supply or ground line, the source is connected to the gate of the output transistor, the start pulse is supplied to the gate in the first stage, and the gate is connected to the gate of the output transistor in the second stage and later. A charge transistor and a drain connected to one end of the bootstrap capacitor, and an output transistor of the next stage is connected to the gate. A first discharge transistor to which a pulse voltage supplied from the source of the transistor is applied, a drain connected to the other end of the bootstrap capacitor, and a pulse voltage supplied from the source of the next output transistor to the gate The logic circuit outputs a high level voltage signal when the source voltage of the output transistor is at a high level, and the logic circuit outputs a source signal of the output transistor. When the voltage is low, a low level voltage signal is output according to the gate voltage of the output transistor.

  Since the logic circuit is configured as described above, pulses are output to the OUT terminal as usual only in the circuit of the stage that generates the original pulse output, and pulse output due to a malfunction, for example, in other stages of the circuit Even if the error occurs, it will be cut off by the switch circuit before it is output to the OUT terminal. Therefore, when viewed from the OUT terminal of the signal transmission circuit, the pulse will normally scan, and the peripheral circuit will Does not adversely affect. That is, it is possible to provide a signal transmission circuit that can output a normal pulse to the external OUT terminal even if a malfunction occurs inside the signal transmission circuit.

  According to the present invention, the pulse voltage is output only from the circuit of the desired stage, and is not output from the circuits of the other stages. For this reason, the signal transmission circuit can be stably operated even when the voltage of the power source is lowered or the circuit drive speed is increased. In particular, it can be expected to be mounted on a MOS type solid-state imaging device or a liquid crystal display device, and the present invention is extremely useful.

(First embodiment)
FIG. 1 is a schematic diagram of a signal transmission circuit according to the first embodiment of the present invention.
The signal transmission circuit according to the present embodiment is a signal transmission circuit that includes a plurality of stage circuits and sequentially outputs a pulse voltage according to a drive pulse from each stage circuit. Here, the case of five stages is shown.

This signal transmission circuit is different from the conventional signal transmission circuit shown in FIG. 8 in that a logic circuit is newly provided in each stage circuit.
The logic circuit outputs a high-level voltage signal when the source voltage of the output transistor T12 (T22 to T52) is high level, and outputs when the source voltage of the output transistor T12 (T22 to T52) is low level. A low-level voltage signal is output in accordance with the gate voltage of the transistor T12 (T22 to T52).

  According to this configuration, only the circuit of the stage that generates the original pulse output outputs a pulse to the OUT terminal as usual, and the other stages of the circuit are output even if a pulse output due to a malfunction occurs. Since the signal is interrupted by the switch circuit before being output to the terminal, the pulse is normally scanned from the OUT terminal of the signal transmission circuit, and the peripheral circuit is not adversely affected. That is, it is possible to provide a signal transmission circuit that can output a normal pulse to the external OUT terminal even if a malfunction occurs inside the signal transmission circuit.

(Second Embodiment)
FIG. 2 is a configuration example of a signal transmission circuit according to the second embodiment of the present invention. This signal transmission circuit is a signal transmission circuit according to the first embodiment in which a logic circuit portion is a specific circuit. The logic circuit includes a first transistor T101 (T201 to T501) having a drain connected to a power source and a gate connected to the source of the output transistor T12 (T22 to T52) of each stage circuit, and the output transistor T12 (T22 to T52). An inverter circuit that receives a gate as an input; a second transistor T102 (T202 to T502) having a gate connected to the output of the inverter circuit; a drain as a source of the output transistor of each stage circuit; and a gate as the second transistor The source of the transistor T102 (T202 to T502), the third transistor T103 (T203 to T503) having the source connected to the ground line, the gate to the gate of the output transistor T12 (T22 to T52) of each stage circuit, and the drain to Third transistor T103 (T203 to T503) And the fourth transistor T104 (T204 to T504) connected to the gate of the first transistor T101, the source of the first transistor T101 (T201 to T501) and the drain of the second transistor T102 (T202 to T502) are connected. Has been.

  The detailed operation will be described with reference to FIG. FIG. 3 is a timing chart showing pulse voltages at various parts in the signal transmission circuit according to the second embodiment. This circuit is a 3V system circuit, and shows the case where the voltage amplitudes of the drive pulses V1 and V2 and the power supply voltage VDD are 3V. However, the voltage amplitude of the start pulse VST is 5V. Here, only the voltage amplitude of the start pulse VST is set to 5 V. Only in the case of the first stage bootstrap capacitive charging transistor T11 to which the start pulse VST is input, a high voltage from the previous stage cannot be supplied, so only the start pulse VST is driven. By driving the transistor T11 with 5V higher than 3V which is the voltage amplitude of the pulses V1 and V2, the voltage drop due to the transistor T11 is prevented and the bootstrap capacitor C1 can be charged to 3V which is the power supply voltage VDD. is there.

  In FIG. 3, when the start pulse VST rises to 5 V at time T0, the first bootstrap capacitor charging transistor T11 is turned on, and the bootstrap capacitor C1 is charged toward the power supply voltage VDD. Here, even when the bootstrap capacitive charging transistor T11 is an enhancement type NMOS, the voltage VN11 of the node N11 to which the gate of the output transistor T12 is connected is not affected by the threshold voltage Vt1 of the transistor T11. The output transistor T12 is turned on.

  Next, at time T1, when a 3V drive pulse V1 is input to the drain of the output transistor T12, the voltage difference between the voltage 3V of the drive pulse V1 and both ends of the bootstrap capacitor C1 is applied to the gate (node N11) of the output transistor T12. The high voltage HB1 added with 3V is applied, and the driving pulse V1 having an amplitude of 3V is reliably output as the output pulse OUT1 from the node N12. At the same time, the voltage HB1 of the node N11 is applied to the gate of the second-stage bootstrap capacitor charging transistor T21, the transistor T21 is turned on, and the bootstrap capacitor C2 drops by the threshold voltage of the transistor T21. When the charging voltage (node N21) of the bootstrap capacitor C2 exceeds the threshold voltage of the output transistor T22, the second-stage output transistor T22 is turned on. At the same time, the voltage at the node N21 is also applied to the gate of the bootstrap capacitor charging transistor T31 at the third stage, so that the transistor T31 is turned on, and the threshold voltage Vt3 of the transistor T31 is applied to the bootstrap capacitor C3. The battery is charged to a voltage (3V-Vt3) that is lower by the amount. In this state, when the drive pulse V1 is 3V that is the logic “High” level, when the drive pulse V1 is output to the first-stage output node N12, the drive pulse V1 is also equal to or less than the drive pulse V1 at the third-stage output node N32. An amplitude pulse is output. Even in this case, in the present embodiment, only the driving pulse V1 of the output node N12 at the first stage is output to the OUT1 terminal, and a pulse having an amplitude equal to or smaller than the driving pulse V1 generated at the output node N32 of the third stage is generated at the OUT3 terminal. I won't let you.

  That is, in order to output the potential of the first-stage node N12 to the OUT1 terminal as it is, at the time T1, the first-stage third transistor T103 is turned off, and the third-stage and subsequent third transistors T303, T403, etc. are turned on. .

  That is, the operation of each node of the first-stage circuit is that the gate voltage (node N11) of the output transistor T11 is at “High” level, the voltage is applied to the gate of the fourth transistor T104, and its inverted voltage “Low”. Since the level is applied to the gate of the second transistor T102, the gate of the third transistor T103 is at the “Low” level, and the source voltage (node N12) of the output transistor T11 outputs the drive pulse V1 to the OUT1 terminal. be able to.

  On the other hand, in the operation of each node of the circuit in the third stage, the gate voltage (node N31) of the output transistor T31 is at the “Low” level, the voltage is applied to the gate of the fourth transistor T304, and the inverted voltage thereof. Since the “High” level is applied to the gate of the second transistor T302, the gate of the third transistor T303 outputs a pulse that is equal to or less than the amplitude of the drive pulse V1 to the source voltage (node N32) of the output transistor. When the first transistor T301 is turned ON, it becomes “High” level, and the OUT3 terminal is set to the ground level even when a pulse having an amplitude equal to or smaller than the amplitude of the drive pulse V1 is output to the source voltage (node N32) of the output transistor. Therefore, only a desired pulse output can be output to the OUT terminal. Note that the input logic level of the inverter circuit that generates the inverted voltage of the gate of the output transistor of each stage circuit can contribute to stable operation, particularly by setting the input “High” level to a high voltage. Further, the threshold voltage of the first transistor of each stage circuit can be set low to contribute to stable operation.

(Third embodiment)
FIG. 4 is a configuration example of a signal transmission circuit according to the third embodiment of the present invention.
The signal transmission circuit according to this embodiment specifically shows the inverter circuit of the signal transmission circuit according to the second embodiment shown in FIG.

  The inverter circuit includes a fifth transistor T105 (T205 to T505) whose gate and drain are connected to a power supply, and a sixth transistor whose drain is connected to the power supply and whose gate is connected to the source of the fifth transistor T105 (T205 to T505). T106 (T206 to T506), a second bootstrap capacitor C100 (C200 to C500) having both ends of the gate and source of the sixth transistor T106 (T206 to T506), and a drain serving as the fifth transistor T105 (T205) To T505) and the seventh transistor T107 (T207 to T507) having the gate connected to the gate of the output transistor T12 (T22 to T52) of each stage circuit, and the sixth transistor T106 (T206). ~ T506) source and seventh run Drain and a node of the static T107 (T207~T507) is connected to the gate of the second transistor T102 (T202~T502).

  That is, an inverter circuit is used in which the inverted voltage of the gate of the output transistor T12 (T22 to T52) of each stage circuit is composed only of NMOS. In this circuit, in particular, by setting the threshold voltage of the seventh transistor T107 (T207 to T507) high, it is possible to contribute to more stable operation.

  Note that the threshold voltage of the seventh transistor T107 (T207 to T507) in each stage circuit is preferably equal to or higher than the threshold voltage of the first transistor T101 (T201 to T501).

  Further, the channel length of the seventh transistor T107 (T207 to T507) of each stage circuit is shorter than the channel length of the first transistor T101 (T201 to T501), and the first transistor T101 (T201 to T501) is turned on. It is desirable that the resistance be lower than that of the seventh transistor T107 (T207 to T507).

  Note that the power supply connected to the drain of the first transistor T101 (T201 to T501), the drain and gate of the fifth transistor T105 (T205 to T505), and the drain of the sixth transistor T106 (T206 to T506) of each stage circuit. May be commonly connected to all signal transmission circuits.

  Further, as shown in FIG. 7, nodes connected to the sources of the first transistors T101 (T201 to T501) and the drains of the second transistors T102 (T202 to T502) of each stage circuit are included in all signal transmission circuits. It may be connected in common.

  In the first, second, and third embodiments, the source of each of the discharge transistor and the malfunction prevention transistor is set to the ground potential (0 V), but the first malfunction prevention transistor is used for each source voltage. The same effect can be obtained even when a voltage lower than the threshold voltage of the output transistor is supplied to the source of the first discharge transistor.

  The signal transmission circuit as described above can be used as a shift register of a solid-state imaging device or a liquid crystal display device. FIG. 6 is a diagram showing an example of such a solid-state imaging device.

  The solid-state imaging device includes a lens 102 that collects light, a pixel group 108 that accumulates the collected light, vertical shift registers 106 and 110 for accessing the pixel group 108 for each row, and a pixel group 108. A noise removing unit 114 for removing a noise component of the read pixel value, a horizontal shift register 116 for accessing the pixel value for each column and outputting the pixel value for each pixel, and the read pixel An amplifier 118 that amplifies the value, an A / D conversion unit 120 that performs A / D conversion on the read pixel value, and a timing generator 112 that generates a timing for reading the pixel value from each pixel. Yes.

  By using the signal transmission circuit according to the present embodiment for such a solid-state imaging device, it is possible to accurately read out pixel values. The signal transmission circuit can also be applied to a liquid crystal display device or the like.

  The signal transmission circuit according to the present invention can be applied to a MOS type solid-state imaging device, a liquid crystal display device, and the like that require low power consumption and high-speed processing.

1 is a circuit diagram of a signal transmission circuit with a malfunction prevention circuit according to a first embodiment of the present invention. It is a circuit diagram of a signal transmission circuit with a malfunction prevention circuit according to a second embodiment of the present invention. It is an operation | movement timing diagram which concerns on the 2nd Embodiment of this invention. It is a circuit diagram of the signal transmission circuit with a malfunction prevention circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram of a signal transmission circuit with a malfunction prevention circuit according to another embodiment of the present invention. 1 is a block diagram of a solid-state imaging device using a signal transmission circuit with a malfunction prevention circuit according to an embodiment of the present invention. It is a circuit diagram of the conventional signal transmission circuit with a malfunction prevention circuit. It is a circuit diagram of a conventional signal transmission circuit with a malfunction prevention circuit. It is an operation | movement timing diagram of the conventional signal transmission circuit with a malfunction prevention circuit.

Explanation of symbols

C1, C2, C3, C4, C5, C100, C200, C300, C400, C500 Bootstrap capacitance OUT1, OUT2, OUT3, OUT4, OUT5 Output pulse (scanning pulse)
T11, T21, T31, T41, T51 Bootstrap capacitive charging transistor (charging transistor)
T12, T22, T32, T42, T52 Output transistor T13, T23, T33, T43, T53 First discharge transistor T14, T24, T34, T44, T54 Brother 2 discharge transistor T35, T45, T55 First prevention of malfunction Transistors T101, T201, T301, T401, T501 First transistors T102, T202, T302, T402, T502 Second transistors T103, T203, T303, T403, T503 Third transistors T104, T204, T304, T404, T504 Fourth transistor T105, T205, T305, T405, T505 Fifth transistor T106, T206, T306, T406, T506 Sixth transistor T107, T207, T307, 407, T507 seventh transistor Vt1, Vt2, Vt3, Vt4, Vt5 threshold voltage of the bootstrap capacitor charging transistor V1, V2 drive pulse VDD supply voltage VST start pulse

Claims (12)

A signal transmission circuit composed of a multi-stage circuit, in which a pulse voltage according to a drive pulse is sequentially output from each stage circuit,
Each stage circuit is
An output transistor for outputting the drive pulse as the pulse voltage to a source;
A bootstrap capacitor connected between the gate and source of the output transistor;
In order to charge the bootstrap capacitor, the drain is connected to the power supply or the ground line, the source is connected to the gate of the output transistor, the start pulse is supplied to the gate in the first stage, and the second and subsequent stages Is a charging transistor whose gate is connected to the gate of the output transistor in the previous stage, and
A first discharge transistor having a drain connected to one end of the bootstrap capacitor and a gate to which a pulse voltage supplied from the source of the next-stage output transistor is applied;
A second discharge transistor having a drain connected to the other end of the bootstrap capacitor and a gate to which a pulse voltage supplied from the source of the next-stage output transistor is applied;
Logic circuit,
The logic circuit outputs a high level voltage signal when the source voltage of the output transistor is high level, and when the source voltage of the output transistor is low level, the logic circuit is low level according to the gate voltage of the output transistor. A signal transmission circuit configured to output a voltage signal. The logic circuit is:
A first transistor having a drain connected to a power source and a gate connected to a source of the output transistor of each stage circuit;
An inverting circuit receiving the gate of the output transistor as an input;
A second transistor having a gate connected to the output of the inverting circuit;
A third transistor having a drain connected to a source of the output transistor of each stage circuit, a gate connected to a source of the second transistor, and a source connected to a ground line;
A fourth transistor having a gate connected to the gate of the output transistor of each stage circuit and a drain connected to the gate of the third transistor;
The signal transmission circuit according to claim 1, wherein a source of the first transistor and a drain of the second transistor are connected. The inverting circuit is
A fifth transistor having a gate and drain connected to a power source;
A sixth transistor having a drain connected to a power source and a gate connected to the source of the fifth transistor;
A second bootstrap capacitor having both ends of the gate and source of the sixth transistor;
A seventh transistor having a drain connected to the source of the fifth transistor and a gate connected to the gate of the output transistor of each stage circuit;
The signal transmission circuit according to claim 2, wherein a node that is a source of the sixth transistor and a drain of the seventh transistor is connected to a gate of the second transistor. The signal transmission circuit according to claim 3, wherein a threshold voltage of the seventh transistor is equal to or higher than a threshold voltage of the first transistor. 5. The channel length of the seventh transistor is shorter than the channel length of the first transistor, and the resistance when the first transistor is conductive is lower than that of the seventh transistor. The signal transmission circuit described. 4. The power source connected to the drain of the first transistor, the drain and gate of the fifth transistor, and the drain of the sixth transistor is commonly connected to all signal transmission circuits. 6. The signal transmission circuit according to any one of 5 above. 8. The node connected to the source of the first transistor and the drain of the second transistor is commonly connected to all signal transmission circuits. 8. Signal transmission circuit. 4. The signal transmission circuit according to claim 1, wherein all of the transistors are NMOS transistors, and a ground potential is supplied to sources of the first to third discharge transistors. 5. . 4. The signal transmission circuit according to claim 1, wherein all of the transistors are NMOS transistors, and a ground potential is supplied to a source of the first malfunction prevention transistor. 5. . The transistors are all NMOS transistors, and a voltage lower than a threshold voltage of the output transistor is supplied to the sources of the first malfunction prevention transistor and the first discharge transistor. Item 4. The signal transmission circuit according to any one of Items 1 to 3. A solid-state imaging device equipped with the signal transmission circuit according to claim 1. The liquid crystal display device carrying the signal transmission circuit of any one of Claims 1-10.

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