JP2005072574A - Circuit board - Google Patents

Circuit board Download PDF

Info

Publication number
JP2005072574A
JP2005072574A JP2004229893A JP2004229893A JP2005072574A JP 2005072574 A JP2005072574 A JP 2005072574A JP 2004229893 A JP2004229893 A JP 2004229893A JP 2004229893 A JP2004229893 A JP 2004229893A JP 2005072574 A JP2005072574 A JP 2005072574A
Authority
JP
Japan
Prior art keywords
substrate
circuit board
ceramic substrate
alumina
board according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004229893A
Other languages
Japanese (ja)
Inventor
Toshifumi Morita
敏文 森田
Shigetoshi Segawa
茂俊 瀬川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2004229893A priority Critical patent/JP2005072574A/en
Publication of JP2005072574A publication Critical patent/JP2005072574A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board, capable of reducing a thermal stress applied to a ceramic substrate side of the circuit board, preventing cracks in the ceramic substrate from occurring and improving a reliability due to thermal stress. <P>SOLUTION: In the circuit board in which a plurality of substrates (11) are stuck on a main board (17) with solder (19), the plurality of substrates (11) contain a substrate whose coefficient of thermal expansion is relatively smaller than that of the main board (17), and the plurality of boards (11) are constituted by pasting a ceramic substrate (12) and a substrate (13) which is located at the main board (17) side of the ceramic substrate (12) and is stronger than the ceramic substrate (12). Thereby, since the substrate (13), which is stronger than the ceramic substrate (12), is pasted at the main substrate (17) side of the ceramic substrate (12), the thermal stress applied to the ceramic substrate (12) side of the circuit substrate is reduced, and it is possible to prevent cracks from occurring at the ceramic substrate (12), and reliability of the circuit board caused by the thermal stress can be improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、電子部品等が実装される回路基板に関するものである。   The present invention relates to a circuit board on which electronic components and the like are mounted.

以下、従来の回路基板について説明する。従来の回路基板は、図４に示すようにセラミックで形成された回路基板（以下、「セラミック基板」という）１の上に接着剤層２１を介して半導体集積回路２が装着されていた。また、このセラミック基板１の下面には端子パッド３が設けられ、半導体集積回路２と配線パターンやスルーホールで接続されていた。   Hereinafter, a conventional circuit board will be described. As shown in FIG. 4, a conventional circuit board has a semiconductor integrated circuit 2 mounted on a circuit board (hereinafter referred to as “ceramic substrate”) 1 made of ceramic via an adhesive layer 21. A terminal pad 3 is provided on the lower surface of the ceramic substrate 1 and is connected to the semiconductor integrated circuit 2 by a wiring pattern or a through hole.

樹脂で形成されたメイン基板４には、端子パッド３に対応した位置に接続パッド５が設けられていた。そして、この接続パッド５と端子パッド３とは、半田６で電気的かつ機械的に接続されていた。   On the main substrate 4 made of resin, connection pads 5 were provided at positions corresponding to the terminal pads 3. The connection pad 5 and the terminal pad 3 are electrically and mechanically connected by the solder 6.

なお、この本発明に関連する先行技術文献情報としては、例えば、特許文献１が知られている
特開平１０−１０７３９８号公報 As prior art document information related to the present invention, for example, Patent Document 1 is known.
JP-A-10-107398

しかし、このような従来のセラミック基板１を樹脂で形成されたメイン基板４に載置して、半田６で電気的かつ機械的に固着すると、両材質の熱膨張係数の相違から以下のような問題が生ずる。   However, when such a conventional ceramic substrate 1 is placed on the main substrate 4 formed of resin and is electrically and mechanically fixed with the solder 6, the following is due to the difference in thermal expansion coefficient between the two materials. Problems arise.

即ち、メイン基板４の熱膨張係数は、低温焼成セラミック基板１の熱膨張係数の略３倍である。このような熱膨張係数の異なる基板１，４同士が半田６で固着され、熱ストレスにさらされると、図５に示すように、お互いの基板１，４に応力が加わる。この応力でセラミック基板１には矢印７に示すように外側に向かって引っ張る力が働く。そのためセラミック基板１にクラックが入る可能性があった。   That is, the thermal expansion coefficient of the main substrate 4 is approximately three times the thermal expansion coefficient of the low-temperature fired ceramic substrate 1. When the substrates 1 and 4 having different thermal expansion coefficients are fixed to each other with the solder 6 and exposed to thermal stress, stress is applied to the substrates 1 and 4 as shown in FIG. Due to this stress, a force pulling outward acts on the ceramic substrate 1 as indicated by an arrow 7. For this reason, there is a possibility that the ceramic substrate 1 is cracked.

本発明は、前記従来の問題を解決するため、回路基板のセラミック基板側に加わる熱応力を軽減し、セラミック基板のクラックの発生を防止し、熱ストレスによる信頼性を向上した回路基板を提供する。   In order to solve the above-mentioned conventional problems, the present invention provides a circuit board that reduces thermal stress applied to the ceramic substrate side of the circuit board, prevents cracks in the ceramic board, and improves reliability due to thermal stress. .

本発明の回路基板は、メイン基板上に複数枚の基板が半田により固着されている回路基板であって、前記複数枚の基板は前記メイン基板より相対的に熱膨張係数の小さい基板を含み、前記複数枚の基板は、セラミック基板と、前記セラミック基板のメイン基板側に前記セラミック基板より高強度の基板が貼り合わせられていることを特徴とする。   The circuit board of the present invention is a circuit board in which a plurality of boards are fixed on a main board by solder, and the plurality of boards includes a board having a relatively smaller thermal expansion coefficient than the main board, The plurality of substrates are characterized in that a ceramic substrate and a substrate having higher strength than the ceramic substrate are bonded to the main substrate side of the ceramic substrate.

本発明によれば、セラミック基板のメイン基板側に前記セラミック基板より高強度の基板が貼り合わされているので、回路基板のセラミック基板側に加わる熱応力は軽減される。従って、セラミック基板にクラックが発生することを防止することができる。よって、回路基板の熱ストレスによる信頼性を向上させることができる。   According to the present invention, since the substrate having higher strength than the ceramic substrate is bonded to the main substrate side of the ceramic substrate, the thermal stress applied to the ceramic substrate side of the circuit substrate is reduced. Therefore, cracks can be prevented from occurring in the ceramic substrate. Therefore, the reliability due to the thermal stress of the circuit board can be improved.

本発明は、熱膨張係数の大きいメイン基板上に半田で固着されるとともに、前記メイン基板より熱膨張係数の小さい回路基板であって、前記回路基板は、セラミック基板と、このセラミック基板の前記メイン基板側に前記セラミック基板より高強度の基板が貼り合わせられているので、セラミック基板に熱応力が加わっても、クラックが発生することを防止することができる。よって、回路基板の熱ストレスに対する信頼性を向上させることができる。   The present invention is a circuit board that is fixed to a main board having a large thermal expansion coefficient by solder and has a smaller thermal expansion coefficient than the main board, the circuit board comprising a ceramic board and the main board of the ceramic board. Since a substrate having a strength higher than that of the ceramic substrate is bonded to the substrate side, cracks can be prevented from occurring even if thermal stress is applied to the ceramic substrate. Therefore, the reliability with respect to the thermal stress of a circuit board can be improved.

前記高強度の基板は、アルミナ基板であることが好ましい。これによりセラミック基板の強度が増す。アルミナ基板の厚みは、０．１９ｍｍ以上０．５ｍｍ以下の範囲であることが好ましい。   The high-strength substrate is preferably an alumina substrate. This increases the strength of the ceramic substrate. The thickness of the alumina substrate is preferably in the range of 0.19 mm to 0.5 mm.

前記アルミナ基板は、厚さ方向に一つ以上の貫通孔が設けられ、前記貫通孔に導電ペーストが充填されて導通していることが好ましい。これにより、アルミナ基板に配線された導体をセラミック基板上に導通させることが出来る。   It is preferable that the alumina substrate is provided with one or more through holes in the thickness direction, and the through holes are filled with a conductive paste to be conductive. Thereby, the conductor wired on the alumina substrate can be conducted on the ceramic substrate.

前記貫通孔は、その直径が０．１ｍｍ以上０．３ｍｍ以下の範囲であることが好ましい。これにより、アルミナ基板に設けられた貫通孔への導電ペーストの充填性を良くすることができる。   The through hole preferably has a diameter in the range of 0.1 mm to 0.3 mm. Thereby, the filling property of the electrically conductive paste to the through-hole provided in the alumina substrate can be improved.

また同様な理由から、前記貫通孔の直径をＡ、前記アルミナ基板の厚みをＢとしたとき、０．９Ｂ≦Ａ≦２．５Ｂの関係にあることが好ましい。   For the same reason, when the diameter of the through hole is A and the thickness of the alumina substrate is B, it is preferable that 0.9B ≦ A ≦ 2.5B.

前記アルミナ基板上に配線パターンを設け、配線パターンは貫通孔に接続され、この配線パターンを介してセラミック基板に設けられた他の回路に接続されていることが好ましい。これにより配線パターンを有しているので、この配線パターンで接続パッドまで配線を敷設することができ、接続パッド配置の自由度が増す。   It is preferable that a wiring pattern is provided on the alumina substrate, the wiring pattern is connected to a through hole, and is connected to another circuit provided on the ceramic substrate via the wiring pattern. Accordingly, since the wiring pattern is provided, the wiring can be laid down to the connection pad with this wiring pattern, and the degree of freedom of the connection pad arrangement is increased.

前記アルミナ基板に設けられた接続用の端子パッドと前記メイン基板に設けられた接続用の接続パッドとの接続は、球状に形成された樹脂と、この樹脂の外表面を覆う少なくとも１層の導電性を持つ金属と、更にこの金属の外表面を覆う半田層とで形成された樹脂ボールにより接続されていることが好ましい。これにより、半田内に形成された樹脂が応力を吸収するので、アルミナ基板に加わる応力が軽減される。   The connection between the terminal pad for connection provided on the alumina substrate and the connection pad for connection provided on the main substrate is made of a resin formed in a spherical shape and at least one conductive layer covering the outer surface of the resin. It is preferable that they are connected by a resin ball formed by a metal having a property and a solder layer covering the outer surface of the metal. Thereby, since the resin formed in the solder absorbs the stress, the stress applied to the alumina substrate is reduced.

前記樹脂ボールの金属層が銅であることが好ましい。電気導通性を良好に保つためである。   The metal layer of the resin ball is preferably copper. This is for maintaining good electrical conductivity.

前記アルミナ基板に設けられた接続用の端子パッドと前記メイン基板に設けられた接続用の接続パッドとの接続は、金属で構成された半田ボールにより接続されていることが好ましい。これにより、従来用いられている半田ボールを使ってアルミナ基板とメイン基板を接続することができる。   The connection between the connection terminal pad provided on the alumina substrate and the connection pad provided on the main substrate is preferably connected by a solder ball made of metal. As a result, the alumina substrate and the main substrate can be connected using the conventionally used solder balls.

前記セラミック基板と、前記高強度基板とは、焼結により一体化するのが好ましい。これにより、両者は強力に貼り合わせることができる。   The ceramic substrate and the high-strength substrate are preferably integrated by sintering. Thereby, both can be bonded together strongly.

（実施の形態１）
以下、本発明の一実施の形態について、図面を用いて説明する。図１は、ガラス繊維織物にエポキシ樹脂を含浸させ硬化した、いわゆるガラスエポキシ基板（厚み２．５ｍｍ）からなるメイン基板１７の上に装着された回路基板１１の断面図である。この回路基板１１は厚さ０．６５ｍｍ、２５０メガパスカルの抗折強度を有する低温焼成セラミック基板１２と、この低温焼成セラミック基板１２の下側に貼り付けられた厚さ０．２８ｍｍのアルミナ基板１３とで構成されている。固着方法は、アルミナ基板１３に低温焼成セラミック基板１２を熱圧着（９０℃程度の温度と２０MＰａ程度の圧力）により貼り付けた後、約９００℃で焼結させて、一体化させている。 (Embodiment 1)
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a circuit board 11 mounted on a main board 17 made of a so-called glass epoxy board (thickness 2.5 mm) obtained by impregnating and curing a glass fiber fabric with an epoxy resin. The circuit board 11 is a low-temperature fired ceramic substrate 12 having a thickness of 0.65 mm and a bending strength of 250 megapascals, and an alumina substrate 13 having a thickness of 0.28 mm attached to the lower side of the low-temperature fired ceramic substrate 12. It consists of and. In the fixing method, the low-temperature fired ceramic substrate 12 is bonded to the alumina substrate 13 by thermocompression bonding (temperature of about 90 ° C. and pressure of about 20 MPa), and then sintered at about 900 ° C. for integration.

このアルミナ基板１３は、抗折強度が３５０メガパスカルであり、低温焼成セラミック基板１２の２５０メガパスカルの抗折強度より約４割大きい。このようにして、低温焼成セラミック基板１２の実質上の抗折強度を大きくしている。   This alumina substrate 13 has a bending strength of 350 megapascals, which is approximately 40% larger than the bending strength of 250 megapascals of the low-temperature fired ceramic substrate 12. In this way, the substantial bending strength of the low-temperature fired ceramic substrate 12 is increased.

なお、低温焼成セラミック基板１２は、アルミナ約５０質量％とガラス約５０質量％の粉体に有機バインダーを加えて作成したグリーンシートを約９００℃で焼成したものである。   The low-temperature fired ceramic substrate 12 is obtained by firing a green sheet prepared by adding an organic binder to a powder of about 50 mass% alumina and about 50 mass% glass at about 900 ° C.

アルミナ基板１３は、アルミナ９６質量％（残余は不可避的天然元素）のアルミナ基板であり、アルミナ基板１３の上方から下方に向けて０．２ｍｍの貫通孔１４が設けられている。そして、この貫通孔１４には、銀を主成分とした導電ペースト１５が充填される。また、アルミナ基板１３の下面には貫通孔１４に接続された端子パッド１６が設けられている。   The alumina substrate 13 is an alumina substrate of 96 mass% alumina (the rest is an inevitable natural element), and a 0.2 mm through-hole 14 is provided from the upper side to the lower side of the alumina substrate 13. The through holes 14 are filled with a conductive paste 15 mainly composed of silver. A terminal pad 16 connected to the through hole 14 is provided on the lower surface of the alumina substrate 13.

メイン基板１７の上面には、端子パッド１６に対応した位置に接続パッド１８が設けられており、その間を半田１９で固着している。このように、メイン基板１７と回路基板１１とは、半田１９で固着されている。ここで、回路基板１１の低温焼成セラミック基板１２は抗折強度の大きなアルミナ基板１３と焼結により貼り合されて一体化されているので、例えメイン基板１７の熱膨張係数が低温焼成セラミック基板１２の熱膨張係数より大きく、低温焼成セラミック基板１２に熱によるストレスが加わっても、低温焼成セラミック基板１２にクラックが生ずるようなことはない。   On the upper surface of the main substrate 17, connection pads 18 are provided at positions corresponding to the terminal pads 16, and between them are fixed with solder 19. Thus, the main board 17 and the circuit board 11 are fixed by the solder 19. Here, since the low-temperature fired ceramic substrate 12 of the circuit board 11 is bonded and integrated with the alumina substrate 13 having a high bending strength by sintering, for example, the thermal expansion coefficient of the main substrate 17 is low-temperature fired ceramic substrate 12. Even if a thermal stress is applied to the low-temperature fired ceramic substrate 12, the low-temperature fired ceramic substrate 12 does not crack.

また、セラミック基板１２の上面にはエポキシ樹脂からなる接着剤層２１を介して半導体集積回路２が固定されており、セラミック基板１２と配線で繋がっている。この配線はアルミナ基板１３の上面に敷設された配線パターン２０に接続されている。この配線パターン２０は貫通孔１４に接続されており、この貫通孔１４に充填された導電ペースト１５を介してメイン基板１７に導かれる。結局、半導体集積回路２の信号はセラミック基板１２の配線を介して、配線パターン２０から導電ペースト１５と、端子パッド１６と、半田１９と、接続パッド１８をこの順に通過してメイン基板１７に導かれる。   The semiconductor integrated circuit 2 is fixed to the upper surface of the ceramic substrate 12 via an adhesive layer 21 made of an epoxy resin, and is connected to the ceramic substrate 12 by wiring. This wiring is connected to a wiring pattern 20 laid on the upper surface of the alumina substrate 13. The wiring pattern 20 is connected to the through hole 14 and is led to the main substrate 17 through the conductive paste 15 filled in the through hole 14. As a result, the signal of the semiconductor integrated circuit 2 passes through the wiring of the ceramic substrate 12, passes through the conductive paste 15, the terminal pad 16, the solder 19, and the connection pad 18 in this order from the wiring pattern 20 to the main substrate 17. It is burned.

このように、アルミナ基板１３上に配線パターン２０を設けて、この配線パターン２０で貫通孔１４に接続するので、貫通孔１４の位置を定間隔に設ける等、設計の自由度を大きくすることができる。   Thus, since the wiring pattern 20 is provided on the alumina substrate 13 and is connected to the through hole 14 by this wiring pattern 20, the degree of freedom in design can be increased, for example, the positions of the through holes 14 are provided at regular intervals. it can.

表１に、半田１９として６３Ｓｎ／３７Ｐｂからなる共晶半田のボールを用いた場合のアルミナ基板１３の厚みと、貫通孔（スルーホール）１４へ導電ペーストを充填したときのスルーホール充填性およびヒートサイクルの試験結果を示す。サンプルの厚みは０．６５ｍｍのセラミック基板１２に９６質量％アルミナ基板（残余は不可避的天然元素）１３を貼り合せ、セラミック基板１２上の半導体集積回路２のサイズは２５．４ｍｍ角、ピン数は１４４ピンであり、アルミナ基板１３に設けられた貫通孔１４の直径は０．２ｍｍとした。また、図６、図７に、ヒートサイクル回数とセラミック基板１２とメイン基板１７との間の接続抵抗値の変化を示す。図１２に、本実施例でのヒートサイクル条件を示す。ヒートサイクルの温度範囲は、−５５℃から＋１２５℃とした。試験開始温度は−５５℃であり、約１５分で１２５℃まで昇温し、１５分保持する。その後、−５５℃まで約１５分で降温し、−５５℃にて１５分保持する。以上の一連の温度変化を１サイクルとする。スルーホール充填性は、20倍の顕微鏡にてアルミナ基板１３の両面を観察し、（１）印刷側から見て、スルーホールの反対面まで導体ペーストが充填されていること、（２）印刷面、反対面について、導体ペーストの著しい飛び出し(0.1mm程度)が無いこと、（３）導体ペーストが充填されたスルーホールに貫通穴が無いこと、を目視評価し、Ａは良好、Ｂはやや良、Ｃは不可とした。   Table 1 shows the thickness of the alumina substrate 13 when eutectic solder balls made of 63Sn / 37Pb are used as the solder 19, the through-hole filling property and heat when the through-hole (through-hole) 14 is filled with the conductive paste. The cycle test results are shown. A 96% alumina substrate (the remainder is an inevitable natural element) 13 is bonded to a ceramic substrate 12 having a thickness of 0.65 mm, the size of the semiconductor integrated circuit 2 on the ceramic substrate 12 is 25.4 mm square, and the number of pins is The diameter of the through-hole 14 provided in the alumina substrate 13 was 144 mm. 6 and 7 show changes in the number of heat cycles and the connection resistance value between the ceramic substrate 12 and the main substrate 17. FIG. 12 shows the heat cycle conditions in this example. The temperature range of the heat cycle was −55 ° C. to + 125 ° C. The test start temperature is −55 ° C., and the temperature is raised to 125 ° C. in about 15 minutes and held for 15 minutes. Thereafter, the temperature is lowered to −55 ° C. in about 15 minutes and held at −55 ° C. for 15 minutes. The above series of temperature changes is defined as one cycle. The through-hole filling property is that both sides of the alumina substrate 13 are observed with a 20 × microscope, and (1) the conductor paste is filled up to the opposite side of the through-hole when viewed from the printing side. On the opposite surface, the conductor paste was not significantly popped out (about 0.1 mm), and (3) the through hole filled with the conductor paste was visually evaluated, and A was good and B was slightly good. , C was not allowed.

Figure 2005072574
Figure 2005072574

表１から明らかなように、スルーホール充填性は、アルミナ基板の厚みに関係する。本実施例では、アルミナ基板厚が０．６３５ｍｍでは、スルーホール内の導体ペーストが十分に充填されなかった。これは、スルーホールの直径よりスルーホールの深さが大きいため、導体ペーストの充填が不十分になり、印刷側から反対側まで導体ペーストが届かなくためである。アルミナ基板厚が０．１９ｍｍから０．５ｍｍの範囲では、スルーホール内の導体ペーストを、完全に充填することが出来た。アルミナ基板厚が０．１５ｍｍでは、スルーホールの直径よりスルーホールの深さが小さいため、スルーホール内部に導体ペーストが保持されず、貫通穴が発生した。スルーホール充填性から見た適正なアルミナ基板１３の厚みは、アルミナ基板１３に設けられた貫通孔１４の直径が０．２ｍｍのとき、０．１９ｍｍから０．５ｍｍである。アルミナ基板を貼り付けていないサンプルでは、信頼性が確保されるのは５０サイクルまでであるが（図５）、本実施例の適正な厚みのアルミナ基板を貼り付けたサンプルでは、１００サイクルまで信頼性が向上した（図７）。すなわち、本実施例の共晶半田のボールを用いた接続では、従来に比べて２倍の信頼性を実現できる。   As is apparent from Table 1, the through hole filling property is related to the thickness of the alumina substrate. In this example, when the alumina substrate thickness was 0.635 mm, the conductor paste in the through hole was not sufficiently filled. This is because the depth of the through hole is larger than the diameter of the through hole, so that the conductor paste is not sufficiently filled, and the conductor paste does not reach from the printing side to the opposite side. When the alumina substrate thickness was in the range of 0.19 mm to 0.5 mm, the conductor paste in the through hole could be completely filled. When the alumina substrate thickness was 0.15 mm, the depth of the through hole was smaller than the diameter of the through hole, so that the conductive paste was not held inside the through hole, and a through hole was generated. The appropriate thickness of the alumina substrate 13 viewed from the through hole filling property is 0.19 mm to 0.5 mm when the diameter of the through hole 14 provided in the alumina substrate 13 is 0.2 mm. In the sample not attached with the alumina substrate, the reliability is ensured up to 50 cycles (FIG. 5). However, in the sample attached with the alumina substrate having an appropriate thickness of this embodiment, the reliability is up to 100 cycles. Improved (FIG. 7). That is, in the connection using the eutectic solder balls of the present embodiment, double the reliability can be realized as compared with the conventional case.

表２は、半田１９として樹脂ボールを用いた場合のアルミナ基板１３の厚みと、貫通孔（スルーホール）１４へ導電ペーストを充填したときのスルーホール充填性およびヒートサイクルの試験結果を示す。サンプルは、厚みが０．６５ｍｍのセラミック基板１２に９６質量％アルミナ基板１３を貼り合せ、セラミック基板１２上の半導体集積回路２のサイズは２５．４ｍｍ角、ピン数は１４４ピンであり、アルミナ基板１３に設けられた貫通孔１４の直径が０．２ｍｍとした。また、図８から図１１にヒートサイクル回数とセラミック基板１２とメイン基板１７との間の接続抵抗値の変化を示す。   Table 2 shows the thickness of the alumina substrate 13 in the case where resin balls are used as the solder 19, the through hole filling property when the through paste (through hole) 14 is filled with the conductive paste, and the heat cycle test results. In the sample, a 96% by mass alumina substrate 13 is bonded to a ceramic substrate 12 having a thickness of 0.65 mm, the size of the semiconductor integrated circuit 2 on the ceramic substrate 12 is 25.4 mm square, and the number of pins is 144 pins. The diameter of the through-hole 14 provided in 13 was 0.2 mm. FIGS. 8 to 11 show the number of heat cycles and the change in the connection resistance value between the ceramic substrate 12 and the main substrate 17.

Figure 2005072574
Figure 2005072574

表２の結果で説明したとおり、適正なアルミナ基板１３の厚みは、アルミナ基板１３に設けられた貫通孔１４の直径が０．２ｍｍのとき、０．１９ｍｍから０．５ｍｍである。アルミナ基板１３を貼り付けていないサンプルでは、信頼性が確保されるのは４００サイクルまでであるが（図８）、本実施例の適正な厚みのアルミナ基板を貼り付けたサンプルでは７５０サイクルまで信頼性が向上した（図９、図１０、図１１）。すなわち、本実施例を用いると、樹脂ボールを用いた接続では、従来に比べて約１．９倍の信頼性を実現できる。   As described in Table 2, the proper thickness of the alumina substrate 13 is 0.19 mm to 0.5 mm when the diameter of the through hole 14 provided in the alumina substrate 13 is 0.2 mm. In the sample in which the alumina substrate 13 is not attached, the reliability is ensured up to 400 cycles (FIG. 8), but in the sample in which the alumina substrate having an appropriate thickness of this embodiment is attached, the reliability is up to 750 cycles. Improved (FIGS. 9, 10, and 11). That is, when this embodiment is used, the connection using the resin ball can realize about 1.9 times higher reliability than the conventional one.

本実施例では、基板はセラミック基板に９６質量％アルミナ基板を貼り合せたもの、セラミック基板の厚みは０．６５ｍｍ、半導体集積回路２のサイズは２５．４ｍｍ角、ピン数は１４４ピンのものをサンプルとした。ここで、セラミック基板の厚みは０．６５ｍｍとしたが、これに限るものではない。   In this embodiment, the substrate is a ceramic substrate bonded with a 96 mass% alumina substrate, the thickness of the ceramic substrate is 0.65 mm, the size of the semiconductor integrated circuit 2 is 25.4 mm square, and the number of pins is 144 pins. A sample was used. Here, the thickness of the ceramic substrate is 0.65 mm, but is not limited thereto.

図２は、回路基板１１とメイン基板１７とを電気的・機械的に接続する樹脂ボール２９の断面図である。図２において、２５は球形状の樹脂コアであり、２６はその外側を覆うニッケル層である。また、２７はニッケル２６を覆う銅層であり、２８は銅層２７を覆う半田層である。そして、全体としても球形状をしている。この樹脂ボール２９には銅層２７が含まれているので電気伝導性が高い。   FIG. 2 is a cross-sectional view of a resin ball 29 that electrically and mechanically connects the circuit board 11 and the main board 17. In FIG. 2, 25 is a spherical resin core, and 26 is a nickel layer covering the outside. Reference numeral 27 denotes a copper layer covering the nickel 26, and reference numeral 28 denotes a solder layer covering the copper layer 27. And it has a spherical shape as a whole. Since the resin balls 29 include the copper layer 27, the electrical conductivity is high.

図３は、この樹脂ボール２９で回路基板１１の端子パッド１６と、メイン基板１７の接続パッド１８を電気的かつ機械的に接続した断面図である。このような樹脂ボール２９を用いることにより、樹脂コア２５が熱応力に対して変形して歪みを吸収するので、回路基板１１とメイン基板１７の熱膨張係数が異なっても、回路基板１１とメイン基板１７にストレスが発生することを防止することができる。   FIG. 3 is a cross-sectional view in which the resin pads 29 electrically and mechanically connect the terminal pads 16 of the circuit board 11 and the connection pads 18 of the main board 17. By using such a resin ball 29, the resin core 25 is deformed by the thermal stress and absorbs the distortion. Therefore, even if the thermal expansion coefficients of the circuit board 11 and the main board 17 are different, the circuit board 11 and the main board It is possible to prevent the substrate 17 from being stressed.

本発明にかかる回路基板は、高強度の基板を低強度の基板に貼り付けることにより熱膨張係数の違いによる二種の材料間の応力によるクラックを防止するものであり、セラミック基板等を用いた機器に有用である。   The circuit board according to the present invention prevents cracking due to stress between two kinds of materials due to a difference in thermal expansion coefficient by sticking a high-strength board to a low-strength board. Useful for equipment.

本発明の一実施の形態におけるメイン基板上に装着された回路基板の断面図Sectional drawing of the circuit board mounted on the main board in one embodiment of this invention 同、メイン基板と回路基板を接続する半田の断面図Same as above, cross-sectional view of solder connecting main board and circuit board 同、半田で接続されたメイン基板と回路基板の断面図Cross section of main board and circuit board connected with solder 従来のメイン基板上に装着された回路基板の断面図Sectional view of a circuit board mounted on a conventional main board 同、熱応力が加わった場合の説明のための断面図Sectional view for explanation when thermal stress is applied アルミナなし＋半田ボールの接続抵抗値変化を示すグラフGraph showing change in connection resistance value of no alumina + solder ball アルミナ厚み０．５０ｍｍ＋半田ボールの接続抵抗値変化を示すグラフGraph showing change in connection resistance value of alumina thickness 0.50mm + solder ball アルミナなし＋樹脂ボールの接続抵抗値変化を示すグラフGraph showing change in connection resistance value of no alumina + resin ball アルミナア厚み０，１９ｍｍ＋樹脂ボールの接続抵抗値変化を示すグラフGraph showing change in connection resistance value of alumina core thickness 0,19 mm + resin ball アルミナ厚み０．２８ｍｍ＋樹脂ボールの接続抵抗値変化を示すグラフGraph showing change in connection resistance value of alumina thickness 0.28 mm + resin ball アルミナ厚み０．５０ｍｍ＋樹脂ボールの接続抵抗値変化を示すグラフGraph showing change in connection resistance value of alumina thickness 0.50 mm + resin ball ヒートサイクル条件を示す図Diagram showing heat cycle conditions

符号の説明Explanation of symbols

１１ 印刷基板
１２ セラミック基板
１３ アルミナ基板
１７ メイン基板
１９ 半田
２９ 樹脂ボール

11 Print substrate 12 Ceramic substrate 13 Alumina substrate 17 Main substrate 19 Solder 29 Resin ball

Claims (11)

メイン基板上に複数枚の基板が半田により固着されている回路基板であって、
前記複数枚の基板は前記メイン基板より相対的に熱膨張係数の小さい基板を含み、
前記複数枚の基板は、セラミック基板と、前記セラミック基板のメイン基板側に前記セラミック基板より高強度の基板が貼り合わせられていることを特徴とする回路基板。 A circuit board in which a plurality of boards are fixed by solder on the main board,
The plurality of substrates includes a substrate having a smaller coefficient of thermal expansion than the main substrate,
The circuit board, wherein the plurality of substrates are a ceramic substrate and a substrate having a strength higher than that of the ceramic substrate is bonded to a main substrate side of the ceramic substrate. 前記高強度の基板は、アルミナ基板である請求項１に記載の回路基板。   The circuit board according to claim 1, wherein the high-strength substrate is an alumina substrate. 前記アルミナ基板の厚みは、０．１９ｍｍ以上０．５ｍｍ以下の範囲である請求項２に記載の回路基板。   The circuit board according to claim 2, wherein a thickness of the alumina substrate is in a range of 0.19 mm to 0.5 mm. 前記アルミナ基板は、厚さ方向に一つ以上の貫通孔が設けられ、前記貫通孔に導電ペーストが充填されて導通している請求項２に記載の回路基板。   The circuit board according to claim 2, wherein the alumina substrate is provided with one or more through holes in a thickness direction, and the through holes are filled with a conductive paste to be conducted. 前記貫通孔は、その直径が０．１ｍｍ以上０．３ｍｍ以下の範囲である請求項４に記載の回路基板。   The circuit board according to claim 4, wherein the through hole has a diameter in a range of 0.1 mm to 0.3 mm. 前記貫通孔の直径をＡ、前記アルミナ基板の厚みをＢとしたとき、０．９Ｂ≦Ａ≦２．５Ｂの関係にある請求項５に記載の回路基板。   6. The circuit board according to claim 5, wherein AB is 0.9B ≦ A ≦ 2.5B, where A is the diameter of the through hole and B is the thickness of the alumina substrate. 前記アルミナ基板上に配線パターンを設け、配線パターンは貫通孔に接続され、この配線パターンを介してセラミック基板に設けられた他の回路に接続されている請求項４に記載の回路基板。   The circuit board according to claim 4, wherein a wiring pattern is provided on the alumina substrate, the wiring pattern is connected to a through hole, and is connected to another circuit provided on the ceramic substrate via the wiring pattern. 前記アルミナ基板に設けられた接続用の端子パッドと前記メイン基板に設けられた接続用の接続パッドとの接続は、球状に形成された樹脂と、この樹脂の外表面を覆う少なくとも１層の導電性を持つ金属と、更にこの金属の外表面を覆う半田層とで形成された樹脂ボールにより接続されている請求項２に記載の回路基板。   The connection between the terminal pad for connection provided on the alumina substrate and the connection pad for connection provided on the main substrate is made of a resin formed in a spherical shape and at least one conductive layer covering the outer surface of the resin. The circuit board according to claim 2, wherein the circuit board is connected by a resin ball formed of a metal having a property and a solder layer covering an outer surface of the metal. 前記樹脂ボールの金属層が銅である請求項８に記載の回路基板。   The circuit board according to claim 8, wherein the metal layer of the resin ball is copper. 前記アルミナ基板に設けられた接続用の端子パッドと前記メイン基板に設けられた接続用の接続パッドとの接続は、金属で構成された半田ボールにより接続されている請求項２に記載の回路基板。   The circuit board according to claim 2, wherein the connection between the connection terminal pad provided on the alumina substrate and the connection pad provided on the main substrate is connected by a solder ball made of metal. . 前記セラミック基板と、前記高強度基板とは、焼結により一体化されている請求項１に記載の回路基板。

The circuit board according to claim 1, wherein the ceramic substrate and the high-strength substrate are integrated by sintering.

JP2004229893A 2003-08-07 2004-08-05 Circuit board Pending JP2005072574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004229893A JP2005072574A (en) 2003-08-07 2004-08-05 Circuit board

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003288744 2003-08-07
JP2004229893A JP2005072574A (en) 2003-08-07 2004-08-05 Circuit board

Publications (1)

Publication Number Publication Date
JP2005072574A true JP2005072574A (en) 2005-03-17

Family

ID=34425252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004229893A Pending JP2005072574A (en) 2003-08-07 2004-08-05 Circuit board

Country Status (1)

Country Link
JP (1) JP2005072574A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101053399B1 (en) * 2009-02-10 2011-08-01 삼성전기주식회사 LTC module and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101053399B1 (en) * 2009-02-10 2011-08-01 삼성전기주식회사 LTC module and its manufacturing method

Similar Documents

Publication Publication Date Title
JP3401767B2 (en) Multilayer ceramic substrate and method of manufacturing the same
TWI232712B (en) Intermediate board, intermediate board with a semiconductor device, substrate board with an intermediate board, structural member including a semiconductor device, an intermediate board and a substrate board, and method of producing an intermediate board
JP4310467B2 (en) Composite multilayer substrate and manufacturing method thereof
JP4111239B2 (en) Composite ceramic substrate
JP4793447B2 (en) Multilayer ceramic substrate, method for manufacturing the same, and electronic component
CN101124675A (en) Stacked electronic component, electronic device and method for manufacturing stacked electronic component
JP4265607B2 (en) Laminated electronic component and mounting structure of laminated electronic component
JP2004304159A (en) Intermediate substrate, intermediate substrate with semiconductor element, substrate with intermediate substrate, and structure composed of semiconductor element, intermediate substrate, and substrate
JP2004266074A (en) Wiring board
JP4432517B2 (en) Composite multilayer board
JP4158798B2 (en) Composite ceramic substrate
KR100903291B1 (en) Space transformer having through via and manufacturing method thereof
JP7243856B2 (en) Circuit board and circuit board manufacturing method
JP2005072574A (en) Circuit board
JP2007173862A (en) Structure comprising relay substrate, relay substrate with semiconductor element, substrate with relay substrate, and structure composed of semiconductor element, relay substrate, and substrate
US20120155044A1 (en) Electronic circuit board and a related method thereof
JP2005191075A (en) Relay substrate and its manufacturing method, and substrate therewith
JP4711757B2 (en) Wiring board
US20050029011A1 (en) Circuit board
JP2000340716A (en) Wiring substrate
JP3692214B2 (en) Multilayer wiring board
JP2006222443A (en) Connection structure and method of forming same, circuit board, electronic component surface-mounted on mounting board, and method of forming connection member
JP2004356619A (en) Intermediate substrate, intermediate substrate with semiconductor element, substrate with intermediate substrate, and structure having semiconductor element, intermediate substrate and substrate
JP2007311643A (en) Laminated semiconductor device
JPH11274372A (en) Semiconductor device and its semiconductor package

Legal Events

Date Code Title Description
A977 Report on retrieval

Effective date: 20051228

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Effective date: 20060106

Free format text: JAPANESE INTERMEDIATE CODE: A131

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060508