JP2005071490A - Information recording device, information reproducing device, information recording medium and method, and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device, a medium and a method for recording additional information difficult to be analyzed in an information recording medium. <P>SOLUTION: According to the constituting bit information "0" or "1" of additional data, a synchronous code is selected from primary or secondary synchronous codes to be set. The state value of a data area including the recording area of the additional data is obtained from the synchronous code during reproduction, for example, an additional constituting bit "0" or "1" is obtained by calculating a parity. During recording, a parity value based on the data area of a synchronous frame into which the additional data are inserted calculated. Based on the parity value and the bit value information "0" or "1" of the additional data, a synchronous code is selected from the primary or secondary synchronous codes to be set. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information recording processing device, an information reproduction processing device, an information recording medium, a method, and a computer program. More specifically, for example, on an information recording medium such as a DVD for recording content such as image data and music data, additional information such as key information applied to content decryption processing, content playback control information, copy control information, etc. The present invention relates to an information recording processing apparatus, an information reproduction processing apparatus, an information recording medium and method, and a computer program that can record and read various additional information in a form that is difficult to analyze by setting control of a synchronization code.

  When data such as music data and image data is recorded as digital data on a recording medium, a recording process according to a predetermined recording format is performed. For example, an error detection / correction code is added to the original data to be recorded, and it is recorded after being converted (coded) into a format corresponding to a specific data recording / reproducing process. As a well-known modulation method, there is an EFM (Eight to Fourteen Modulation) modulation method. The EFM modulation is a modulation process for converting the input 8 bits into 14 bits. For example, in an EFM modulation method used for CD recording, input 8 bits are converted into 14 information bits, and further, bit information combined through 3 margin bits is generated, and further, [0] or [1] Is recorded on the recording medium as an NRZI (Non Return to Zero Inverted) signal for inverting the polarity of the pulse according to the value of.

  Furthermore, in a DVD (Digital Versatile Disc) capable of high-density recording, an 8-16 modulation system that directly converts input 8 bits into 16 bits without applying margin bits is applied. This modulation method is called an EFMplus modulation method. For code conversion in EFMplus modulation, a conversion table is used, a 16-bit code word is acquired from the conversion table based on 8-bit input, and data generated based on the acquired 16-bit code word is DVD or the like. Recorded on the recording medium.

  By the way, as contents to be stored in an information recording medium such as a DVD, there are, for example, a movie and music data. Many contents, such as music data and image data, generally have distribution rights or the like held by the creator or seller. Therefore, when distributing these contents, it is common to adopt a configuration that restricts the use of the contents, that is, permits the use of the contents only to authorized users and prevents unauthorized copying or the like. It is the target.

  A large-capacity recording medium such as a DVD or a recording medium using a blue laser recording method capable of recording a higher capacity can record data for one movie to several movies on one medium. is there. As content can easily be recorded as digital information, the problem of flooding of illegal copies often occurs, and the problem of obstructing the interests of copyright holders and distributors of content becomes large. ing. Under such circumstances, how to prevent illegal copying and protect the interests of copyright holders and distribution rights holders is an important issue.

  In order to prevent such unauthorized use of content, content stored in an information recording medium such as a DVD is recorded as encrypted content, and encryption key information or encryption key applied to use of the encrypted content is generated. A configuration has been proposed in which necessary information or various control information such as content reproduction control and copy control is stored as secret information in an information recording medium. A configuration in which a playback processing program executed in a playback device of a user reads secret information such as a key corresponding to the content to be played, decrypts the content according to the read secret information, and executes use of the content according to the playback control information It is.

  For example, Patent Document 1 discloses a configuration in which special data is embedded by applying a connection bit (margin bit) of EFM modulation data as a prior art that discloses a secret information embedding processing configuration. Patent Document 2 discloses a configuration in which a plurality of conversion tables are applied to the modulation process, and data related to the conversion table applied to the modulation is extracted during reproduction, and additional data is acquired based on the extracted data. Disclosure.

However, if information such as where such an encryption key or control information is stored in an information recording medium is acquired by a user or an unauthorized content user, additional information can be leaked or altered. There is a problem of end. For example, problems such as falsification of reproduction control information and copy control information, or leakage of key information occur. If the encryption key is leaked or the control information is tampered with, the usage form of the content based on the legitimate content usage right will be lost, and the copyright and usage right of the content will not be adequately protected. is there.
JP 2003-45128 A JP 2002-367282 A

  The present invention has been made in view of the above-described problems. In a content storage recording medium such as a DVD, an encryption key stored in the recording medium together with the content, encryption key generation information, content reproduction control information, content copy control information, Alternatively, various additional information such as other content attribute information can be recorded in a manner that cannot be read by a general data reading process by controlling the setting of the synchronization code, and information recording processing that makes illegal data reading difficult It is an object to provide an apparatus, an information reproduction processing apparatus, an information recording medium and method, and a computer program.

The first aspect of the present invention is:
In the information recording processing apparatus,
A modulator for modulating data;
A signal processing unit that selects one synchronization code from a primary synchronization code and a secondary synchronization code set with different synchronization codes, adds the selected synchronization code to the modulated data, and outputs a synchronization frame;
Based on the configuration bit value of the additional data and the state of the data area in the synchronization frame including the additional data recording area in which the additional data is embedded, the synchronization code set in the synchronization frame is the primary synchronization code or the secondary synchronization code. A control unit for selecting one of them,
It is in the information recording processing apparatus characterized by having.

Furthermore, in one embodiment of the information recording processing apparatus of the present invention, the state of the data area in the synchronization frame including the additional data recording area is such that the parity of the data area including the additional data recording area is immediately after the synchronization code in the synchronization frame. Whether it is an even number or an odd number, and the control unit
a. Whether the configuration bit value of the additional data is 0 or 1, and
b. Whether the parity is even or odd,
A. b. Based on two conditions, it is characterized in that it is determined whether to select a primary synchronization code or a secondary synchronization code as a synchronization code to be set in the synchronization frame.

  Furthermore, in one embodiment of the information recording processing apparatus of the present invention, the control unit is configured such that the number of bits [1] included in each synchronization code of the primary synchronization code and the secondary synchronization code is an even number and an odd number, that is, different parity. The present invention is characterized in that a selection process of either a primary synchronization code or a secondary synchronization code is executed based on a combination of synchronization codes.

  Furthermore, in one embodiment of the information recording processing apparatus of the present invention, the information recording processing apparatus includes: encryption key information, encryption key generation information, content reproduction control information of content stored in the information recording medium, the additional data, The content copy control information is set as configuration information of at least one piece of information.

  Furthermore, in one embodiment of the information recording processing device of the present invention, the storage position of the constituent bits of the additional data is set in a reserved field in a data frame generated in the data modulation process. To do.

  Furthermore, in one embodiment of the information recording processing apparatus of the present invention, the signal processing unit converts the input 8-bit data into a 16-bit code word by a conversion process based on a conversion table, and the data based on the 16-bit code word. A recording process is performed, and the recording data set in the recording area of the additional data is recording data based on a 16-bit code word converted based on the conversion table.

  Furthermore, in an embodiment of the information recording processing apparatus of the present invention, the conversion process based on the code word selection is configured to be executed as a data conversion process that satisfies RLL (2, 10) as a run length rule. Features.

Furthermore, the second aspect of the present invention provides
An information reproduction processing device that executes reproduction processing of information stored in an information recording medium,
A demodulator that performs demodulation processing of data read from the information recording medium;
Additional data configuration as recording information stored in the additional data recording area based on a result of the status calculation, at least in the recording data area including the additional data recording area from the synchronization code An additional data decoding unit that executes a bit information acquisition process;
The information reproduction processing apparatus is characterized by comprising:

  Furthermore, in one embodiment of the information reproduction processing apparatus of the present invention, the state of the recording data calculated by the additional data decoding unit is such that the synchronization code set in the synchronization frame including the additional data recording area is the primary synchronization code. Or a secondary synchronization code depending on whether the value is different.

  Furthermore, in an embodiment of the information reproduction processing apparatus of the present invention, the state of the recording data calculated by the additional data decoding unit is a parity in a recording data area including the recording area of the additional data from the synchronization code, and the parity is , The configuration is such that identification processing is performed to determine whether the constituent bit value of the additional data is 0 or 1 based on whether it is an even number or an odd number.

  Furthermore, in an embodiment of the information reproduction processing device of the present invention, the information reproduction processing device generates encryption key information and encryption key of content stored in the information recording medium based on the acquired additional data configuration bit information. The present invention is characterized in that a process for generating at least one of information, content reproduction control information, and content copy control information is executed.

Furthermore, the third aspect of the present invention provides
An information recording medium storing recording data based on a synchronization frame in which one synchronization code is selected from a primary synchronization code and a secondary synchronization code in which a different synchronization code is set, and a selection synchronization code is set,
In the additional data recording area,
a. Configuration bit value of additional data,
b. The state of the data area in the synchronization frame including the additional data recording area;
A. b. The information recording medium has a configuration in which data based on an additional data configuration bit storage synchronization frame in which either a primary synchronization code or a secondary synchronization code determined based on two conditions is set is recorded.

Furthermore, in an embodiment of the information recording medium of the present invention, the state of the data area in the synchronization frame including the additional data recording area is such that the parity of the data area including the additional data recording area is even immediately after the synchronization code in the synchronization frame. Or an odd number, and in the additional data recording area,
a. Whether the configuration bit value of the additional data is 0 or 1, and
b. Whether the parity is even or odd,
A. b. It has a configuration in which data based on an additional data configuration bit storage synchronization frame in which either a primary synchronization code or a secondary synchronization code determined based on two conditions is set is recorded.

  Furthermore, in an embodiment of the information recording medium of the present invention, the information recording medium has an even number and an odd number of bits [1] included in each synchronization code of the primary synchronization code and the secondary synchronization code, that is, different parity. It has a configuration in which data based on a synchronization frame in which one of the primary synchronization code or secondary synchronization code selected from a combination of synchronization codes is set.

  Furthermore, in an embodiment of the information recording medium of the present invention, the information recording medium has a structure in which data recording is performed based on a 16-bit code word obtained by converting input 8-bit data by a conversion process based on a conversion table. It is characterized by that.

  Furthermore, in one embodiment of the information recording medium of the present invention, the additional data is at least one of encryption key information, encryption key generation information, content reproduction control information, and content copy control information of content stored in the information recording medium. It is the structure information of this information.

Furthermore, the fourth aspect of the present invention provides
It is an information recording processing method that selects one synchronization code from a primary synchronization code and a secondary synchronization code set with different synchronization codes, and executes data recording processing based on a synchronization frame set with a selected synchronization code,
In the additional data recording process,
a. Configuration bit value of additional data,
b. The state of the data area in the synchronization frame including the additional data recording area;
A. b. A condition identification step for identifying two conditions;
Based on the identification result in the condition identification step, a synchronization code determination step for determining which of the primary synchronization code or the secondary synchronization code is selected as the synchronization code to be set in the synchronization frame;
A data recording step of generating an additional data configuration bit storage frame in which the determined synchronization code is set and executing an additional data recording process;
An information recording processing method characterized by comprising:

Furthermore, in one embodiment of the information recording processing method of the present invention, the state of the data area in the synchronization frame including the additional data recording area is such that the parity of the data area including the additional data recording area is immediately after the synchronization code in the synchronization frame. The condition identification step is an even number or odd number state.
a. Whether the configuration bit value of the additional data is 0 or 1, and
b. Whether the parity is even or odd,
A. b. It is a step for identifying two conditions.

  Furthermore, in one embodiment of the information recording processing method of the present invention, in the synchronization code determination step, the number of bits [1] included in each synchronization code of the primary synchronization code and the secondary synchronization code is even and odd, that is, different. It is a step of executing a selection process of either a primary synchronization code or a secondary synchronization code from a combination of synchronization codes having a parity.

  Furthermore, in one embodiment of the information recording processing method of the present invention, the additional data is at least one of content encryption key information, encryption key generation information, content reproduction control information, and content copy control information stored in the information recording medium. It is characterized in that it is set as configuration information of such information.

  Furthermore, in an embodiment of the information recording processing method of the present invention, the storage position of the constituent bits of the additional data is set in a reserved field in a data frame generated in the data modulation process.

  Furthermore, in one embodiment of the information recording processing method of the present invention, the information recording processing method converts input 8-bit data into a 16-bit code word by a conversion process based on a conversion table, and based on the 16-bit code word. The recording data to be executed in the data recording process and set in the recording area of the additional data is recording data based on a 16-bit code word converted based on the conversion table.

  Furthermore, in one embodiment of the information recording processing method of the present invention, the conversion processing based on the code word selection is configured to be executed as data conversion processing satisfying RLL (2, 10) as a run length rule. Features.

Furthermore, the fifth aspect of the present invention provides
An information reproduction processing method for executing reproduction processing of information stored in an information recording medium,
A state calculation step for executing a recording data state calculation process in a recording data area including at least a recording area of additional data from a synchronization code;
Based on the state acquired in the state calculation step, an additional data information acquisition step for executing an acquisition process of additional data configuration bit information as recording information stored in the recording area of the additional data;
An information reproduction processing method characterized by comprising:

  Furthermore, in one embodiment of the information reproduction processing method of the present invention, the state calculated in the state calculating step is that the synchronization code set in the synchronization frame including the additional data recording area is a primary synchronization code or a secondary synchronization code. Depending on whether it is, it is in a state that becomes a different value.

  Furthermore, in an embodiment of the information reproduction processing method of the present invention, the state calculated in the state calculation step is a parity in a recording data area including a recording area of additional data from a synchronization code, and in the additional data information acquisition step Is characterized in that, based on the state of whether the parity is an even number or an odd number, identification processing of whether the constituent bit value of the additional data is 0 or 1 is executed.

  Furthermore, in an embodiment of the information reproduction processing method of the present invention, the information reproduction processing method further includes: encryption key information of content stored in the information recording medium based on acquisition of additional data configuration bit information, encryption The method includes a step of executing processing for generating at least one of key generation information, content reproduction control information, and content copy control information.

Furthermore, the sixth aspect of the present invention provides
A computer program that selects one synchronization code from a primary synchronization code and a secondary synchronization code set with different synchronization codes, and executes data recording processing based on a synchronization frame set with a selected synchronization code,
In the additional data recording process,
a. Configuration bit value of additional data,
b. The state of the data area in the synchronization frame including the additional data recording area;
A. b. A condition identification step for identifying two conditions;
Based on the identification result in the condition identification step, a synchronization code determination step for determining which of the primary synchronization code or the secondary synchronization code is selected as the synchronization code to be set in the synchronization frame;
A data recording step of generating an additional data configuration bit storage frame in which the determined synchronization code is set and executing an additional data recording process;
There is a computer program characterized by comprising:

Furthermore, the seventh aspect of the present invention provides
A computer program for executing reproduction processing of information stored in an information recording medium;
A state calculation step for executing a recording data state calculation process in a recording data area including at least a recording area of additional data from a synchronization code;
Based on the state acquired in the state calculation step, an additional data information acquisition step for executing an acquisition process of additional data configuration bit information as recording information stored in the recording area of the additional data;
There is a computer program characterized by comprising:

  The computer program of the present invention is, for example, a storage medium or communication medium provided in a computer-readable format to a computer system capable of executing various program codes, such as a CD, FD, or MO. It is a computer program that can be provided by a recording medium or a communication medium such as a network. By providing such a program in a computer-readable format, processing corresponding to the program is realized on the computer system.

  Other objects, features, and advantages of the present invention will become apparent from a more detailed description based on embodiments of the present invention described later and the accompanying drawings. In this specification, the system is a logical set configuration of a plurality of devices, and is not limited to one in which the devices of each configuration are in the same casing.

  According to the configuration of the present invention, when additional information such as key information, key generation information, content reproduction control information, and copy control information applied to recording of additional data on an information recording medium, for example, content decryption processing is recorded, A data area including an additional data recording area from the synchronization code during reproduction by selecting and setting the synchronization code from the primary synchronization code or the secondary synchronization code according to the configuration bit information [0] or [1] of the additional data The additional configuration bit information [0] or [1] can be acquired by calculating the state value, for example, parity, for example, key information, key generation information, or content reproduction control information applied to the content decryption process. In this configuration, additional information such as copy control information is embedded in a difficult-to-analyze manner and is reliably read during playback. It is.

  According to the configuration of the present invention, for example, in the additional data recording process, the parity value based on the data area of the synchronization frame into which the additional data is inserted is calculated, and the parity value and the bit value information of the additional data, [0] Alternatively, based on [1], the configuration code [0] or [1] of the additional data is recorded only by selecting and setting the synchronization code in the synchronization frame storing the additional data from the primary synchronization code or the secondary synchronization code. It becomes possible. At the time of reproduction, additional information can be acquired only by detecting the parity.

Details of an information recording processing device, an information reproduction processing device, an information recording medium and method, and a computer program according to the present invention will be described below with reference to the drawings. The description will be made according to the following items.
1. 1. Overview of data recording process 2. Conversion processing based on the conversion table 3. Select sync code 4. Data recording processing sequence Additional data storage configuration 6. 6. Data recording processing sequence with storage of additional data 7. Data recording processing device configuration 8. Data reproduction processing apparatus and reproduction sequence Specific sequence for recording / reproducing additional information

[1. Overview of data recording]
First, a digital data recording processing configuration for a high-density information recording medium such as a DVD (Digital Versatile Disc) will be described.

FIG. 1 is a diagram for explaining a digital data recording processing procedure for a high-density information recording medium such as a DVD (Digital Versatile Disc). As shown in FIG. 1, digital data constituting original content such as video content input from a host is as shown in FIG.
a. Data frame 101
b. Scramble frame 102
c. ECC block 103
d. 16 recording frames 104
e. Modulation processing & NRZI conversion data 105
f. 16 physical sectors 106
g. Recording unit 107
The data is converted in this order and stored in the information recording medium 110.

  The data frame 101 has a data configuration shown in FIG. 2, for example. The data frame 101 shown in FIG. 2 shows an example of the DVD + RW format. A 4-byte data frame ID, a 2-byte IED as an ID error detection code, a 2048-byte main data (input content data) after a 6-byte reserved field, and a 4-byte error detection code ( EDC) is stored.

  Further, as shown in FIG. 1, the data frame 101 is scrambled to generate a scramble frame 102. A bit shift process or the like is performed on the 2048-byte main data frame of the data frame 101 to generate a scramble frame 102.

  Further, as shown in FIG. 1, an ECC block 103 is generated based on the scramble frame 102. The ECC frame 103 has a configuration as shown in FIG. A data area of 192 rows (row) in which one row is 172 byte data, and parity data PI and PO are added. Each byte data is B0,0 to B207,181 as Bi, j, B0,0 to B191,171 are scrambled frames, and the others are parity data.

  Further, as shown in FIG. 1, 16 recording frames 104 are generated based on the ECC block 103. The 16 recording frames 104 are generated by interleaving processing for the ECC block 103. As shown in FIG. 4, the 16 recording frames 104 are composed of 13 rows of recording frames 0 to 15 set as 182 bytes per row.

  Each recording frame is configured as a combination of a scramble frame and parity data. In this manner, 16 recording frames 104 are generated by recording frames 0 to 15 in which 192 bytes × 13 rows are set as a frame unit.

  Further, as shown in FIG. 1, the 16 recording frames 104 are subjected to modulation processing and NRZI (Non Return to Zero Inverted) conversion processing, and modulation processing and NRZI conversion data 105 are generated. That is, 8 bits of each recording frame are converted into a 16-bit code word, and an NRZI conversion pulse based on the 16-bit code word is generated.

  FIG. 5 shows an apparatus configuration for executing modulation processing and NRZI (Non Return to Zero Inverted) conversion processing. First, 8 bits sequentially input from the 16 recording frames 104 are converted into 16-bit code words by the modulation processing means 151.

  In the process of converting from 8 bits to 16 bits, conversion is performed in accordance with the run length restriction of RLL (2, 10) in which the continuous [0] is in the range of a minimum of two and a maximum of ten. . In this conversion process, a conversion table is used. A specific use example of the conversion table will be described later.

  The 16-bit code word output from the modulation processing unit 151 is input to a configuration including an NRZ conversion unit 152, an exclusive OR unit (XOR) 153, and a delay unit 154. FIG. 5A shows a 16-bit code word, FIG. 5B shows an output signal from the NRZ conversion unit 152, and FIG. 5C shows an NRZI conversion pulse that is a final output.

  As shown in FIG. 1, a physical sector 106 is configured based on the NRZI conversion pulse.

  The physical sector 106 has the configuration shown in FIG. Each row has two sync frames, and one sync frame is composed of a sync code of 32 channel bits and 1456 channel bits. 1456 channel bits correspond to 91 × 8 bits of data in the recording frame.

  The 32-channel bit synchronization code set in each sync frame is set to a code selected from a synchronization code table storing a plurality of synchronization codes (SY0 to SY7). . The configuration of the sync code table and the sync code selection method will be described later.

  Next, as shown in FIG. 1, a recording unit (RUN) 107 is configured based on the physical sector 106 and recorded on the recording medium 110.

  Data recording on the recording medium 110 is performed by forming pits or marks on the recording medium based on the NRZI converted signal. For example, a pit row is formed in a spiral shape or a concentric shape to form a track.

[2. Conversion processing based on conversion table]
As described above, in the modulation process and the data conversion from the 16 recording frame 104 shown in FIG. 1 to the NRZI converted data 105, a process of converting 8 bits of each recording frame into a 16-bit code word is performed.

A conversion table is used for this conversion process. The conversion table contains
Main conversion table,
There are two sub-conversion tables. In each conversion process, one of the tables is selected, and a 16-bit code word is acquired based on the selection table.

  The configuration of the main conversion table is shown in FIG. 7, and the configuration of the sub conversion table is shown in FIG. The main conversion table is associated with input 8 bits [00000000] to [11111111], that is, 16-bit code words corresponding to 0 to 255, and the sub-conversion table is 16-bit code only for the range of input 8 bits from 0 to 87. It is configured as a table associated with words.

  As shown in FIGS. 7 and 8, both the main conversion table and the sub conversion table have four states 1 to 4, and a different 16-bit code word is set depending on the state, and the next state is determined. It has a configuration.

That is, when performing the process of converting 8 bits of each recording frame into a 16-bit codeword,
(1) Which of the main conversion table and the sub conversion table is applied,
(2) State 1 to 4
And a data conversion process for selecting a code word as one modulation data from one of the conversion tables is executed.

  The process of converting 8 bits of each recording frame into a 16-bit code word is executed based on the configuration shown in FIG.

  The conversion means 210 stores a main conversion table 211 and a sub-conversion table 212, and is converted data. The 8-bit B (t) of each recording frame and the state setting value S (t) determined based on the previous code word are input.

  The conversion unit 210 determines a state to be applied in the main conversion table 211 or the sub conversion table 212 based on the input state setting value S (t), and a 16-bit code word X (t) as the determined table storage value. The next state S (t + 1) determined based on the table is fed back to the conversion unit 210 via the delay unit 220. By repeatedly executing these processes, a process of converting 8 bits of each recording frame into a 16-bit code word is performed.

  As shown in FIG. 7 and FIG. 8, if the code word to be output is determined, the next state is also determined. This is because the continuous [0] has a minimum of two ranges and a maximum of ten ranges. In order to execute the conversion according to the run length restriction of RLL (2, 10), it is possible to select code words from a plurality of candidates.

  The relationship shown in FIG. 10 exists between the next state S (t + 1), the current codeword X (t), and the next codeword X (t + 1).

That is,
a. If the end [0] of the end of the current codeword is 0 to 1 and the next state is state 1, the next codeword has 2 to 9 [0] (leading ZERO) at the beginning of the codeword. It becomes.
b. When the current codeword end [0] is 2 to 5 and the next state is state 2, the next codeword has 1 to 5 [0] (leading ZERO) at the beginning of the codeword. , And X ₁₅ (t + 1), X ₃ (t + 1) = 0,0. X ₁₅ is the most significant bit (msb) of the code word, and X ₀ is the least significant bit (lsb) of the code word.
c. When the current codeword end [0] is 2 to 5 and the next state is state 3, the next codeword has 0 [leading ZERO] at the beginning of the codeword 0 to 5 And X ₁₅ (t + 1), X ₃ (t + 1) ≠ 0,0.
d. When the current codeword end [0] is 6-9 and the next state is state 4, the next codeword has the codeword head [1] or continuous [0] (leading ZERO) 1.

  In the relationship described above, the state is determined, and conversion is performed according to the run length restriction of RLL (2, 10) in which the continuous [0] is in the range of a minimum of two and a maximum of ten.

  Furthermore, as described above, in the conversion process, it is necessary to determine whether to perform conversion based on the main conversion table (see FIG. 7) or based on the sub conversion table (see FIG. 8). Become.

  Which of the main conversion table and the sub conversion table is applied is based on the principle of selecting a code with a smaller DSV (Digital Sum Value) as an index of DC balance of the NRZI pulse. .

  Specifically, the bit [0] of the recording bit sequence (NRZI conversion signal) is set to “−1”, the bit [1] is set to “+1”, and the accumulated value is set as DSV, and the deviation from 0 of DSV is further reduced. A codeword that can be selected is selected from the main conversion table or the sub-conversion table. That is, the DSV when the 16-bit conversion code word of each of the main conversion table and the sub conversion table is selected is compared, and the code word that has a smaller absolute value, that is, a DSV close to 0 is selected.

  However, since the sub-conversion table stores only the conversion codeword when the converted 8-bit data is in the range of 0 to 87, only when the converted 8-bit data is in the range of 0 to 87, Whether to apply the main conversion table or the sub conversion table is determined based on the DSV comparison. When the converted 8-bit data is in the range of 88 to 255 except for the data area, only the main conversion table is applied without comparing DSVs. However, even in the range from 88 to 255, if the state is 1, 4 and the code satisfies RLL (2, 10), the code of state 1 can be replaced with the code of state 4 or state 4 can be replaced with the code of state 1. I can do it. Therefore, DSV comparison may be performed.

  As described above, in the modulation process and the data conversion from the 16 recording frame 104 shown in FIG. 1 to the NRZI conversion data 105, a process of converting 8 bits of each recording frame into a 16-bit code word is performed. Based on the DSV comparison, the main conversion table and sub conversion table are selected, and the state is determined to perform conversion according to the run length restriction of RLL (2, 10). Conversion will be performed.

[3. Select Sync Code]
Conversion to a 16-bit code word is performed based on the above-described processing, and an NRZI conversion pulse (see FIG. 5) is generated based on the 16-bit code word. Based on the NRZI conversion pulse, the 16 physical sectors 106 in FIG. Is generated.

  As described above with reference to FIG. 6, the 16 physical sectors have two sync frames in each row, and one sync frame includes a 32-bit sync code and 1456 channel bits. Consists of. 1456 channel bits correspond to 91 × 8 bits of data in the recording frame.

  As shown in FIG. 6, in each sync frame, it is determined in advance which of the sync codes SY0 to SY7 is set, and the sync code is selected from the sync code table. And set.

  The synchronization code table has a configuration as shown in FIG. That is, different synchronization (sync) codes SY0 to SY7 are set depending on the correspondence between the current state and the next state, and further, either the primary synchronization (sync) code or the secondary synchronization (sync) code is selected.

  States 1 to 4 are state values determined during the conversion process based on the conversion table described above, and the upper or lower table of FIG. 11 is selected according to this state.

  Further, whether the primary synchronization (sync) code or the secondary synchronization (sync) code is selected is determined by the DSV as an index of the DC balance of the NRZI pulse, as in the main conversion table and sub conversion table selection processes described above. The principle of selecting a synchronization (sync) code is applied so that (Digital Sum Value) becomes smaller. A value obtained by accumulating the bit [0] of the recording bit sequence (NRZI conversion signal) as “−1” and the bit [1] as “+1” is defined as DSV, and synchronization in which the deviation from 0 of DSV can be further reduced ( The sync code is selected from the primary sync (sync) code or the secondary sync (sync) code. That is, the DSV when the synchronization code of the primary synchronization (sync) code and the secondary synchronization (sync) code is selected is compared, and synchronization with which a DSV having a smaller absolute value, that is, close to 0 is obtained ( Sync code is selected.

[4. Data recording processing sequence]
As described above, in the data recording process for the information recording medium, as shown in FIG.
a. Data frame 101
b. Scramble frame 102
c. ECC block 103
d. 16 recording frames 104
e. Modulation processing & NRZI conversion data 105
f. 16 physical sectors 106
g. Recording unit 107
The data is converted in this order and stored in the information recording medium 110.

  However, as described above, in actuality, it is necessary to determine which of the main conversion table and the sub conversion table is selected based on the DSV in the generation of the modulation processing & NRZI conversion data. It is necessary to determine the selection of the sync code based on DSV. Therefore, the above-described data conversions a to g are not necessarily executed as one sequence, but a plurality of data conversion streams are generated, and each DSV is compared to obtain a good DSV, that is, a stream having a DSV closer to 0. Processing such as selection is performed.

  An example of a sync frame generation processing sequence will be described with reference to FIG. The sync frame generation processing sequence shown in FIG. 12 shows an example of processing in DVD + RW.

Note that the principle of sync frame generation processing in DVD + RW is that, as two different data streams, stream 1 in which a primary sync code is set and stream 2 in which a secondary sync code is set are generated, and DSV comparison is performed on the generated streams. And select the stream with the lower DSV and copy it to the other,
(1) When the input data is from 00 to 87, the main conversion table value is added to stream 1, and the sub conversion table value is added to stream 2.
(2) If the input data is 88 to 255 and the state is 1 or 4, if the continuation state is 1, even if it is replaced with 4, the code satisfies the specified run length rule, for example, RLL (2, 10) , Added to the stream 2, and the code of the state 1 is added to the stream 1. Finally, if the recording frame does not satisfy −64 <DSV <+63 (in the case of DVD + RW), the synchronization code is replaced. If | DSV | Note that DVD-ROM, DVD-RW, DVD-RAM, and the like perform processing by determining whether -65 <DSV <+64.

  A sync frame generation process is executed under the above principle. The sync frame generation processing sequence shown in FIG. 12 is a sequence that outlines the processing related to the present invention during the processing based on the above principle. The actual processing sequence is different depending on the DVD + RW, DVD-ROM, DVD-RW, DVD-RAM, etc.

  Hereinafter, each step of the processing sequence illustrated in FIG. 12 will be described. First, in step S101, a primary sync code and a secondary sync code are additionally set for a generated data stream (sync frame). If there is no generated data stream (sync frame), a new data stream is generated. That is, two streams are generated: a stream 1 with a primary sync code set and a stream 2 with a secondary sync code set.

  As described with reference to FIG. 6, one of the sync codes SY0 to SY7 is determined in advance according to the data 1, and any one of the sync codes SY0 and SY7 is the sync code table shown in FIG. Then, the primary sync code and the secondary sync code are selected, and two set streams are generated.

  In step S102, data to be converted is input. In step S103, it is determined whether or not the input data requires DSV comparison processing. That is, as understood from the configuration of the main conversion table and the sub-conversion table shown in FIGS. 7 and 8, when converting 8-bit data into a 16-bit code word, when the input data is 0 to 87, the main It is necessary to determine whether to apply the conversion table or the sub-conversion table based on the DSV comparison. However, when the input data is 88 to 255, only the main conversion table is applied. , DSV comparison processing is unnecessary. However, even if the input data is 88 to 255, if the next state 1 or 4 is set, the code word of state 1 or state 4 in the main conversion table is determined based on the DSV comparison. However, it is a requirement to satisfy the RLL rule.

  When data that does not require DSV comparison is input, in step S104, a 16-bit codeword is selected based on the main conversion table, added to each stream, and stream 1 and stream 2 are generated, respectively. As described above, in the code word selection process, the state value is taken into consideration, and the code word according to the RLL (2, 10) rule is selected.

  On the other hand, if data requiring DSV comparison is input, the process proceeds to step S105, where the input data is converted into two different code words. That is, conversion based on the main conversion table or the sub-conversion table, or conversion according to the states 1 or 4.

  Next, in step S106, | DSV | comparison between the current stream 1 and the current stream 2 is performed, and a stream having a low | DSV | is selected. In step S107, the selected stream is changed to the two different ones generated in step S105. One of the codewords is set, and the other codeword is set in the non-selected stream.

  In step S108, the end of the sync frame is confirmed. If the sync frame has not been completed, the process returns to step S102, and the same processing is executed for the next input data.

  When stream 1 and stream 2 are generated for all sync frames, in step S109, | DSV | comparison between stream 1 and stream 2 is executed, and a stream with a small | DSV | is selected. Next, in step S110, it is determined whether or not the DSV value of the selected stream is in a range of −64 <DSV <+63.

  If −64 <DSV <+63 is satisfied, it is determined in step S112 whether there is still a bit to be converted that needs to be converted in the input data, that is, the code word. If there is processing data, step S101 is determined. The following process is repeated.

  If it is determined in step S110 that −64 <DSV <+63 is not satisfied, the process proceeds to step S111, where the currently selected sync code (primary or secondary) is replaced with the other, and the current stream is replaced with the stream. | DSV | comparison is performed, and a stream having a small | DSV | is selected. Further, it is determined in step S112 whether there is unprocessed data. If there is unprocessed data, the processes in and after step S101 are repeatedly executed.

  In step S112, the determination is made that there is no unprocessed data, and the processing ends, that is, the generation processing of the physical sector 106 (see FIG. 6) shown in FIG.

The process described above
(1) Selection of main conversion code and sub-conversion code (2) Selection of primary sync code and secondary sync code is executed according to the principle of decreasing the value of | DSV |. The code conversion satisfying the RLL (2, 10) criterion is realized by setting and selecting the above.

[5. Additional data storage configuration]
Next, in the configuration in which data recording is performed by the above-described process, for example, additional information such as key information applied to encryption / decryption of recorded content, key generation information, content copy control information, content reproduction control information, or the like. A structure to be embedded will be described.

  In the present invention, control is performed as to whether the primary synchronization (sync) code or the secondary synchronization (sync) code is applied as the synchronization (sync) code in accordance with the configuration bit information of the additional data.

  During playback, the data state in the data area from the synchronization (sync) code to the additional data storage area, for example, the parity in the data area from the synchronization (sync) code to the additional data storage area is calculated, and according to the calculated parity Thus, it is possible to determine whether the additional data configuration bit value is [0] or [1].

At the time of recording additional data, for example, a synchronization (sync) code selection criterion as shown in FIG. That is, when calculating the parity in the preceding data area where the additional data is inserted, that is, in the data area from the synchronization (sync) code in the sync frame to the data immediately before the position where the additional data is inserted, and the parity is an even number,
a. When the bit value of the additional data is [0], the set synchronization (sync) code is maintained as it is, and the synchronization (sync) code is not changed (replaced).
b. When the bit value of the additional data is [1], a change (replacement) of the set synchronization (sync) code is executed.

  The change (replacement) of the synchronization (sync) code is a change from the primary synchronization (sync) code to the secondary synchronization (sync) code, or a change from the secondary synchronization (sync) code to the primary synchronization (sync) code. means.

Further, when the parity in the data area from the synchronization (sync) code in the sync frame to the data immediately before the position where the additional data is inserted is an odd number,
c. When the bit value of the additional data is [0], change (replacement) of the set sync code is executed.
d. When the bit value of the additional data is [1], the set synchronization (sync) code is maintained as it is, and the synchronization (sync) code is not changed (replaced).

  As described above with reference to FIG. 7, the sync code set in the sync frame (see FIG. 6) is selected from the primary sync code or the secondary sync code. In the synchronization (sync) code selection process when recording general data, as described above, the DSVs in the streams in which the respective sync codes are set are compared, and the one that can obtain a smaller | DSV | is selected. To do.

  That is, in the same way as the selection process of the main conversion table and the sub conversion table described above, the synchronization (sync) code is set so that the DSV (Digital Sum Value) as an index of DC balance of the NRZI pulse becomes smaller. The principle of choosing applies. A value obtained by accumulating the bit [0] of the recording bit sequence (NRZI conversion signal) as “−1” and the bit [1] as “+1” is defined as DSV, and synchronization in which the deviation from 0 of DSV can be further reduced ( The sync code is selected from the primary sync (sync) code or the secondary sync (sync) code. That is, the DSV when the synchronization code of the primary synchronization (sync) code and the secondary synchronization (sync) code is selected is compared, and synchronization with which a DSV having a smaller absolute value, that is, close to 0 is obtained ( Sync code is selected.

  The primary (sync) code and the secondary sync (sync) code are both 32-channel bit codes as understood by comparing the respective codes in FIG. That is, in each set of primary (sync) code and secondary (sync) code in SY0 to SY7, the number of [1] included in each code is an even number for the primary sync (sync) code and an odd number for the secondary (sync) code. It is set as a related code configuration.

  That is, in any case of SYn (n = 0 to 7), for example, the number of [1] included in the primary (sync) code is an even number, and the number of [1] included in the secondary (sync) code is an odd number. It has become.

  As a result, by performing the sync code setting process applying the sync code selection criteria shown in FIG. 13, the data in the data area from the sync code to the additional data storage area is reproduced during playback. The parity in the data area from the state, that is, the synchronization (sync) code to the additional data storage area is calculated, and whether the additional data configuration bit value is [0] or [1] according to the calculated parity Discrimination becomes possible.

  The fact that the parity in a certain data area is an even number corresponds to the cumulative value of the number of 1 included in the concatenated data of the sync (synchronization) code and code word included in the data area being an even number. The fact that the parity in a certain data area is an odd number corresponds to the cumulative value of the number of 1 included in the concatenated data of the sync (synchronization) code and code word included in the data area being an odd number.

  In the following, an example is shown in which parity information is used as the state value of the data area including the additional data insertion position, but various other detectable state values can be applied as the state value of the data area. is there.

  As described above, according to the additional information storage configuration of the present invention, whether the configuration bit of the additional information is [0] just by calculating the total parity including the additional data insertion position from the synchronization (sync) code in the playback device. ] Can be determined.

  If the additional information is n bits, at least n additional data insertion positions are set, and these bits are concatenated to generate additional information, that is, content encryption key generation information and content reproduction control information. . In view of reading errors and the like, it is desirable to record the additional information repeatedly.

  A specific example of inserting additional data will be described with reference to FIGS. FIG. 14 and FIG. 15 both show a processing example in the case where the configuration bit [0] of the additional information is stored.

  FIG. 14 shows primary synchronization in normal modulation processing, that is, synchronization (sync) code setting processing according to the processing sequence described above with reference to FIG. 12, that is, synchronization (sync) code setting processing based on DSV. FIG. 15 shows an example in which [0] is set as the additional data bit when the (sync) code is set. FIG. 15 shows the secondary sync (sync) code in the sync (sync) code setting process based on the DSV. When set, an example in which [0] is set as the additional data bit is shown.

  First, referring to FIG. 14, the primary synchronization (sync) code is set in the DSV-based synchronization (sync) code setting process, and data up to the additional data storage area in the data area below the primary synchronization (sync) code. A process in the case where [0] is set as the additional data bit when the parity in the area section is an odd parity will be described.

  FIG. 14A1 shows data before modulation, and FIG. 14A2 shows a normal modulation data configuration generated by a sync (sync) code setting process based on DSV. In (a2), a primary synchronization (sync) code is set as a synchronization (sync) code, and the parity in the data area section up to the additional data storage area in the data area below the primary synchronization (sync) code is an odd parity It is an example. The primary synchronization (sync) code has an even number of [1] included in the code, that is, even parity. In this case, the total parity of the total area from the primary synchronization (sync) code to the additional data storage area is an odd number.

  The normal modulation data structure shown in (a2) corresponds to the case of c in FIG. That is, the total parity of the total area from the primary synchronization (sync) code to the additional data storage area is an odd number, and the additional data bit is [0].

  Therefore, a change process from the primary synchronization (sync) code to the secondary synchronization (sync) code is performed, and additional information setting modulation data as shown in FIG. 14 (a3) is generated. The secondary synchronization (sync) code has an odd number of [1] included in the code, that is, an odd parity. As a result, the total parity of the total area from the secondary synchronization (sync) code to the additional data storage area is changed to an even number.

  In a reproducing apparatus that reads additional data, the total parity of the total area from the secondary synchronization (sync) code to the additional data storage area is calculated, and is detected as an even number. ].

  Next, referring to FIG. 15, in the sync (sync) code setting process based on DSV, a secondary sync (sync) code is set, and in the data area below the secondary sync (sync) code, up to the additional data storage area A process in the case where [0] is set as the additional data bit when the parity in the data area section is even parity will be described.

  FIG. 15B1 shows data before modulation, and FIG. 15B2 shows a normal modulation data configuration generated by a sync (sync) code setting process based on DSV. In (b2), the secondary synchronization (sync) code is set as the synchronization (sync) code, and the parity in the data area section up to the additional data storage area in the data area below the secondary synchronization (sync) code is an even parity. It is an example. The secondary synchronization (sync) code has an odd number of [1] included in the code, that is, an odd parity. In this case, the total parity of the total area from the secondary synchronization (sync) code to the additional data storage area is an odd number.

  The normal modulation data structure shown in (b2) also corresponds to the case of c in FIG. That is, the total parity of the total area from the secondary synchronization (sync) code to the additional data storage area is an odd number, and the additional data bit is [0].

  Therefore, a change process from the secondary synchronization (sync) code to the primary synchronization (sync) code is performed, and additional information setting modulation data as shown in FIG. 15 (b3) is generated. The primary synchronization (sync) code has an even number of [1] included in the code, that is, even parity. As a result, the total parity of the total area from the primary synchronization (sync) code to the additional data storage area is changed to an even number.

  In a reproducing apparatus that reads additional data, the total parity of the total area from the primary synchronization (sync) code to the additional data storage area is calculated, and is detected to be an even number. ].

  That is, when [0] is set as a component bit of the additional information, the synchronization (sync) code is set so that the total parity of the total area from the synchronization (sync) code to the additional data storage area is an even number. Conversely, when [1] is set as a component bit of the additional information, the synchronization (sync) code is set so that the total parity of the total area from the synchronization (sync) code to the additional data storage area becomes an odd number. .

  FIG. 16 is a diagram summarizing the control mode of the synchronization (sync) code according to the configuration of the normal modulation data in the case where [0] and [1] are set as the constituent bits of the additional information.

  In the setting example of FIG. 16, when [0] is set as the additional information configuration bit, the total parity of the total area from the synchronization (sync) code to the additional data storage area is set as an even number, and the additional information configuration bit is set. When [1] is set, the total parity of the total area from the synchronization (sync) code to the additional data storage area is set as an odd number. This is an example of the rule to be set, and the reverse rule can be set.

In the setting example of FIG. 16, for example, when the additional information configuration bit is [0],
(A) When the sync (sync) code based on the DSV standard is primary (even parity) (A1) After the sync (synchronize) code and when the additional data storage area is even parity, the current total parity is even and the synchronization There is no need to change the (sync) code, and the adjusted total parity is set to an even number.
(A2) After synchronization (sync) code to additional data storage area with odd parity, the current total parity is odd, the synchronization (sync) code needs to be changed, and the adjusted total parity is set to an even number .

(B) When the sync (sync) code based on the DSV standard is secondary (odd parity) (B1) After the sync (sync) code and when the additional data storage area is even parity, the current total parity is odd and the sync The (sync) code needs to be changed, and the adjusted total parity is set to an even number.
(B2) After synchronization (sync) code to additional data storage area with odd parity, the current total parity is an even number, and there is no need to change the synchronization (sync) code, and the adjusted total parity is set to an even number. .

When the additional information configuration bit is [1],
(C) When the sync (sync) code based on the DSV standard is primary (even parity) (C1) After the sync (synchronize) code and when the additional data storage area is even parity, the current total parity is even, The (sync) code needs to be changed, and the adjusted total parity is set to an odd number.
(C2) After synchronization (sync) code to additional data storage area with odd parity, the current total parity is an odd number, and there is no need to change the synchronization (sync) code, and the adjusted total parity is set to an odd number. .

(D) When the sync (sync) code based on the DSV standard is secondary (odd parity) (D1) After the sync (sync) code and when the additional data storage area is even parity, the current total parity is odd and the sync There is no need to change the (sync) code, and the adjusted total parity is set to an odd number.
(D2) After synchronization (sync) code to additional data storage area with odd parity, the current total parity is an even number, the synchronization (sync) code needs to be changed, and the adjusted total parity is set to an odd number .

  With such a configuration, a playback device that reads additional data calculates the total parity of the total area from the sync (sync) code to the additional data storage area. Is determined to be [0], and if it is an odd number, it is determined that the configuration bit information of the additional data is [1].

  For example, in the case of the DVD + RW format, the insertion position of the component bits of the additional information is set in the reserved field following the IED as the error detection code of the data frame ID and ID in the data frame shown in FIG.

  In such an additional information storage position configuration, one bit is stored in each data frame, and n-bit data stored in a plurality of data frames, for example, n data frames, are concatenated to generate encryption key generation information. In addition, additional information of n bits such as various control information can be recorded. These bit information can be acquired at the time of playback in an information processing apparatus such as a DVD playback apparatus or a PC that executes playback processing. For example, the bit information of the encrypted content is acquired based on the acquired encryption key. It is possible to perform decryption and content reproduction.

  The additional information storage position is not limited to the position shown in FIG. 17 and may be set to other positions. In FIG. 17, one bit of additional information is set in the reserve field and one additional information bit is set for one data frame. However, a plurality of additional information setting positions are set in one data frame. To embed a plurality of additional information bits.

[6. Data recording processing sequence with additional data storage]
Next, as a sequence corresponding to the sync frame generation processing sequence based on the DSV determination described above with reference to FIG. 12, the sync frame generation processing sequence for performing additional information insertion processing will be described with reference to FIG. This will be described with reference to FIG.

  The sync frame generation processing sequence shown in FIGS. 18 and 19 shows an example of processing in DVD + RW.

Note that, as described above, the principle of sync frame generation processing in DVD + RW is that two different data streams are generated by generating stream 1 in which a primary sync code is set and stream 2 in which a secondary sync code is set. In the stream, perform a DSV comparison, select the stream with the lower DSV and copy it to the other,
(1) When the input data is from 00 to 87, the main conversion table value is added to stream 1, and the sub conversion table value is added to stream 2.
(2) If the input data is 88 to 255 and the state is 1 or 4, if the continuation state is 1, even if it is replaced with 4, the code satisfies the specified run length rule, for example, RLL (2, 10) , Added to the stream 2, and the code of the state 1 is added to the stream 1. Finally, if the recording frame does not satisfy −64 <DSV <+63 (in the case of DVD + RW), the synchronization code is replaced. If | DSV | Note that DVD-ROM, DVD-RW, DVD-RAM, and the like perform processing by determining whether -65 <DSV <+64.

  A sync frame generation process is executed under the above principle. The sync frame generation processing sequence shown in FIG. 18 and FIG. 19 is a sequence describing processing related to the present invention during processing based on the above principle. The actual processing sequence is different depending on the DVD + RW, DVD-ROM, DVD-RW, DVD-RAM, etc.

  First, each step of the processing sequence shown in FIG. 18 will be described. First, in step S201, a primary sync code and a secondary sync code are additionally set for a generated data stream (sync frame). If there is no generated data stream (sync frame), a new data stream is generated. That is, two streams are generated: a stream 1 with a primary sync code set and a stream 2 with a secondary sync code set.

  As shown in FIG. 6, one of the synchronization (sync) codes SY0 to SY7 previously associated with each sync frame is set as a synchronization (sync) code for each sync frame. That is, from the synchronization code table shown in FIG. 11, a primary synchronization (sync) code, a secondary synchronization (sync) code, two synchronization codes are selected, and two synchronization codes are set. A stream (stream 1, stream 2) is generated.

  In step S202, data to be converted is input. In step S203, it is determined whether the input data requires DSV comparison processing. That is, as understood from the configuration of the main conversion table and the sub-conversion table shown in FIGS. 7 and 8, when converting 8-bit data into a 16-bit code word, when the input data is 0 to 87, the main It is necessary to determine whether to apply the conversion table or the sub-conversion table based on the DSV comparison. However, when the input data is 88 to 255, only the main conversion table is applied. , DSV comparison processing is unnecessary. However, even if the input data is 88 to 255, if the next state 1 or 4 is set, the code word of state 1 or state 4 in the main conversion table is determined based on the DSV comparison. However, it is a requirement to satisfy the RLL rule.

  When data that does not require DSV comparison is input, in step S204, a 16-bit codeword is selected based on the main conversion table, added to each stream, and stream 1 and stream 2 are generated, respectively. As described above, in the code word selection process, the state value is taken into consideration, and the code word according to the RLL (2, 10) rule is selected.

  On the other hand, if data requiring DSV comparison is input, the process proceeds to step S205, where the input data is converted into two different code words. That is, conversion based on the main conversion table or the sub-conversion table, or conversion according to the states 1 or 4.

  Next, in step S206, | DSV | comparison between the current stream 1 and the current stream 2 is performed, and a stream having a low | DSV | is selected, and in step S207, the two different streams generated in step S205 are selected. One of the codewords is set, and the other codeword is set in the non-selected stream.

  In step S208, the end of the sync frame is confirmed. If the sync frame has not been completed, the process returns to step S202, and the same processing is executed for the next input data.

  When stream 1 and stream 2 are generated for all sync frames, in step S209, | DSV | comparison between stream 1 and stream 2 is executed, and a stream with a small | DSV | is selected. Next, in step S210, it is determined whether or not the DSV value of the selected stream is in a range of −64 <DSV <+63.

  If −64 <DSV <+63 is satisfied, the process proceeds to step S212 (FIG. 19). If it is determined in step S210 that −64 <DSV <+63 is not satisfied, the process proceeds to step S211, where the currently selected sync code (primary or secondary) is replaced with the other, and the current stream is replaced with the stream. | DSV | comparison is performed, a stream having a small | DSV |

  In step S212, a sync frame including the additional data storage area is extracted. For example, as described with reference to FIG. 17, when the reserve (RSV) field following the ID and IED of the data frame is set as the additional data storage area, the sync frame storing the data corresponding to the data field To extract.

  In step S213, for the extracted sync frame, a status value, for example, parity is calculated in the data area immediately after the synchronization (sync) code to the additional data storage area, and the calculated status value (parity) and the additional data storage area are calculated. Synchronization (sync) to be set so that the correspondence with the additional data configuration bit value [0] or [1] to be set to corresponds to the rule set in advance, that is, the rule described above with reference to FIGS. ) Determine the code.

  For example, when the additional data configuration bit value to be set in the additional data storage area is [0], the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area is set to an even number. It is determined whether it is set to an odd number or an odd number, and a synchronization (sync) code to be set is determined based on the determination result.

  That is, as described above, when the additional data configuration bit value is [0], the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area is an even rule. Determines the synchronization (sync) code so that the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area is an even number.

  When the additional data configuration bit value to be set in the additional data storage area is [1], the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area is set to an even number. Is set to an odd number or an odd number, and a synchronization (sync) code to be set is determined based on the determination result.

  If the additional data component bit value is [1], if the rule is to set the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area as an odd number, the synchronization (sync) code To the additional data storage area, the synchronization (sync) code is determined so that the state value (parity) in the data area is an odd number.

  In step S214, the synchronization (sync) code determined in step S213 is set in a sync frame having an additional data storage area.

  In step S215, it is determined whether or not unprocessed input data, that is, a bit to be converted that needs to be converted into a codeword still exists, and if there is unprocessed data, the processes in and after step S201 are performed. Run repeatedly.

  In step S215, the determination is made that there is no unprocessed data, and the processing ends, that is, the generation processing of the physical sector 106 (see FIG. 6) shown in FIG. 1 ends.

  In accordance with the above-described processing, recording data into which additional information bits are inserted is generated.

[7. Data recording processing device configuration]
Next, a configuration of a data recording processing apparatus that performs processing for recording the above-described additional information together with contents (main data) such as movies and music will be described. The data recording processing apparatus described here includes a mastering apparatus as a master manufacturing apparatus called a so-called master disk, and further includes an information recording medium drive such as a DVD recording / reproducing apparatus or a PC that can be used by general users. Including the device. That is, it includes not only a master disk but also an information processing apparatus capable of writing data to various information recording media that are writable (recordable) and rewritable (rewritable).

  The configuration and processing of the data recording processing device will be described with reference to FIG. The data recording processing apparatus includes an information recording medium 301 that can record data, a pickup 302 that outputs a data recording signal to the information recording medium 301, a spindle motor 303 that drives the information recording medium 301, a control of the pickup 302 and the spindle motor 303. Servo circuit 304, additional data error correction encoding unit 305, main data error correction encoding unit 306, additional data recording area control unit 307, switch 308, EFMPlus modulation / recording unit generation circuit 309, main conversion table storage memory 310 , A sub-conversion table storage memory 311, a recording signal processing circuit 313, a primary synchronization (sync) code storage memory 321, a secondary synchronization (sync) code storage memory 322, and a synchronization (sync) code selection unit 323.

  The content data to be recorded on the information recording medium 301 is, for example, encrypted content data, and is input to the main data error correction encoding unit 306 as main data. The main data error correction encoding unit 306 An encoding process for generating and adding an error correction code such as ECC is performed.

After that, in the EFMPlus modulation / recording unit generation circuit 309, the modulation process, that is, the description with reference to FIG. Data frame 101
b. Scramble frame 102
c. ECC block 103
d. 16 recording frames 104
e. Perform modulation processing.
e. NRZI conversion data 105
f. 16 physical sectors 106
g. Recording unit (RUN) 107
Is executed in the recording signal processing circuit 313.

  On the other hand, additional data composed of various information such as encryption key information, encryption key generation information, content reproduction control information, content copy control information, and other content attribute information is input to the additional data error correction encoding unit 305. Again, for example, an encoding process for adding an error correction code such as ECC is performed.

  A bit string of additional data to which an error correction code is added is input from the additional data error correction encoding unit 305 to the sync code selection unit 323. For example, a data string such as [0, 0, 0, 1, 0, 0, 0. This bit string is a bit string including, for example, additional data of any one of encryption key information, encryption key generation information, content reproduction control information, content copy control information, and other content attribute information, and an error correction code for the additional data.

  The sync code selection unit 323 determines whether the sync code set in the sync frame is a primary sync code or a secondary sync code, and outputs a signal for controlling the switch 308 To do. That is, when the sync code set in the sync frame is the primary sync code, the control signal for setting the switch 308 on the primary sync code storage memory 321 side is output to the switch 308, and the primary The synchronization (sync) code is output to the EFMPlus modulation / recording unit generation circuit 309.

  On the other hand, when the sync code set in the sync frame is the secondary sync code, the control signal for setting the switch 308 on the secondary sync code storage memory 322 side is output to the switch 308 and the secondary The synchronization (sync) code is output to the EFMPlus modulation / recording unit generation circuit 309.

  The sync code selection unit 323 performs synchronization (synchronization) code selection based on the DSV as described above when setting the synchronization (synchronization) code of the data portion other than the additional information bit setting unit. That is, control is performed such that a synchronization (sync) code that can reduce the value of | DSV | is selected from a primary synchronization (sync) code or a secondary synchronization (sync) code. As shown in the figure, the sync code selection unit 323 receives an NRZI level signal via the recording signal processing circuit 313 as a signal for executing the DSV comparison.

  When selecting a sync code by DSV comparison, a modulated data stream in which a code of a primary sync (sync) code and a secondary sync (sync) code is set is generated, and based on an NRZI signal based on these two streams A DSV comparison will be made to perform the final selection. Therefore, the sync code selection unit 323 also outputs a control signal of the switch 308 for these processes.

  Also, the sync code selection unit 323, for a sync frame having an additional information bit setting area, shows the state values, for example, parity, in the data area from immediately after the synchronization (sync) code to the additional data storage area, as shown in FIG. As described above, the correspondence between the input state value (parity) input from the EFMPlus modulation / recording unit generation circuit 309 and the additional data configuration bit value [0] or [1] to be set in the additional data storage area is set in advance. The synchronization (sync) code to be set is determined so as to correspond to the rule described above, that is, the rule described above with reference to FIGS.

  For example, the additional data configuration bit value to be set in the additional data storage area is [0], and the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area is set to an even number. In this case, the primary synchronization (sync) code is set, and the total parity of the data area from the synchronization (sync) code to the additional data storage area is set to an even number.

  In this case, the sync code selection unit 323 outputs a control signal to the switch 308 to cause the EFMPlus modulation / recording unit generation circuit 309 to perform the primary sync (sync) code setting process, and the primary sync (sync) code is set. The data is output from the primary synchronization (sync) code storage memory 321 to the EFMPlus modulation / recording unit generation circuit 309.

  The additional data configuration bit value to be set in the additional data storage area is [0], and the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area is set to an odd number. If so, a secondary synchronization (sync) code is set, and the total parity of the data area from the synchronization (sync) code to the additional data storage area is set to an even number.

  In this case, the sync code selection unit 323 outputs a control signal to the switch 308 to cause the EFMPlus modulation / recording unit generation circuit 309 to execute the secondary sync (sync) code setting process, and the secondary sync (sync) code is set. The data is output from the secondary synchronization (sync) code storage memory 322 to the EFMPlus modulation / recording unit generation circuit 309.

  The additional data configuration bit value to be set in the additional data storage area is [1], and the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area is set to an even number. If so, a secondary synchronization (sync) code is set, and the total parity of the data area from the synchronization (sync) code to the additional data storage area is set to an odd number.

  In this case, the sync code selection unit 323 outputs a control signal to the switch 308 to cause the EFMPlus modulation / recording unit generation circuit 309 to execute the secondary sync (sync) code setting process, and the secondary sync (sync) code is set. The data is output from the secondary synchronization (sync) code storage memory 322 to the EFMPlus modulation / recording unit generation circuit 309.

  Further, the additional data configuration bit value to be set in the additional data storage area is [1], and the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area is set to an odd number. If so, the primary synchronization (sync) code is set, and the total parity of the data area from the synchronization (sync) code to the additional data storage area is set to an odd number.

  In this case, the sync code selection unit 323 outputs a control signal to the switch 308 to cause the EFMPlus modulation / recording unit generation circuit 309 to perform the primary sync (sync) code setting process, and the primary sync (sync) code is set. The data is output from the primary synchronization (sync) code storage memory 321 to the EFMPlus modulation / recording unit generation circuit 309.

  The EFMPlus modulation / recording unit generation circuit 309 executes a sync code replacement process set in a sync frame including an additional data storage area in accordance with an instruction from the sync code selection unit 323.

  Area information indicating whether it is a setting area for additional information bits or a normal data part other than the setting area for additional information bits, and main data information are input from the additional data recording area control unit 307 to the sync code selection unit 323. The

As described above, the EFMPlus modulation / recording unit generation circuit 309 executes the modulation process using the sync code selected by the sync code selection process based on the DSV or the additional information bit in the sync code selection unit 323. Then, the data conversion process described with reference to FIG.
a. Data frame 101
b. Scramble frame 102
c. ECC block 103
d. 16 recording frames 104
e. Perform modulation processing.
e. NRZI conversion data 105
f. 16 physical sectors 106
g. Recording unit (RUN) 107
Is executed in the recording signal processing circuit 313.

  The recording signal processing circuit 313 outputs a recording unit (RUN: recording unit) to the pickup 302, and recording unit (RUN: recording unit) information is recorded on the information recording medium 301 under the control of the servo circuit 304.

[8. Data reproduction processing apparatus and reproduction sequence]
Next, a configuration and a playback processing sequence of a data playback processing apparatus that performs playback processing of an information recording medium storing the above-described additional information and content (main data) such as movies and music will be described.

  The configuration and processing of the data reproduction processing device will be described with reference to FIG. The data reproduction processing apparatus includes an information recording medium 401, a pickup 402 that reads data from the information recording medium 401, a spindle motor 403 that drives the information recording medium 401, a servo circuit 404 that controls the pickup 402 and the spindle motor 403, a reading RF circuit unit 405 that performs signal processing such as signal gain adjustment to generate an RF signal, synchronization detection unit 406 that extracts a synchronization signal from the RF signal, EFMPplus demodulation processing unit 407 that executes EFMPplus demodulation processing, main conversion table storage memory 408, the sub-conversion table storage memory 409, and the additional data area only, the switch 410 for outputting the read signal of the information recording medium to the additional data decoding section 412, the additional data area is detected, and the switch 410 is controlled. Additional data recording area detection unit 411, additional data decoding unit 412 that performs decoding processing of additional data, main data error correction unit 413 that performs error correction processing of main data, and additional data error correction unit that performs error correction processing of additional data 414.

  The content data stored in the information recording medium 401 is, for example, encrypted content data, and the additional data stored in the information recording medium 401 is key data applied to decryption processing of encrypted content, or key generation information, Or content reproduction control information, content copy control information, and other content attribute information.

  Data read from the information recording medium 401 via the pickup 402 is subjected to signal processing such as gain adjustment in the RF circuit unit 405 and input to the synchronization detection unit 406. The synchronization detection unit 406 detects a synchronization signal (sync) in the recording signal and outputs the detection signal to the additional data recording area control unit 411. The additional data recording area control unit 411 discriminates the recording area of the additional data based on the synchronization signal input from the synchronization detection unit 406, controls the switch 410 based on the discrimination information, and decodes the additional data. Is input to the additional data decoding unit 412 that executes the above.

  The additional data decoding unit 412 executes a decoding process for acquiring additional data based on the input modulation data. For example, the additional data has the condition described above with reference to FIGS. 13 to 16, that is, a predetermined modulation data area including the additional data storage area, that is, a data state value (synchronization (sync) code) to data state value in the additional data storage area ( (Parity) is modulation data controlled in association with the additional data constituent bits, the additional data decoding unit 412 determines a predetermined modulation data area including the additional data storage area from the input modulation data, that is, synchronization The (sync) code to additional data storage area parity is verified to determine whether the parity is even or odd. By this discrimination processing, it is identified whether the additional information bit set at the insertion position of the additional information bit is [0] or [1].

  As described above, in the reproducing apparatus, the additional information bit set at the insertion position of the additional information bit is [0] only by calculating the total parity of the data area from the synchronization (sync) code to the additional data storage area. Or [1].

  The additional data decoding unit 412 performs the same processing based on the modulation data in the area necessary for decoding the additional data input intermittently, for example, key data of n-bit information, key generation information, or content Additional data such as reproduction control information, content copy control information, and other content attribute information is acquired. As described in the description of the data recording processing apparatus, the additional data includes an error correction code such as ECC, and is output after error correction is performed in the additional data error correction unit 413.

  When the additional data is, for example, key information applied to content decryption, the output destination of the additional data is a decryption processing unit that executes content decryption processing. In the case of content reproduction control information, it becomes a reproduction control unit.

  On the other hand, general data other than the additional data is read data of the information recording medium, that is, the recording unit is output from the synchronization detecting unit to the EFMPlus demodulating unit 407, and the reverse data conversion described above with reference to FIG. Executed. That is, the data frame 101 is restored from the recording unit (RUN) 107.

  In this demodulation processing, the main conversion table stored in the main conversion table storage memory 408 and the sub conversion table stored in the sub conversion table storage memory 409 are applied, and inverse conversion of 8-bit data from the 16-bit code word is performed. Will be executed.

  Similarly to the additional data, the main data as demodulated data also includes an error correction code such as ECC, and is output after being corrected in the main data error correction unit 414.

  When the output data is, for example, encrypted content, decryption processing using an encryption key that can be generated based on key generation information output as additional data is performed, and then output via an output unit such as a display or a speaker. Is output.

  Next, a reproduction processing sequence including additional information reading will be described with reference to FIG. The process of FIG. 22 is a process executed in the reproduction processing apparatus shown in FIG.

  In step S301, an RF signal is generated based on a read signal from the information recording medium, and in step S302, EFMPlus demodulation processing is executed based on the RF signal.

In step S303, it is determined whether it is an additional information storage area. For example, as described above with reference to FIG. 17, the additional information storage area can be set as a specific data area, for example, a reserve (RSV) field in the data frame, and can be determined based on this area. . Alternatively, specific demodulated data, for example, specific 8-bit data, for example, [86] = [010110110] is configured as data to be set in the additional information storage area, and added when data [86] appears in the demodulation result. You may determine with it being an information storage area.

  If it is not the additional information storage area, error correction processing is executed in step S304 for the data after EFMPlus demodulation processing, and output as main data in step S305.

  If it is the additional information storage area, the process proceeds to step S311 and a decoding process for acquiring the additional data is executed based on the input modulation data. For example, the additional data has the condition described above with reference to FIGS. 13 to 16, that is, a predetermined modulation data area including the additional data storage area, that is, a data state value (synchronization (sync) code) to data state value in the additional data storage area ( (Parity) is modulation data controlled in association with the additional data constituent bits, the additional data decoding unit 412 determines a predetermined modulation data area including the additional data storage area from the input modulation data, that is, synchronization The (sync) code to additional data storage area parity is verified to determine whether the parity is even or odd. By this discrimination processing, it is identified whether the additional information bit set at the insertion position of the additional information bit is [0] or [1].

  In step S311, additional information bits are intermittently acquired. Further, in step S312, error correction processing is performed, and additional data is output in step S313.

[9. Specific sequence for recording / reproducing additional information]
As described above with reference to FIG. 17, the configuration bit of the additional information can be set to a specific data position, for example, a reserve field, and the specific data position can be identified and recorded and reproduced. Alternatively, the data to be set in the additional information insertion section can be set as specific data, for example, [86] data, that is, [010110110] as 8-bit data. With such a configuration, it is possible to determine that it is additional information based on the appearance of data (demodulated data) [86] = [010110110] during data recording or reproduction.

  FIG. 23 and FIG. 24 are flowcharts for concisely explaining only the additional data recording process and the additional data acquisition process during reproduction according to the present invention.

  First, the additional data recording process flow of FIG. 23 will be described. In step S401, additional data after error correction coding is input. That is, n-bit information such as encryption key information.

  In step S402, 1 bit of additional data is extracted. If it is determined in step S403 that the extracted bit is [0], in step S404, the additional data insertion position, that is, the additional data insertion position immediately after the synchronization (sync) code of the synchronization (sync) frame having the additional data insertion unit. Data state values (parity) up to are calculated.

  Here, when the additional data configuration bit value is [0], the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area is an even number, and the additional data configuration bit value is [1]. In this case, it is assumed that the rule is to set the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area as an odd number.

  Therefore, the additional data configuration bit value to be set in the additional data storage area is [0] (step S403: Yes), and the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area Is set to an even number (step S404, Yes), a primary synchronization (sync) code is set in step S406, and the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area is set. ) Is set to an even number.

  The additional data configuration bit value to be set in the additional data storage area is [0] (step S403: Yes), and the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area Is set to an odd number (step S404, No), a secondary synchronization (sync) code is set in step S407, and the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area is set. ) Is set to an odd number.

  The additional data configuration bit value to be set in the additional data storage area is [1] (step S403: No), and the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area Is set to an even number (step S405, Yes), a secondary synchronization (sync) code is set in step S407, and the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area is set. ) Is set to an odd number.

  The additional data configuration bit value to be set in the additional data storage area is [1] (step S403: No), and the parity as the state value in the data area immediately after the synchronization (sync) code to the additional data storage area Is set to an odd number (step S405, No), a primary synchronization (sync) code is set in step S406, and the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area is set. ) Is set to an odd number.

  With these processes, when the additional data configuration bit value is [0], the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area is an even number, and the additional data configuration bit value is [ 1], data setting is executed in accordance with a rule for setting the state value (parity) in the data area from the synchronization (sync) code to the additional data storage area as an odd number.

  Next, in step S408, it is determined whether or not the processing up to the last bit of the additional data has been completed. If there are unprocessed bits, the processing in step S402 and subsequent steps is repeated, and in step S408, the additional data If it is determined that the processing up to the last bit has been completed, the processing ends.

  Next, an additional data acquisition sequence executed in the data reproduction process will be described with reference to FIG.

  In step S501, an RF signal is generated based on a read signal from the information recording medium. In step S502, EFMPlus demodulation processing is executed based on the RF signal, and the data area including the additional data storage area is synchronized (sinked). ) The state value (parity) in the data area from the code to the additional data storage area is calculated.

  Note that the data area including the additional data storage area is set as a specific data area, for example, a reserve area, as described above with reference to FIG. 17, and additional data is acquired in the reserve area demodulation process. Or specific demodulated data, for example, [86] = [010110110] is preset as setting data corresponding to the additional data storage area, and the demodulated data [86] = [010110110] is obtained by demodulation. In this case, the sync frame including the data may be determined to be the data area including the additional data storage area.

  In step S502, the state value (total parity) up to the additional data storage area is calculated from the synchronization (sync) code of the data area including the additional data storage area. In step S503, it is determined whether the total parity is even or odd. .

  When it is determined that the parity is even, the process proceeds to step S504, where it is determined that [0] is set as the additional data, and when it is determined that the parity is odd, the process proceeds to step S505, where [1] ] Is set.

  Next, in step S506, it is determined whether or not the processing up to the last bit of the additional data has been completed. If there are unprocessed bits, the processing from step S502 is repeated, and in step S506, the additional data If it is determined that the processing up to the last bit has been completed, the processing ends.

  In the above-described embodiments, the example using the parity information has been mainly described. However, various other state values that can be detected can be applied as the state of the preceding data area. That is, various information other than parity can be applied as long as it is obtained from the additional data.

  The present invention has been described in detail above with reference to specific embodiments. However, it is obvious that those skilled in the art can make modifications and substitutions of the embodiments without departing from the gist of the present invention. In other words, the present invention has been disclosed in the form of exemplification, and should not be interpreted in a limited manner. In order to determine the gist of the present invention, the claims section described at the beginning should be considered.

  The series of processes described in the specification can be executed by hardware, software, or a combined configuration of both. When executing processing by software, the program recording the processing sequence is installed in a memory in a computer incorporated in dedicated hardware and executed, or the program is executed on a general-purpose computer capable of executing various processing. It can be installed and run.

  For example, the program can be recorded in advance on a hard disk or ROM (Read Only Memory) as a recording medium. Alternatively, the program is temporarily or permanently stored on a removable recording medium such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, or a semiconductor memory. It can be stored (recorded). Such a removable recording medium can be provided as so-called package software.

  The program is installed on the computer from the removable recording medium as described above, or is wirelessly transferred from the download site to the computer, or is wired to the computer via a network such as a LAN (Local Area Network) or the Internet. The computer can receive the program transferred in this manner and install it on a recording medium such as a built-in hard disk.

  Note that the various processes described in the specification are not only executed in time series according to the description, but may be executed in parallel or individually according to the processing capability of the apparatus that executes the processes or as necessary. Further, in this specification, the system is a logical set configuration of a plurality of devices, and the devices of each configuration are not limited to being in the same casing.

  As described above, according to the configuration of the present invention, additional data is recorded on the information recording medium, for example, key information, key generation information, content reproduction control information, copy control information, etc. applied to content decryption processing. When recording the additional information, the synchronization code is selected from the primary synchronization code or the secondary synchronization code and set according to the configuration bit information [0] or [1] of the additional data, so that the additional data from the synchronization code can be reproduced. The additional configuration bit information [0] or [1] can be obtained by calculating the state value of the data area including the recording area, for example, parity, for example, key information and key generation applied to the content decryption process Information or additional information such as content playback control information and copy control information is embedded in a difficult-to-analyze manner, and during playback Read indeed configuration is achieved. Therefore, for example, content that requires copyright protection is stored in a recording medium, and it is difficult to analyze additional information such as key information, key generation information, content reproduction control information, and copy control information applied to the decryption processing of the content. The present invention can be applied to an information recording processing apparatus, an information reproduction processing apparatus, and an information recording medium when it is necessary to embed in various forms.

  Further, according to the configuration of the present invention, for example, in the additional data recording process, a parity value based on the data area of the synchronization frame into which the additional data is inserted is calculated, and the parity value and the bit value information of the additional data, [ Based on [0] or [1], the configuration code [0] or [1] of the additional data can be set only by selecting and setting the synchronization code in the synchronization frame storing the additional data from the primary synchronization code or the secondary synchronization code. It becomes possible to record, and at the time of reproduction, additional information can be acquired only by detecting the parity. Therefore, for example, content that requires copyright protection is stored in a recording medium, and it is difficult to analyze additional information such as key information, key generation information, content reproduction control information, and copy control information applied to the decryption processing of the content. The present invention can be applied to an information recording processing apparatus, an information reproduction processing apparatus, and an information recording medium when it is necessary to embed in various forms.

It is a figure explaining the recording processing procedure of the digital data with respect to high-density information recording media, such as DVD (Digital Versatile Disc). It is a figure explaining the data structure of a data frame. It is a figure explaining the data structure of an ECC frame. It is a figure explaining the data structure of 16 recording frames. It is a figure which shows the apparatus structure which performs a modulation process and a NRZI (Non Return to Zero Inverted) conversion process. It is a figure explaining the data structure of a physical sector. It is a figure which shows the structure of a main conversion table. It is a figure which shows the structure of a sub conversion table. It is a figure explaining the process which converts 8 bits of a recording frame into a 16-bit code word. It is a figure explaining the relationship between next state S (t + 1), the present code word X (t), and the next code word X (t + 1). It is a figure explaining the structure of a synchronization (sync) code table. It is a flowchart explaining an example of the production | generation process sequence of a sync frame. It is a figure explaining the example of a setting structure of a synchronous (sync) code selection condition. It is a figure explaining the example of a synchronous (sync) code | symbol setting in specific insertion of additional data. It is a figure explaining the example of a synchronous (sync) code | symbol setting in specific insertion of additional data. It is a figure explaining the setting aspect of an additional data structure bit and a synchronous (sync) code | symbol. It is a figure explaining the example of a setting of a specific additional information storage position. It is a flowchart explaining the generation process sequence of the sync frame which performs the insertion process of additional information. It is a flowchart explaining the generation process sequence of the sync frame which performs the insertion process of additional information. It is a figure explaining the structure of a data recording processing apparatus, and a process. It is a figure explaining the structure of a data reproduction | regeneration processing apparatus, and a process. It is a flowchart explaining the reproduction | regeneration processing sequence containing additional information reading. It is a flowchart explaining an additional data recording process procedure. It is a flowchart explaining an additional data reproduction | regeneration processing procedure.

Explanation of symbols

101 Data Frame 102 Scramble Frame 103 ECC Block 104 16 Recording Frame 105 Modulation Processing NRZI Conversion Data 106 16 Physical Sector 107 Recording Unit (RUN)
DESCRIPTION OF SYMBOLS 110 Information recording medium 151 Modulation processing means 152 NRZ conversion means 153 Exclusive OR circuit 154 Delay means 210 Conversion means 211 Main conversion table 212 Sub conversion table 220 Delay means 301 Information recording medium 302 Pickup 303 Spindle motor 304 Servo circuit 305 Additional data error Correction encoding unit 306 Main data error correction encoding unit 307 Additional data recording area control unit 308 Switch 309 EFMPlus modulation / recording unit generation circuit 310 Main conversion table storage memory 311 Sub conversion table storage memory 313 Recording signal processing circuit 321 Primary synchronization ( Sync) code storage memory 322 Secondary synchronization (sync) code storage memory 323 Synchronization (sync) code selection unit 401 Information recording medium 402 Kkuappu 403 spindle motor 404 servo circuit 405 RF circuit unit 406 synchronization detection unit 407 EFMPlus demodulation processing unit 408 main conversion table storage memory 409 sub conversion table storage memory 410 switch 410
411 Additional data recording area detection unit 412 Additional data decoding unit 413 Main data error correction unit 414 Additional data error correction unit

Claims (29)

In the information recording processing apparatus,
A modulator for modulating data;
A signal processing unit that selects one synchronization code from a primary synchronization code and a secondary synchronization code set with different synchronization codes, adds the selected synchronization code to the modulated data, and outputs a synchronization frame;
Based on the configuration bit value of the additional data and the state of the data area in the synchronization frame including the additional data recording area in which the additional data is embedded, the synchronization code set in the synchronization frame is the primary synchronization code or the secondary synchronization code. A control unit for selecting one of them,
An information recording processing apparatus comprising: The state of the data area in the synchronization frame including the additional data recording area is a state whether the parity of the data area including the additional data recording area is even or odd immediately after the synchronization code in the synchronization frame,
The controller is
a. Whether the configuration bit value of the additional data is 0 or 1, and
b. Whether the parity is even or odd,
A. b. 2. The configuration according to claim 1, wherein the primary synchronization code or the secondary synchronization code is selected as a synchronization code to be set in the synchronization frame based on two conditions. Information recording processing device. The controller is
The number of bits [1] included in each synchronization code of the primary synchronization code and the secondary synchronization code is an even number and an odd number, that is, from a combination of synchronization codes having different parity, either a primary synchronization code or a secondary synchronization code. The information recording processing apparatus according to claim 1, wherein the synchronization code selecting process is executed. The information recording processing apparatus includes:
The additional data is
2. The configuration set as configuration information of at least one of content encryption key information, encryption key generation information, content reproduction control information, and content copy control information stored in the information recording medium. The information recording processing apparatus described in 1.   The information recording processing apparatus according to claim 1, wherein a storage position of the constituent bits of the additional data is set in a reserved field in a data frame generated in a data modulation process. The signal processing unit
The input 8-bit data is converted into a 16-bit code word by a conversion process based on a conversion table, and a data recording process based on the 16-bit code word is executed. The recording data set in the recording area of the additional data is The information recording processing apparatus according to claim 1, wherein the information recording processing apparatus is recording data based on a 16-bit codeword converted based on the conversion table.   7. The information recording processing apparatus according to claim 6, wherein the conversion process based on the code word selection is configured as a data conversion process that satisfies RLL (2, 10) as a run length rule. An information reproduction processing device that executes reproduction processing of information stored in an information recording medium,
A demodulator that performs demodulation processing of data read from the information recording medium;
Additional data configuration as recording information stored in the additional data recording area based on a result of the status calculation, at least in the recording data area including the additional data recording area from the synchronization code An additional data decoding unit that executes a bit information acquisition process;
An information reproduction processing apparatus comprising:   The state of the recording data calculated by the additional data decoding unit varies depending on whether the synchronization code set in the synchronization frame including the additional data recording area is the primary synchronization code or the secondary synchronization code. The information reproduction processing apparatus according to claim 8, wherein the information reproduction processing apparatus is in a state.   The state of the recording data calculated by the additional data decoding unit is a parity in the recording data area including the recording area of the additional data from the synchronization code. Based on whether the parity is an even number or an odd number 9. The information reproduction processing apparatus according to claim 8, wherein the information reproduction processing device is configured to execute identification processing of whether the configuration bit value of the additional data is 0 or 1. The information reproduction processing device includes:
Processing for generating at least one of content encryption key information, encryption key generation information, content reproduction control information, and content copy control information stored in the information recording medium based on the acquired additional data configuration bit information The information reproduction processing apparatus according to claim 8, wherein the information reproduction processing apparatus is configured to execute. An information recording medium storing recording data based on a synchronization frame in which one synchronization code is selected from a primary synchronization code and a secondary synchronization code in which a different synchronization code is set, and a selection synchronization code is set,
In the additional data recording area,
a. Configuration bit value of additional data,
b. The state of the data area in the synchronization frame including the additional data recording area;
A. b. An information recording medium having a configuration in which data based on an additional data configuration bit storage synchronization frame in which either a primary synchronization code or a secondary synchronization code determined based on two conditions is set is recorded. The state of the data area in the synchronization frame including the additional data recording area is a state whether the parity of the data area including the additional data recording area is even or odd immediately after the synchronization code in the synchronization frame,
In the recording area of the additional data,
a. Whether the configuration bit value of the additional data is 0 or 1, and
b. Whether the parity is even or odd,
A. b. 13. The information according to claim 12, wherein the information is recorded based on an additional data configuration bit storage synchronization frame in which either a primary synchronization code or a secondary synchronization code determined based on two conditions is set. recoding media. The information recording medium is
The primary synchronization code or the secondary synchronization code selected from the combination of the synchronization codes of the combination of the even and odd numbers of bits [1] included in the synchronization codes of the primary synchronization code and the secondary synchronization code, that is, combinations having different parity, 13. The information recording medium according to claim 12, wherein the information recording medium has a configuration in which data based on a synchronization frame in which one of the synchronization codes is set is recorded. The information recording medium is
13. The information recording medium according to claim 12, wherein the input 8-bit data is configured to record data based on a 16-bit code word converted by a conversion process based on a conversion table. The additional data is
13. The information according to claim 12, wherein the information is configuration information of at least one of encryption key information, encryption key generation information, content reproduction control information, and content copy control information of content stored in the information recording medium. recoding media. It is an information recording processing method that selects one synchronization code from a primary synchronization code and a secondary synchronization code set with different synchronization codes, and executes data recording processing based on a synchronization frame set with a selected synchronization code,
In the additional data recording process,
a. Configuration bit value of additional data,
b. The state of the data area in the synchronization frame including the additional data recording area;
A. b. A condition identification step for identifying two conditions;
Based on the identification result in the condition identification step, a synchronization code determination step for determining which of the primary synchronization code or the secondary synchronization code is selected as the synchronization code to be set in the synchronization frame;
A data recording step of generating an additional data configuration bit storage frame in which the determined synchronization code is set and executing an additional data recording process;
An information recording processing method characterized by comprising: The state of the data area in the synchronization frame including the additional data recording area is a state whether the parity of the data area including the additional data recording area is even or odd immediately after the synchronization code in the synchronization frame,
The condition identifying step includes:
a. Whether the configuration bit value of the additional data is 0 or 1, and
b. Whether the parity is even or odd,
A. b. The information recording processing method according to claim 17, wherein the information recording processing method is a step of identifying two conditions. The synchronization code determination step includes
The number of bits [1] included in each synchronization code of the primary synchronization code and the secondary synchronization code is an even number and an odd number, that is, from a combination of synchronization codes having different parity, either a primary synchronization code or a secondary synchronization code. 18. The information recording processing method according to claim 17, wherein the information recording processing is a step of executing a synchronization code selection process.   The additional data is set as configuration information of at least one of content encryption key information, encryption key generation information, content playback control information, and content copy control information stored in the information recording medium. Item 18. The information recording processing method according to Item 17.   18. The information recording processing method according to claim 17, wherein the storage position of the constituent bits of the additional data is set in a reserved field in a data frame generated in a data modulation process. The information recording processing method includes:
The input 8-bit data is converted into a 16-bit code word by a conversion process based on the conversion table, the data recording process based on the 16-bit code word is executed, and the recording data set in the additional data recording area is 18. The information recording processing method according to claim 17, wherein the data is recording data based on a 16-bit codeword converted based on a table.   23. The information recording processing method according to claim 22, wherein the conversion process based on the code word selection is configured as a data conversion process that satisfies RLL (2, 10) as a run length rule. An information reproduction processing method for executing reproduction processing of information stored in an information recording medium,
A state calculation step for executing a recording data state calculation process in a recording data area including at least a recording area of additional data from a synchronization code;
Based on the state acquired in the state calculation step, an additional data information acquisition step for executing an acquisition process of additional data configuration bit information as recording information stored in the recording area of the additional data;
An information reproduction processing method characterized by comprising:   The state calculated in the state calculating step is a state having different values depending on whether the synchronization code set in the synchronization frame including the additional data recording area is the primary synchronization code or the secondary synchronization code. 25. The information reproduction processing method according to claim 24. The state calculated in the state calculating step is a parity in a recording data area including a recording area of additional data from the synchronization code,
In the additional data information acquisition step,
25. The identification process according to claim 24, wherein identification processing is performed to determine whether the constituent bit value of the additional data is 0 or 1 based on whether the parity is an even number or an odd number. The information reproduction processing method described. The information reproduction processing method further includes:
Processing for generating at least one of encryption key information, encryption key generation information, content reproduction control information, and content copy control information of the content stored in the information recording medium based on the acquisition of the additional data configuration bit information The information reproduction processing method according to claim 24, further comprising a step of executing. A computer program that selects one synchronization code from a primary synchronization code and a secondary synchronization code set with different synchronization codes, and executes data recording processing based on a synchronization frame set with a selected synchronization code,
In the additional data recording process,
a. Configuration bit value of additional data,
b. The state of the data area in the synchronization frame including the additional data recording area;
A. b. A condition identification step for identifying two conditions;
Based on the identification result in the condition identification step, a synchronization code determination step for determining which of the primary synchronization code or the secondary synchronization code is selected as the synchronization code to be set in the synchronization frame;
A data recording step of generating an additional data configuration bit storage frame in which the determined synchronization code is set and executing an additional data recording process;
A computer program characterized by comprising: A computer program for executing reproduction processing of information stored in an information recording medium;
A state calculation step for executing a recording data state calculation process in a recording data area including at least a recording area of additional data from a synchronization code;
Based on the state acquired in the state calculation step, an additional data information acquisition step for executing an acquisition process of additional data configuration bit information as recording information stored in the recording area of the additional data;
A computer program characterized by comprising:

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