JP2005071131A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a physical security function and high information reliability. <P>SOLUTION: This semiconductor device 100 includes an insulation layer 101, a wiring pattern 102 formed at the insulation layer 101, a via hole conductor 103 which connects between the wiring patterns 102 and a semiconductor 104 which is arranged inside the insulation layer 101 and mounted on the wiring pattern 102. Bonding strength between the insulation layer 101 and the semiconductor 104 is higher than the fracture strength of the semiconductor 104. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device that is required to have high security, such as an IC card and a cryptographic module.

  In recent years, IC cards are becoming popular in place of magnetic recording cards from the viewpoint of information volume, security, and the like. A semiconductor device that encrypts data is also used for the purpose of copyright protection, personal information protection, and the like. Such a semiconductor device is provided with a security function in terms of software, and personal information and encrypted information (such as an encryption key) cannot be easily viewed.

  As an aspect of providing physical security, as a method of preventing unauthorized use of a semiconductor device, by applying a coating or a seal to the semiconductor device, if these are destroyed, it is determined that there has been unauthorized access There are an example using a method for providing a slit, and an example using a method for providing a slit as a means for breaking a connection, as described in JP-A No. 2000-90224 and JP-A No. 8-39977.

Also, in order to obtain security information (encryption information, etc.) of the semiconductor device rather than illegally using the semiconductor device, the probe electrode is pressed against the substrate wiring on which the semiconductor device is mounted, or an electromagnetic wave is generated using a loop coil. There is also a probing signal analysis technique such as monitoring the signal. As a countermeasure against such probing, for example, a memory portion and an encryption portion are manufactured on the same semiconductor device, thereby making decryption difficult.
JP 2000-90224 A JP-A-8-39977

  The method of providing a slit or the like for preventing unauthorized use of the semiconductor device may reduce the reliability of the semiconductor device itself. Furthermore, it is possible to protect the information by providing slits or attaching a seal, but it is possible to physically disable the semiconductor device itself such as a card, but as a security against unauthorized analysis of information. Does not work.

  In addition, for the purpose of analyzing the semiconductor device itself, not unauthorized use, for example, to produce the memory part and the encrypted part on the same semiconductor device as a measure against probing, the process rules such as the wiring width are different, The manufacturing cost of the semiconductor device is increased. In addition, if the encryption key information leaks out, it is necessary to redesign the entire semiconductor device. Further, basically, it has only a software security function, and it is easy to perform information analysis by probing, and there is a possibility that information is stolen.

  Therefore, the present invention aims to provide a semiconductor device having high information reliability by adding a new physical security function to the semiconductor device, making it difficult to analyze information in the device. is there.

  In the first aspect, the present invention provides an insulating layer (or an electric insulating layer), at least one surface of the insulating layer, a predetermined wiring pattern formed inside the insulating layer, and a wiring pattern connected in a predetermined manner. A via-hole conductor, and a semiconductor element disposed inside the insulating layer and connected in a predetermined manner to a wiring pattern in the insulating layer, and the adhesive strength between the insulating layer and the semiconductor element is Provided is a semiconductor device characterized by being larger than its own breaking strength.

  In this semiconductor device, the semiconductor element is built in the insulating layer, and as a result, the structure cannot be easily analyzed. In addition, since the semiconductor element is bonded to the insulating layer with an adhesive strength stronger than its breaking strength, if the semiconductor element is peeled off in order to separate the semiconductor element from the insulating layer, the semiconductor is destroyed. When the semiconductor element is destroyed in this way, the information held by the semiconductor element cannot be altered, analyzed, and the like, and as a result, no information leaks. As a result, such a semiconductor device is provided with physical security, and a semiconductor device with improved information reliability can be provided by such a structure of the present invention.

  In this specification, “the adhesive strength between the insulating layer and the semiconductor element is larger than the breaking strength of the semiconductor element itself” means that the semiconductor element is taken out from the semiconductor device by separating the semiconductor element from the insulating layer. In addition, it means that the strength relationship between the breaking strength and the adhesive strength is such that the semiconductor element is substantially broken. The breaking strength of a semiconductor is substantially lower than the original breaking strength of the material due to the influence of polishing, cutting and cracking. Recognizing that such a strength relationship should be achieved, various factors that affect the breaking strength of semiconductor elements (materials constituting the element, element shape and size, etc.), and factors that affect adhesive strength Various semiconductor devices were manufactured by changing variously (the kind and composition of the material constituting the insulating layer, the kind and composition of the resin encapsulating the semiconductor element, etc.), and these semiconductor devices were separated from the insulating layer of the semiconductor element. A person skilled in the art can appropriately manufacture a semiconductor device satisfying such a strength relationship by attempting separation and repeatedly investigating whether or not the semiconductor element is destroyed at the time of separation. Since the size and the like vary depending on the semiconductor device to be manufactured, it is difficult to set uniform conditions, but for example, measurement can be performed with reference to Japanese Industrial Standards JIS K6848-1 and K6849.

  In the second aspect, the present invention provides an insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed therein, a via-hole conductor in the insulating layer for connecting the wiring pattern in a predetermined manner, and insulation The semiconductor element is disposed inside the layer and connected in a predetermined manner to the wiring pattern in the insulating layer, and the bonding strength between the insulating layer and the semiconductor element is connected to the semiconductor element. Provided is a semiconductor device characterized in that the strength of connection with a wiring pattern is higher.

  In this semiconductor device, the semiconductor element is built in the insulating layer, and as a result, the structure cannot be easily analyzed. In addition, since the semiconductor element is bonded to the insulating layer with an adhesive strength stronger than the connection strength to the wiring pattern, if the semiconductor element is peeled off in order to separate the semiconductor element from the insulating layer, the semiconductor element and the wiring pattern The electrical connection between the two is interrupted, and the semiconductor element cannot be operated. That is, the terminal cannot be pressed against the wiring pattern on which the semiconductor element is mounted for probing. Therefore, a semiconductor device with improved information reliability can be provided by such a structure of the present invention.

  In this specification, “the adhesive strength between the insulating layer and the semiconductor element is greater than the connection strength between the semiconductor element and the wiring pattern connected thereto” means that the semiconductor element is separated from the insulating layer. Thus, when the semiconductor element is taken out from the semiconductor device, the relationship between the adhesive strength and the connection strength is such that the electrical connection relationship between the semiconductor element and the wiring pattern connected thereto is substantially destroyed. Means that. Recognizing that such a strength relationship should be achieved, various factors affecting the adhesive strength (such as the type and composition of the material constituting the insulating layer and the type and composition of the resin encapsulating the semiconductor element) can be varied. In addition, various semiconductor devices were manufactured by changing the factors affecting the connection strength (material and size used for connection, material and width of the wiring pattern, etc.), and these semiconductor devices were separated from the insulating layer of the semiconductor element. Those who are skilled in the art can appropriately select a semiconductor device satisfying such a strength relationship by attempting to separate the semiconductor device and examining whether or not the electrical connection between the semiconductor element and the wiring pattern is broken at the time of separation. Can be manufactured. Since the size and the like vary depending on the semiconductor device to be manufactured, it is difficult to set uniform conditions, but for example, measurement can be performed with reference to Japanese Industrial Standards JIS K6848-1 and K6849.

  In the third aspect, the present invention provides a first insulating layer, a predetermined wiring pattern formed on at least one surface of the first insulating layer and the first insulating layer, and a connection between the wiring patterns in a predetermined manner. The via-hole conductor and the semiconductor element disposed in the first insulating layer and connected in a predetermined manner to the wiring pattern in the first insulating layer, the semiconductor element being built in the second insulating layer Provided is a semiconductor device which is disposed inside a first insulating layer in a state where the adhesive strength between the second insulating layer and the semiconductor element is larger than the breaking strength of the semiconductor element.

  In this semiconductor device, an insulating layer containing a semiconductor element is distinguished from an insulating layer having a wiring pattern, and each insulating layer can be made of a material corresponding to its function. For example, for the second insulating layer, an appropriate material can be selected by paying attention to the adhesion to the semiconductor element, and for the first insulating layer, an appropriate material can be selected by paying attention to the formability of the wiring pattern. As a whole, a suitable semiconductor device can be obtained. The strength relationship in this semiconductor device is the same as that of the semiconductor device of the first gist, except that the insulating layer corresponds to the second insulating layer. Therefore, when the semiconductor element is peeled off from the second insulating layer, the semiconductor element is destroyed. This semiconductor device may further have the strength-related features of the first aspect described above.

  According to a fourth aspect of the present invention, in the fourth aspect, the first insulating layer, at least one surface of the first insulating layer, a predetermined wiring pattern formed inside the first insulating layer, and the wiring pattern connected in a predetermined manner in the first insulating layer The via-hole conductor and the semiconductor element disposed in the first insulating layer and connected in a predetermined manner to the wiring pattern in the first insulating layer, the semiconductor element being built in the second insulating layer The adhesive strength between the second insulating layer and the semiconductor element is higher than the connection strength between the semiconductor element and the wiring pattern connected to the semiconductor element. A semiconductor device is provided.

  Also in this semiconductor device, as in the semiconductor device of the third aspect, an insulating layer containing a semiconductor element is distinguished from an insulating layer having a wiring pattern, and each insulating layer is made of a material corresponding to its function. Can be configured. For example, for the second insulating layer, an appropriate material can be selected by paying attention to the adhesion to the semiconductor element, and for the first insulating layer, an appropriate material can be selected by paying attention to the formability of the wiring pattern. As a whole, a suitable semiconductor device can be obtained. The strength relationship in this semiconductor device is the same as that of the semiconductor device in the second aspect except that the insulating layer corresponds to the second insulating layer. Therefore, if the semiconductor element is peeled from the second insulating layer, the electrical connection between the semiconductor element and the wiring pattern is interrupted, and the semiconductor element cannot be operated. This semiconductor device may further have the strength-related features of the second aspect described above.

  In the fifth aspect, the insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed therein, a via-hole conductor in the insulating layer for connecting the wiring pattern in a predetermined manner, and the inside of the insulating layer Provided is a semiconductor device comprising a semiconductor element disposed and connected in a predetermined manner to a wiring pattern in an insulating layer, wherein the insulating layer has a residual stress greater than the breaking strength of the semiconductor element.

  In this specification, the “residual stress” is the stress remaining in the insulating layer, and when the insulating layer of the semiconductor device is intact, the insulating layer remains in the stress state. It is a force that is released when the insulating layer is mechanically damaged.

  As a result, in order to analyze the semiconductor element, if the insulating layer around the semiconductor element is removed by grinding or polishing the semiconductor device, the residual stress is released. Since it is substantially greater than strength, the semiconductor will be destroyed when the residual stress is released, adding physical security. As a result, the information of the semiconductor element is protected without being leaked. Therefore, with such a structure, a semiconductor device with improved information reliability can be provided.

  In the sixth aspect, the insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed therein, a via-hole conductor in the insulating layer for connecting the wiring pattern in a predetermined manner, and the inside of the insulating layer The semiconductor device includes a semiconductor element disposed and connected in a predetermined manner to a wiring pattern in the insulating layer, and the insulating layer has a residual stress larger than a connection strength between the semiconductor element and the wiring pattern connected thereto. A semiconductor device is provided.

  As a result, residual stress is released when an attempt is made to remove the insulating layer around the semiconductor element by scraping or polishing the semiconductor device in order to analyze the semiconductor element. Since this residual stress is greater than the connection strength between the semiconductor element and the wiring pattern, the connection between them is broken and the semiconductor element cannot be operated. That is, the terminal cannot be pressed against the wiring pattern on which the semiconductor element is mounted for probing. Therefore, such a structure can provide a semiconductor device to which physical security is added and information reliability is improved.

  Any suitable method may be used to cause the insulating layer to have residual stress. For example, a method of generating a residual stress by curing the resin of the insulating layer at a high temperature and reducing it to room temperature can be exemplified. In this case, the magnitude of the residual stress changes depending on the Tg (glass transition temperature), thermal expansion, and Young's modulus of the insulating layer. The insulating layer includes a first insulating layer that preferably at least partially surrounds the semiconductor element, and preferably has a built-in wiring pattern for mounting the semiconductor element, and a second insulating layer adjacent to the first insulating layer. In addition, the first insulating layer can have a residual stress by making the materials constituting these insulating layers have different properties (for example, thermal expansion coefficient, elastic modulus, thermal conductivity, etc.). .

  For example, in one aspect, the thermal expansion coefficient in the planar direction of the first insulating layer is configured to be greater than the thermal expansion coefficient in the planar direction of the second insulating layer. In this case, after forming the second insulating layer (which is already dimensionally stable), forming the first insulating layer adjacent to the second insulating layer by cooling after forming under heat and pressure, the first Since the insulating layer has a large coefficient of thermal expansion, the insulating layer is solidified in a state stretched by the second insulating layer, and the first insulating layer has a large residual stress, particularly in a direction normal to the extending direction of the first insulating layer. It comes to have a stress including the component.

  For example, in another aspect, the elastic modulus of the first insulating layer is configured to be larger than the elastic modulus of the second insulating layer. In this case, if the first insulating layer is formed adjacent to the second insulating layer by cooling after forming the second insulating layer and then forming under heat and pressure, the first insulating layer has a large elastic modulus, so The first insulating layer is solidified in a state of being stretched by the two insulating layers, and the first insulating layer has a residual stress, particularly a stress including a large component in the normal direction with respect to the extending direction of the first insulating layer.

The first insulating layer may contain a semiconductor element or may cover a part of the semiconductor element. When the residual stress of the first insulating layer is released, the semiconductor element or the semiconductor element The connection with the wiring pattern connected to it is broken.

In the fifth or sixth aspect, when the semiconductor element has an underfill as a part of the insulating layer between the semiconductor element and the wiring pattern on which the semiconductor element is mounted, the elastic modulus of the underfill is higher than the elastic modulus of the other part of the insulating layer. By increasing the size, the insulating layer has a residual stress as a whole. In this case, by releasing the residual stress, the mounting surface (underfill contact surface) of the semiconductor element is destroyed, and the information on the semiconductor element can be reliably destroyed.

  In a seventh aspect, the present invention provides an insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed therein, a via-hole conductor in the insulating layer for connecting the wiring pattern in a predetermined manner, and insulation A plurality of semiconductor elements disposed within the insulating layer and disposed within the insulating layer, wherein at least two of these semiconductor elements are connected in a predetermined manner by a wiring pattern in the insulating layer; A semiconductor device is provided.

  In this semiconductor device, a wiring pattern for connecting at least two semiconductor elements is built in the insulating layer, and as a result, it cannot be easily analyzed by probing or the like. With such a structure, when information or the like of some semiconductor elements is leaked, the design of the semiconductor elements can be changed, and it is not necessary to change the design of all the semiconductor elements. In addition, it is possible to provide a semiconductor device having information reliability and suitable for production, such that each semiconductor element can be shared by various devices.

  In a preferred embodiment, the wiring pattern connected to each semiconductor element is connected to the at least two semiconductor elements via via hole conductors. With this configuration, it becomes difficult to expose the connection portion between the semiconductor elements by polishing or the like, and it becomes difficult to analyze from the outside. Therefore, a semiconductor device having information reliability and suitable for production can be provided.

  In another preferred embodiment, the via hole conductor is formed around the semiconductor element. As a result, if the semiconductor element is to be exposed in order to analyze the semiconductor element, the electrical connection made by the via-hole conductor is first broken, so that it cannot be easily analyzed from the outside. Therefore, a semiconductor device having information reliability and suitable for production can be provided.

  In still another preferred embodiment of the present invention of the seventh aspect, the semiconductor device is provided between a wiring pattern connecting at least two semiconductor elements and the surface of the insulating layer (thus, inside the insulating layer), or of the wiring pattern. A shield layer is provided on the surface of the insulating layer located above. By adopting such a structure, it is possible to prevent a signal flowing through the wiring pattern from being monitored by a probe or the like from the outside. The potential of the shield layer is preferably a ground potential, whereby the potential of the shield layer is stabilized and the operation of the semiconductor or circuit is also stabilized. The shield layer may be made of any appropriate material (for example, copper foil or soft magnetic material) used for shielding.

  The semiconductor device of the present invention may be manufactured by any appropriate method. If the structure of the device as described above is known, those skilled in the art can easily select appropriate materials and methods. The semiconductor device can be manufactured.

  The semiconductor device of the present invention has a new physical security function that has not been conventionally known regardless of the gist of the semiconductor device, and it is not easy to analyze information in the device. It has information reliability.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 schematically shows an example of an embodiment of a semiconductor device of the present invention in a sectional view. In FIG. 1, the semiconductor device 100 includes an electrical insulating layer 101, wiring patterns 102 a and 102 b, a via-hole conductor 103, a semiconductor element 104, and a bump 105. In FIG. 1, an insulating layer 101 contains a semiconductor element 104, and the element 104 is electrically connected to a wiring pattern 102 a via a bump 105, and the wiring pattern 102 a is formed on the surface of the insulating layer via a via-hole conductor 103. The wiring layer 102b thus formed is electrically connected in a predetermined manner.

  The insulating layer 101 can be formed from known materials generally used in the manufacture of semiconductor devices. For example, the insulating layer 101 can be formed using an insulating resin, a mixture of a filler and an insulating resin, or the like. The insulating resin or mixture may further contain a reinforcing material such as glass cloth. As the insulating resin, a resin that exhibits electrical insulation, such as a thermosetting resin, a photocurable resin, or a thermoplastic resin, can be used. In particular, the heat resistance of the insulating layer 101 is improved by using a curable resin such as an epoxy resin, a phenol resin, or an isocyanate resin having high heat resistance.

  Insulation using PTFE (polytetrafluoroethylene) resin and other fluororesins with low dielectric loss tangent, PPO (polyphenylene oxide) resin, PPE (polyphenylene ether) resin, liquid crystal polymer and modified resins thereof By forming the layer, the high-frequency characteristics of the insulating layer are improved.

  When the insulating layer 101 is formed from a mixture of a filler and an insulating resin, by appropriately selecting the filler and the insulating resin, the thermal expansion coefficient (for example, the linear expansion coefficient), the thermal conductivity, the elastic modulus of the insulating layer 101, The dielectric constant and the like can be set to a predetermined value. In addition, the coefficient of thermal expansion can be particularly controlled by adjusting the blending ratio of the filler and the insulating resin.

  For example, alumina, magnesia, boron nitride, aluminum nitride, silicon nitride, PTFE resin (for example, Teflon), silica, or the like can be used as the filler material. By using alumina, boron nitride, aluminum nitride or the like, it becomes possible to manufacture a substrate having a higher thermal conductivity than an insulating layer made of a conventional glass-epoxy substrate, and effectively dissipates heat generated in the built-in semiconductor element 104. Can be made. Alumina also has the advantage of low cost. When silica is used, the electrical insulating layer 101 having a low dielectric constant is obtained and the specific gravity is low. Therefore, the semiconductor device is preferable for high-frequency applications such as cellular phones. Even when silicon nitride or PTFE resin is used, an electrically insulating layer having a low dielectric constant can be formed. The linear expansion coefficient can be reduced by using boron nitride.

  The insulating resin may contain a dispersant, a colorant, a coupling agent, a release agent, or the like. The filler in the insulating resin can be uniformly dispersed by the dispersant. Since the insulating layer can be colored by the colorant, the automatic recognition device can be easily used. Since the coupling agent can increase the adhesive strength between the insulating resin and the filler, the insulating property of the electrical insulating layer 101 can be improved. The release agent improves the releasability of the insulating resin from the mold, thereby improving productivity.

  The wiring pattern 102 is made of a material having electrical conductivity, and can be formed from a material generally used for manufacturing a semiconductor device. For example, a metal foil, a conductive resin composition, a lead frame processed from a metal plate, or the like can be used. When a metal foil is used, a fine wiring pattern can be easily formed by etching or the like. In particular, copper foil is preferable because it is inexpensive and has high electrical conductivity. When the conductive resin composition is used, the wiring pattern can be easily formed by screen printing or the like. When forming a wiring pattern with a lead frame, a metal with low electrical resistance and thickness can be used, and a simple manufacturing method such as fine patterning by etching or punching can be used. In another aspect, the wiring pattern may be formed by transfer using a release film. In this case, since the wiring pattern is formed on the release film, the wiring pattern can be easily handled.

  The wiring pattern 102 as described above can improve corrosion resistance and electrical conductivity by plating the surface. Also, by roughening the contact surface of the wiring pattern 102 with the insulating layer 101, the adhesion between them can be improved. It is also possible to form a coupler, a filter, etc. with a wiring pattern. In the semiconductor device of the present invention, the wiring pattern 102 may be electrically connected to the semiconductor element and / or the electronic component not only on one side but also on the other side as shown.

  The via-hole conductor 103 has a function of electrically connecting the wiring patterns 102a and 102b in a predetermined manner, and is made of, for example, a cured product of a thermosetting conductive material (so-called conductive paste), through-hole plating, or the like. . As the thermosetting conductive material, for example, a conductive resin composition in which metal particles and a thermosetting resin are mixed can be used. As the metal particles, gold, silver, copper, nickel or the like can be used. These metals are preferable because of their high conductivity, and copper is particularly preferable because of its high conductivity and low migration. Even when metal particles obtained by coating copper with silver are used, it is possible to satisfy both characteristics of low migration and high conductivity. As the thermosetting resin, for example, an epoxy resin, a phenol resin, or a cyanate resin can be used. Epoxy resins are particularly preferred because of their high heat resistance. The via-hole conductor 104 can be formed by forming a via hole in the insulating layer and then plating the inner surface thereof with through-hole plating, or by filling a conductive resin composition and curing as necessary. Thereafter, if necessary, the through hole may be filled with a filling resin, filled plating, or the like, or a combination of metal and solder may be formed. In another embodiment, the via-hole conductor 104 can be formed by forming a via hole in the insulating layer, filling the via hole with a conductive resin composition, and curing as necessary.

  The semiconductor element 104 is mounted on the wiring pattern 102a. As the semiconductor element 104, for example, an element such as a transistor, IC, or LSI is used. In addition, the semiconductor element may be subjected to a process for reducing the substantial breaking strength, such as formation of a fragile layer by polishing or thinning. Moreover, the semiconductor element 104 may seal at least a part of the periphery of the connection portion between the semiconductor element 104 and the bump 105 and / or the connection portion between the bump 105 and the wiring pattern 102a using a sealing resin. . By injecting the sealing resin, it is possible to prevent a gap from being formed between the semiconductor element 104 and the wiring pattern 102a when the semiconductor element 104 is embedded in the insulating layer 101. As the sealing resin, an underfill resin used for normal flip chip bonding can be used. For the connection between the wiring pattern 102a and the semiconductor element 104, for example, flip chip bonding using bumps 105 can be used as shown in FIG. As a method for mounting a semiconductor element, a method using a conductive adhesive, an anisotropic conductive film (ACF), a non-conductive film (NCF) or the like and a bump can be used. Also, solder mounting using a chip size package (CSP) is an easy mounting method. Further, the back surface of the semiconductor element 104 (upper side surface in the drawing) may be roughened or coated with a coupling material or the like in order to improve the adhesion strength with the insulating layer.

  The bump 105 connects the semiconductor element 104 and the wiring pattern 102. For example, bumps can be formed using a metal such as gold, copper, or solder. The bump 105 can be formed by wire bonding, plating, printing, or the like. In addition, the description about the above-mentioned insulating layer, wiring pattern, via-hole conductor, semiconductor element, and bump is applicable not only to the aspect of FIG. 1 but also to any aspect of the present invention.

  In the semiconductor device 100 shown in FIG. 1, the insulating layer 101 is firmly bonded to the semiconductor element 104. As a result, the bonding strength between the insulating layer 101 and the semiconductor 104 is the same as that of the semiconductor device according to the first aspect. Is substantially larger than the breaking strength of the semiconductor element 104, and is substantially larger than the connection strength between the semiconductor element 104 and the wiring pattern 102a in the semiconductor device according to the second aspect. As a result, when the semiconductor element 104 is to be peeled off from the insulating layer 101 for analysis purposes, naturally, the semiconductor element 104 itself or the electrical connection between the wiring pattern and the semiconductor element is destroyed before the element is peeled off. End up. When such destruction occurs, information stored in the semiconductor element cannot be tampered with, analyzed, and the information does not leak. In conclusion, the semiconductor device 100 is a semiconductor device to which physical security is added, and a semiconductor device with improved information reliability is provided.

(Embodiment 2)
FIG. 2 schematically shows an example of another embodiment of the semiconductor device of the present invention in a sectional view. The semiconductor device 200 in the present embodiment is substantially the same as that shown in FIG. 1 except that the semiconductor element 204 is covered with the second electrical insulating layer 201b. Therefore, the elements described in the first embodiment can be used as elements constituting the semiconductor device of the second embodiment unless otherwise specified.

In FIG. 2, the semiconductor device 200 includes a first insulating layer 201a and a second insulating layer 201b, a first wiring pattern 202a and a second wiring pattern 202b, a via-hole conductor 203, a semiconductor element 204, and a bump 205. doing. The second insulating layer 201b contains the semiconductor element 204, which is firmly bonded. The first insulating layer 201a has a second wiring pattern 202b formed on the surface thereof and a first wiring pattern 202a formed therein. As shown, the second insulating layer 201b is adjacent to the first insulating layer 201a, and the first wiring pattern 202a formed inside the first insulating layer 201a can be said to be formed on the second insulating layer 201b. . In other words, the first insulating layer 201 a includes the second insulating layer 201 b that includes the semiconductor element 204.

  In FIG. 2, the semiconductor element 204 is electrically connected to the first wiring pattern 202a via the bump 205, and the first wiring pattern 202a is formed on the surface of the first insulating layer 201a via the via-hole conductor 203. The second wiring pattern 202b is electrically connected in a predetermined manner.

  By forming the second insulating layer 201b containing the semiconductor element 204 and the first insulating layer 201a forming the wiring patterns 202a and 202b from different materials, each insulating layer can be used in accordance with its application. The appropriate material can be selected. For example, the first insulating layer 201a can be easily formed with a wiring pattern, for example, a substrate having a multilayer wiring pattern, and a highly reliable material can be selected. The second insulating layer 201b can be connected to the semiconductor element 204. A material with strong adhesive strength can be selected. Further, different materials may be selected for the second insulating layer 201b in a portion in which the semiconductor element 204 is incorporated and a portion in which the wiring pattern 202a for mounting the semiconductor element 204 is formed. The latter part may be composed of an underfill resin.

  In this embodiment, the adhesive strength between the second insulating layer 201b and the semiconductor element 204 is configured to be larger than the breaking strength of the semiconductor element 204 itself. In another aspect, the adhesive strength between the second insulating layer 201b and the semiconductor element 204 is such that the connection strength between the semiconductor element 204 and the bump 205 and / or the connection between the first wiring pattern 202a and the bump 205 is obtained. It is configured to be larger than the strength. These strengths correspond to the connection strength between the wiring pattern and the semiconductor element. In general, the connection strength of the bump 205 to the first wiring pattern 202 a and the connection strength to the semiconductor element 204 are substantially smaller than the breaking strength of the semiconductor element 204.

  When the semiconductor element 204 is to be peeled off from the second electrical insulating layer 201b for the purpose of analysis due to the strength relationship as described above, the semiconductor element 204 is broken in the former aspect described above, and the semiconductor element 204 and the second element in the latter aspect described above. The electrical connection with one wiring pattern 202a is interrupted, and the semiconductor element 204 cannot be operated. That is, even if the terminal is pressed against the wiring pattern 202a on which the semiconductor element 204 is mounted, no signal is obtained and probing cannot be performed. Therefore, a semiconductor device to which physical security is added and information reliability is improved is provided.

  In the embodiment shown in FIG. 2, the first insulating layer 201 a is provided with the third wiring pattern 202 c on the other surface, and the third wiring pattern 202 c and the first wiring pattern 202 a are predetermined by the via-hole conductor 206. So connected. In another aspect, the third wiring pattern 202c may be connected to the second wiring pattern 202b in a predetermined manner by a via hole conductor in addition to or instead of the first wiring pattern 202a.

(Embodiment 3)
FIG. 3 schematically shows an example of still another embodiment of the semiconductor device of the present invention in a sectional view. The semiconductor device 300 according to the present embodiment is the same as that of the first embodiment described above except that an underfill exists below the semiconductor element and that the insulating layer has residual stress. Therefore, the elements described in Embodiment 1 can be used as elements constituting the semiconductor device of Embodiment 3 unless otherwise specified.

  In FIG. 3, the semiconductor element 304 is electrically connected to the first wiring pattern 302 a formed on the lower surface of the first insulating layer 301 a via the bump 305, and the first wiring pattern 302 a is connected via the via-hole conductor 303. The second wiring pattern 302b formed on the surface of the second insulating layer 301b is electrically connected in a predetermined manner. An underfill 306 exists between the semiconductor element 304 and the first wiring pattern 302a below the semiconductor element 304, and a second insulating layer 301b exists below the first wiring pattern 302a and the underfill 306 on which the semiconductor element 304 is mounted. May be the same as or different from the first insulating layer 301 a existing around the semiconductor element 304.

  In general, the resin constituting the insulating layer is cured by, for example, press molding under heat and pressure and then cooled, or it is cooled and bonded to a material having a different coefficient of thermal expansion. As a result, the insulating layer remains in a state having residual stress therein.

  In the present embodiment, the material constituting the insulating layers (301a and 301b) is heated and cured while applying pressure by press molding, and then cooled in the pressed state, whereby the insulating layer is obtained. Residual stress remains in the resin constituting 301. In the illustrated embodiment, an underfill 306 is filled below the semiconductor element 304. As the underfill 306, any known material may be used. For example, a sheet-like or liquid resin material may be used.

  In the illustrated form, the first insulating layer 301a and the semiconductor element 304, and the semiconductor element 304 and the underfill 306 are firmly bonded. Further, the residual stress remaining in the first insulating layer 301a is configured to be stronger than the breaking strength of the semiconductor element 304. The strength of a semiconductor element is usually governed by a force acting in the peeling or bending direction, not in the compression direction. For this reason, in the state in which the semiconductor element is built in, no force in the bending direction acts, so that the semiconductor device can be operated normally. However, if an attempt is made to remove the insulating layer by cutting or polishing the surrounding insulating layer 301 in order to analyze the semiconductor element, the residual stress is released. Therefore, if this residual stress is made larger than the breaking strength of the semiconductor 304, the semiconductor element 304 will be broken by the stress when the residual stress is released, thereby adding physical security to the semiconductor device. be able to.

  In another aspect, in the semiconductor element, the underfill 306 has a higher elastic modulus than the insulating layer (301a and / or 301b), and the insulating layer holds the stretched state of the underfill 306. deep. In this case, if the insulating layer is removed by scraping or polishing the surrounding insulating layer 301, the insulating layer cannot maintain the stretched state of the underfill and tends to shrink. It is configured such that a strong force acts on the surface in contact with the underfill 306 and the semiconductor element 304 is destroyed. As a result, the information in the semiconductor element 304 is not leaked and protected, and a semiconductor device with improved information reliability is provided.

  In the form shown in FIG. 3, the first insulating layer 301a has other wiring patterns 307a and 307b on the side opposite to the wiring patterns 302a and 302b. These wiring patterns may be electrically connected to the wiring patterns 302a and / or 302b as required.

(Embodiment 4)
FIG. 4 schematically shows an example of still another embodiment of the semiconductor device of the present invention in a sectional view. The semiconductor device 400 according to the present embodiment is the same as that of the first embodiment except that the two insulating layers 401a and 401b are formed of two materials having different thermal expansion coefficients. Therefore, the elements described in the first embodiment can be used as elements constituting the semiconductor device of the fourth embodiment unless otherwise specified.

  In FIG. 4, the semiconductor element 404 incorporated in the first insulating layer 401a is electrically connected to the first wiring pattern 402a formed on the lower surface of the first insulating layer 401a via the bumps 405, so that the first wiring The pattern 402a is electrically connected to the second wiring pattern 402b formed on the surface of the second insulating layer 401b via the via-hole conductor 403 in a predetermined manner.

  In this embodiment, the semiconductor device 400 is formed of two types of insulating layers 401a and 401b having different thermal expansion coefficients. These insulating layers are formed from a curable resin, preferably a thermosetting resin, and when the first insulating layer 401a is formed by curing, the second insulating layer 401b is already cured (ie, dimensioned). In this case, the residual stress remaining in the first insulating layer can be further increased. The thermal expansion coefficient of the first insulating layer 401a is preferably larger than the thermal expansion coefficient of the second insulating layer 401b.

  When the curable resin forming the first insulating layer 401a is heated to be cured and then cooled, the resin expanded by heating tends to shrink, but the already cured second insulating layer has a dimensional change due to a temperature change. Since it is small, the resin constituting the first insulating layer 401a cannot shrink, and as a result, the residual stress is held in a fixed state. That is, the cured resin forming the first insulating layer 401a is cooled and solidified while being expanded by heating, while the expanded state is maintained by the second insulating layer 401b. Accordingly, when the ability of the second insulating layer 401b to maintain the expanded state is reduced or eliminated, the residual stress of the first insulating layer 401a appears. Such residual stress is also maintained by the mechanical strength of the first insulating layer itself. Therefore, the residual stress of the first insulating layer 401a also appears when the first insulating layer 401a is thinned by cutting or a part thereof is removed.

  In this case, if the coefficient of thermal expansion in the planar direction of the second insulating layer 401b is made smaller than the coefficient of thermal expansion in the planar direction of the first insulating layer 401a, the first insulating layer 401a is cured to form the first insulating layer 401a. Residual stress acting in the vertical direction is strongly generated. For example, the thermal expansion coefficient in the planar direction of the second insulating layer 401b can be suppressed by including a reinforcing material having a small coefficient of thermal expansion such as glass cloth or aramid. Further, the generated stress becomes stronger as the elastic modulus of the first insulating layer 401a is higher. Therefore, it is effective to make the elastic modulus of the first insulating layer 401a containing the semiconductor element 404 higher than that of the second insulating layer 401b.

  In the illustrated embodiment, the first insulating layer 401a and the semiconductor element 404 are firmly bonded. In addition, the residual stress generated in the first insulating layer 401 a is configured to be stronger than the bonding strength between the semiconductor element 404 and the bump 405 or the bonding strength between the first wiring pattern 402 a and the bump 405. As a result, if the first insulating layer 401a and / or the second insulating layer 401b is removed by grinding or polishing to analyze the semiconductor element 404, the residual stress of the first insulating layer is released. .

  This stress is higher than the connection strength between the semiconductor element 404 and the first wiring pattern 402a, that is, the bonding strength between the semiconductor element 404 and the bump 405 or the bonding strength between the bump 405 and the first wiring pattern 402. As a result, the electrical connection between the semiconductor element 404 and the first wiring pattern 402 is interrupted, and the semiconductor element 404 cannot be operated. As a result, the terminal cannot be pressed against the first wiring pattern 402a on which the semiconductor element 404 is mounted to perform probing, and therefore, a semiconductor device to which physical security is added and information reliability is improved is provided.

  In the form shown in FIG. 4, the first insulating layer 401a has other wiring patterns 407a and 407b on the opposite side to the wiring patterns 402a and 402b. These wiring patterns may be electrically connected to the wiring patterns 402a and / or 402b as required by, for example, via hole conductors.

(Embodiment 5)
FIG. 5 schematically shows an example of still another embodiment of the semiconductor device of the present invention in a sectional view. With respect to the semiconductor device 500 in the present embodiment, two semiconductor elements 504a and 504b are incorporated, and there is a wiring pattern 502d that connects between these semiconductor elements, and the same as in the first embodiment. It is the same. Therefore, the elements described in the first embodiment can be used as elements constituting the semiconductor device of the fifth embodiment unless otherwise specified.

  In FIG. 5, the semiconductor element 504a is electrically connected to the first wiring pattern 502a located inside the insulating layer 501 through the bump 505a, and the first wiring pattern 502a is connected to the insulating layer 501 through the via-hole conductor 503a. The second wiring pattern 502b formed on the surface is electrically connected in a predetermined manner. The semiconductor element 504b is electrically connected to the first wiring pattern 502a located inside the insulating layer 501 through the bump 505b, and the first wiring pattern 502a is formed on the surface of the insulating layer 501 through the via-hole conductor 503b. The second wiring pattern 502b is electrically connected in a predetermined manner. Note that a wiring pattern 502d, which is a part of the wiring pattern 502a, connects two semiconductor elements. Each of the two semiconductor elements acts complementarily and functions as one new semiconductor element. In this example, two semiconductor elements act complementarily to function as one semiconductor element, but the number of semiconductor elements acting complementarily is not limited to two, but two or more. Any of these may be used.

  As a specific example, the semiconductor element 504a is an element (for example, an encryption circuit element) having a function of performing signal conversion by encryption or the like and applying software security to information, and when the semiconductor element 504b leaks personal information or the like. An element (for example, a memory) in which troublesome information is stored. In this case, the wiring pattern 502 d connects the semiconductor elements 504 a to 504 b, and information contained in the semiconductor element 504 b is encrypted by the semiconductor element 504 a and output to the outside of the semiconductor device 500.

  Therefore, there is a risk that information between the semiconductor elements 504a and 504b is probed when mounted on a normal substrate. Therefore, in this embodiment, the semiconductors 504a and 504b are incorporated in the insulating layer 501, and at least the wiring pattern 502d for connecting them is preferably incorporated so that they are not exposed to the outside. As a result, it is difficult to analyze. By adopting such a structure, even if, for example, encryption key information or the like leaks, it is possible to change the design of only the semiconductor element 504a, and it is not necessary to change the design of all the semiconductor elements. In addition, a semiconductor device having information reliability and suitable for production is provided, such that each semiconductor element can be shared by various devices.

(Embodiment 6)
FIG. 6 schematically shows an example of still another embodiment of the semiconductor device of the present invention in a sectional view. Regarding semiconductor device 600 in the present embodiment, the above-described implementation is performed except that via-hole conductor 604b is used for connection between semiconductor element 604a and semiconductor element 604b and electronic component 607 is also incorporated. This is the same as the fifth embodiment. Therefore, in the present embodiment, elements that are not particularly described may be the same as those in the fifth embodiment.

  The electronic component 607 is an element that forms a circuit of a semiconductor device, and is different from a semiconductor element in that it is a passive element. Examples of electronic components include chip components such as capacitors, inductors, resistors, diodes, thermistors, switches, and the like. Such an electronic component is a discrete component. By incorporating the electronic component, it is not necessary to newly develop a built-in component. In addition, existing parts can be used according to accuracy, temperature characteristics, applications, etc., leading to improved reliability. In addition, printed resistors, thin film capacitors, inductors, and the like may be formed as electronic components. For mounting the electronic component 607, solder, a conductive adhesive, or the like can be used. When using high-temperature solder and conductive adhesive, remelting of the solder when the module is mounted by reflow can be prevented. In addition, when lead-free solder is used, the burden on the environment can be reduced.

  The via-hole conductor 603b connects the semiconductor elements 604a to 604b through the wiring pattern 602a. By using the via-hole conductor 603b for the connection between the semiconductor elements 604a-604b, it becomes difficult to expose the wiring pattern 602a by polishing from the side of the semiconductor device, and it becomes difficult to analyze from the outside. Thus, a semiconductor device having information reliability and suitable for production is provided.

(Embodiment 7)
FIG. 7 schematically shows an example of still another embodiment of the semiconductor device of the present invention in a sectional view. The semiconductor device 700 in the present embodiment is the same as that in the fifth embodiment described above except that the shield 708 is used. Therefore, in the present embodiment, elements that are not particularly described may be the same as those in the fifth embodiment. The semiconductor device 700 includes at least two semiconductor elements 704a and 704b, which are connected in a predetermined manner by 702d which is a part of the wiring pattern 702a for mounting them. The wiring pattern 702a is connected to the wiring pattern 702b on the surface of the insulating layer 701 through the via-hole conductor 703.

  In the illustrated embodiment, the shields 708 are disposed on both upper and lower sides of the semiconductor elements 704a and 704b, but may be disposed on one side, or may be disposed on both sides or one side of one semiconductor element. Most preferably, as shown, the shield is disposed on one or both sides of substantially all of the semiconductor elements and the wiring pattern 702d connecting them, but the shield forms part of such an arrangement. It may be only. What is necessary is just to comprise so that the wiring pattern 702d may be shielded at least.

  The shield 708 is formed of, for example, a conductor such as copper foil or a magnetic absorption material, and can prevent the signal of the wiring pattern 702a from being monitored by a probe or the like from the outside. The shield 708 can be formed using the same material as the wiring patterns 702a and 702b in the same manner as the step of forming the wiring pattern. In another aspect, a sheet of a mixture of ferrite powder and resin can be used to form the shield, and when the insulating layer 701 is formed, the sheet may be included therein. Further, the shield 708 is connected to the ground potential by a via-hole conductor, a wiring pattern, or the like, so that the semiconductor device can be operated more stably. The shield may be a single layer as shown in the figure, or a plurality of layers may be stacked.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a typical sectional view of a semiconductor device in a 2nd embodiment of the present invention. It is a typical sectional view of a semiconductor device in a 3rd embodiment of the present invention. It is typical sectional drawing of the semiconductor device in the 4th Embodiment of this invention. It is a typical sectional view of a semiconductor device in a 5th embodiment of the present invention. It is a typical sectional view of a semiconductor device in a 6th embodiment of the present invention. It is typical sectional drawing of the semiconductor device in the 7th Embodiment of this invention.

Explanation of symbols

100, 200, 300, 400, 500, 600, 700 ... Semiconductor device 101, 201, 301, 401, 501, 601, 701 ... Insulating layer 102, 202, 302, 307, 402, 407, 502, 602, 702 ... Wiring pattern 103, 203, 206, 303, 403, 503, 603, 703 ... Via-hole conductor 104, 204, 304, 404, 504, 604, 704 ... Semiconductor element 105, 205, 405, 505, 605, 705 ... Bump 306 ... Underfill 607 ... Electronic components 708 ... Shield

Claims (14)

  Insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed inside the insulating layer, a via-hole conductor in the insulating layer that connects the wiring pattern in a predetermined manner, and the insulating layer disposed inside the insulating layer A semiconductor device comprising a semiconductor element connected to the wiring pattern in a predetermined manner, wherein an adhesive strength between the insulating layer and the semiconductor element is larger than a breaking strength of the semiconductor element itself.   Insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed inside the insulating layer, a via-hole conductor in the insulating layer that connects the wiring pattern in a predetermined manner, and the insulating layer disposed inside the insulating layer And having a semiconductor element connected to the wiring pattern in a predetermined manner, and the bonding strength between the insulating layer and the semiconductor element is larger than the connection strength between the semiconductor element and the wiring pattern connected thereto. A semiconductor device.   A first insulating layer, at least one surface of the first insulating layer and a predetermined wiring pattern formed therein, a via-hole conductor in the first insulating layer for connecting the wiring pattern in a predetermined manner, and the first insulating layer; The semiconductor element is disposed inside and connected in a predetermined manner to the wiring pattern in the first insulating layer. The semiconductor element is embedded in the second insulating layer, and is embedded in the first insulating layer. The semiconductor device is characterized in that the adhesive strength between the second insulating layer and the semiconductor element is greater than the breaking strength of the semiconductor element.   A first insulating layer, at least one surface of the first insulating layer and a predetermined wiring pattern formed therein, a via-hole conductor in the first insulating layer for connecting the wiring pattern in a predetermined manner, and the first insulating layer; The semiconductor element is disposed inside and connected in a predetermined manner to the wiring pattern in the first insulating layer. The semiconductor element is embedded in the second insulating layer, and is embedded in the first insulating layer. The semiconductor device is characterized in that the adhesive strength between the second insulating layer and the semiconductor element is stronger than the connection strength between the semiconductor element and the wiring pattern connected thereto.   Insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed inside the insulating layer, a via-hole conductor in the insulating layer that connects the wiring pattern in a predetermined manner, and the insulating layer disposed inside the insulating layer A semiconductor device comprising: a semiconductor element connected to the wiring pattern in a predetermined manner, wherein the insulating layer has a residual stress greater than a breaking strength of the semiconductor element.   Insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed inside the insulating layer, a via-hole conductor in the insulating layer that connects the wiring pattern in a predetermined manner, and the insulating layer disposed inside the insulating layer A semiconductor device comprising: a semiconductor element connected to the wiring pattern in a predetermined manner, wherein the insulating layer has a residual stress larger than a connection strength between the semiconductor element and the wiring pattern connected to the semiconductor element. apparatus.   The insulating layer includes a first insulating layer containing a semiconductor element and a second insulating layer formed with a wiring pattern, and the thermal expansion coefficient in the planar direction of the first insulating layer is greater than the thermal expansion coefficient in the planar direction of the second insulating layer. 7. The semiconductor device according to claim 5, wherein   The insulating layer includes a first insulating layer containing a semiconductor element and a second insulating layer formed with a wiring pattern, and the elastic modulus in the planar direction of the first insulating layer is greater than the elastic modulus in the planar direction of the second insulating layer. 8. The semiconductor device according to claim 5, wherein   7. The underfill filled around a connecting portion between a semiconductor element and a wiring pattern for mounting the semiconductor element, wherein the elastic modulus of the insulating layer is smaller than the elastic modulus of the underfill. Semiconductor device.   Insulating layer, at least one surface of the insulating layer and a predetermined wiring pattern formed inside the insulating layer, a via-hole conductor in the insulating layer that connects the wiring pattern in a predetermined manner, and the insulating layer disposed inside the insulating layer A semiconductor device comprising a plurality of semiconductor elements arranged in a semiconductor device, wherein at least two of these semiconductor elements are connected in a predetermined manner by a wiring pattern in an insulating layer.   11. The semiconductor device according to claim 10, wherein the connection between the semiconductor elements is formed by a wiring pattern and a via hole conductor.   12. The semiconductor device according to claim 10, wherein a via-hole conductor is formed around the semiconductor.   13. The semiconductor device according to any one of 10 to 12, wherein a shield is provided between a wiring pattern connecting the semiconductor elements and the surface of the insulating layer, or on a surface of the insulating layer portion surrounding the wiring pattern. 14. The semiconductor device according to claim 13, wherein the potential of the shield is a ground potential.

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