JP2005070966A - Information processing apparatus and information processor control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus suited for the parallel processing of processing objects matching a variety of applications and also for parallel processing by a small number of arithmetic processing units. <P>SOLUTION: The information processing apparatus 1 comprises first to third information processing parts 10-12, an I/O control processor (hereinafter referred to as IOP) 13, a global bus (hereinafter referred to as G-bus) 14, and a data storage part 15. The first to third information processing parts 10-12 each include two BPCs (Basic Processing Cell) and a respective local bus (hereinafter referred to as L-bus) exclusively for the BPC. The three information processing parts are connected in series with one another via the L-buses and the BPC of the third information processing part is connected to the L-bus of the first information processing part. Depending on processing objects, the IOP 13 selects an exclusive program and sends it to each BPC. Each BPC in turn executes the exclusive program, thus processing the processing object. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to the field of information processing in which a common processing target is processed in parallel using a plurality of arithmetic processing devices, and in particular, an information processing device suitable for performing parallel processing on various types of information processing targets. About.

Conventionally, as a technique for performing high-speed information processing by a plurality of arithmetic processing devices, for example, an image processing device disclosed in Patent Document 1 (hereinafter referred to as a first conventional example), Patent Document 2 (hereinafter referred to as a second technology). There is a microcomputer disclosed in the prior art example.
The first conventional example has an object to provide an image processing apparatus for performing pattern matching processing at high speed, and performs predetermined processing by inputting data, and output data as a result of the processing. Are processed as input data to the subsequent image processing block, and each of the image processing blocks includes a plurality of image processing blocks that perform pipeline processing. An image processing block, a buffer memory, and a fifo (FIFO (First In First Out)) memory are provided, and output data as a processing result of the image processing block is sequentially passed through the buffer memory for each unit of a predetermined data amount. The pointer indicating the storage position of the output data in the buffer memory is sequentially transferred to the next image processing block. And it has a configuration to pass to the next stage of the image processing blocks through the FIFO memory.

The second conventional example has an object to provide a microcomputer that can easily perform pipeline control even when a stall occurs and can realize power saving. The pipeline stage of each issued instruction is piped. A central processing unit that performs parallel processing by line control; and a clock control circuit that controls a first clock that operates the central processing unit, wherein the clock control circuit is at least one of pipeline stages that are processed in parallel. When one stalls due to a given factor, control is performed to stop the first clock. A central processing unit (CPU), which is the central processing unit, processes instructions in parallel through a pipeline, and a clock control circuit controls CLK1 that operates most of the CPU. By stopping CLK1 when the pipeline is stalled, pipeline control is optimized and power is saved.
Japanese Patent Laid-Open No. 2001-157049 Japanese Patent Laid-Open No. 10-31222

However, the first conventional example is an apparatus specialized for image processing and cannot be used for purposes other than image processing.
Further, both the first conventional example and the second conventional example have a configuration in which the number of processing blocks must be increased according to the type of processing each time the number of processes to be processed in parallel increases. Accordingly, there is a possibility that problems such as an increase in cost and an enlargement of the circuit structure may occur due to an increase in processing blocks accompanying an increase in the number of processes.

  Therefore, the present invention has been made paying attention to such an unsolved problem of the conventional technology, and is suitable for parallel processing of processing objects corresponding to various uses, and a small number of them. It is an object of the present invention to provide an information processing apparatus suitable for performing parallel processing by the arithmetic processing apparatus.

[Invention 1]
In order to achieve the above object, an information processing apparatus according to a first aspect of the present invention is an information processing apparatus that processes a processing target in parallel by a plurality of arithmetic processing devices,
Each arithmetic processing unit includes a dedicated data transmission line,
The plurality of arithmetic processing units are grouped into a plurality of stages, and each stage is connected via the data transmission line,
Processing target data acquisition means for acquiring processing target data which is the processing target data;
Based on the processing target, the dedicated program for the processing target from among a plurality of types of dedicated programs for causing the plurality of arithmetic processing devices to perform predetermined processing according to the processing content of the processing target data in parallel A dedicated program setting means for selecting and setting each of the processing units,
The arithmetic processing unit performs arithmetic processing by the set dedicated program, and the arithmetic processing result data is processed by using the arithmetic processing result data. It is characterized by the fact that it is transmitted through the network.

  In such a configuration, a plurality of arithmetic processing units are grouped into a plurality of stages, and each stage is connected via the data transmission line, so a dedicated data transmission line is used between each stage. It is possible to transmit data, and it is possible to acquire processing target data that is common processing target data by the processing target data acquisition means, and to the processing contents of the processing target data in a plurality of arithmetic processing units. A plurality of types of dedicated programs for performing parallel processing of the corresponding predetermined arithmetic processing, and the dedicated program setting means converts the dedicated programs for the processing targets based on the processing targets to the plurality of types of dedicated programs. Can be selected and set for each arithmetic processing unit.

  Therefore, since each arithmetic processing unit can transmit data through a dedicated data transmission line, data collision in the data transmission path does not occur. Therefore, each arithmetic processing unit does not interrupt processing in data transmission. It is possible to continue. Furthermore, since the dedicated program is selected according to the processing target and set in each arithmetic processing unit, it is possible to flexibly cope with various types of processing target. Furthermore, since each arithmetic processing unit performs arithmetic processing by a dedicated program for each processing target, high-speed arithmetic processing can be performed by specializing the arithmetic processing contents in each arithmetic processing device. Furthermore, high-speed processing can be performed by performing parallel processing (pipeline processing) with a plurality of stages on the same type of processing target that is continuously performed.

Here, the plurality of arithmetic processing devices may not be the same type as long as they can solve the dedicated program with the same configuration, for example, different types such as a mixture of different processing speeds. You may comprise by the combination of arithmetic processing units.
Further, the dedicated data transmission line is a dedicated data acquisition line for each arithmetic processing unit to acquire data of the arithmetic result of another arithmetic processing unit included in the preceding group, and each arithmetic processing unit Data can be independently acquired at a predetermined timing.
[Invention 2]
Furthermore, the information processing apparatus of the invention 2 is characterized in that, in the information processing apparatus of the invention 1, each stage grouped into the plurality of stages is configured by two or more arithmetic processing devices.

In other words, since each stage of the arithmetic processing device grouped into a plurality of stages is composed of two or more, parallel processing can be performed in each stage. Furthermore, it is possible to perform a plurality of types of processing performed on the same processing target in parallel. For example, different types of processing such as voice and image can be processed in parallel between a plurality of arithmetic processing devices and stages.
[Invention 3]
Furthermore, the information processing device of the invention 3 is the processing data for causing the arithmetic processing device of each stage to perform the predetermined arithmetic processing in parallel in the information processing device of the invention 1 or the invention 2 based on the processing target data. Is provided with a processing data supply means for supplying the processing data to an arithmetic processing device that starts the arithmetic processing.

That is, the processing data supply means supplies the processing data for causing the arithmetic processing devices in the respective stages to perform the predetermined arithmetic processing in parallel based on the processing target data to the arithmetic processing device that starts the arithmetic processing. Is possible.
Therefore, for example, when the processing target is data including sound and image, the sound bit stream and the image bit stream are separated and supplied to the corresponding arithmetic processing units, respectively. It is possible to process different types of data in parallel.
[Invention 4]
Furthermore, an information processing apparatus according to a fourth aspect is characterized in that in the information processing apparatus according to any one of the first to third aspects, the plurality of groups are connected in a ring shape via the data transmission line.

That is, since the groups of the plurality of stages are connected in a ring shape via the data transmission line, data loop transmission is possible.
Therefore, it is possible to continue the processing from the first stage arithmetic processing apparatus by using the final stage arithmetic processing result as it is. That is, it is possible to perform this with a small number of stages when similar arithmetic processing such as learning calculation is repeatedly performed. As a result, the number of arithmetic processing units can be reduced, thereby making it possible to save circuit space and reduce costs.

Here, the ring shape means that when each group in which a plurality of arithmetic processing units are divided into a plurality of stages are connected together by a data transmission line, the data input unit of the arithmetic processing unit included in the uppermost stage is connected to the uppermost stage. In this state, the data output unit of the arithmetic processing unit included in the lower stage is connected via the data transmission line.
[Invention 5]
Further, the information processing apparatus of the invention 5 is the information processing apparatus of the invention 4, further comprising program changing means for changing the dedicated program set in the arithmetic processing device to another type at a predetermined timing. It is said.

That is, the program changing means can change the dedicated program set in each arithmetic processing unit to another type at a predetermined timing.
Therefore, data can be transmitted in a loop, and the program of each arithmetic processing unit can be changed at a predetermined timing. For example, in the final stage arithmetic processing unit, each arithmetic processing is performed at the timing when arithmetic processing by a dedicated program is performed. By changing the program of the processing device, it is possible to continue to perform another arithmetic processing from the arithmetic processing device of the first stage by using the arithmetic processing result of the final stage as it is. As a result, it is possible to perform arithmetic processing with the number of steps equal to or greater than the number of configured steps with a smaller number of steps than the number of steps, thereby reducing the number of arithmetic processing devices, saving circuit space and reducing costs. It becomes possible.
[Invention 6]
Furthermore, the information processing apparatus of the invention 6 is the information processing apparatus of the invention 5, wherein the predetermined timing is a predetermined series of arithmetic processing performed by the arithmetic processing devices from the start stage to the final stage of the arithmetic processing in the plurality of stages. Is the timing of the
At the timing, the program changing means changes the dedicated program of the arithmetic processing unit at each stage to another type of program that continues the series of arithmetic processing.

That is, the predetermined timing is a timing at which a series of arithmetic processing is performed a predetermined number of times by each arithmetic processing device from the start stage to the final stage of the arithmetic processing in the plurality of stages, and at this timing, the program changing means The dedicated program of the arithmetic processing unit at each stage is changed to another type of program that continues the series of arithmetic processing.
Therefore, since the number of processes can be performed with a smaller number of steps than the number of steps, the number of operation processing devices can be reduced, thereby reducing circuit space and cost. Etc. are possible.
[Invention 7]
Furthermore, the information processing apparatus of the invention 4 is the information processing apparatus of any of the inventions 1 to 6, wherein the dedicated program selected by the dedicated program setting means, the number of constituent stages of the arithmetic processing device, and the calculation of each stage. Based on the number of processing devices, an arithmetic processing device setting means is provided for setting an arithmetic processing device that performs the predetermined arithmetic processing on the processing target from the plurality of arithmetic processing devices.

That is, based on the dedicated program selected by the dedicated program setting unit by the arithmetic processing unit setting unit, the number of stages of the arithmetic processing unit, and the number of arithmetic processings of each stage, the plurality of arithmetic processing units It is possible to set an arithmetic processing unit that performs the predetermined arithmetic processing on the processing target.
Accordingly, when a new processing target is added, it is possible to automatically set an arithmetic processing unit necessary for processing based on the selected dedicated program, the number of processing steps, and the like. Accordingly, it is not necessary to consider the configuration and the like, and it is easy to upgrade the version such as adding a new dedicated program. Here, the arithmetic processing unit setting means has a configuration in which the number of stages of the arithmetic processing unit is smaller than the number of processing steps to be processed when the loop transmission of data is possible as described above in a plurality of stages of the arithmetic processing unit. For example, in consideration of setting a plurality of processing steps in one arithmetic processing unit, an arithmetic processing unit that performs processing is set.
[Invention 8]
Further, the information processing apparatus control program of the invention 8 is a program executable by a computer for controlling the information processing apparatus of the invention 1,
A processing target data acquisition step for acquiring processing target data which is the common processing target data;
And a dedicated program setting step of selecting the dedicated program for the processing target from the plurality of types of dedicated programs and setting the processing program in each arithmetic processing unit based on the processing target.

  Here, the present invention is a program for controlling the information processing apparatus according to the first aspect, and since the effects thereof are duplicated, description thereof is omitted.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 12 are diagrams showing an embodiment of an information processing apparatus according to the present invention.
First, the configuration of the information processing apparatus according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration example of an information processing apparatus according to the present invention.
The information processing apparatus 1 includes a first information processing unit 10, a second information processing unit 11, a third information processing unit 12, an I / O control processor (hereinafter referred to as IOP) 13, a global bus (Hereinafter referred to as G bus) 14 and a data storage unit 15 are included.

The first information processing unit 10 includes a BPC (Basic Processing Cell) 100, a BPC 101, a local bus (hereinafter referred to as an L bus) 102, an L bus 103, a bus bridge 104, and a bus bridge 105. It is a configuration that includes.
Each of the BPC 100 and the BPC 101 is an arithmetic processing device that performs arithmetic processing according to the type of dedicated program set in its own memory. Details will be described later.

The L bus 102 is dedicated to the BPC 100 and transmits output from the preceding BPC (here, the BPC of the third information processing unit 12) or data input through the G bus 14 to the BPC 100. is there.
The L bus 103 is dedicated to the BPC 101, and transmits the output from the preceding BPC (here, the BPC of the third information processing unit 12) or the data input via the G bus 14 to the BPC 101. is there.

The bus bridge 104 serves as a bridge between the L bus 102 and the G bus 14, and exchanges bus cycles with each other by bus conversion.
The bus bridge 105 serves as a bridge between the L bus 103 and the G bus 14, and exchanges bus cycles with each other by bus conversion.
The second information processing unit 11 includes a BPC (Basic Processing Cell) 110, a BPC 111, an L bus 112, an L bus 113, a bus bridge 114, and a bus bridge 115.

Each of the BPC 110 and the BPC 111 is an arithmetic processing device that performs arithmetic processing according to the type of dedicated program set in its own memory. Details will be described later.
The L bus 112 is dedicated to the BPC 110, and transmits data output from the preceding BPC (here, the BPC of the first information processing unit 10) or data input via the G bus 14 to the BPC 110. is there.

The L bus 113 is dedicated to the BPC 111 and transmits output from the preceding BPC (here, BPC of the first information processing unit 10) or data input via the G bus 14 to the BPC 111. is there.
The bus bridge 114 serves as a bridge between the L bus 112 and the G bus 14, and exchanges bus cycles with each other by bus conversion.

The bus bridge 115 serves as a bridge between the L bus 113 and the G bus 14, and exchanges bus cycles with each other by bus conversion.
The third information processing unit 12 includes a BPC (Basic Processing Cell) 120, a BPC 121, an L bus 122, an L bus 123, a bus bridge 124, and a bus bridge 125.

Each of the BPC 120 and the BPC 121 is an arithmetic processing device that performs arithmetic processing according to the type of dedicated program set in its own memory. Details will be described later.
The L bus 122 is dedicated to the BPC 120, and transmits data output from the preceding BPC (here, the BPC of the second information processing unit 11) or data input via the G bus 14 to the BPC 120. is there.

The L bus 123 is dedicated to the BPC 121, and transmits data output from the preceding BPC (here, the BPC of the second information processing unit 11) or data input through the G bus 14 to the BPC 121. is there.
The bus bridge 124 serves as a bridge between the L bus 122 and the G bus 14, and exchanges bus cycles with each other by bus conversion.

The bus bridge 125 serves as a bridge between the L bus 123 and the G bus 14, and exchanges bus cycles with each other by bus conversion.
That is, the BPC 100 and the BPC 101 in the first information processing unit 10 are respectively connected to the L bus 112 and the L bus 113 in the second information processing unit 11, and the BPC 110 and the BPC 111 in the second information processing unit 11 are connected. Are connected to the L bus 122 and the L bus 123 in the third information processing unit 12, respectively. The BPC 120 and the BPC 121 in the third information processing unit 12 are connected to the L bus 102 and the L information in the first information processing unit 10, respectively. Each is connected to the L bus 103. As a result, it is possible to transmit the arithmetic processing result data of the third information processing unit 12 to the first information processing unit 10. That is, loop transmission of data is possible.

  The IOP 13 operates in response to a command from the outside, and supplies various data from the data storage unit 15 to the first to third information processing units 10 to 12 via the G bus 14, or the first to third information Data output from the information processing units 10 to 12 is acquired via the G bus 14 and stored in the data storage unit 15, or data exchange between the data storage unit 15 and each information processing unit is controlled. . Further, the data to be processed is analyzed. For example, if the processing target is composite data obtained by combining a plurality of types of data, the data is divided into types and transmitted to the BPC in each information processing unit. Examples of the composite data include audio and image composite data. Furthermore, the number of BPCs required for processing and the flow of processing are determined according to the processing target, the number of information processing units, and the number of BPCs in each information processing unit, and the processing configuration for the processing target is set. Furthermore, a dedicated program necessary for the set processing configuration is read from the data storage unit 15 and transmitted to the BPC of each information processing unit.

The G bus 14 is a data transmission line for performing data transmission between the IOP 13 and the first to third information processing units 10 to 12.
The data storage unit 15 causes the BPCs in the first to third information processing units 10 to 12 to perform predetermined arithmetic processing on the common processing target in parallel for the common processing target. A plurality of types of dedicated programs or data to be processed are stored.

Further, a detailed configuration of the BPC will be described with reference to FIG. FIG. 2 is a block diagram showing a detailed configuration of the BPC. In the present embodiment, it is assumed that each BPC in the first to third information processing units 10 to 12 has the same configuration. Therefore, the detailed configuration of the BPC 100 will be described as a representative.
As shown in FIG. 2, the BPC 100 includes an element processor (hereinafter referred to as EP) 100a and a local memory 100b.

The EP 100a is an arithmetic processing unit that performs arithmetic processing of the dedicated program on data to be processed according to the type of the dedicated program set in the local memory 100b.
The local memory 100b corresponds to each BPC of a dedicated unit that can be accessed only by the EP 100a in which a dedicated program or the like for determining the arithmetic processing content of the EP 100a is stored, and an information processing unit in the next stage that stores data of the arithmetic processing result And a shared unit accessible by the L bus. Here, the data transmitted from the preceding BPC is stored in the dedicated part or the shared part of the local memory 100b via the EP 100a, and the data transmitted from the IOP 13 is transmitted to the local memory 100b via the latter L bus. Is stored in the sharing unit.

Here, in the information processing apparatus 1 shown in FIG. 1, as described above, each information processing unit is configured by two BPCs in parallel, and further, three information processing units are connected in series via the L bus, and The configuration is such that data loop transmission is possible. However, the present invention is not limited to this, and the number of information processing units and the number of BPCs of each information processing unit may be configured as arbitrary numbers.
Further, the configuration of the information processing apparatus will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of a configuration image of the information processing apparatus.

As shown in the information processing apparatus 2 of FIG. 3, the number of simultaneous parallel processes (parallelism) increases by increasing the number of BPCs constituting each information processing unit, and more by increasing the number of information processing units. It is possible to simultaneously support the algorithm.
Furthermore, since the information processing apparatus has a cylinder shape configuration (a configuration capable of data loop transmission), when the number of information processing units is smaller than the number of algorithms to be processed, for example, an image of rotating the cylinder Each time the calculation process is completed (represented as one rotation) in all the information processing units constituting the information processing apparatus, such as algorithm A for the first rotation and algorithm B for the second rotation for each BPC. Then, by changing the dedicated program of each BPC to another one and performing the second rotation process, the algorithms that are equal to or more than the number of information processing units for the common processing target are continuously performed.

  In other words, a plurality of arithmetic processes for the common data are sequentially performed from the information processing unit that has started processing, and at the timing when the processing returns to the information processing unit that has started processing again (end of the first rotation) The program is changed to an algorithm that is a continuation of the arithmetic processing in the information processing unit in the previous stage, and the processing is continued (to the second rotation). This is compensated for by the necessary number of rotations according to the number of algorithms. Therefore, it is possible to deal with a processing target having an algorithm number equal to or greater than the number of information processing units.

  Further, based on FIGS. 4 to 9, as a more specific operation of the information processing apparatus, the information processing apparatus 3 having the configuration in which the fourth information processing unit 16 is added to the information processing apparatus 1 of FIG. (Moving Picture Experts Group) An example of performing a bitstream composite process of 2 standards will be described. FIG. 4 is a diagram illustrating an example of setting a dedicated program in the BPC, and FIG. 5 is a diagram illustrating an example of data flow and processing in the first information processing unit 10 when data to be processed is transmitted to the BPC. FIG. 6 is a diagram illustrating an example of a data flow from the first information processing unit 10 to the second information processing unit 11 and an example of processing in the second information processing unit 11, and FIG. FIG. 8 is a diagram illustrating an example of a data flow from the second information processing unit 11 to the third information processing unit 12 and an example of processing in the third information processing unit 12, and FIG. 8 illustrates the third information processing unit. FIG. 9 is a diagram illustrating an example of the flow of data from 12 to the fourth information processing unit 13 and an example of processing in the fourth information processing unit 13. FIG. 9 is a data storage unit that stores the combined data via the IOP 13. One of the processes stored in 15 Is a diagram illustrating a.

First, the configuration of the information processing apparatus 3 will be described with reference to FIG.
As shown in FIG. 4, the information processing device 3 includes first to third information processing devices 10 to 12, a fourth information processing device 16, an IOP 13, a G bus 14, a data storage unit 15, It has a configuration that includes.
Here, the information processing apparatus 3 has a configuration in which a fourth information processing apparatus 16 is added to the information processing apparatus 1 described above. In addition, description of the overlapping part with the said information processing apparatus 1 is abbreviate | omitted.

The fourth information processing apparatus 16 includes a BPC (Basic Processing Cell) 130, a BPC 131, an L bus 132, an L bus 133, a bus bridge 134, and a bus bridge 135.
Each of the BPC 130 and the BPC 131 is an arithmetic processing device that performs arithmetic processing according to the type of dedicated program set in its own memory. Details will be described later.

The L bus 132 is dedicated to the BPC 130, and transmits data output from the preceding BPC (here, the BPC of the second information processing unit 11) or data input via the G bus 14 to the BPC 130. is there.
The L bus 133 is dedicated to the BPC 131 and transmits the output from the preceding BPC (here, the BPC of the third information processing unit 12) or the data input via the G bus 14 to the BPC 131. is there.

The bus bridge 134 serves as a bridge between the L bus 132 and the G bus 14, and exchanges bus cycles with each other by bus conversion.
The bus bridge 135 serves as a bridge between the L bus 133 and the G bus 14, and exchanges bus cycles with each other by bus conversion.
Further, with the addition of the fourth information processing unit 16, the output from the BPC in the fourth information processing unit 16 is sent to each BPC via the L bus 102 or the L bus 103. Will be transmitted. That is, the BPC 130 and the BPC 131 in the fourth information processing unit 16 are respectively connected to the L bus 102 and the L bus 103 in the first information processing unit 10, and thereby the calculation of the fourth information processing unit 16. It is possible to transmit the processing result data to the first information processing unit 10. That is, loop transmission of data is possible.

  Next, the flow of the dedicated program setting process will be described with reference to FIG. First, when the IOP 13 acquires an external command, the IOP 13 analyzes the command and confirms that the MPEG2 standard bitstream stored in the designated address of the data storage unit 15 is to be combined. Then, from among a plurality of types of dedicated programs prepared in the data storage unit 15, a dedicated program necessary for decoding the MPEG2 standard bit stream is selected. Further, based on the selected program, a configuration necessary for performing arithmetic processing by the dedicated program is set. The setting contents vary depending on the number of dedicated programs and the number of types of data to be processed. Here, in the case of a bit stream of the MPEG2 standard, there are two types of data to be processed: an image bit stream and an audio bit stream, and each processing step is four steps. However, the fourth step is processing for the combined data, and can be processed by a common dedicated program (algorithm) for the image and audio bit streams.

  There are four image bitstreams: image VLC (Variable Length Code) processing, IDCT (Inverse Discrete Cosine Transorm) processing, motion compensation processing, and output shaping processing. There are four types of voice VLC processing, IMDCT (Inverse Modified Discrete Cosine Transform) processing, filter processing, and output shaping processing.

Accordingly, as the setting contents, the four information processing units of the first to third information processing units 10 to 12 and the fourth information processing unit 16 are used, and the first to third information processing units 10 to 10 are used. 12, all BPCs are used, and the fourth information processing unit 16 is set to use only the BPC 131.
Then, the BPC 100, BPC 110, and BPC 120 in the first to third information processing units 10 to 12 are set to perform an audio bitstream decoding process, and the first to third information processing units 10 to 12 perform the processing. The BPC 101, the BPC 111, and the BPC 121 are set to perform the composite processing of the image bitstream, and the BPC 131 in the fourth information processing unit 16 is set to perform the output shaping process. Further, based on the set contents, each dedicated program is read from the data storage unit 15 and transmitted to the corresponding BPC via the G bus 14 and the L bus corresponding to each BPC. Here, in the present embodiment, it is set in advance to start the composite processing from the first information processing unit 10, and the flow direction of the processing is also directed to the first to fourth directions. Is set.

  As shown in FIG. 4, the data flow of the dedicated program is as follows. For the BPC 120 in the third information processing unit 12, first, the IOP 13 sends a dedicated program for filtering the audio bitstream from the data storage unit 15. Read and pass this to the G bus 14. This dedicated program reaches the bus bridge 134 via the G bus 14, and further reaches the BPC 120 via the L bus 132 via the bus bridge 134. More precisely, the data is written to the shared part of the local memory of the BPC 120 via the L bus 132. For other BPCs, a dedicated program for audio VLC processing is transmitted to the BPC 100 via the L bus 112, and a dedicated program for IMDCT processing is transmitted to the BPC 120 via the L bus 122 for video VLC processing. The dedicated program for the image compensation is transmitted to the BPC 101 via the L bus 112, the dedicated program for the IDCT processing is transmitted to the BPC 111 via the L bus 122, and the dedicated program for the motion compensation processing is transmitted via the L bus 132. The dedicated program for output shaping processing is transmitted to the BPC 131 via the L bus 102.

Note that the right to use the L bus is abandoned to the BPC 130 that is not used in the MPEG2 standard bitstream decoding process.
Further, based on FIG. 5, processing data transmission processing and processing in each BPC of the information processing unit 10 will be described.
For transmission of processing data, first, in the IOP 13, a bit stream of the MPEG2 standard to be processed is read from the data storage unit 15 and stored in the internal memory. Then, the MPEG2 standard bit stream stored in the internal memory is analyzed and separated into an audio bit stream and an image bit stream. Each separated bit stream is transmitted to each BPC of the corresponding information processing unit. As described above, since processing is started from the first information processing unit 10, the audio bit stream is transmitted to the BPC 100 via the G bus 14, the bus bridge 104, and the L bus 102, and the image bit stream is The data is transmitted to the BPC 101 via the G bus 14, the bus bridge 105 and the L bus 103.

When the BPC 100 acquires the audio bit stream, the BPC 100 performs VLC processing on the bit stream using the acquired dedicated program for audio VLC processing, and writes the processing result in the shared portion of the local memory.
On the other hand, when the BPC 101 acquires the bit stream of the image, the BPC 101 performs VLC processing on the bit stream using the acquired dedicated program for image VLC processing, and writes the processing result in the shared part of the local memory.

Furthermore, based on FIG. 6, processing result data transmission processing and processing in each BPC of the information processing unit 11 will be described.
When the processing result is written to the shared part of the local memory of each BPC in the first information processing unit 10, the processing result of the BPC 100 is sent to the second information processing unit via the L bus 112 as shown in FIG. 11 is transmitted to the BPC 110, and the processing result of the BPC 101 is transmitted to the BPC 111 of the second information processing unit 11 via the L bus 113.

When the BPC 110 acquires the processing result data, the BPC 110 performs IMDCT processing on the data by the acquired dedicated program for IMDCT processing, and writes the processing result in the shared unit of the local memory.
On the other hand, when the BPC 111 acquires the processing result data, the BPC 111 performs DCT processing on the data by the acquired dedicated program for DCT processing, and writes the processing result in the shared part of the local memory.

  Here, in the present embodiment, a new MPEG2 standard bit stream is transmitted from the IOP 13 to the first information processing unit 10 while the second information processing unit 11 performs the above-described processing. The audio VLC process and the image VLC process described above are performed. That is, in the present embodiment, the same processing target (standard) data sent continuously is processed in parallel with other information processing units.

Furthermore, the processing result data transmission processing and the processing in each BPC of the information processing unit 12 will be described with reference to FIG.
When the processing result is written in the shared part of the local memory of each BPC in the second information processing unit 11, the processing result of the BPC 110 is transmitted to the third information processing unit via the L bus 122 as shown in FIG. 12, and the processing result of the BPC 111 is transmitted to the BPC 121 of the third information processing unit 12 via the L bus 123.

When the BPC 120 acquires the processing result data, the BPC 120 performs a filtering process on the data by the acquired dedicated program for the filtering process, and writes the processing result in the shared part of the local memory.
On the other hand, when the BPC 121 acquires the processing result data, the BPC 121 performs a motion compensation process on the data by the acquired dedicated program for the motion compensation process, and writes the processing result in the shared part of the local memory.

Here, while the above-described processing is being performed in the third information processing unit 12, the second information processing unit 11 also performs the next processing in the first information processing unit 10 as in the first information processing unit 10. The above processing is performed on the processing result data.
Furthermore, based on FIG. 8, the transmission process of processing result data and the output shaping process in the BPC 131 of the information processing unit 12 will be described.

When the processing result is written in the shared part of the local memory of each BPC in the third information processing unit 12, the processing result of the BPC 120 and BPC 121 is sent to the fourth information via the L bus 133 as shown in FIG. The data is transmitted to the BPC 131 of the processing unit 16.
When the BPC 131 acquires the processing result data for the audio and image bitstreams, the BPC 131 performs processing for shaping the data into output data depending on the external I / O by the acquired dedicated program for output shaping processing. And write the processing result to the shared part of the local memory.

Here, while the above-described processing is performed in the fourth information processing unit 16, the third information processing unit 12 also performs the same processing as the first information processing unit 10 and the second information processing unit 11. The above processing is performed on the next processing result data in the second information processing unit 11.
Further, the final process result data transmission process will be described with reference to FIG.
When the processing result is written to the shared part of the local memory of the BPC 131 in the fourth information processing unit 16, as shown in FIG. 9, the processing result data of the BPC 131 is the L bus 102, The data is transmitted to the IOP 13 via the bus bridge 104 and the G bus 14. These data are stored in the data storage unit 15 by the IOP 13.

Furthermore, the flow of operation processing of the IOP 13 will be described with reference to FIG. FIG. 10 is a flowchart showing the operation process of the IOP 13.
As shown in FIG. 10, first, the process proceeds to step S100, where it is determined whether or not an external command has been acquired in IOP13. If it is determined that the command has been acquired (Yes), the process proceeds to step S102; If (No), wait until acquisition.

When the process proceeds to step S102, the IOP 13 analyzes the command and proceeds to step S104.
In step S104, the corresponding dedicated program is selected in IOP13 based on the analysis result, and the process proceeds to step S106.
In step S106, in IOP13, based on the selected dedicated program and the configuration of the information processing unit of the information processing apparatus, a configuration for performing processing is set, and the process proceeds to step S108.

In step S108, in the IOP 13, based on the set configuration content, the selected dedicated program is read from the data storage unit 15, and the process proceeds to step S110.
In step S110, in the IOP 13, the read dedicated program is transmitted to the corresponding BPC via the G bus 14, the bus bridge, and the L bus, and the process proceeds to step S112.

In step S112, in IOP13, it is determined whether or not the dedicated program transmission process has been completed. If it is determined that the process has ended (Yes), the process proceeds to step S114. If not (No), the process proceeds to step S108. To do.
When the process proceeds to step S114, the processing countermeasure data is read from the data storage unit 15 in the IOP 13, and the process proceeds to step S116.

In step S116, the IOP 13 analyzes the read processing data, extracts the processing data, and transmits the processing data to each BPC of the information processing unit that starts the preset processing, and proceeds to step S118. To do.
In step S118, in IOP13, it is determined whether or not the data of the final processing result has been acquired. If it is determined that the data has been acquired (Yes), the process proceeds to step S120. If not (No), the process proceeds to step S122. To do.

If the process proceeds to step S120, the acquired processing result data is stored in the data storage unit 15 in the IOP 13, and the process proceeds to step S122.
In step S122, in IOP13, it is determined whether or not the process for the command has been completed. If it is determined that the process has been completed (Yes), the process proceeds to step S100. If not (No), the process proceeds to step S114.

  Further, based on FIG. 11 and FIG. 12, the MPEG2 standard bitstream decoding process is performed by the information processing apparatus 4 constituted by the two information processing units, the first information processing unit 10 and the second information processing unit 11. An example of performing this will be described. FIG. 11 is a diagram illustrating processing of the (2N−1) -th cycle by the first information processing unit 10 and the second information processing unit 11, and FIG. 12 illustrates the first information processing unit 10 and the second information processing unit 10. It is a figure which shows the process of the 2Nth round by the information processing part. 11 and 12, N is a positive integer (N = 1, 2, 3,...).

The information processing apparatus 4 includes a first information processing unit 10, a second information processing unit 11, an I / O control processor (hereinafter referred to as IOP) 13, and a global bus (hereinafter referred to as G bus) 14. And a data storage unit 15. In addition, description of the overlapping part with the said information processing apparatus 1 is abbreviate | omitted.
Further, since the first information processing unit 10 and the second information processing unit 11 are configured, the output from the BPC in the second information processing unit 11 is transmitted to the first information processing unit 10 by the L bus 102 or The data is transmitted to each BPC via the L bus 103. That is, the BPC 110 and the BPC 111 in the second information processing unit 11 are connected to the L bus 102 and the L bus 103 in the first information processing unit 10, respectively. It is possible to transmit the processing result data to the first information processing unit 10. That is, loop transmission of data is possible.

  Furthermore, the flow of dedicated program setting processing will be described. First, when the IOP 13 acquires an external command, the IOP 13 analyzes the command and confirms that the MPEG2 standard bitstream stored in the designated address of the data storage unit 15 is to be combined. Then, from among a plurality of types of dedicated programs prepared in the data storage unit 15, a dedicated program necessary for decoding the MPEG2 standard bit stream is selected. Further, based on the selected dedicated program, a configuration necessary for performing arithmetic processing by the dedicated program is set. The setting contents vary depending on the number of dedicated programs and the number of types of data to be processed. Here, in the case of a bit stream of the MPEG2 standard, there are two types of data to be processed: an image bit stream and an audio bit stream, and each processing step is four steps. However, the fourth step is processing for the combined data, and can be processed by a common dedicated program (algorithm) for the image and audio bit streams.

Similarly to the above, there are four image bitstreams: image VLC processing, IDCT processing, motion compensation processing, and output shaping processing. For audio bitstreams, audio VLC processing, IMDCT processing, There are four types of filter processing and output shaping processing.
Therefore, as the setting contents, the two information processing units of the first and second information processing units 10 and 11 are used, and the BPC of the first information processing unit 10 has two types of dedicated programs for each BPC. Allocating and setting is such that one type of dedicated program is allocated to the BPC 110 of the second information processing unit 11 and two types of dedicated programs are allocated to the BPC 111. Then, the BPC 100 and the BPC 110 in the first and second information processing units 10 and 11 are set to perform an audio bitstream decoding process, and the BPC 101 in the first and second information processing units 10 and 11 are set. The BPC 111 is set to perform the composite processing of the bit stream of the image.

  Further, based on the set contents, each dedicated program is read from the data storage unit 15 and transmitted to the corresponding BPC via the G bus 14 and the L bus corresponding to each BPC. Here, in the present embodiment, the first information processing unit 10 is set in advance to start the composite processing, and the flow direction of the processing is also first to second to first to first. ... is set.

  Then, for the BPC 100 in the first information processing unit 10, the IOP 13 reads out a dedicated program for audio VLC processing and a dedicated program for filter processing for the audio bitstream from the data storage unit 15. 14 This dedicated program reaches the bus bridge 114 via the G bus 14, and further reaches the BPC 100 via the L bus 112 by the bus bridge 114. More precisely, the data is written to the shared part of the local memory 100b of the BPC 100 via the L bus 112. For other BPCs, a dedicated program for image VLC processing and a dedicated program for motion compensation are transmitted to the BPC 101 via the L bus 112, and a dedicated program for IMDCT processing is transmitted to the BPC 110 via the L bus 102. The dedicated program for IDCT processing and the dedicated program for output shaping processing are transmitted to the BPC 111 via the L bus 102.

  For transmission of processing data, first, in the IOP 13, a bit stream conforming to the MPEG2 standard to be processed is read from the data storage unit 15 and stored in the internal memory. Then, the MPEG2 standard bit stream stored in the internal memory is analyzed and separated into an audio bit stream and an image bit stream. Each separated bit stream is transmitted to each BPC of the corresponding information processing unit. As described above, since processing is started from the first information processing unit 10, the audio bit stream is transmitted to the BPC 100 via the G bus 14, the bus bridge 104, and the L bus 102, and the image bit stream is The data is transmitted to the BPC 101 via the G bus 14, the bus bridge 105 and the L bus 103.

Furthermore, the process in each BPC of the first information processing unit 10 and the second information processing unit 11 in the (2N-1) th lap will be described with reference to FIG.
In the (2N-1) -th cycle processing, the BPC 100 acquires an audio bitstream from the IOP 13, performs VLC processing on the bitstream by the acquired dedicated program for audio VLC processing, and outputs the processing result. Write to shared part of local memory. Then, when the processing result is written in the sharing unit, the currently set dedicated program for the audio VLC processing is changed to the other acquired dedicated program for the filter processing.

  On the other hand, the BPC 101 acquires a bit stream of an image from the IOP 13, performs VLC processing on the bit stream using the acquired dedicated program for image VLC processing, and writes the processing result to a shared part of the local memory. When the processing result is written in the sharing unit, the currently set dedicated program for image VLC processing is changed to the other dedicated program for motion compensation processing that has been acquired.

Further, when the processing result is written to the shared part of the local memory of each BPC in the first information processing unit 10, the processing result of the BPC 100 is transmitted to the BPC 110 of the second information processing unit 11 via the L bus 112. Then, the processing result of the BPC 101 is transmitted to the BPC 111 of the second information processing unit 11 via the L bus 113.
When the BPC 110 acquires the processing result data, the BPC 110 performs IMDCT processing on the data by the acquired dedicated program for IMDCT processing, and writes the processing result in the shared unit of the local memory.

  On the other hand, when the BPC 111 acquires the processing result data, the BPC 111 performs DCT processing on the data by the acquired dedicated program for DCT processing, and writes the processing result in the shared part of the local memory. Then, when the processing result is written in the sharing unit, the currently set dedicated program for DCT processing is changed to the other acquired dedicated program for output shaping processing.

Furthermore, the processing in each BPC of the first information processing unit 10 and the second information processing unit 11 in the 2Nth cycle will be described with reference to FIG.
When the processing result is written to the shared part of the local memory of each BPC in the second information processing unit 11, the processing result of the BPC 110 is transmitted to the BPC 100 of the first information processing unit 10 via the L bus 122. The processing result of the BPC 111 is transmitted to the BPC 101 of the first information processing unit 10 via the L bus 123.

  When the BPC 100 acquires the processing result data, the BPC 100 performs a filtering process on the data with the changed dedicated program for the filtering process, and writes the processing result in the shared part of the local memory. When the processing result is written in the shared unit, the currently set dedicated program for filter processing is changed to another dedicated program for audio VLC processing.

  On the other hand, when the BPC 101 obtains the processing result data, the BPC 101 performs motion compensation processing on the data by the changed dedicated program for motion compensation processing, and writes the processing result in the sharing unit of the local memory. Then, when the processing result is written in the sharing unit, the currently set dedicated program for motion compensation processing is changed to another dedicated program for image VLC processing.

Further, when the processing result is written in the local memory sharing unit of each BPC in the first information processing unit 10, the processing results of the BPC 100 and BPC 101 are transmitted to the BPC 111 of the second information processing unit 11 via the L bus 113. Is transmitted.
When the BPC 111 acquires the processing result data for the audio and image bitstreams, the BPC 111 performs processing for shaping the data into output data depending on the external I / O by the acquired dedicated program for output shaping processing. And write the processing result to the shared part of the local memory.

  Further, when the processing result is written to the shared part of the local memory of the BPC 131 in the second information processing unit 10 in the 2Nth cycle, the processing result data of the BPC 131 is converted into the L bus 102 and the bus as the final combined data. The data is transmitted to the IOP 13 via the bridge 104 and the G bus 14. These data are stored in the data storage unit 15 by the IOP 13. After transmitting the processing result data, the BPC 131 changes the currently set dedicated program for output shaping to another dedicated program for IDCT processing.

That is, for the audio bit stream, the audio VLC process and the IMDCT process are performed by the BPC 100 and the BPC 110 of the first information processing unit 10 and the second information processing unit 11 on the (2N-1) th cycle. As a round, filter processing is performed by the BPC 100 of the first information processing unit 10 using the processing result of the BPC 110 of the (2N-1) th round.
On the other hand, for the image bit stream, as the (2N-1) th cycle, the BPC 101 and the BPC 111 of the first information processing unit 10 and the second information processing unit 11 perform image VLC processing and IDCT processing. As a round, motion compensation processing and output shaping processing are performed by the BPC 101 and the BPC 111 of the first information processing unit 10 and the second information processing unit 11 using the processing result of the BPC 111 of the (2N-1) th round. .

As described above, according to the above-described embodiment, it is possible to select a corresponding dedicated program from a plurality of types of dedicated programs and set it in each BPC to perform processing according to the processing target. .
Further, since each BPC has a dedicated L bus, the collision that occurs in the shared bus does not occur.

Further, since each information processing unit is configured by two BPCs, it is possible to perform processing on two types of data in parallel.
In addition, since a plurality of information processing apparatuses are connected by the L bus, a plurality of processing contents can be distributed.
In addition, since the information processing units at both ends are connected by the L bus and the dedicated program set in each BPC can be changed, the processing result data is looped in the information processing units connected through the L bus. It is possible to change the dedicated program set in the BPC in the (2N-1) th and 2Nth cycles according to the flow of processing.

  Here, BPC shown in FIG. 1 to FIG. 9, FIG. 11 and FIG. 12 corresponds to the arithmetic processing unit of any one of inventions 1 to 8, and the L bus corresponds to the data transmission line of invention 1 or 4. The processing target data acquisition process by the data storage unit 15 and the IOP 13 corresponds to the processing target data acquisition unit of the invention 1, and the selection of the dedicated program and the setting process to the BPC by the data storage unit 15, the IOP 13 and the BPC are as follows. Corresponding to the dedicated program setting means of the invention 1 or 7, the processing for transmitting the processing data to the BPC by the IOP 13 corresponds to the processing data supply means of the invention 3, and performs the arithmetic processing by the dedicated program in the IOP 13. The processing for setting the necessary configuration corresponds to the arithmetic processing unit setting means of the invention 7, and the dedicated program in each BPC shown in FIGS. Process changes, corresponding to the program change means of the present invention 5 or 6.

In the above embodiment, when the dedicated program is transmitted to each BPC of the information processing unit in the preceding stage, it is transmitted via the L bus for the BPC in the subsequent stage. When the dedicated program is transmitted to the BPC, it may be transmitted via the L bus for each BPC.
Further, in the above-described embodiment, the dedicated program change process is determined by each BPC, but is not limited thereto, and may be performed by the control of the IOP 13.

  Further, in the above-described embodiment, the process of combining the MPEG2 standard bit stream is described as an example. However, the present invention is not limited to this, and processes for other MPEG standards such as MPEG1 and MPEG4 are included in the picture. You may apply with respect to other processes, such as the picture in picture process and routing process which display another picture.

It is a block diagram which shows one structural example of the information processing apparatus which concerns on this invention. It is a block diagram which shows the detailed structure of BPC. It is a figure which shows an example of the structure image of information processing apparatus. It is a figure which shows an example which sets a dedicated program to BPC. FIG. 3 is a diagram illustrating an example of a data flow and processing in the first information processing unit 10 when transmitting processing target data to a BPC. 3 is a diagram illustrating an example of a data flow from the first information processing unit 10 to a second information processing unit 11 and an example of processing in the second information processing unit 11. FIG. 6 is a diagram illustrating an example of a data flow from the second information processing unit 11 to the third information processing unit 12 and an example of processing in the third information processing unit 12. FIG. 6 is a diagram illustrating an example of a data flow from the third information processing unit 12 to a fourth information processing unit 13 and an example of processing in the fourth information processing unit 13; FIG. It is a figure which shows an example of the process which memorize | stores the compounded data in the data storage part 15 via IOP13. It is a flowchart which shows the operation | movement process of IOP13. It is a figure which shows the process of the (2N-1) th round by the 1st information processing part 10 and the 2nd information processing part 11. FIG. It is a figure which shows the 2Nth round process by the 1st information processing part 10 and the 2nd information processing part 11. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 3, 4 ... Information processing apparatus, 2 ... Information processing apparatus (image), 10-12 ... 1st-3rd information processing part, 13 ... IOP, 14 ... G bus, 15 ... Data storage part, 16 ... Fourth information processing unit, 100, 101, 110, 111, 120, 121, 130, 131... BPC, 102, 103, 112, 113, 122, 123, 132, 133 ... L bus, 104, 105, 114, 115, 124, 125, 134, 135 ... bus bridge

Claims (8)

An information processing apparatus for processing objects to be processed in parallel by a plurality of processing units,
Each arithmetic processing unit includes a dedicated data transmission line,
The plurality of arithmetic processing units are grouped into a plurality of stages, and each stage is connected via the data transmission line,
Processing target data acquisition means for acquiring processing target data which is the processing target data;
Based on the processing target, the dedicated program for the processing target from among a plurality of types of dedicated programs for causing the plurality of arithmetic processing devices to perform predetermined processing according to the processing content of the processing target data in parallel A dedicated program setting means for selecting and setting each of the processing units,
The arithmetic processing unit performs arithmetic processing by the set dedicated program, and the arithmetic processing result data is processed by using the arithmetic processing result data. An information processing apparatus which is adapted to transmit via a network.   The information processing apparatus according to claim 1, wherein each of the stages grouped into the plurality of stages is configured by two or more arithmetic processing devices.   Processing data supply means for supplying processing data for causing the arithmetic processing devices of the respective stages to perform the predetermined arithmetic processing in parallel based on the processing target data to the arithmetic processing device for starting the arithmetic processing. The information processing apparatus according to claim 2.   The information processing apparatus according to claim 1, wherein the plurality of groups are connected in a ring shape through the data transmission line.   5. The information processing apparatus according to claim 4, further comprising program changing means for changing the dedicated program set in the arithmetic processing apparatus to another type at a predetermined timing. The predetermined timing is a timing at which a series of arithmetic processing is performed a predetermined number of times by each arithmetic processing device from the start stage to the final stage of the arithmetic processing in the plurality of stages.
6. The information processing apparatus according to claim 5, wherein, at the timing, the program changing unit changes the dedicated program of the arithmetic processing device at each stage to another type of program that continues the series of arithmetic processing. .   Based on the dedicated program selected by the dedicated program setting means, the number of stages of the arithmetic processing device, and the number of arithmetic processing devices in each stage, the processing target for the processing target is selected from the plurality of arithmetic processing devices. The information processing apparatus according to claim 1, further comprising: an arithmetic processing device setting unit that sets an arithmetic processing device that performs predetermined arithmetic processing. A computer-executable program for controlling the information processing apparatus according to claim 1,
A processing target data acquisition step for acquiring processing target data which is the common processing target data;
A dedicated program setting step for selecting the dedicated program for the processing target from the plurality of types of dedicated programs and setting the dedicated program for each processing unit based on the processing target. Processor control program.

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