JP2005064663A - Voltage controlled oscillator and pll frequency synthesizer modulation circuit using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage controlled oscillator in which the degree of modulation can easily be controlled and the change of the degree of modulation due to the change of ambient temperature is suppressed, and to provide a PLL frequency synthesizer modulation circuit using the oscillator. <P>SOLUTION: A voltage controlled oscillator 1 having control terminals V<SB>t</SB>and V<SB>m</SB>is provided with a variable capacity diode 21 controlled by an analog signal inputted from the control terminal V<SB>t</SB>and a switching capacitor element 22 controlled by a digital signal inputted from the control terminal V<SB>m</SB>. The variable capacity diode 21 controls oscillation frequency, and the switching capacitor element 22 modulates it. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a voltage controlled oscillator and a PLL frequency synthesizer modulation circuit using the same.

  A modulation circuit using a PLL frequency synthesizer having a PLL circuit is generally well known. Such a modulation circuit includes a variable frequency divider, a voltage controlled oscillator, and the like, and changes the frequency dividing ratio of the variable frequency divider at high speed to output a modulated RF (Radio Frequency) output from the voltage controlled oscillator. Get the signal. The modulation circuit using this PLL frequency synthesizer has fewer analog circuits for handling RF signals than a modulator using a mixer circuit, and is a small number of analog circuits for configuring the PLL and a digital circuit for control. Since it can be configured, there is an advantage that current consumption can be reduced.

  However, since the modulation signal band of the modulation circuit using the PLL frequency synthesizer is limited to the loop band of the PLL frequency synthesizer, it can be modulated with a narrow band modulation signal. However, in recent mobile communication systems, etc. The wideband modulation employed cannot be applied. Thus, attention is paid to a two-point modulation type PLL synthesizer that applies a modulation signal directly to the control terminal of the voltage controlled oscillator at the same time as modulation is performed by changing the division ratio of the variable frequency divider (see, for example, Patent Document 1). ).

  FIG. 8 is a schematic configuration diagram showing a conventional PLL synthesizer. As shown in FIG. 8, this PLL synthesizer includes a voltage controlled oscillator 81, a variable frequency divider 82, a phase comparator 83, and a loop filter 84.

The oscillation frequency of the voltage controlled oscillator 81 is controlled by a voltage applied to the control terminal V _t, and outputs a RF signal 802. The variable frequency divider 82 divides the RF signal 802 output from the voltage controlled oscillator 81. The phase comparator 83 compares the output signal of the variable frequency divider 82 and the phase of the reference signal 801, and outputs a signal corresponding to the phase difference. The loop filter 84 averages the output of the phase comparator.

Further, the PLL synthesizer shown in FIG. 8 has a modulation sensitivity table 85 that outputs a modulation signal based on the modulation data 803, a control unit 86 that outputs channel selection data 804 and a gain control signal 805, and an output from the control unit 86. A DA converter 88 that adjusts the gain according to the gain control signal 805 and converts the output signal of the modulation sensitivity table 85 into an analog voltage, and a signal obtained by adding channel selection information to the output signal from the modulation sensitivity table 85 a delta-sigma modulator 87 for output to the variable frequency divider 87 as a multiplied frequency division ratio delta-sigma modulation, the control unit 85 a voltage value input to the voltage terminal V _t is converted into a digital value of the voltage controlled oscillator 81 An AD converter 89 for output.

Regarding the modulation operation, the modulation within the band of the loop filter 84 is performed by changing the division ratio of the variable frequency divider 82, and the modulation outside the band of the loop filter 84 is performed by the control terminal V of the voltage controlled oscillator 81. _This is done by giving directly to _t . As a result, an RF modulation signal 802 is obtained from the output of the voltage controlled oscillator 81. At this time, the modulation signal applied to the control terminal V _t of the voltage controlled oscillator 81 is obtained by combining the output voltage of the loop filter 84 the digital modulated data 803 into an analog value by the DA converter 88.

In two-point modulation scheme described above, fluctuation of the oscillation frequency f of the voltage controlled oscillator 81 for amplitude variations of the modulated signal applied to the V _t, i.e. the frequency sensitivity K _m for the modulation signal is always must be constant. It shall be frequency sensitivity K _m fluctuates, will be the band of modulation i.e. the modulation signal is changed, in order to lead to deterioration of modulation characteristics.

Here, the voltage controlled oscillator used in the PLL modulation circuit usually includes a variable capacitance diode. However, due to the nonlinearity of the variable capacitance diode, the frequency sensitivity K _m fluctuates. Figure 9 is a diagram showing changes in the frequency sensitivity K _m. 9, the voltage input to the control terminal V _t of the voltage controlled oscillator 81 - the tangent slope of each point in the oscillation frequency characteristics showing a frequency sensitivity K _m. As is clear from FIG. 9, it can be seen that the frequency sensitivity K _m is different at different frequencies (for example, f ₁ and f ₃ ).

Therefore, in the example shown in FIG. 8, the control voltage V _t of the voltage controlled oscillator 81 is detected by the AD converter 89, and the frequency sensitivity K _m is calculated by the control unit 86. Here, the oscillation frequency of the voltage controlled oscillator 81 is known from the channel selection data 804 output from the control unit 86. Therefore, the frequency sensitivity K _m is obtained by dividing the frequency change amount Δf at the time of channel switching by the voltage change amount ΔV _t detected by the AD converter 89. That is, when the frequency sensitivity is K _m , K _m = Δf / ΔV _t . This result is stored in the modulation degree table 85, and the gain of the DA converter 88 is controlled with reference to the table according to the channel selection data 804 to correct the amplitude of the modulation signal.

Further, when the lock operation is performed as the PLL frequency synthesizer, the frequency sensitivity K _{m is} detected and the table data of the modulation degree table 85 is updated when the channel is switched to the adjacent or next adjacent (f ₁ and f ₂ ). To do. Thus, variations in the modulation degree so allows the correction of frequency sensitivity K _m in accordance with the operating environment can be suppressed.
US Pat. No. 6,211,747

However, in the conventional PLL frequency synthesizer modulation circuit, the voltage V _t when the channel frequency is locked is sampled, the frequency sensitivity K _m corresponding to the channel frequency is calculated, and the modulation degree table is created. There is a need. This is because the frequency sensitivity fluctuation is caused by the non-linearity of the variable capacitance diode, and has a unique value due to the element variation for each individual. Therefore, it takes a lot of man-hours to create the modulation degree table.

Furthermore, when the ambient temperature changes during the operation of the PLL frequency synthesizer, the frequency sensitivity changes due to the temperature change of the variable capacitance diode characteristics, so the modulation degree table needs to be updated. However, for detection of frequency sensitivity K _m, it is necessary to switch spite of channels. Furthermore, this switching must be a minute frequency change between adjacent or next adjacent. However, when this temperature change occurs, channel switching to the adjacent or the next adjacent does not always occur, and there is a possibility that the degree of modulation is deteriorated.

  The present invention has been made in order to solve the above-described conventional problems, and it is easy to control the degree of modulation, and further, a voltage-controlled oscillator that suppresses changes in the degree of modulation due to changes in ambient temperature, and a PLL using the same An object of the present invention is to provide a frequency synthesizer modulation circuit.

  A voltage-controlled oscillator according to the present invention is a voltage-controlled oscillator including a resonator including a variable capacitance diode whose capacitance value changes based on an analog input signal for controlling an oscillation frequency. It has a configuration including a switching capacitor whose capacitance value is switched based on a digital signal.

  With this configuration, the capacitance change value with respect to the modulation signal can be digitally controlled, so that the change ratio of the capacitance with respect to the modulation signal does not depend on the carrier frequency, and the modulation degree can be easily controlled. Furthermore, since the change ratio of the switching capacitance does not change with respect to the temperature, the change in the modulation factor can be suppressed.

  Furthermore, in the voltage controlled oscillator of the present invention, a plurality of the switching capacitors are connected in parallel, and the capacitance values of the plurality of switching capacitors are switched based on the corresponding bits of the input digital signal, The modulation is performed by changing the total capacitance value of the plurality of switching capacitors.

  With this configuration, the modulation degree can be controlled more finely by switching the capacitance values of a plurality of switching capacitors.

  The voltage controlled oscillator according to the present invention has a configuration in which the plurality of switching capacitors have substantially the same capacitance value.

  With this configuration, each switching capacitor can be configured on the basis of substantially the same layout shape, so that the relative variation of the capacitance value can be suppressed and suppressed.

  A PLL frequency synthesizer modulation circuit according to the present invention includes a voltage controlled oscillator, a frequency divider that divides the output of the voltage controlled oscillator, a phase comparator connected to an output side of the frequency divider, and the phase comparator A charge pump connected to the subsequent stage, and a loop filter connected to the subsequent stage of the charge pump and outputting the analog signal input to the voltage controlled oscillator, wherein the analog signal is generated based on carrier frequency data The digital signal is generated based on the modulation data.

  With this configuration, the PLL closed-loop control signal for generating the channel frequency is analog, so that a good C / N characteristic can be obtained. Further, since the modulation data is given as a digital signal and the switching capacitance value is controlled, the change ratio of the capacitance with respect to the modulation signal does not depend on the carrier frequency, and the modulation degree can be easily controlled.

  Further, in the PLL frequency synthesizer modulation circuit of the present invention, the frequency divider variably controls the frequency division ratio based on the carrier frequency data and the modulation data, and the switching capacity of the voltage controlled oscillator is controlled based on the modulation data. It has a configuration to control.

  With this configuration, modulation data is digitally supplied to the switching capacitor, so that adjustment with the timing for applying modulation is easy even when a variable frequency divider is used.

  Further, the PLL frequency synthesizer modulation circuit of the present invention further includes a direct digital synthesizer, the direct digital synthesizer outputs a control signal based on the modulation data and the carrier frequency data, and the frequency divider is a frequency division ratio fixed. A frequency divider configured to control the oscillation frequency of the voltage controlled oscillator based on the output of the direct digital synthesizer and the output of the frequency divider.

  With this configuration, the power consumption of the PLL frequency synthesizer can be reduced.

  The PLL frequency synthesizer modulation circuit according to the present invention further includes a correction table calculated based on the carrier frequency data, and the digital signal has a configuration in which the modulation data is corrected using the correction table.

  With this configuration, the frequency sensitivity can be kept constant regardless of the change in the capacitance value of the variable capacitance diode.

  The polar modulation system of the present invention includes a PLL frequency synthesizer modulation circuit, a modulation signal generation unit that separates the modulation data into phase modulation data and amplitude modulation data, and outputs the phase modulation data to the PLL frequency synthesizer modulation circuit. And a polar modulator that generates a modulation signal based on the output of the voltage controlled oscillator of the PLL frequency synthesizer modulation circuit and the amplitude modulation data output from the modulation signal generator.

  With this configuration, since modulation is performed with digital modulation data, timing adjustment of phase modulation data and amplitude modulation data when generating a modulation signal can be easily performed.

  The modulation degree table calculation method of the present invention is a correction table calculation method for correcting the modulation degree of a PLL frequency synthesizer modulation circuit, and is provided in a voltage controlled oscillator based on carrier frequency data for controlling a carrier frequency. A step of calculating a correction value depending on the capacitance value of the variable capacitance diode is provided.

  Since the correction value is calculated based on the carrier frequency by this method, the modulation degree correction table can be set in advance, so that deterioration of the modulation degree can be prevented.

  According to the present invention, it is possible to provide a voltage-controlled oscillator that can easily control the degree of modulation and that suppresses a change in the degree of modulation caused by a change in ambient temperature, and a PLL frequency synthesizer modulation circuit using the voltage-controlled oscillator.

(First embodiment)
FIG. 1 is a schematic configuration diagram showing a PLL frequency synthesizer modulation circuit for explaining a first embodiment of the present invention. As shown in FIG. 1, the PLL frequency synthesizer modulation circuit 10 of the present embodiment includes a voltage-controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a charge pump that converts the control signal to the voltage-controlled oscillator 1. 4, a loop filter 5, a frequency division ratio generation unit 6, a modulation degree correction table 7, and a variable amplifier 8.

The voltage controlled oscillator 1 generates and outputs an RF modulation signal 102. The variable frequency divider 2 divides the RF modulation signal 102 output from the voltage controlled oscillator 1. The phase comparator 3 compares the phase of the reference signal 101 with the phase of the output signal of the variable frequency divider 2 and outputs a signal corresponding to the phase difference. The charge pump 4 converts the output signal of the phase comparator 3 into a control signal of the voltage controlled oscillator 1. Loop filter 5, the output signal of the charge pump 4 is smoothed, and outputs to the control terminal V _t of the voltage controlled oscillator 1. The oscillation frequency of the voltage controlled oscillator 1 is controlled by a voltage applied to the control terminal V _t.

  Further, the PLL frequency synthesizer modulation circuit 10 includes a frequency division ratio generation unit 6, a modulation degree correction table 7, and a variable amplifier 8, and performs a modulation operation.

The frequency division ratio generation unit 6 generates a signal for controlling the frequency division ratio of the variable frequency divider 2 based on the carrier frequency data 103 and the modulation data 104. The variable amplifier 8 controls the amplitude of the modulation data 104 and generates a signal applied to the V _m terminal of the voltage controlled oscillator 1. At this time, the amplification degree of the variable amplifier 8 is controlled by the modulation degree correction table 7 that outputs a signal corresponding to the carrier frequency data 103.

The above modulation operation is performed by changing the frequency division ratio of the variable frequency divider 2 for modulation below the band of the loop filter 5, and voltage control is performed with a digital signal for modulation above the band of the loop filter 5. This is done by applying the signal directly to the control terminal V _m of the oscillator 1.

Voltage controlled oscillator 1, a variable capacitance diode 21, such as a varactor diode, a switching capacitor 22, variable capacitance diode 21 controls the oscillation frequency based on the control voltage of the analog signal applied to the control terminal V _t, switching capacity 22 is to apply a modulated based on the digital signal supplied to the control terminal V _m.

  FIG. 2 is a diagram illustrating an example of a voltage-controlled oscillator for explaining the first embodiment of the present invention. This voltage controlled oscillator 1 includes a variable capacitance diode 21, n switching capacitors 22 (1), 22 (2),..., 22 (n−1), 22 (n) (n ≧ 1), a fixed capacitor. 23 and an LC resonance type oscillator including a resonator having an inductor 24 and an oscillator having an active element 25.

The variable capacitance diode 21, the switching capacitor 22, the fixed capacitor 23, and the inductor 24 are grounded at one end and connected in parallel. Further, the switching capacitors 22 (1), 22 (2),..., 22 (n−1), 22 (n) are connected to the control terminals V _{m (1)} , V _{m (2)} ,. Capacitance values are switched by signals input to _{m (n−1)} and V _{m (n)} , respectively.

Here, the capacitance of the variable capacitance diode 21 is C _v , and the capacitance values of the switching capacitors 22 (1), 22 (2),..., 22 (n−1), and 22 (n) are C ₁ and C ₂ , respectively. ,..., C _n−1 , C _n , the capacitance value of the fixed capacitor 23 is C _o , and the inductance of the inductor 24 is L _o , the oscillation frequency f _osc of the voltage controlled oscillator 1 is expressed by the following equation (1).

Here, the capacitance value C _v of the variable capacitance diode 21, the oscillation frequency is controlled by a voltage applied to the control terminal V _t, to determine the carrier frequency. The capacitance values C ₁ , C ₂ ,..., C _n−1 , C _n of the switching capacitors 22 (1), 22 (2),..., 22 (n−1), 22 (n) are controlled. The carrier frequency is modulated by switching the capacitance value according to the modulation data applied to the terminal V _{m (1: n)} and controlling the capacitance value. The modulation data given to the switching capacitors 22 (1) to 22 (n) is given as a digital signal, and the corresponding control terminals _{Vm (1)} to _{Vm (n)} have, for example, bits of the digital signal. The information constituting the modulation signal corresponding to the control terminals V _{m (1)} to V _{m (n)} is input.

3 and 4 are diagrams illustrating a configuration example of the switching capacitor 22. In the switching capacitor shown in FIG. 3, a fixed capacitor 31 and a switching transistor 32 are connected in series, and the capacitance value is switched to a binary value by turning on and off the transistor by a control voltage D _n applied to the V _m terminal. is there. The switching capacitance shown in FIG. 4 connects the drain and the source of the MOS transistor 41 in common, and switches the channel capacitance between the gate and the drain-source to a binary value by the control voltage D _n applied to the V _m terminal.

Figure 5 shows how the capacitance change with respect to the control voltage D _n of the switching capacity. 5, the control voltage _{D n} is in the region of the voltage value of near 0V and _{V cc,} the capacitance value is changed to a binary C_H and C_L. Therefore, the capacitance value can be switched to a binary value by a digital signal.

  Here, as a transistor included in the switching capacitor of the present embodiment as shown in FIGS. 3 and 4, an Nch or PchMOS transistor, a bipolar transistor, an element for performing a switching operation, or the like is used. Further, the capacitor can be composed of a MIM (Metal Insulator Metal) structure, a MOS structure, or the like. Further, a fringe capacity using a capacity between cross sections of parallel wirings may be used. The fringe capacity is generally said to have good absolute accuracy.

  Further, when configuring the switching capacitors, it is preferable to configure all the switching capacitors based on a common minimum unit capacity. For example, when the minimum unit of the switching capacity is 10 fF and a capacity of 100 fF is configured, 10 capacitors of 10 fF are connected in parallel to obtain 100 fF. As a result, each switching capacitor can be configured based on substantially the same layout shape, so that relative variations in capacitance values can be suppressed.

  According to the voltage controlled oscillator 1 of the first embodiment, since the capacitance change value for the modulation signal can be digitally controlled by the switching capacitor, the change ratio of the capacitance for the modulation signal does not depend on the carrier frequency, and the modulation is performed. The degree of control becomes easier. Furthermore, since the change ratio of the switching capacitance does not change with respect to the temperature, it is possible to suppress the change in the modulation factor due to the temperature change. If a plurality of switching capacitors are provided, the total capacitance value can be changed by switching control of each switching capacitor, and the modulation degree can be controlled more finely.

Hereinafter, we describe the calculation of the frequency sensitivity K _m when controlling the switching capacitance. Since the frequency sensitivity K _m for the modulation signal of the voltage controlled oscillator is a change in frequency with respect to the change in the capacitance of the switching capacitor controlled by the digital signal, the frequency sensitivity K _m can be expressed as in Equation 2.

Therefore, f _osc of _{Equation 1} is differentiated by the sum of switching capacitances (C ₁ + C ₂ +... + C _n−1 + C _n ). _Equation 3 shows a value f ′ _osc obtained by differentiating _fosc .

Here, the band of the channel frequency is several hundred MHz, whereas the band of the modulation signal is several MHz. Therefore, the sum of the capacitance values _{{C o + C v + (} C 1 + C 2 + ··· + C n-1 + C n)} to the sum of the switching capacity _{(C 1 + C 2 + ···} + C n-1 + C It can be seen that the variation of _n ) is very small. Therefore, Equation 3 can be approximated as Equation 4.

Therefore, the frequency sensitivity K _m is changed to one-to-one correspondence with the capacitance value C _v of the variable capacitance diode that is controlled by a control voltage V _t. Here, the change of C _v, namely to keep the K _m regardless of change in carrier frequency constant may be multiplied by the correction value A represented by the number 5.

If the corrected frequency sensitivity is K _m ′, it is expressed by Equation 6.

Therefore, it is possible to maintain it Mote the value of A in the modulation correction table, regardless of the change of the capacitance value C _v of the variable capacitance diode 21 a frequency sensitivity K _m constant. Furthermore, the capacitance value _Cv has a one-to-one correspondence with the carrier frequency. Therefore, the correction value A can be calculated based on the carrier frequency data.

According to the PLL frequency synthesizer modulation circuit of the first embodiment of this invention, V _t control signal of the PLL loop for generating the channel frequency in order to be analog, good C / N characteristics. In addition, since the modulation is performed by the switching capacitor of the voltage controlled oscillator, the capacitance change value with respect to the modulation signal can be digitally controlled, and the change ratio of the capacitance with respect to the modulation signal does not depend on the carrier frequency, and the modulation degree can be easily controlled. . Furthermore, since the modulation data is given as a digital signal to control the capacitance value, the frequency sensitivity K _m can be calculated. For this reason, the value of the modulation degree correction table corresponding to the carrier frequency can be set in advance. Therefore, the deterioration of the modulation degree can be prevented. Further, since modulation data is given digitally, it is easy to adjust the modulation timing according to the frequency division ratio of the variable frequency divider. Furthermore, since the change ratio of the switching capacitance does not change with respect to the temperature, the change in the modulation factor due to the temperature can be suppressed.

(Second Embodiment)
FIG. 6 is a schematic configuration diagram showing a PLL frequency synthesizer modulation circuit for explaining the second embodiment of the present invention. In FIG. 6, the same reference numerals are given to the portions overlapping those in FIG. 1 described in the first embodiment.

  As shown in FIG. 6, the PLL synthesizer modulation circuit according to the second embodiment includes a frequency divider 61 with a fixed frequency division ratio and a direct digital synthesizer (hereinafter referred to as DDS) 62.

  The DDS 62 performs numerical calculation based on the carrier frequency data 103 and the modulation data 104. Then, the result of the numerical operation is directly generated and output using a built-in DA converter or the like. Therefore, since a waveform is generated by numerical calculation, a carrier signal and a modulation signal having an arbitrary frequency can be obtained.

  The output signal of the DDS 62 is input to the phase comparator 3. As described above, since the output of the DDS 62 directly generates a waveform by numerical calculation, the frequency divider 61 with a fixed frequency division ratio can be applied as a frequency divider provided in the PLL frequency synthesizer. The fixed frequency divider 61 can be configured by cascading a plurality of frequency dividers, and the operating frequency is further lowered in the subsequent stage, so that power consumption can be reduced.

  According to the PLL frequency synthesizer modulation circuit of the second embodiment of the present invention, since a fixed frequency divider can be used in the PLL circuit, power consumption can be reduced.

(Third embodiment)
FIG. 7 is a schematic configuration diagram showing a polar modulation system for explaining the third embodiment. In FIG. 7, the same reference numerals are given to the portions overlapping those in FIG. 1 described in the first embodiment. As shown in FIG. 7, the polar modulation system according to the third embodiment includes a PLL frequency synthesizer modulation circuit 10, a polar modulator 71, an envelope signal generation unit 72, and a modulation signal generation unit 73.

  The modulation data 104 is separated into phase modulation data 701 and amplitude modulation data 702 by the modulation signal generator 73. The phase modulation data 701 is input to the PLL frequency synthesizer modulation circuit 10, and the PLL frequency synthesizer modulation circuit 10 outputs a phase-modulated RF signal.

  On the other hand, the amplitude modulation data 702 is input to the envelope signal generation unit 72, and the envelope signal generation unit 72 converts the digital amplitude modulation data into an analog envelope signal. The polar modulator 71 combines the RF phase modulation signal output from the PLL frequency synthesizer modulation circuit 10 and the envelope signal output from the envelope signal generation unit 72 on a polar coordinate plane to generate and output an RF modulation signal 703. To do.

  In a polar modulation system, in order to ensure the modulation characteristics, it is necessary to control the timing for synthesizing the phase modulation data 701 and the amplitude modulation data 702. As a means for performing phase modulation, digital modulation data By using the PLL frequency synthesizer modulation circuit 10 that performs modulation at, timing adjustment can be easily performed.

  In the third embodiment, an example using the PLL frequency synthesizer modulation circuit 10 according to the first embodiment has been described. However, instead of the PLL frequency synthesizer modulation circuit 10, a PLL frequency synthesizer modulation circuit 60 is used. Also good. Also in this case, the PLL frequency synthesizer modulation circuit 60 has a configuration in which modulation is performed using digital modulation data, and timing adjustment for combining the phase modulation data 701 and the amplitude modulation data 702 can be facilitated.

  The voltage-controlled oscillator of the present invention has an effect that the modulation degree can be easily controlled, and is useful for a PLL frequency synthesizer modulation circuit, a polar modulation system, and the like.

Schematic configuration diagram showing a PLL frequency synthesizer modulation circuit for explaining the first embodiment of the present invention The figure which shows an example of the voltage controlled oscillator for demonstrating the 1st Embodiment of this invention Diagram showing configuration example of switching capacitor Diagram showing configuration example of switching capacitor The figure which shows capacity change with respect to control voltage of switching capacity Schematic configuration diagram showing a PLL frequency synthesizer modulation circuit for explaining a second embodiment of the present invention Schematic configuration diagram showing a polar modulation system for explaining a third embodiment of the present invention Schematic configuration diagram showing a conventional PLL frequency synthesizer modulation circuit Diagram showing how frequency sensitivity changes

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Voltage controlled oscillator 2 Variable frequency divider 3 Phase comparator 4 Charge pump 5 Loop filter 6 Division ratio production | generation part 7 Modulation degree correction table 8 Variable amplifier 21 Variable capacity diode 22 (1) -22 (n) Switching capacity 23 Fixed Capacitance 24 Inductor 61 Divider 62 DDS
71 Polar Modulator 72 Envelope Signal Generation Unit 73 Modulation Signal Generation Unit

Claims (9)

  A voltage-controlled oscillator including a resonator including a variable capacitance diode whose capacitance value changes based on an analog input signal for controlling an oscillation frequency, wherein the capacitance value is based on a modulation digital signal in the resonator. A voltage controlled oscillator with a switching capacitance that can be switched.   2. The voltage controlled oscillator according to claim 1, wherein a plurality of said switching capacitors are connected in parallel, and a capacitance value of each of said plurality of switching capacitors is switched based on a corresponding bit of said inputted digital signal. Thus, a voltage-controlled oscillator that modulates by changing the total capacitance value of the plurality of switching capacitors.   3. The voltage controlled oscillator according to claim 2, wherein each of the plurality of switching capacitors has substantially the same capacitance value.   The voltage controlled oscillator according to any one of claims 1 to 3, a frequency divider that divides an output of the voltage controlled oscillator, a phase comparator connected to an output side of the frequency divider, and the phase A charge pump connected to the subsequent stage of the comparator; and a loop filter connected to the subsequent stage of the charge pump and outputting the analog signal input to the voltage controlled oscillator, wherein the analog signal is based on carrier frequency data A PLL frequency synthesizer modulation circuit, wherein the digital signal is generated based on modulation data.   5. The PLL frequency synthesizer modulation circuit according to claim 4, wherein the frequency divider variably controls a frequency division ratio based on the carrier frequency data and the modulation data, and switching of the voltage controlled oscillator based on the modulation data. A PLL frequency synthesizer modulation circuit that controls the capacitance.   5. The PLL frequency synthesizer modulation circuit according to claim 4, further comprising a direct digital synthesizer, wherein the direct digital synthesizer outputs a control signal based on modulation data and carrier frequency data, and the frequency divider has a fixed frequency division ratio. A PLL frequency synthesizer modulation circuit that controls the oscillation frequency of the voltage controlled oscillator based on the output of the direct digital synthesizer and the output of the frequency divider.   7. The PLL frequency synthesizer modulation circuit according to claim 4, further comprising a correction table calculated based on the carrier frequency data, wherein the digital signal uses the modulation data as the modulation table. PLL frequency synthesizer modulation circuit which is corrected by the above.   A PLL frequency synthesizer modulation circuit according to any one of claims 4 to 7, and a modulation for separating the modulation data into phase modulation data and amplitude modulation data and outputting the phase modulation data to the PLL frequency synthesizer modulation circuit A polar modulation system comprising: a signal generation unit; and a polar modulator that generates a modulation signal based on an output of the voltage controlled oscillator of the PLL frequency synthesizer modulation circuit and amplitude modulation data output from the modulation signal generation unit.   A method of calculating a correction table for correcting the modulation factor of a PLL frequency synthesizer modulation circuit, which is based on the carrier frequency data for controlling the carrier frequency and is dependent on the capacitance value of the variable capacitance diode provided in the voltage controlled oscillator A correction table calculation method comprising a step of calculating a value.

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