JP2005064190A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor provided with a gate insulating film of a high dielectric constant material, wherein an electric field at an end in the direction of the channel length of a gate electrode is mitigated, and a sufficient high-speed operation and a high reliability are realized simultaneously. <P>SOLUTION: A gate insulating film 5 exists on a source-drain region 7, and the gate insulating film 5 on the source/drain region 7 has a different thickness from the gate insulating film 5 under a gate electrode 6 containing a metal. By doing so, a position of a polarization electric charge induced on the top or bottom of the gate insulating film 5 is adjusted, and the electric field at the angular part of the lower end of the gate electrode 6 is mitigated. As the result, a problem such as a puncture or a reduction in a reliability in the gate insulating film is suppressed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a field effect transistor including a gate insulating film made of a high dielectric constant material.

  Conventionally, in a field effect transistor used in a semiconductor integrated circuit device, electric field concentration at a gate electrode end becomes a problem as integration progresses. In order to alleviate this electric field concentration, the gate oxide film of the gate electrode is made thicker by performing a thermal oxidation process after processing the gate electrode wiring of polycrystalline silicon (see Patent Document 1).

In addition, a gate electrode having a low resistance using a refractory metal is used to increase the operation speed of the field effect transistor, and a high dielectric constant material is used for the gate insulating film in order to increase the current driving capability. It has been proposed. The high dielectric constant material is a material having a dielectric constant higher than that of silicon oxide conventionally used for a gate insulating film, such as metal silicate.
JP-A-11-307774

  In a gate electrode comprising metal or metal silicide (hereinafter referred to as a metal gate), unlike the polycrystalline silicon gate electrode, as described in the above-mentioned patent document, an oxidation process for rounding the corner at the lower end of the electrode after processing the gate electrode It is not preferable to perform the process because it causes deterioration of characteristics of the gate electrode.

  Even if a polycrystalline silicon gate electrode is used, the oxidation process after processing the gate electrode is not preferable in view of the alteration of the high dielectric constant material used for the gate insulating film.

  Further, when a high dielectric constant material is used for the gate insulating film, the behavior of the electric field concentration becomes complicated because the dielectric constants of the gate insulating film and the surrounding interlayer insulating film are different. Japanese Patent Application No. 2002-8287 described in detail the behavior of this electric field concentration.

  In other words, when the high dielectric constant material for forming the gate insulating film is processed in accordance with the channel direction end of the gate electrode, the electric field becomes the smallest, even if the end of the gate insulating film is on the center side of the gate electrode. Even if it is on the opposite side, the electric field suddenly increases. In particular, when the gate insulating film is extended and processed outside the gate electrode, the electric field value increases.

  Here, since it is not preferable that the gate electrode material remains in an unnecessary region of the gate electrode when the gate electrode is processed, the removal process of the gate electrode material is usually performed under excessive conditions. If the semiconductor substrate under the gate electrode material is scraped by the process, the source / drain junction depth must be increased in order to reduce the resistance of the source / drain on the surface of the semiconductor substrate. For this reason, when the short channel effect becomes prominent and is remarkable, normal operation of the device cannot be obtained.

  In order to prevent this, the gate insulating film is usually used also as a protective material for the semiconductor substrate when processing the gate electrode, so that the gate insulating film is also present on the source / drain regions. Alternatively, in order to prevent a short circuit between the source / drain region and the gate electrode, the gate insulating film on the source / drain region is removed in a state where gate sidewalls are provided on both side walls of the gate electrode to protect the gate end.

  As a result, the gate insulating film protrudes beyond the gate electrode and exists on the source / drain regions by either method. There is a problem that the electric field at the channel long end of the gate electrode becomes extremely strong, which causes problems such as dielectric breakdown of the insulating film, increase of withstand voltage required for the insulating film, and deterioration of reliability.

  Under such circumstances, it has been difficult to satisfy both the requirements for improving the current driving capability of the element and reducing the gate resistance, and ensuring the withstand voltage of the insulating film and the requirements for reliability. Therefore, it has been an obstacle to realizing both high speed operation and high reliability.

  The present invention has been made to solve the above-mentioned problems, and its purpose is to maintain high speed operation and at the same time relax the electric field at the channel length direction end of the gate electrode, and has high reliability with sufficient high speed operation. It is to provide an element.

  To achieve the above object, the present invention includes a semiconductor substrate, a pair of source / drain regions arranged adjacent to each other in a gate length direction of a channel planned region formed on the surface of the semiconductor substrate, and a metal on the semiconductor substrate side, A gate electrode formed on the planned channel region, a central portion having a first thickness formed in an overlapping region of the semiconductor substrate and the gate electrode, and a source / drain region sandwiching the central portion from the gate length direction And a gate insulating film having a pair of end portions having a film thickness different from the first thickness, which is formed on a part of the semiconductor device.

  The present invention also includes a step of forming a gate insulating film on the surface of the semiconductor substrate, a step of forming a gate electrode containing metal on a portion in contact with the gate insulating film, and an upper portion of the gate insulating film on both sides of the gate electrode. A method of manufacturing a semiconductor device, comprising: removing and leaving only the lower part on the surface of the semiconductor substrate; and adding a impurity to the surface of the semiconductor substrate sandwiching the gate electrode to form a source / drain region I will provide a.

  Furthermore, the present invention includes a step of forming a gate insulating film on the surface of the semiconductor substrate, a step of forming a pattern surrounding the gate electrode formation planned region on the gate insulating film, and a gate electrode formation planned region surrounded by the pattern. Removing the upper portion of the gate insulating film and leaving only the lower portion on the surface of the semiconductor substrate; forming a gate electrode containing metal in a portion in contact with the gate insulating film in the region where the gate electrode is to be formed; and And a step of forming a source / drain region by adding an impurity to the surface of the semiconductor substrate to be sandwiched.

  According to the semiconductor device and the manufacturing method thereof of the present invention, a high dielectric constant gate insulating film for obtaining a high current driving force, a metal gate for realizing a low gate resistance, and an insulating film by suppressing electric field concentration. Prevention of dielectric breakdown and high reliability of the element are realized. Therefore, a high-speed operation and highly reliable element is provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram to help explain and understand the invention, and its shape, dimensions, ratio, etc. are different from the actual device, but these are considered in the following explanation and known technology. The design can be changed as appropriate.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view for explaining Embodiment 1 of the present invention. FIG. 1 shows a cross-sectional view of the field effect transistor of Embodiment 1 parallel to the channel length direction.

  In this embodiment, an N-channel field effect transistor will be described as an example. If the conductivity type of the impurity is reversed, the same applies to the P-channel field effect transistor. Further, if a method such as injecting impurities only into a specific region in the substrate using a method such as a photo-etching method, a complementary field effect transistor can be formed, and the same effect can be obtained.

  First, the structure of the field effect transistor of Embodiment 1 will be described. On the surface of the semiconductor substrate 1 such as a P-type silicon substrate, a groove-type element isolation region 2 that electrically isolates adjacent element regions is formed. A P well region 3 is formed in an element region where the field effect transistor is formed, and a gate insulating film 5 and a gate electrode 6 are formed thereon.

  Further, a pair of source / drain regions 7 sandwiching the gate electrode 6 from the channel length direction is formed on the surface of the P well region 3. An N channel region 4 is formed on the substrate surface between the source / drain regions 7. On the gate electrode 6 and the source / drain region 7, contact wirings 8 are formed so as to be connected to each other. An interlayer insulating film 9 is formed between the contact wires 8 to electrically insulate the wires and the transistors.

  In the field effect transistor of the first embodiment, the gate insulating film 5 is also present on the source / drain region 7, and the gate insulating film 5 on the source / drain region 7 is more than the gate insulating film 5 below the gate electrode 6. It is characterized by being thin. When the thick region under the gate electrode 6 is a central portion of the gate insulating film 5, the thin region on the source / drain region 7 is a pair of end portions sandwiching the central portion.

  The gate insulating film 5 and the interlayer insulating film 9 are polarized by electric lines of force coming out of the gate electrode 6 and reaching the substrate, and the surface of the gate insulating film 5 on the source / drain region 7 and the lower surface of the interlayer insulating film 9 thereon. A polarization charge is generated. Considering that the gate insulating film 5 has a higher dielectric constant than the interlayer insulating film 9, the net charge appearing at this interface is a negative charge when a positive potential is applied to the gate electrode 6 with respect to the substrate 1. Since a positive charge is applied when a negative potential is applied, the potential at the interface always acts away from the potential of the gate electrode 6.

  Therefore, although the electric field at the lower end corner of the gate electrode 6 is promoted, the electric field in the gate insulating film 5 near the lower end corner of the gate insulating film 5 is relaxed because the upper surface of the gate insulating film 5 exists away from the lower end corner of the gate electrode 6. As a result, a semiconductor device with a highly reliable insulating film can be provided.

  Such electric field relaxation will be described in detail here. In the field effect transistor, the gate insulating film and the interlayer insulating film are polarized by electric lines of force that penetrate the surface and side surfaces of the gate insulating film and connect the gate electrode and the substrate. Therefore, a polarization charge corresponding to a difference in polarization due to a difference in dielectric constant between the gate insulating film and the interlayer insulating film is induced on the surface and side surfaces of the gate insulating film. This state will be described with reference to the schematic diagram of FIG.

  FIG. 2 is an enlarged schematic cross-sectional view of the corner of the gate electrode 6 in the channel length direction and the vicinity thereof in the field effect transistor shown in FIG. Consider a case where a positive potential is applied to the gate electrode 6 with respect to the semiconductor substrate 1. Even when a negative potential is applied, the entire sign is reversed, and the following story is exactly the same.

In FIG. 2, only two lines of electric force extending from the gate electrode 6 to the semiconductor substrate 1 are shown. Further, the electric lines of force are bent at the interface of the media having different dielectric constants, but the bending is omitted in FIG.

  While a high dielectric constant material such as a metal oxide is used for the gate insulating film, generally, a high dielectric constant material is not used for the interlayer insulating film or the like. Therefore, the gate insulating film has a higher dielectric constant. Since a positive potential is applied to the gate electrode, the direction of the electric field on the surface of the gate insulating film is directed from the outside to the inside of the gate insulating film. Then, negative polarization charges are induced on the surface of the gate insulating film, and positive polarization charges are induced on the lower surface of the interlayer insulating film facing the gate insulating film.

  In this state, since the gate insulating film has a higher dielectric constant than the interlayer insulating film, the net charge induced at the interface is negative. This increases the electric field in the vicinity of the channel long end of the gate electrode because the potential on the surface of the gate insulating film is kept away from the gate electrode.

  Here, if the gate insulating film has the same thickness both on the source / drain region and below the gate electrode, this negative charge is in contact with the lower end corner of the gate electrode, so the electric field near the lower end corner of the gate electrode is the most. Become stronger. If the gate insulating film on the source / drain region has a different thickness from that of the gate insulating film below the gate electrode, the negative electric charge is separated from the lower end corner of the gate electrode, so that the above-described electric field is weakened. The electric field near the bottom corner is weakened.

  As shown in FIG. 2, the direction of the electric field on the side surface that appears on the gate insulating film 5 below the lower end corner of the gate electrode 6 is directed from the inside to the outside of the gate insulating film 5. Then, contrary to the case of the surface of the gate insulating film 5 described above, a positive polarization charge is induced on this side surface, and a negative polarization charge is induced on the side surface on the side of the interlayer insulating film 9 facing it.

  Since the gate insulating film 5 has a higher dielectric constant than the interlayer insulating film 9 or the like, the net charge induced at the interface is positive. This brings the potential of the surface of the gate insulating film 5 closer to the gate electrode 6 and weakens the electric field near the lower end corner of the gate electrode 6. Therefore, if the gate insulating film 5 on the source / drain region 7 is made thinner than the gate insulating film 5 below the gate electrode 6, the electric field in the vicinity of the lower end corner of the gate electrode 6 will be further weakened. In this way, the electric field in the vicinity of the lower end corner of the gate electrode 6 is reduced.

  FIG. 3 is a schematic cross-sectional view of a part of the field effect transistor parallel to the channel direction. With respect to the field effect transistor, the value of the electric field in the gate insulating film 5 at the lower end of the gate electrode 6 (marked with a circle in the figure) was examined by simulation using Δ2 in FIG. The dielectric constant of the interlayer insulating film covering the elements such as the side walls of the gate was set to 3.9, which is the dielectric constant of silicon oxide. The result is shown in FIG.

  The sign of Δ2 is positive when the gate insulating film 5 on the source / drain region 7 is thicker than the gate insulating film 5 below the gate electrode 6 as shown in FIG. When Δ2 is zero, that is, when the thickness of the gate insulating film 5 on the source / drain region 7 is equal to the thickness of the gate insulating film 5 below the gate electrode 6, the electric field is strongest, and when Δ2 is away from zero, the electric field is You can see that it is weakened.

  Furthermore, it can be seen that the electric field is weaker when Δ2 is negative, that is, when the thickness of the gate insulating film 5 on the source / drain region 7 is thinner than the thickness of the gate insulating film 5 below the gate electrode 6. Therefore, it is preferable that the thickness of the gate insulating film 5 on the source / drain region 7 is thinner than the thickness of the gate insulating film 5 below the gate electrode 6.

Furthermore, the result of investigating the relationship between Δ2 and the capacitance of the structure shown in FIG. 3 is shown in FIG. From FIG. 5, when the thickness of the gate insulating film 5 on the source / drain region 7 is thicker than the thickness of the gate insulating film 5 below the gate electrode 6, the gap between the gate electrode 6 and the source / drain region 7 is It is considered that the capacitance formed is increased. An increase in the capacitance between the gate electrode 6 and the source / drain region 7 means an increase in the parasitic capacitance of the device, leading to a decrease in the operation speed of the device, and the gate electrode 6 and the source / drain region 7. The capacitance between the two is preferably small.

  From the above, when Δ2 is decreased, the capacitance decreases monotonously, and Δ2 is set to be negative, that is, the thickness of the gate insulating film 5 on the source / drain region 7 is set to the gate insulating film 5 below the gate electrode 6. It can be seen that it is more preferable to set the thickness to be smaller than the thickness of.

  In Japanese Patent Application No. 2002-8287, the potential of the gate insulating film in the vicinity of the lower end corner of the gate electrode is brought close to the potential of the gate electrode by the polarization charge that appears when a potential is applied to the gate electrode with respect to the semiconductor substrate. Reduced the electric field. On the other hand, in the present invention, the potential of the gate insulating film in the vicinity of the lower end angle of the gate electrode is moved away from the potential of the gate electrode by the polarization charge that appears when the potential is applied to the gate electrode with respect to the semiconductor substrate, and the electric field is Reduce the electric field by preventing it from being encouraged.

  Furthermore, the structure in which the gate electrode is provided with a side wall made of a high dielectric constant material is not limited to the patent of Japanese Patent Application No. 2002-8287, and all electric lines of force extending from the side surface of the gate electrode to the semiconductor substrate are made of a high dielectric constant material. Pass through the side wall. The high dielectric constant material used for the sidewall may be the same as or different from the gate insulating film material. For this reason, the capacitance formed between the gate electrode and the semiconductor substrate becomes extremely large, which hinders high-speed operation of the element, which is not preferable. On the other hand, in the structure of the present invention, the upper part of the side surface of the gate electrode is not in contact with an insulator made of a high dielectric constant material, and the capacitance formed between the side surface of the gate electrode and the semiconductor substrate is suppressed. The Therefore, a sufficiently high speed operation is realized.

  Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be described with reference to schematic cross-sectional views in the channel length direction of FIGS.

First, as shown in FIG. 6, an element isolation region 2 is formed on a P-type silicon substrate 1 by, for example, a groove type element isolation method. Subsequently, for example, B ions are about 100 keV, about 2.0 × 10 ^{13 in} the P well formation region.
Implantation is performed at cm ⁻² , and then a P well region 3 is formed by a thermal process of about 1050 ° C. for about 30 seconds, for example. In order to obtain a desired threshold voltage, for example, B ions are implanted into the P well region 3 at about 30 keV and about 1.0 × 10 ¹³ cm ⁻² to adjust the concentration of the surface of the N channel 4.

Next, the HfO ₂ film 11 having a thickness of, for example, 5 nm is formed on the silicon substrate 1 by using, for example, a sputtering method (FIG. 7).

A refractory metal film such as tungsten having a thickness of about 100 nm is deposited on the HfO ₂ film 11 by, eg, CVD. The refractory metal film is subjected to anisotropic etching such as RIE using a mask pattern formed by forming a resist film and processing using photolithography to form the gate electrode 6 (FIG. 8). Subsequently, the upper portion of the HfO ₂ film 11 is removed by performing anisotropic etching such as RIE (FIG. 8).

Next, for example, arsenic (As) ions are implanted into the surface of the silicon substrate 1 at 50 keV and 5.0 × 10 ¹⁵ cm ⁻² . Then, impurity regions (source / drain regions) 7 in which As ions are diffused are formed by a thermal process (FIG. 9).

Next, as shown in FIG. 10, a silicon oxide film 9 is deposited on the surface of the silicon substrate 1 as an interlayer insulating film by a CVD method, for example, by about 500 nm. For example, wiring holes 12 connected to the source / drain regions 7 and the gate electrode 6 are opened in the silicon oxide film 9 by RIE using a mask pattern.

  Contact wiring is formed in the opening 12. For example, an Al film having a thickness of about 300 nm containing 1% Si, for example, is formed on the surface of the silicon substrate 1 by sputtering or the like. The Al film is removed from the interlayer insulating film 9 adjacent to the opening by subjecting this Al film to anisotropic etching such as RIE. Thus, the field effect transistor shown in FIG. 1 is formed.

  In the first embodiment described above, various modifications described below are possible.

  In the present embodiment, an N-type field effect transistor has been described as an example. However, the present invention can be similarly applied to a P-type field effect transistor if the conductivity type of impurities is reversed. The same applies to the complementary field effect transistor if impurities are introduced only into a specific region in the substrate using a method such as photo-etching. Further, it can be used for a semiconductor device including them as a part.

  In addition to field effect transistors, as part of a semiconductor device including other active elements such as bipolar transistors and single electron transistors, passive elements such as resistors, diodes, inductors, and / or capacitors, The field effect transistors described can also be formed. The same applies to the case where a field effect transistor is formed as a part of OEIC (Opt-Electrical Integrated Circuit) or MEMS (Microelectro Mechanical System). It is also used in the same manner for SOI (Silicon On Insulator) structure elements. Furthermore, it can be used in the same manner for FIN type or columnar elements.

  In this embodiment, As is used as an impurity for forming the N-type semiconductor layer, and B (boron) is used as an impurity for forming the P-type semiconductor layer. Other group V impurities may be used as impurities for forming the N-type semiconductor layer, and other group III impurities may be used as impurities for forming the P-type semiconductor layer. The introduction of Group III or Group V impurities may be carried out in the form of a compound containing them.

  In this embodiment mode, the introduction of impurities is performed using ion implantation, but may be performed using a method other than ion implantation such as solid phase diffusion or gas phase diffusion. Alternatively, a method of depositing or growing a semiconductor containing impurities may be used.

In the present embodiment, an element having a single drain structure is shown. However, for example, an extension structure to an LDD (Lightly Doped Drain) structure or a GDD (Graded) other than the single drain structure is shown.
You may apply to the element of structures, such as a Diffused Drain) structure. Moreover, you may use elements, such as a halo structure thru | or a pocket structure, and an elevator structure.

  In this embodiment, the source / drain regions are formed after the processing of the gate electrode and the gate insulating film. However, the order is not essential, and the order may be reversed. Depending on the material of the gate electrode and the gate insulating film, it may not be preferable to perform the thermal process. In such a case, it is preferable to introduce impurities into the source / drain regions prior to processing of the gate electrode and the gate insulating film.

  In this embodiment, the metal layer for wiring is formed by sputtering, but the metal layer may be formed by using a different method such as a deposition method in addition to the sputtering method. Further, a method such as selective growth of metal may be used, or a method such as damascene method may be used. In addition, the wiring metal material is not necessarily Si containing Al, and other metals such as Cu may be used. In particular, Cu is preferable because of its low resistivity.

  In this embodiment mode, a refractory metal is used for the gate electrode. However, a metal that does not necessarily have a high melting point, a compound containing a metal, or the like may be used. Furthermore, the gate electrode is not limited to a single metal layer. For example, a stack of a semiconductor such as polycrystalline silicon, single crystal silicon, or amorphous silicon and a metal may be used. However, when the non-metal layer and the metal layer are stacked, a metal layer is formed from the gate insulating film, and the non-metal layer is formed on the metal layer.

  Furthermore, a stacked gate electrode of a metal that is not necessarily a high melting point or a compound containing a metal and a high melting point metal may be used. At this time, it is preferable to form the gate electrode with a metal or a compound containing a metal because the gate resistance can be suppressed, so that the device can operate at high speed.

  In the present embodiment, the upper portion of the gate electrode has a structure in which the electrode is exposed (see FIG. 9), but an insulator such as silicon oxide or silicon nitride may be provided on the upper portion. In particular, when the gate electrode is formed of a material containing metal and a silicide layer is formed on the source / drain region, it is necessary to protect the gate electrode during the manufacturing process. It is essential to provide a protective material such as silicon oxide or silicon nitride on the top.

  In this embodiment, the gate electrode is formed by a method of performing anisotropic etching after depositing the gate electrode material. However, the gate electrode is formed by using a method such as embedding such as a damascene process. An electrode may be formed.

  In this embodiment, the length of the gate electrode measured in the main direction of the current flowing through the element (the left-right direction in FIG. 1) is equal to the upper and lower portions of the gate electrode, but this is not essential. . For example, the length of the upper part of the gate electrode measured in the shape of an alphabet “T” may be longer than the length measured in the lower part. In this case, there is another advantage that the gate resistance can be reduced.

In this embodiment, an HfO ₂ film formed by a sputtering method is used as the gate insulating film, but oxides having different valences of Hf, Zr, Ti, Sc, Y, Ta, Al, La, Ce, Pr, metal oxides such as lanthanoid series elements, silicate materials containing various elements including these elements, insulating films containing nitrogen in these silicate materials, other high dielectric films, or their An insulating film such as a stack may be used as the gate insulating film.

  In this embodiment, polarization charges induced on the surface of the gate insulating film and the lower surface of the interlayer insulating film facing the gate insulating film are used. In general, the polarization charge induced at the interface between two types of insulators is the difference between the polarization charges induced on the surface of each insulator, so the higher the dielectric constant of the gate insulating film, the more the net polarization charge induced Become more. That is, the effect obtained in this embodiment is due to the high dielectric constant of the gate insulating film. Therefore, if the gate insulating film is formed of a material having a low dielectric constant, such as a silicon nitride film or silicon nitride oxide, which is often used for a conventional gate insulating film, the effect of this embodiment cannot be expected.

  The method for forming the gate insulating film is not limited to the sputtering method, and other methods such as an evaporation method, a CVD method, or an epitaxial growth method may be used. When an oxide of a certain material is used as the gate insulating film, a method of first forming a film of the material and oxidizing it may be used. An element using a ferroelectric film may be formed as the gate insulating film.

  In the present embodiment, the element isolation region 2 is formed using the trench type element isolation method. However, the element isolation may be performed using another method such as a local oxidation method or a mesa type element isolation method.

In the case of using a material containing metal for the gate electrode or the gate insulating film, the problem of electric field concentration becomes remarkable when the post-oxidation process is impossible in view of the properties of the material. The method particularly effectively reduces the electric field.

  In this embodiment, a silicon oxide film is used as an interlayer insulating film, but a substance other than silicon oxide such as a low dielectric constant material may be used for the interlayer insulating film. In this embodiment, polarization charges induced on the surface of the gate insulating film and the lower surface of the interlayer insulating film facing the gate insulating film are used. In general, the polarization charge induced at the interface between two insulators is the difference between the polarization charges induced on the surface of each insulator, so the lower the dielectric constant of the interlayer insulation film, the more the net polarization charge induced. Will be more. Therefore, the above-described effect becomes remarkable when a material having a low dielectric constant is used for the interlayer insulating film.

  It is also possible to form a self-aligned contact with respect to the contact hole.

  In the present embodiment, only the first layer wiring has been described, but the elements, wirings, and the like may be two or more layers. In that case, it is preferable because the degree of integration of elements increases.

  In this embodiment, the side surface of the gate insulating film that appears in the vicinity of the lower end angle of the gate electrode is a plane perpendicular to the surface of the semiconductor substrate, but this is not essential. For example, a modified structure shown in FIGS. 11 and 12 which are cross-sectional views in the channel length direction can be used. That is, as shown in these drawings, the same effect can be obtained even if the side surface adjacent to the lower end corner of the gate electrode of the gate insulating film 5 is not perpendicular to the surface of the semiconductor substrate.

  Further, the inclination angles of the side surface on the source region side and the side surface on the drain region side do not have to be equal, one may be inclined outward from the gate electrode 6 and the other may be inclined inward. Further, the side surface need not be a flat surface, and may be a curved surface as shown in FIGS. 13 and 14, for example.

  For example, as shown in FIGS. 15 and 16, the side surface of the gate insulating film 5 and the surface on the source / drain region 7 may be smoothly connected. Further, for example, as shown in FIGS. 17 and 18, the thickness of the gate insulating film in the source / drain region 7 may not be uniform.

  Changing the shape of the gate insulating film 7 in the vicinity of the lower end corner of the gate electrode changes the capacitance formed between the gate electrode 5 and the source / drain region 7.

  The capacitance formed between the gate electrode 6 and the source / drain region 7 is preferably large from the viewpoint of suppression of parasitic resistance due to the resistance of the source / drain region 7. The smaller one is preferable from the viewpoint of reduction. The capacitance formed between the gate electrode 6 and the source / drain region 7 is adjusted by changing the shape of the gate insulating film 5 in the vicinity of the lower end angle of the gate electrode as in the modification examples shown in FIGS. This has the advantage that optimization can be measured.

(Embodiment 2)
Next, Embodiment 2 according to the present invention will be described with reference to FIGS. 19 to 23 are schematic cross-sectional views parallel to the gate length direction of the field effect transistor.

  As shown in FIG. 23, in this embodiment, since the silicide layer 15 is formed on the surface of the source / drain region 7, the parasitic resistance of the element can be reduced and the operation speed of the element can be increased.

  A method for manufacturing the field effect transistor according to the second embodiment will be described below.

After the process described with reference to FIG. 7, a refractory metal film such as tungsten having a thickness of about 100 nm is formed on the HfO ₂ film 11 by, eg, CVD. Further, a silicon nitride film 13 having a thickness of about 50 nm is formed by, eg, CVD. Then, a resist pattern is formed by formation of a resist film and photolithography. The silicon nitride film 13 and the refractory metal film 11 are processed by performing anisotropic etching such as RIE using this resist pattern as a mask to form the gate electrode 6 (FIG. 19). Further, the upper portion of the HfO ₂ film 11 is removed by performing anisotropic etching such as RIE (FIG. 19).

Next, for example, As ions are implanted into the surface of the silicon substrate 1 at about 50 keV and about 5.0 × 10 ¹⁵ cm ⁻² . Then, As is activated by a thermal process to form source / drain regions 7 (FIG. 20).

  Next, a silicon nitride film 14 of, eg, a thickness of about 5 nm is formed on the surface of the silicon substrate 1 by, eg, CVD (FIG. 21).

Then, as shown in FIG. 22, the gate sidewall 10 is formed by performing anisotropic etching such as RIE on the silicon nitride film 14. Subsequently, by performing the anisotropic etching such as RIE in the HfO ₂ film 11, the gate insulating film 5 by removing the HfO ₂ film 11 of the other region excluding the 6 under the gate sidewalls 10 and the gate electrode (FIG. 22).

  Next, a metal silicide layer 15 such as Co or Ni is formed by a normal silicide formation method. The unreacted metal is removed from the surface of the silicon substrate 1 (FIG. 23). Since the subsequent steps are the same as those in the first embodiment, details are omitted.

  In this embodiment, the silicide layer 15 is formed on the source / drain region 7, but when the remaining portion of the gate electrode 6 except the substrate side or the surface of the gate electrode 6 is formed of polycrystalline silicon or the like, the surface of the polycrystalline silicon is formed. May be silicided. Further, a method of depositing or growing a metal layer on the source / drain region 7 may be used.

  Also in the present embodiment, various modifications in the first embodiment are possible, and similar effects can be expected.

  Further, in this embodiment, silicon nitride is used for the gate sidewall 10, but the gate sidewall 10 may be formed using other materials such as silicon oxide or silicon nitride oxide. However, if the gate side wall 10 is formed of a material having a high dielectric constant, the capacitance between the gate electrode 6 and the source / drain region 7 is increased, which increases the parasitic capacitance of the element. Therefore, the sidewall 10 is preferably formed of a material such as silicon oxide, silicon nitride, or silicon nitride oxide.

In this embodiment, the side surface of the gate insulating film 5 is aligned with the outer surface of the gate side wall 10, but this is not essential, and the side surface of the gate insulating film 5 is inside the outer surface of the gate side wall 10. Or even if it exists outside, the effect similar to this Embodiment is acquired. However, if the side surface of the gate insulating film 5 protrudes to the outside much larger than the outer surface of the gate side wall 10, the distance between the channel region and the region where the silicide layer can be formed in the source / drain region 7 is increased. The parasitic resistance of the element increases. This is undesirable because it increases the operating speed of the device. Therefore, it is preferable that the side surface of the gate insulating film does not protrude so much from the outer surface of the gate side wall. On the contrary, if the side surface of the gate insulating film is much larger than the side surface of the gate sidewall, the distance between the silicide layer formed on the source / drain region and the gate electrode is shortened, and the source / drain region A short circuit may occur with the gate electrode, or a dielectric breakdown may occur between the gate insulating film and the like. Therefore, it is preferable that the side surface of the gate insulating film does not enter the inside much more than the side surface of the gate side wall.

  Here, the preferable thickness of the gate side wall 10 and the preferable length of the gate insulating film 5 left on the source / drain region 7 will be described. In the structure of FIG. 3, the dependence of the electric field intensity in the gate insulating film 5 in the vicinity of the lower end corner of the gate electrode 6 on Y in FIG. The result is shown in FIG.

  The vertical axis in FIG. 24 shows values normalized by the electric field strength of the structure of Δ2 = 0. That is, the vertical axis indicates the rate at which the electric field strength is suppressed by making the gate insulating film 5 on the source / drain region 7 thinner.

  From FIG. 24, it can be seen that the greater the Y, the more effective the suppression of the electric field strength by reducing the thickness of the gate insulating film on the source / drain regions. When Y is about 5 nm or more, the dependency of the efficiency of suppressing the electric field intensity on Y is considerably small, and when Y is about 7 to 8 nm or more, the dependency of the electric field intensity on the suppression of Y is It becomes even smaller. It can be seen that when Y is about 10 nm or more, the dependence of the electric field intensity on the Y is further reduced. 5 nm is equal to the thickness of the gate insulating film assumed in this study. 7 to 8 nm is about 1.5 times the gate insulating film thickness. And 10 nm is twice the gate insulating film thickness. Here, in the electromagnetic field equation, when the size of the boundary condition is changed in a similar shape, the electromagnetic field also changes while maintaining the similar shape. In view of this, it can be seen that this embodiment is effective when the thickness of the gate sidewall and the length of the gate insulating film left on the source / drain regions are equal to or greater than the gate insulating film thickness of the device. It is more effective if the thickness of the gate sidewall and the length of the gate insulating film left on the source / drain region is 1.5 times or more of the gate insulating film thickness, and more effective if it is more than twice the gate insulating film thickness. Is. Therefore, it is preferable that the thickness of the gate side wall 10 (width in the horizontal direction in FIG. 23) and the length of the gate insulating film 5 left on the source / drain region 7 are equal to or greater than the gate insulating film thickness of the device. In particular, it is preferably 1.5 times or more of the gate insulating film thickness, and more preferably twice or more of the gate insulating film thickness.

(Embodiment 3)
Next, a method for manufacturing a field effect transistor according to the third embodiment of the present invention will be described with reference to FIG.

  FIG. 25 shows a process in the middle of manufacturing the field effect transistor of the present embodiment, and is a cross-sectional schematic view in the channel length direction.

First, after the step shown in FIG. 7, a refractory metal film such as tungsten having a thickness of about 100 nm is deposited on the HfO ₂ film 11 by, eg, CVD. A resist mask is formed only on the gate electrode planned region of the refractory metal film, and the region of the refractory metal film that is not covered with this mask is removed by performing anisotropic etching such as RIE method. The electrode 6 is formed (FIG. 25). Thereafter, isotropic etching such as wet processing is performed to remove the upper portion of the HfO ₂ film 11 and the end of the gate electrode 6 in the channel length direction.

  Thereafter, the field effect transistor according to the present embodiment can be formed by performing the process as described in Embodiment 1 with reference to FIGS. 9 and 10 (FIG. 26).

  Also in this embodiment, various modifications as described in other embodiments are possible, and the same effect can be expected.

In the present embodiment, unlike the first embodiment, isotropic etching is used for processing the gate insulating film 5 on the source / drain regions 7. Therefore, the gate insulating film 5 under the gate electrode 6
Is also processed thin near the end of the gate electrode. That is, a pair of thin end portions extends to the bottom of the gate electrode 5. In this way, the capacitance formed between the gate electrode 6 and the source / drain region 7 can be further reduced.

  In this embodiment, the silicide process is not mentioned, but a silicide layer may be formed on the source / drain region 7. Further, a method of depositing or growing a metal layer on the source / drain region 7 may be used. Further, when the remaining portion of the gate electrode 6 other than the substrate side or the surface of the gate electrode 6 is formed of polycrystalline silicon or the like, the surface of the polycrystalline silicon may be silicided.

  Further, when the gate insulating film 5 on the source / drain region 7 is processed, anisotropic etching is used in the first embodiment, and isotropic etching is used in the present embodiment. A method may be used in which isotropic etching is performed after isotropic etching, anisotropic etching is performed after isotropic etching, or at least one etching is repeated a plurality of times. This is preferable because both the thickness of the gate insulating film 5 on the source / drain region 7 and the amount of removal of the gate insulating film 5 below the gate electrode 6 can be adjusted to optimum values. .

  Further, the shape of the gate insulating film 5 in the vicinity of the lower end corner of the gate electrode 6 does not need to be the shape shown in FIG. 25. For example, the same effect can be expected even in the shapes shown in FIGS. Optimum because the capacitance formed between the gate electrode and the source / drain region can be adjusted by changing the shape of the gate insulating film in the vicinity of the lower end corner of the gate electrode as in the modification shown here. It becomes possible to measure the conversion.

(Embodiment 4)
Next, a field effect transistor according to the fourth embodiment of the present invention will be described with reference to FIGS.

  34 and 35 are schematic cross-sectional views in the channel length direction of the field effect transistor according to the present embodiment.

First, after performing the process described with reference to FIG. 7 in the first embodiment, a refractory metal film such as tungsten having a thickness of about 100 nm is deposited on the HfO ₂ film 11 by, for example, the CVD method. A resist pattern is formed on the refractory metal film to cover the gate electrode planned region. Using this resist pattern as a mask, anisotropic etching such as RIE is performed to process the refractory metal film. Thereby, the gate electrode 6 shown in FIG. 34 is formed. A silicon nitride film 14 having a thickness of 3 nm is formed on the silicon substrate 1 on which the gate electrode 6 is formed by, for example, a CVD method.

A gate sidewall 10 is formed on the silicon nitride film 14 by performing anisotropic etching such as RIE (FIG. 35). Subsequently, the exposed upper portion of the HfO ₂ film 11 is removed by anisotropic etching such as RIE (FIG. 35).

  Thereafter, the field effect transistor of the present embodiment can be manufactured through the same steps as in the first embodiment.

  Also in this embodiment, various modifications described in other embodiments are possible, and the same effect can be obtained.

The gate sidewall 10 may be removed after the gate insulating film is processed, or may be left as it is. If the gate sidewall 10 is removed, for example, a field effect transistor having a cross-sectional structure shown in FIG. 36 is obtained. Further, silicon nitride is not necessarily used as the gate sidewall material, and other materials may be used.

  In the present embodiment, the vicinity of the end portion of the gate electrode 6 of the gate insulating film 5 has a film thickness equivalent to that immediately below the gate electrode 6. That is, the central portion extends outside the side wall of the gate electrode. In this way, since the capacitive coupling between the source / drain region 7 and the gate electrode 6 is strengthened, the resistance of the source / drain region 7 is lowered, and a reduction in the parasitic resistance of the element can be expected.

  In the present embodiment, the gate insulating film 5 on the source / drain region 7 is processed using anisotropic etching, but this step may be performed using isotropic etching.

  Further, a method may be used in which isotropic etching is performed after anisotropic etching, anisotropic etching is performed after isotropic etching, or at least one etching is performed a plurality of times. In this way, it is possible to adjust both the thickness of the gate insulating film on the source / drain region and the distance between the thin region of the gate insulating film on the source / drain region and the gate electrode to optimum values. Become.

  Further, the shape of the gate insulating film 5 in the vicinity of the lower end corner of the gate electrode 6 does not have to be the shape shown in FIGS. 35 and 36. For example, the shape shown in the schematic sectional views of FIGS. Can be expected.

  If the shape of the gate insulating film near the lower end angle of the gate electrode is changed as in the modification shown here, the capacitance formed between the gate electrode 6 and the source / drain region 7 can be adjusted. It is possible to measure optimization. Which structure is used can be determined by the balance between the parasitic resistance and the parasitic capacitance by changing the capacitance formed between the source / drain region and the gate.

(Embodiment 5)
Next, a field effect transistor according to the fifth embodiment of the present invention will be described with reference to FIGS.

  FIG. 45 is a reference diagram for explaining the field-effect transistor according to the present embodiment, and schematically shows a cross section in the channel length direction.

  This field effect transistor is characterized in that the gate insulating film 5 also exists on the source / drain region 7 and the gate insulating film 5 on the source / drain region 7 is thicker than the gate insulating film 5 below the gate electrode 6. There is.

  The field effect transistor is manufactured as follows, for example. 46 to 49 are reference diagrams for explaining the process of the manufacturing process, and schematically show a cross section in the channel length direction of the field effect transistor.

First, after the process described with reference to FIG. 6, as shown in FIG. 46, an HfO ₂ film 11 having a thickness of about 10 nm is formed on the silicon substrate 1 by, eg, sputtering. On the HfO ₂ film 11, silicon nitride having a thickness of about 150 nm is deposited by, eg, CVD. A resist mask is formed on the gate electrode planned region on the silicon nitride film, and the silicon nitride film is processed by performing anisotropic etching such as RIE on the surface of the silicon substrate 1 to form the dummy gate electrode 16. Form (FIG. 46). Thereafter, for example, As ions are implanted at about 50 keV and about 5.0 × 10 ¹⁵ cm ⁻² . Then, by subjecting the silicon substrate 1 to a thermal process, As ions are activated to form source / drain regions 7 (FIG. 46).

  A silicon oxide film 17 having a thickness of about 200 nm is formed on the silicon substrate 1 with the dummy gate electrode 16 by, for example, the CVD method. The surface of the dummy gate electrode 16 is exposed by flattening the surface of the silicon substrate on which the silicon oxide film 17 is formed by the CMP method or the like. Then, the dummy gate electrode 16 is selectively removed from the silicon substrate 1 to form an opening (FIG. 47).

The upper portion of the HfO ₂ film 11 exposed at the bottom of the opening is removed by etching by the RIE method or the like (FIG. 48).

A refractory metal film such as tungsten having a thickness of about 200 nm is deposited on the silicon substrate including the HfO ₂ film 11 which is thinned by removing the upper part by, for example, the CVD method. As for the refractory metal film, the gate electrode 6 is formed in the opening by planarizing the surface by, for example, the CMP method (FIG. 49). Thereafter, the silicon oxide film 17 is removed from the surface of the silicon substrate 1.

  Thereafter, the field effect transistor according to the present embodiment is completed by performing the steps described with reference to FIG.

  Also in this embodiment, various modifications as described in the above embodiment are possible, and the same effect can be obtained.

  The silicon oxide film formed around the dummy gate electrode after forming the dummy gate electrode may be left as a part of the interlayer insulating film or may be removed. Further, there is no necessity to use silicon oxide as the material, and other materials may be used. The same applies to the material of the dummy gate electrode.

In this embodiment, anisotropic etching is used for processing the HfO ₂ film after removing the dummy gate electrode, but isotropic etching such as CVD or wet etching may be used.

  After planarizing the surface after depositing the gate electrode material, the gate electrode material may be further etched to adjust the height of the gate electrode 6.

  In this embodiment, since the gate insulating film 5 on the source / drain region 7 is formed thicker than the gate insulating film 5 below the gate electrode 6, capacitive coupling between the source / drain region 7 and the gate electrode 6 is further strengthened. Therefore, the resistance of the source / drain region 7 is lowered, and as a result, the parasitic resistance of the element can be reduced.

  The shape of the gate insulating film 5 in the vicinity of the lower end corner of the gate electrode does not have to be the shape shown in FIG. 45. For example, the same effect can be expected even when the cross-sectional shapes shown in FIGS. As in the modification shown here, the capacitance formed between the gate electrode 6 and the source / drain region 7 can be adjusted by changing the shape of the gate insulating film 5 in the vicinity of the lower end angle of the gate electrode. Since it can, optimization can be measured.

(Embodiment 6)
Next, a field effect transistor according to the sixth embodiment of the present invention will be described with reference to FIGS.

FIG. 57 is a cross-sectional view for explaining the field effect transistor of this embodiment, and schematically shows a cross section in the channel length direction. In this field effect transistor, the gate insulating film 5 also exists on the source / drain region 7, the gate insulating film 5 on the source / drain region 7 is thicker than the gate insulating film 5 on the channel region 4, and It is characterized in that the thick gate insulating film 5 and the gate electrode 6 on the drain region 7 are separated from each other. Therefore, since the electrostatic capacitance formed between the source / drain region 7 and the gate electrode 6 can be suppressed, the parasitic capacitance of the element can be reduced.

  Next, a method for manufacturing the field effect transistor of FIG. 57 will be described.

  First, after the process described in Embodiment 5 with reference to FIG. 48, as shown in FIG. 58, a silicon nitride film having a thickness of about 5 nm is formed by a method such as a CVD method. Subsequently, the silicon nitride film is processed by performing anisotropic etching such as the RIE method to form the side wall 18 on the side surface of the hole. Thereafter, the process can be continued from the process described in Embodiment 5 with reference to FIG.

  Also in this embodiment, various modifications as described in the above embodiment are possible, and similar effects can be obtained.

  Further, the silicon oxide film formed around the dummy gate electrode after forming the dummy gate electrode may be used as a part of the interlayer insulating film or may be removed. Further, there is no necessity to use silicon oxide as the material, and other materials may be used. The same applies to the opening side wall 18.

  In the field effect transistor shown in FIG. 57, the side wall 18 is removed after the gate electrode 6 is formed, and the height is adjusted by etching the gate electrode 6 after the surface of the gate electrode material is planarized. .

  In the present embodiment, the gate insulating film 5 on the source / drain region 7 is processed using anisotropic etching, but isotropic etching may be used for this step. Further, for example, a method may be used in which isotropic etching is performed after anisotropic etching, anisotropic etching is performed after isotropic etching, or at least one etching is performed a plurality of times. .

  Further, when the thickness of the gate insulating film 5 formed first is also adjusted, the thickness of the gate insulating film 5 below the gate electrode 6 and the source / drain region 7 and the thickness of the gate insulating film 5 on the source / drain region 7 are increased. It is more preferable because the distance between the region and the gate electrode 6 can be adjusted to an optimum value.

  Further, the shape of the gate insulating film in the vicinity of the lower end corner of the gate electrode 6 does not have to be the shape shown in FIG. 57, and the same effect can be obtained even if it has the shape shown in any of FIGS. 59 to 67, for example.

  The distance formed between the gate electrode 6 and the source / drain region 7 can be adjusted by changing the shape of the gate insulating film 5 in the vicinity of the lower end corner of the gate electrode 6 as in the modification shown here. Therefore, the capacitance can be set within a suitable range.

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to these, In the category of the summary of the invention as described in a claim, it can change variously.

  In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage.

Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

Sectional schematic diagram for demonstrating the field effect transistor which concerns on Embodiment 1 of this invention Enlarged view for explaining the field-effect transistor according to the first embodiment Enlarged view for explaining the field-effect transistor according to the first embodiment The figure of the result of having examined the electric field of the field effect transistor concerning Embodiment 1 The figure of the result of having examined about the electrostatic capacitance of the field effect transistor concerning Embodiment 1 Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 1. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 1. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 1. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 1. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 1. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on the modification of Embodiment 1. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on the modification of Embodiment 1. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on the modification of Embodiment 1. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on the modification of Embodiment 1. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on the modification of Embodiment 1. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on the modification of Embodiment 1. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on the modification of Embodiment 1. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on the modification of Embodiment 1. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 2 of this invention. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 2. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 2. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 2. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on Embodiment 2. FIG. Sectional schematic diagram for demonstrating the manufacturing process of the field effect transistor which concerns on Embodiment 2. FIG. Sectional schematic diagram for demonstrating the manufacturing process of the field effect transistor which concerns on Embodiment 3 of this invention. Sectional schematic diagram which shows the modification of the field effect transistor which concerns on Embodiment 3. FIG. Sectional schematic diagram which shows the modification of the field effect transistor which concerns on Embodiment 3. FIG. Sectional schematic diagram which shows the modification of the field effect transistor which concerns on Embodiment 3. FIG. Sectional schematic diagram which shows the modification of the field effect transistor which concerns on Embodiment 3. FIG. Sectional schematic diagram which shows the modification of the field effect transistor which concerns on Embodiment 3. FIG. Sectional schematic diagram which shows the modification of the field effect transistor which concerns on Embodiment 3. FIG. Sectional schematic diagram which shows the modification of the field effect transistor which concerns on Embodiment 3. FIG. Sectional schematic diagram which shows the modification of the field effect transistor which concerns on Embodiment 3. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on Embodiment 4 of this invention. Sectional schematic diagram for demonstrating the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 4. FIG. Sectional schematic diagram for demonstrating the field effect transistor which concerns on Embodiment 5 of this invention. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 5. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 5. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 5. FIG. Sectional schematic diagram for demonstrating the manufacturing method of the field effect transistor which concerns on Embodiment 5. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 5 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 5 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 5 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 5 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 5 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 5 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 5 Sectional schematic diagram for demonstrating the field effect transistor which concerns on Embodiment 6 of this invention. Sectional schematic diagram for demonstrating the field effect transistor which concerns on Embodiment 6. FIG. Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6 Sectional schematic diagram for demonstrating the modification of the field effect transistor which concerns on Embodiment 6

Explanation of symbols

1 ... semiconductor substrate 2 ... isolation region 3 ... P-well region 4 ... N-channel region 5 ... gate insulating film 6 ... gate electrode 7 ... drain region 8 ... wiring 9 ... interlayer insulating film 10 ... gate sidewalls 11 ... HfO ₂ Film 12 ... Wiring hole 13 ... Silicon nitride film 14 ... Silicon nitride film 15 ... Silicide layer 16 ... Dummy gate electrode 17 ... Silicon oxide film 18 ... Side wall

Claims (13)

A semiconductor substrate;
A pair of source / drain regions arranged adjacent to each other in a gate length direction of a channel planned region formed on the surface of the semiconductor substrate;
A gate electrode including a metal on the semiconductor substrate side and formed on the planned channel region;
A central portion having a first thickness formed in an overlapping region between the semiconductor substrate and the gate electrode, and the central portion sandwiched from the gate length direction and formed on a part of the source / drain region. A semiconductor device comprising: a gate insulating film having a pair of end portions having a film thickness different from the first thickness. The semiconductor device according to claim 1, wherein the gate insulating film contains a metal. 3. The semiconductor device according to claim 1, further comprising a gate sidewall or an interlayer insulating film having a lower dielectric constant than the gate insulating film on a pair of end portions of the gate insulating film. 4. The semiconductor device according to claim 1, wherein a film thickness of the pair of end portions is thinner than the first thickness. 5. 5. The semiconductor device according to claim 4, wherein a length parallel to the gate length direction of the pair of end portions is longer than the first thickness. 6. The semiconductor device according to claim 5, wherein a length parallel to the gate length direction of the pair of end portions is longer than 1.5 times the first thickness. 7. The semiconductor device according to claim 4, wherein a gate side wall is formed on the pair of end portions. The semiconductor device according to claim 4, wherein the pair of end portions extend under the gate electrode. The semiconductor device according to claim 4, wherein the central portion extends to the outside of the side wall of the gate electrode. 4. The semiconductor device according to claim 1, wherein a film thickness of the pair of end portions is larger than the first thickness. 5. 11. The semiconductor device according to claim 10, wherein the pair of thick end portions are separated from a side surface of the gate electrode. Forming a gate insulating film on the surface of the semiconductor substrate;
Forming a gate electrode containing a metal in a portion in contact with the gate insulating film;
Removing the upper part of the gate insulating film on both sides of the gate electrode, leaving only the lower part on the surface of the semiconductor substrate;
And a step of forming a source / drain region by adding impurities to the surface of the semiconductor substrate sandwiching the gate electrode. Forming a gate insulating film on the surface of the semiconductor substrate;
Forming a pattern surrounding a gate electrode formation scheduled region on the gate insulating film;
Removing the upper part of the gate insulating film in the gate electrode formation scheduled region surrounded by the pattern, leaving only the lower part on the semiconductor substrate surface;
Forming a gate electrode containing metal in a portion in contact with the gate insulating film in the gate electrode formation scheduled region;
And a step of forming a source / drain region by adding impurities to the surface of the semiconductor substrate sandwiching the gate electrode.

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