JP2005063564A - Dynamic associative storage cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten retrieving processing time by controlling an increase of a circuit area of a dynamic associative device. <P>SOLUTION: A dynamic associative storage cell is provided with a pair of DRAM cells consisting of a pair of storage capacitors C1, C2 and a pair of transistors Q1, Q2, an XNOR transfer gate consisting of a pair of ground transistors Q3, Q4 and a pair of retrieval transistors Q5, Q6, a pair of transistors Q7, Q8, a DRAM cell consisting of a mask storage capacitor C3 and a transistor Q9, and a mask transistor Q10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a dynamic content addressable memory cell, and more particularly, to a dynamic content addressable memory cell including a DRAM cell that stores a bit signal of mask data for masking retrieval of entry data.

  In a digital system such as a digital computer or a network router, a content addressable memory (CAM) is used to search memory data at high speed. When the capacity of the associative memory device is increased, the area overhead is large in the SRAM configuration, and a dynamic associative memory device having a DRAM structure has been proposed.

  FIG. 10 is a circuit diagram showing an example of a dynamic content addressable memory cell constituting the cell array unit of this dynamic content addressable memory device (see Patent Document 1).

  This conventional dynamic associative memory cell includes a DRAM cell pair composed of a storage capacitor pair C1, C2 and a transistor pair Q1, Q2, and an XNOR (exclusive NOR) transfer gate composed of a ground transistor pair Q3, Q4 and a search transistor pair Q5, Q6. And a transistor pair Q7, Q8.

  Storage capacitor pair C1, C2 and transistor pair Q1, Q2 constitute a DRAM cell pair comprising a storage capacitor and a transistor, respectively, and complementary bit signal pairs of entry data are respectively written from complementary bit line pairs based on word lines. Remember. The storage capacitor pair C1, C2 stores the complementary bit signal pair written from the complementary bit line pair DT, DB via the transistor pair Q1, Q2 in the node pair NOT, NOB, respectively, and the transistor pair Q1, Q2 Each have a gate connected to the word line NWL, a drain connected to the complementary bit line pair DT, DB, and a source connected to the storage capacitor pair C1, C2, respectively. Here, the potential of the power supply Vcp is, for example, a 1/2 power supply level.

  The ground transistor pair Q3, Q4 and the search transistor pair Q5, Q6 are connected between the match line ML and the ground, and transfer charges corresponding to the signal pairs of the search line pair ST, SB and the storage capacitor pair C1, C2. This XNOR transfer gate, which constitutes a gate, is turned off when the search data and the entry data match, and turns on when the bits do not match. The ground transistor pair Q3, Q4 has a gate connected to the storage capacitor pair C1, C2 and the source grounded, respectively, and the search transistor pair Q5, Q6 has the gate connected to the search line pair ST, SB in an inverted manner, respectively. The sources are connected to the drain pairs of the transistor pairs Q3 and Q4, and the drains are connected to the match line ML.

  Transistor pair Q7, Q8 has a gate connected to read word line RWL, a drain connected to bit line pair DT, DB, and a source connected to the drain pair of grounded transistor pair Q3, Q4, respectively.

  This conventional dynamic associative memory cell constitutes a DRAM cell pair and can logically store four values of 2-bit data, and three of these four values are used to form a ternary dynamic associative memory cell. Works as. That is, the value (1, 0) and the value (0, 1) are used for the complementary bit signal pair of the entry data, and the value (0, 0) is the bit signal of the mask data that masks the search for the entry data. The value (1,1) is not used.

  This conventional dynamic associative memory cell has a ground transistor pair Q3 of an XNOR transfer gate connected between the match line ML and the ground, for example, when the bit values of the entry data and the search data stored in the DRAM cell pair match. , Q4 and the search transistor pair Q5, Q6 are turned off, the precharge charge of the match line ML is not discharged to the ground, and the match line ML holds the power supply level. For example, when a value (0, 0) is stored in the DRAM cell pair corresponding to the bit signal of the mask data, both the ground transistor pair Q3, Q4 of the XNOR transfer gate are turned off and the bit value of the search data is concerned. First, the precharge charge of the match line ML is not discharged to the ground, and the match line ML holds the power supply level.

  For this reason, in a memory cell array in which dynamic associative memory cells are arranged in a matrix, when entry data and search data match except for the bit position of mask data, a match line connected in parallel to the dynamic associative memory cells of all bits of each word The ML precharge charge is not discharged, the match line ML holds the power supply level, and a match signal is obtained. Thereby, it is possible to search for one bit range for each entry data.

  In addition, since this conventional dynamic associative memory cell uses a DRAM cell instead of a static memory cell, an increase in the area of the memory cell array due to the addition of functions is suppressed, and further, transistor pairs Q7 and Q8 are added. The data stored in the DRAM cell pair can be read non-destructively, the search operation can be performed independently of the refresh operation, and the memory control becomes easy.

Japanese Patent Laid-Open No. 2002-197872 (FIGS. 2 to 4)

  However, the above-described conventional dynamic associative memory cell stores data in which entry data is modified by mask data, does not store entry data and mask data itself, but as ternary data corresponding to entry data and mask data. Remember. When searching by updating one of the entry data and the mask data, it is necessary to read both the entry data and the mask data from a separate memory, modify the entry data with the mask data, and write it. There is a problem that becomes longer.

  Further, in the conventional dynamic associative memory cell, when the logic value (0, 0) is stored in the DRAM cell pair corresponding to the mask data, the bit line pair DT, DB does not perform complementary operation during refresh, A sense amplifier that amplifies the difference potential between the bit line pairs cannot be used, and a single-ended sense amplifier is required for each of the complementary bit line pairs, and at the time of refresh, the transistor pair is based on the read word line RWL. When data is read to the bit line pair DT, DB via Q7, Q8, it is necessary to reinvert and rewrite data because the read data is inverted, and an increase in circuit area is inevitable as a dynamic associative device.

  Accordingly, an object of the present invention is to suppress an increase in the circuit area of the dynamic associative device and shorten the search processing time.

For this reason, the present invention provides a complementary bit signal pair of entry data written from a complementary bit line pair based on a word line and stored by a storage capacitor pair, and a complementary cell connected between a match line and ground. In a dynamic associative memory cell comprising: a XNOR transfer gate which charges is transferred in response to a search line pair and a signal pair of the storage capacitor pair and is turned off by a bit match between the search data and the entry data;
A DRAM cell in which a bit signal of mask data for masking retrieval of the entry data is written from one of the bit line pairs based on a mask word line and stored by a storage capacitor;
A mask transistor connected between the coincidence line and the XNOR transfer gate is connected to a storage capacitor of the DRAM cell.

The present invention also provides a complementary bit signal pair of entry data written from the complementary bit line pair on the basis of the word line and stored by the storage capacitor pair, and connected between the coincidence line and the ground. In a dynamic associative memory cell comprising: a XNOR transfer gate which charges is transferred in response to a search line pair and a signal pair of the storage capacitor pair and is turned off by a bit match between the search data and the entry data;
A DRAM cell in which a bit signal of mask data for masking the search of the entry data is written from one of the search line pairs based on a mask word line and stored by a storage capacitor;
A mask transistor connected between the coincidence line and the XNOR transfer gate is connected to a storage capacitor of the DRAM cell.

The dynamic associative memory cell of the present invention includes a storage capacitor pair that stores a complementary bit signal pair of entry data, and
A pair of transistors each having a gate connected to a word line, a drain connected to a complementary bit line pair, and a source connected to the storage capacitor pair;
An XNOR transfer gate connected between a match line and ground and transferring charges corresponding to a complementary search line pair and a signal pair of the storage capacitor pair and turning off when the search data and the entry data match,
A mask storage capacitor for storing a bit signal of mask data for masking retrieval of the entry data;
A transistor having a gate connected to a mask word line, a drain connected to one of the bit line pairs, and a source connected to the mask storage capacitor;
And a mask transistor connected between the coincidence line and the XNOR transfer gate with a gate connected to the mask storage capacitor.

The dynamic associative memory cell of the present invention includes a storage capacitor pair that stores a complementary bit signal pair of entry data, and
A pair of transistors each having a gate connected to a word line, a drain connected to a complementary bit line pair, and a source connected to the storage capacitor pair;
An XNOR transfer gate connected between a match line and ground and transferring charges corresponding to a complementary search line pair and a signal pair of the storage capacitor pair and turning off when the search data and the entry data match,
A mask storage capacitor for storing a bit signal of mask data for masking retrieval of the entry data;
A transistor having a gate connected to a mask word line, a drain connected to one of the search line pairs, and a source connected to the mask storage capacitor;
And a mask transistor connected between the coincidence line and the XNOR transfer gate with a gate connected to the mask storage capacitor.

The XNOR transfer gates are connected to the storage capacitor pair, respectively, and a grounded transistor pair having a source connected to the ground,
A search transistor pair having a gate connected to the search line pair, a drain pair of the ground transistor pair, a source connected to each other in an inverted manner, and a drain connected to each other is provided.

The XNOR transfer gates are connected to the storage capacitor pair, respectively, and a grounded transistor pair having a source connected to the ground,
The search line pair includes a search transistor pair in which gates are connected in an inverted manner, a source is connected to a drain pair of the ground transistor pair, and a drain is connected to each other.

  In addition, a transistor pair having a gate connected to the read word line, a drain connected to the bit line pair, and a drain pair of the ground transistor pair each having a source connected in an inverted manner is provided.

  The dynamic associative memory cell according to the present invention stores the entry data and the mask data by providing each associative memory cell with a DRAM cell for storing a bit signal of the mask data for masking the retrieval of the entry data. An algorithm for searching by masking some of the columns can be handled by updating only the mask data, so that the application range of the CAM function can be expanded, and as a result, the search processing time is shortened.

  For reading and refreshing entry data, the bit line pair DT, DB operates in a complementary manner, and a normal sense amplifier that amplifies the difference potential between the bit line pair can be used. In addition, when a sense amplifier for single end is unnecessary, and when data is read to the bit line pair DT, DB via the transistor pair Q7, Q8 based on the read word line RWL at the time of refresh, the read data is not inverted. Rewriting can be performed continuously, the refresh control becomes easy, and the circuit area around the memory cell array is reduced.

  Further, since the additional element for storing the mask data is constituted by the DRAM cell, there is an effect that an increase in the area of the memory cell array due to the addition of the function is suppressed to a minimum as compared with the configuration by the SRAM cell.

  Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the best mode for carrying out the dynamic content addressable memory cell of the present invention. The dynamic associative memory cell of this embodiment includes a DRAM cell pair comprising a storage capacitor pair C1, C2 and a transistor pair Q1, Q2, an XNOR transfer gate comprising a ground transistor pair Q3, Q4 and a search transistor pair Q5, Q6, and a transistor pair. A DRAM cell comprising Q7, Q8, a mask storage capacitor C3 and a transistor Q9, and a mask transistor Q10 are provided.

  As in the prior art, the storage capacitor pair C1, C2 and the transistor pair Q1, Q2 constitute a DRAM cell pair comprising a storage capacitor and a transistor, respectively, and a complementary bit signal pair of entry data is transferred from the bit line pair DT, DB to the word line. Are written and stored based on The storage capacitor pair C1, C2 has one end connected to the power supply VCP, and stores the complementary bit signal pair written from the bit line pair DT, DB via the transistor pair Q1, Q2 in the node pair NOT, NOB, respectively. The transistor pair Q1, Q2 has a gate connected to the word line NWL, a drain connected to the bit line pair DT, DB, and a source connected to the storage capacitor pair C1, C2, respectively. Here, the potential of the power supply Vcp is, for example, a 1/2 power supply level.

  The ground transistor pair Q3, Q4 and the search transistor pair Q5, Q6 are connected between the match line ML and the ground, and transfer charges corresponding to the signal pairs of the search line pair ST, SB and the storage capacitor pair C1, C2. This XNOR transfer gate is configured by a bit match between search data and entry data, and is turned on by a bit mismatch. The ground transistor pair Q3, Q4 has a gate connected to the storage capacitor pair C1, C2, respectively, and the source grounded. The search transistor pair Q5, Q6 has a gate connected to the search line pair ST, SB, respectively. The sources are connected to the drain pairs of Q3 and Q4 in an inverted manner, and the drains are connected to the match line ML. This XNOR transfer gate has the same logical configuration as the conventional XNOR transfer gate in FIG.

  Transistor pair Q7, Q8 has a gate connected to read word line RWL, a drain connected to bit line pair DT, DB, respectively, and a source connected to the drain pair of grounded transistor pair Q3, Q4 in an inverted manner.

  Mask storage capacitor C3 and transistor Q9 constitute a DRAM cell, and store a bit signal of mask data for masking retrieval of entry data. The mask storage capacitor C3 has one end connected to the power supply VCP and stores the bit signal written from the bit line DT via the transistor Q9 in the node MOT. The transistor Q9 has a gate connected to the mask word line MWL and a bit A drain is connected to the line DT, and a source is connected to the mask storage capacitor C3.

  Mask transistor Q10 is connected between match line ML and the XNOR transfer gate, and has its gate connected to mask storage capacitor C3.

  As described above, the dynamic content addressable memory cell according to the present embodiment independently stores a pair of complementary bit signals of entry data and a bit signal of mask data for masking retrieval of entry data. The XNOR transfer gate and the mask transistor Q10 are connected in series between each other, and, for example, if the bit values of the entry data and the search data stored in the DRAM cell pair match, the XNOR transfer gate ground transistor pair Q3, Q4 and the search The series-parallel circuit of the transistor pair Q5 and Q6 is turned off, the match line ML and the ground are turned off, and the precharge charge of the match line ML is not discharged to the ground. Further, for example, when the value 0 is stored as a bit signal of mask data in the DRAM cell, the mask transistor Q10 is turned off, the line between the match line ML and the ground is turned off, and the match line ML is set regardless of the bit value of the search data. Are not discharged to ground.

  For this reason, in the memory cell array in which dynamic associative memory cells are arranged in a matrix, the match line ML connected in parallel to the dynamic associative memory cells of all the bits of each word excludes the bit position of the stored value 0 of the mask data. If the entry data and the search data match, the match line ML holds the precharge charge and becomes a high level, and a match signal is obtained. Thereby, it is possible to search for one bit range for each entry data.

  Furthermore, in the dynamic content addressable memory cell of this embodiment, when one of the entry data and the mask data is updated and searched, unlike the conventional case, the entry data and the mask data can be written independently, and the entry data is modified by the mask data. Thus, the writing process is not required, and the search processing time is shortened. Further, since the DRAM cell is used instead of the static memory cell, the increase in the area of the memory cell array due to the function addition is suppressed to the minimum as in the conventional case.

  FIG. 2 is a block diagram showing a configuration example of a dynamic content addressable memory device using the dynamic content addressable memory cell of the present embodiment. This dynamic associative memory device includes a storage cell array 1, an address input circuit 2, an internal row address generation circuit 3, a row selection decoder 4, a bit line control circuit 5, a sense amplifier control circuit 6, a sense amplifier 7, a data input / output circuit 8, A match line control circuit 9, an encoder 10, a match determination circuit 11, and a control circuit 12 are provided.

  The memory cell array 1 is configured by arranging the dynamic associative memory cells of this embodiment of FIG. 1 in m + 1 rows and n + 1 columns, and FIG. 3 is a block diagram showing a configuration example thereof. The memory cell array 1 includes a word line NWLj, a read word line RWLj, and a match line MLj for each row j (j = 0, 1,..., M), and a column i (i = 0, 1,..., N). Each includes a bit line pair DTi, DBi and a search line pair STi, SBi. Here, the RAM operation and the refresh operation of each dynamic content addressable memory cell are performed using word line NWLj, read word line RWLj and bit line pair DTi, DBi, and mask data write and refresh operations are performed using word line MWLj and refresh operation. The bit line DTi is used, and the CAM operation is performed using the match line MLj and the search line pair STi, SBi.

  The address input circuit 2 takes in an external address in the RAM operation and the CAM operation. During refresh, an external address may be fetched, but an operation of fetching an internal row address generated by the internal row address generation circuit 3 is also performed. The internal row address generation circuit 3 generates a row address at the time of refresh.

  The row selection decoder 4 receives the output signal of the address input circuit 2, and selects and outputs one of the m word lines NWL0 to NWLm shown in FIG. 3 when writing and refreshing entry data. When reading entry data, one of m read word lines RWL0 to RWLm is selected and output. When mask data is written and mask data is refreshed, m mask word lines MWL0 to MWLm are selected. Select one from the list and output it.

  The bit line control circuit 5 equalizes the n bit line pairs DTi, DBi (i = 0, 1,..., N) shown in FIG. Charge and do. It should be noted that the bit line control circuit 5 performs the bit line pair DTi, DBi (i = 0, 1,...) For a certain period before and after the rising period of the m word lines NWL0 to NWLm and the m read word lines RWL0 to RWLm. n) Equalization and precharge to 1/2 power supply level are stopped. By doing so, it becomes possible to propagate the stored data of the memory cell to the bit line pair DTi, DBi (i = 0, 1,..., N).

  The sense amplifier control circuit 6 controls the sense amplifier 7 with the signal ΦS.

  The sense amplifier 7 amplifies the difference potential generated in the bit line pair DTi, DBi by the control signal of the sense amplifier control circuit 6.

  The data input / output circuit 8 receives data input, mask data input, and search data input by the control circuit 12 and outputs data. When writing entry data and mask data to the memory cell, the data is transferred to the bit line pair DTi, DBi (i = 0, 1,..., N) of the memory cell without passing through the sense amplifier. When the entry data is read, the data input / output circuit 8 outputs the data amplified by the sense amplifier 7.

  The match line control circuit 9 is controlled by a signal ΦM ′, and controls precharge and level holding of the match line MLj (j = 0, 1,..., M) shown in FIG.

  The encoder 10 is controlled by the signal ΦE and encodes the match line MLj (j = 0, 1,..., M) to generate and output a match address.

  The coincidence determination circuit 11 is controlled by the signal ΦM, receives the coincidence line MLj (j = 0, 1,..., M) and the output of the encoder, calculates the number of coincidence addresses, and outputs a coincidence flag.

  The control circuit 12 receives a control signal and controls the address input circuit 2, the internal row address generation circuit 3, the data input / output circuit 8, the bit line control circuit 5, the sense amplifier control circuit 6, and the match line control circuit 9. The control signals ΦP, ΦS, ΦM ′, ΦE and ΦM of the encoder 10 and the coincidence determination circuit 11 are output. These control signals direct and control the RAM operation, the CAM operation, and the refresh operation, respectively.

  Next, each operation example of the dynamic content addressable memory cell of this embodiment in the dynamic content addressable memory device of FIG. 2 will be described using timing charts.

  FIG. 4 is a timing chart showing an example of an entry data write operation. Entry data is written by the word line NWL and the bit line pair DT, DB as in the conventional case. First, in the initial state, the word line NWL is at the ground level, the bit line pair DT, DB is at the 1/2 power supply level, the node N0T is at the ground level, and the node N0B is at the power supply level.

  At time t41, the control of the data input / output circuit 8 causes the bit line DT to be at the power supply level and the bit line DB to be at the ground level.

  At time t42, when the word line NWL rises, the transistors Q1 and Q2 are turned on, the bit line pair DT and DB are connected to the node pair N0T and N0B, the potential of the node N0T is the power supply level, and the potential of the node N0B is Becomes ground level. Here, since the transistors Q1 and Q2 are N-type MOSFETs, the potential of the word line NWL is boosted to a potential obtained by adding about twice the threshold voltage to the power supply voltage. As a result, the power supply voltage can be stored in the node N0T or N0B, and the retention characteristic of the entry data is improved.

  At time t43, when the word line NWL falls to the ground level, the transistors Q1 and Q2 are turned off.

  At time t44, the bit line control circuit 5 functions to equalize and precharge the potentials of the bit line pair DT and DB, and the potential of the bit line pair DT and DB becomes 1/2 power supply level. This completes writing of entry data.

  FIG. 5 is a timing chart showing an example of an entry data read operation. The entry data is read out by the read word line NWL and the bit line pair DT, DB as in the conventional case. First, in the initial state, read word line RWL is set to the ground level, bit line pair DT, DB is set to the ½ power supply level, node N0T is set to the power supply level, and node N0B is set to the ground level.

  When read word line RWL rises at time t51, transistors Q7 and Q8 are turned on. Since the potential of node N0T is at the power supply level, transistor Q3 is on, bit line DB is connected to ground power supply GND through transistors Q8 and Q3, and the potential of bit line DB is at the ground level. On the other hand, since the potential of the node N0B is at the ground level, the transistor Q4 is in the off state, there is no path connecting the bit line DT to the ground power supply GND, and the potential of the bit line DT floats at the 1/2 power supply level. It becomes a state.

  At time t52, with the activation of the sense amplifier 7, the differential potential generated in the bit line pair DT, DB is amplified, and the bit line DT becomes the power supply level and the bit line DB becomes the ground level.

  When the word line NWL falls at time t53, the transistors Q7 and Q8 are turned off.

  At time t54, the bit line control circuit 5 functions to equalize and precharge the potentials of the bit line pair DT and DB, and the potential of the bit line pair DT and DB becomes 1/2 power supply level. Thus, reading of entry data is completed.

  As described above, reading by this read word line RWL does not cause destruction of cell data, and the potentials of the nodes N0T and N0B hardly change from the initial values as in the conventional case, and reading is possible even during the search operation. It becomes possible. In addition, the read data of the bit line pair DT, DB is not inverted, and data can be read and rewritten continuously during the refresh operation.

  FIG. 6 is a timing chart showing an example of a mask data write operation. Mask data is written by the mask word line RWL and the bit line DT. First, in the initial state, the mask word line MWL is at the ground level, the bit line pair DT, DB is at the 1/2 power supply level, and the node M0T is at the ground level.

  At time t61, under the control of the data input / output circuit 8, the bit line DT is set to the power supply level and the bit line DB is set to the ground level.

  When the potential of mask word line MWL rises at time t62, transistor Q9 is turned on, bit line DT is connected to node M0T, and the potential of node M0T is at the power supply level. The potential of the third word line NWL is boosted to a potential obtained by adding about twice the threshold voltage to the power supply voltage, as in the case of entry data writing by the word line NWL, so that the power supply level can be stored in the node N0T. Is possible.

  At time t63, when the potential of the mask word line MWL falls to the ground level, the transistor Q9 is turned off.

  At time t64, the potential of the bit line pair DT, DB is equalized and precharged by the action of the bit line control circuit 5, and the potential of the bit line pair DT, DB becomes 1/2 power supply level. This completes the mask data writing. The broken line portion of the node M0T shown in FIG. 6 indicates the case where the mask data “0” is written.

  FIG. 7 is a timing chart showing an example of an entry data search operation when the entry data and the mask data are 1 and 1. The search for entry data is performed using the search line pair ST, SB and the match line ML. Here, it is assumed that match line ML is precharged by a P-type MOSFET based on match line precharge signal MLPC.

  First, the case where the entry data and the search data match is shown. In the initial state, the search lines ST and SB are at the ground level, the match line precharge signal MLPC is at the power supply level, and the match line ML is at the ground level.

  When match line precharge signal MLPC falls at time t71, match line ML is precharged to the power supply level. When match line precharge signal MLPC rises at time t72, precharge ends.

  When the search line ST rises at time t73 because the search data is 1, the transistor Q5 is turned on, but since the node N0B is at the ground level, the transistor Q4 is off, and the match line ML is connected to the ground power supply GND. Since there is no path connected to, the match line ML maintains the power supply level.

  At time t74, the search line ST falls and the search ends. As a result, since the match line ML holds the VDD level, the encoder determines that the entry data and the search data match.

  Next, a case where entry data and search data do not match is shown. When match line precharge signal MLPC falls at time t75, match line ML is precharged to the power supply level, and when match line precharge signal MLPC rises at time t76, precharge ends.

  At time t77, since the search data is 0, when the search line SB rises, the transistor Q6 is turned on. Since node N0T is at the power supply level, transistor Q3 is on, match line ML is connected to ground power supply GND through the paths of transistors Q10, Q6 and Q3, and match line ML falls.

  At time t78, the search line SB falls and the search ends. As a result, since the match line ML is at the ground level, the encoder determines that the entry data and the search data do not match.

  FIG. 8 is a timing chart showing an example of an entry data search operation when entry data and mask data are 0 and 1.

  First, the case where entry data and search data do not match is shown. In the initial state, the search lines ST and SB are at the ground level, the match line precharge signal MLPC is at the power supply level, and the match line ML is at the ground level.

  When match line precharge signal MLPC falls at time t81, match line ML is precharged to the power supply level, and when match line precharge signal MLPC rises at time t82, precharge ends.

  At time t83, since the search data is 1, when the search line ST rises, the transistor Q5 is turned on. Since node N0B is at the power supply level, transistor Q4 is on, match line ML is connected to ground power supply GND through the paths of transistors Q10, Q5 and Q4, and match line ML falls.

  At time t84, the search line ST falls and the search ends. As a result, since the match line ML is at the ground level, the encoder determines that the entry data and the search data do not match.

  Next, a case where the entry data and the search data match is shown. When match line precharge signal MLPC falls at time t85, match line ML is precharged to the power supply level. When match line precharge signal MLPC rises at time t86, precharge ends.

  At time t87, since the search data is 0, when the search line SB rises, the transistor Q6 is turned on. Since node N0T is at the ground level, transistor Q3 is off, and there is no path connecting match line ML to ground power supply GND, so match line ML maintains the power supply level.

  At time t88, the search line SB falls and the search ends. As a result, since the match line ML holds the VDD level, the encoder determines that the entry data matches the search data.

  As shown in FIG. 7 and FIG. 8, in the dynamic associative memory cell of this embodiment, when the mask data is 1, if the entry data and the search data match, the match line ML holds the power supply level, and the mismatch data The match line ML is at the ground level. When the mask data is 0, the mask transistor Q10 is in the off state, and therefore the match line ML maintains the power supply level regardless of the values of the entry data and the search data. FIG. 9 is an explanatory diagram showing a truth table of the coincidence line ML output in the dynamic associative memory cell according to the present embodiment, corresponding to the contents described above.

  As the dynamic associative memory device shown in FIG. 2, as shown in FIG. 3, the dynamic associative memory cells of this embodiment are arranged in a matrix and the match lines ML in the same row are bundled. When entry data and search data do not match in any cell, the signal falls to the ground level, and the encoder determines that entry data and search data do not match, and entry data and search data match in all cells The match line ML holds the VDD level, and the encoder determines that the entry data and the search data match.

  Finally, the refresh operation will be described. In general DRAM refresh, all row addresses are sequentially accessed within a predetermined time, and data is read and rewritten. In the dynamic associative memory device using the dynamic associative memory cell of this embodiment shown in FIG. Done. At this time, in the memory array 1 shown in FIG. 3, among the row addresses, the read word line groups RWL0 to RWLm and the word line groups NWL0 to NWLm are sequentially selected to read and rewrite entry data. The entry data is refreshed nondestructively, and the mask data is refreshed by sequentially selecting the mask word line groups MWL0 to MWLm and reading and rewriting the mask data.

  In the dynamic content addressable memory cell of this embodiment, the DRAM cell storing the bit signal of the mask data has been described as being written from the bit line DT. However, the present invention is not limited to this description, and various modifications can be considered. For example, a modification in which a DRAM cell storing a bit signal of mask data is written from the other bit line DB is possible, and the same effect can be obtained. Further, this modification and the dynamic associative memory of the present embodiment By alternately arranging the cells in the column direction, the junction capacitance of the mask transistor Q9 is evenly distributed to the bit line pair DTi, DBi, the capacity unbalance of the bit line pair DTi, DBi is reduced, and the cause of malfunction is eliminated. The effect that is done is produced.

  Further, for example, a modification in which a DRAM cell storing a bit signal of mask data is written from one of the search line pairs ST and SB is possible, and it is obvious that the same effect can be obtained.

It is a circuit diagram which shows the best form for implementing the dynamic content addressable memory cell of this invention. It is a block diagram which shows the structural example of the dynamic content addressable memory device using the dynamic content addressable memory cell of FIG. FIG. 3 is a block diagram illustrating a configuration example of a memory cell array 1 in the dynamic associative memory device of FIG. 2. FIG. 3 is a timing diagram illustrating an example of an entry data write operation in the dynamic content addressable memory cell of FIG. 1. FIG. 3 is a timing diagram showing an example of an entry data read operation in the dynamic content addressable memory cell of FIG. 1. FIG. 3 is a timing diagram illustrating an example of a mask data write operation in the dynamic content addressable memory cell of FIG. 1. FIG. 3 is a timing chart showing an example of an entry data search operation in the dynamic content addressable memory cell of FIG. 1. FIG. 12 is a timing chart showing another example of search operation for entry data in the dynamic content addressable memory cell of FIG. 1. FIG. 2 is an explanatory diagram showing a truth table of coincidence line ML output in the dynamic associative memory cell of FIG. 1. It is a circuit diagram which shows the example of the conventional dynamic content addressable memory cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Address input circuit 3 Internal row address generation circuit 4 Row selection decoder 5 Bit line control circuit 6 Sense amplifier control circuit 7 Sense amplifier 8 Data input / output circuit 9 Match line control circuit 10 Encoder 11 Match determination circuit 12 Control circuit C1 ˜C3 storage capacitor DT, DB bit line ML match line MOT, NOT, NOB node MWL mask word line NWL word line RWL read word line ST, SB search line Q1-Q10 transistor Vcp power supply

Claims (7)

A complementary bit signal pair of entry data is written from a complementary bit line pair based on a word line and stored by a storage capacitor pair, respectively, a complementary search line pair connected between a match line and ground, and the storage In a dynamic associative memory cell comprising an XNOR transfer gate that transfers charges corresponding to a signal pair of a capacitor pair and turns off when the search data and bit data of the entry data match,
A DRAM cell in which a bit signal of mask data for masking retrieval of the entry data is written from one of the bit line pairs based on a mask word line and stored by a storage capacitor;
A dynamic associative memory cell comprising: a mask transistor connected between the coincidence line and the XNOR transfer gate, with a gate connected to the storage capacitor of the DRAM cell. A complementary bit signal pair of entry data is written from a complementary bit line pair based on a word line and stored by a storage capacitor pair, respectively, a complementary search line pair connected between a match line and ground, and the storage In a dynamic associative memory cell comprising an XNOR transfer gate that transfers charges corresponding to a signal pair of a capacitor pair and turns off when the search data and bit data of the entry data match,
A DRAM cell in which a bit signal of mask data for masking the search of the entry data is written from one of the search line pairs based on a mask word line and stored by a storage capacitor;
A dynamic associative memory cell comprising: a mask transistor connected between the coincidence line and the XNOR transfer gate, with a gate connected to the storage capacitor of the DRAM cell. Storage capacitor pairs each storing complementary bit signal pairs of entry data;
A pair of transistors each having a gate connected to a word line, a drain connected to a complementary bit line pair, and a source connected to the storage capacitor pair;
An XNOR transfer gate connected between a match line and ground and transferring charges corresponding to a complementary search line pair and a signal pair of the storage capacitor pair and turning off when the search data and the entry data match,
A mask storage capacitor for storing a bit signal of mask data for masking retrieval of the entry data;
A transistor having a gate connected to a mask word line, a drain connected to one of the bit line pairs, and a source connected to the mask storage capacitor;
A dynamic associative memory cell comprising: a mask transistor connected to a gate of the mask storage capacitor and connected between the match line and the XNOR transfer gate. Storage capacitor pairs each storing complementary bit signal pairs of entry data;
A pair of transistors each having a gate connected to a word line, a drain connected to a complementary bit line pair, and a source connected to the storage capacitor pair;
An XNOR transfer gate connected between a match line and ground and transferring charges corresponding to a complementary search line pair and a signal pair of the storage capacitor pair and turning off when the search data and the entry data match,
A mask storage capacitor for storing a bit signal of mask data for masking retrieval of the entry data;
A transistor having a gate connected to a mask word line, a drain connected to one of the search line pairs, and a source connected to the mask storage capacitor;
A dynamic associative memory cell comprising: a mask transistor connected to a gate of the mask storage capacitor and connected between the match line and the XNOR transfer gate. The XNOR transfer gate is connected to the storage capacitor pair, and a grounded transistor pair having a source grounded;
5. The dynamic association as claimed in claim 1, further comprising: a search transistor pair having a gate connected to the search line pair, a drain pair of the ground transistor pair having a source connected to each other in an inverted connection, and a drain connected to each other. Memory cell. The XNOR transfer gate is connected to the storage capacitor pair, and a grounded transistor pair having a source grounded;
5. The dynamic association as claimed in claim 1, further comprising: a search transistor pair having a gate connected to the search line pair in an inverted manner, a source connected to the drain pair of the ground transistor pair, and a drain connected to each other. Memory cell.   7. The dynamic associative memory cell according to claim 5, further comprising: a transistor pair having a gate connected to each read word line, a drain connected to each of said bit line pair, and a drain pair of said ground transistor pair each having a source connected in an inverted manner. .

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