JP2005063170A - Memory system and memory access method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely protect a secret code stored in a memory. <P>SOLUTION: This memory system comprises a first memory storing secret codes; a processor having an address conversion buffer for converting a virtual address to a physical address, the processor executing a program using the virtual address; and an access propriety determination circuit for determining the propriety of access to the first memory by the processor. The access propriety determination circuit stores an access propriety determination code which is the criterion for the determination of access propriety in a second memory and, on receipt of the physical address converted from the virtual address of the access propriety determination code from the processor, determines the access propriety based on the access propriety determination code stored in this physical address in the second memory and an access code outputted from the processor that is a determination object in the determination of access propriety. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory system and a memory access method.

  FIG. 4 is a block diagram showing a configuration of a conventional memory system.

  In this memory system, a ROM (Read Only Memory) 21 stores a secret code such as a decryption key used for decrypting encrypted data (for example, video data or music data stored on a DVD). Various programs executed by the CPU 23 are stored in the ROMs 22 (1) to 22 (n). The CPU 23 executes the program, extracts the secret code from the ROM 21, and performs various processes (for example, decoding of video data and music data).

  In order to acquire the secret code in the ROM 21, the CPU 23 first sends the physical address MADR in which the secret code is stored to the address line 24. The dividing circuit 25 connected to the address line 24 specifies the physical address MADR, the upper address UADR for selecting the ROM 21, 22 (1) to 22 (n), and the physical address in the selected ROM. For the lower address LADR. The dividing circuit 25 sends the upper address UADR to the decoding circuit 26, while sending the lower address LADR to the ROMs 21, 22 (1) to 22 (n).

  The decode circuit 26 selects one of the ROMs 21, 22 (1) to 22 (n) based on the received upper address UADR. Specifically, the decode circuit 26 outputs a chip selection signal (low level) to the ROM to be selected. Here, it is assumed that the decoding circuit 26 selects the ROM 21 in which the secret code is stored.

  The selected ROM 21 reads out the data (the secret code here) stored in the lower address LADR received from the dividing circuit 25 and sends it to the CPU 23 via a data line (not shown).

  As can be seen from the above, in this memory system, the CPU 23 sends the physical address MADR storing the secret code to the address line 24 in order to obtain the secret code in the ROM 21.

  Here, the physical address MADR flowing through the address line 24 can be observed by using a semiconductor analyzer.

  Therefore, in the configuration described above, a person who has an unauthorized purpose observes the address line 24 and acquires the physical address MADR of the confidential code, thereby creating a program for acquiring the confidential code, Easily access sensitive code.

  FIG. 5 is a block diagram showing a configuration of another conventional memory system.

  This other memory system is obtained by adding an access permission determination circuit 28 for determining whether or not the processor 23 is permitted to access the ROM 21 to the memory system described above.

  The access permission determination circuit 28 includes a register 29 that stores an access permission determination code serving as a determination criterion for access permission. The register 29 has a predetermined physical address MADR.

  When accessing the ROM 21, the CPU 23 first sends an access code to be determined in determining whether access is possible to the access permission determination circuit 28 by designating the physical address MADR of the register 29.

  The access permission determination circuit 28 compares the access permission determination code in the register 29 with the received access code, and outputs a permission signal (low level) indicating access permission to the OR circuit 30 if the two match.

  The OR circuit 30 passes the chip selection signal (low level) from the decoding circuit 26 to the ROM 21 only when the permission signal (low level) is input from the access permission determination circuit 28.

However, even in the memory system as described above, the physical address MADR of the register 29 can be easily obtained by observing the address line 24. If the physical address MADR of the register 29 is known, the access permission determination code in the register 29 can be easily obtained. As a result, the secret code is easily obtained.
Japanese Patent Laid-Open No. 2000-276397 JP 2001-265654 A JP 2002-31239 A

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory system and a memory access method capable of effectively protecting a confidential code stored in a memory.

  A first memory system of the present invention includes a first memory storing a secret code, an address translation buffer that translates a virtual address into a physical address, a processor that executes a program using the virtual address, An access permission determination circuit for determining whether a processor can access the first memory, wherein an access permission determination code serving as a determination criterion in the determination of the access permission is stored in a second memory, and the access permission determination code When the physical address converted from the virtual address is received from the processor, the access permission determination code stored at the physical address in the second memory and the determination target in the determination of the access permission Based on the access code output from the processor There are, characterized by comprising a an access determination circuit determines the access permission.

  In the second memory system of the present invention, when access to the first memory is permitted, the processor converts the virtual address of the confidential code into the physical address using the address conversion buffer. The secret code is acquired from the first memory using the physical address.

  The memory access method of the present invention includes a first memory storing a secret code, a processor having an address translation buffer for executing a program using a virtual address and converting the virtual address to a physical address, and the processor. In a memory system comprising: an access enable / disable determining circuit that stores an access enable / disable determination code serving as a determination criterion in the access enable / disable determination that determines whether or not access to the first memory is stored in the second memory; A memory access method for obtaining the secret code from the first memory, wherein the access permission determination circuit receives the physical address converted from the virtual address of the access permission determination code from the processor; The access permission / inhibition judgment circuit A step of receiving from the processor an access code to be determined in determination of accessibility; the access determination circuit receiving the access determination code stored in the physical address in the second memory; Determining whether or not the processor can access the first memory based on an access code; and when the processor is permitted to access the first memory, the processor uses the address translation buffer. And converting the virtual address of the secret code into the physical address and obtaining the secret code from the first memory using the physical address.

  According to the present invention, a virtual address is used as a memory address in a program, and the processor is provided with an address translation buffer that translates a virtual address into a physical address. Even when the physical address of the confidential code is exposed, the confidential code can be reliably protected.

  FIG. 1 is a block diagram showing a configuration of a memory system as an embodiment of the present invention.

  This memory system is composed of, for example, one chip.

  As shown in FIG. 1, a ROM (memory) 1 stores a secret code such as a decryption key for decrypting encrypted data.

  On the other hand, the ROMs 2 (1) to 2 (n) store a program that realizes acquisition of a confidential code from the ROM 1, a program that realizes various processes using the acquired confidential code, and the like. Various processes include, for example, decrypting encrypted music data using a secret code.

  The CPU 3 executes various programs including programs stored in the ROMs 2 (1) to 2 (n). The program to be executed by the CPU 3 uses the virtual address VADR as a memory address.

  The CPU 3 includes a memory management unit (MMU: Memory Management Unit) 10 including an address translation buffer (TLB: Translation Lookaside Buffer) (not shown) that converts the virtual address VADR into a physical address MADR.

  The address translation buffer has an address translation table in which the virtual address VADR and the physical address MADR are mapped as shown in FIG. The address conversion buffer uses this address conversion table to convert the virtual address VADR to the physical address MADR as shown in FIG. This address conversion table is prepared in advance by the user, for example.

  When accessing the ROMs 1, 2 (1) to 2 (n), the CPU 3 converts the virtual address VADR into the physical address MADR using the memory management unit 10. Such a mechanism is also employed in operating systems such as Windows-CE (registered trademark), Linux (registered trademark), and EPOC (registered trademark).

  The access permission determination circuit 4 determines whether or not the CPU 3 permits access to the ROM 1. The access enable / disable determining circuit 4 includes a register 5 that holds an access enable / disable determination code (for example, a code having a size of 1 byte) that serves as a determination reference when determining access enable / disable. The register 5 has a predetermined physical address MADR.

  When the CPU 3 accesses the ROM 1, an access code that is a determination target in determining whether access is possible is sent to the access permission determination circuit 4 by specifying the physical address MADR of the register 5. The access permission determination circuit 4 permits access to the ROM 1 if the access permission determination code in the register 5 matches the received access code.

  On the other hand, when the designated physical address MADR is different from the physical address MADR of the register 5 or when the access code does not match the access permission determination code, the access permission determination circuit 4 does not permit access to the ROM 1.

  The access permission determination circuit 4 outputs a permission signal (low level) to the OR circuit 9 when permitting access, and outputs a non-permission signal (high level) to the OR circuit 9 when not permitted.

  The dividing circuit 8 receives the physical address MADR from the CPU 3, and receives a higher address UADR for selecting one of the ROMs 1, 2 (1) to 2 (n), and a lower address for specifying the physical address in each ROM. The physical address MADR is divided into LADR. Of the upper address UADR and the lower address LADR, the dividing circuit 8 sends the upper address UADR to the decoding circuit 6 and the lower address LADR to ROM1, ROM2 (1) to ROM2 (n).

  The decode circuit 6 selects one of the ROM 1 and the ROMs 2 (1) to 2 (n) based on the upper address UADR received from the dividing circuit 8.

  Specifically, when selecting the ROM 1, the decode circuit 6 outputs a chip selection signal (low level) to the OR circuit 9 and does not select the chips for the ROMs 2 (1) to 2 (n). A signal (high level) is output. The OR circuit 9 passes the chip selection signal (low level) from the decoding circuit 6 to the ROM 1 only when the permission signal (low level) is input from the above-described access permission determination circuit 4.

  On the other hand, when selecting any one of the ROMs 2 (1) to 2 (n), the decode circuit 6 outputs a chip selection signal (low level) to the selected ROM, and outputs it to the unselected ROM and the OR circuit 9 On the other hand, a chip non-selection signal (high level) is output.

  The selected ROMs 1, 2 (1) to 2 (n) take out the data stored in the lower address LADR received from the dividing circuit 8 and send it to the CPU 3 via a data line (not shown).

  Next, the processing operation by the above-described memory system will be described by taking as an example the case where the CPU 3 reads the confidential code in the ROM 1.

  First, the CPU 3 reads the virtual address VADR of the register 5 from the program, and reads an access code that is an access permission determination target from the program. The CPU 3 uses the memory management unit 10 to convert the virtual address VADR into a physical address MADR and sends the physical address MADR and the access code to the access permission determination circuit 4.

  When the received physical address MADR matches the physical address MADR of the register 5, the access permission determination circuit 4 determines whether or not the access permission determination code in the register 5 matches the received access code. . When determining that the access permission determination code matches the access code, the access permission determination circuit 4 sends an access permission signal (low level) to the OR circuit 9.

  On the other hand, the CPU 3 reads the virtual address VADR of the secret code from the program, and converts this virtual address VADR into a physical address MADR using the memory management unit 10. The CPU 3 sends this physical address MADR to the dividing circuit 8.

  The dividing circuit 8 divides the received physical address MADR into an upper address UADR and a lower address LADR, and sends the upper address UADR to the decoding circuit 6. On the other hand, the dividing circuit 8 sends the lower address LADR to the ROMs 1, 2 (1) to 2 (n).

  The decode circuit 6 selects the ROM 1 based on the received upper address UADR. That is, the decode circuit 6 outputs a chip selection signal (low level) to the OR circuit 9, and outputs a chip non-selection signal (high level) to the ROMs 2 (1) to 2 (n).

  Since the OR circuit 9 receives the access permission signal (low level) from the access permission determination circuit 4, it passes the chip selection signal (low level) from the decoding circuit 6 to the ROM 1.

  The ROM 1 takes out the confidential code stored in the lower address LADR received from the dividing circuit 8 and sends it to the CPU 3 via a data line (not shown). Thereby, CPU3 acquires a secret code.

  As described above, according to the present embodiment, a virtual address is used as a memory address in a program to be executed by the CPU, and the CPU is provided with an address conversion buffer that converts the virtual address into a physical address. Therefore, even if the physical address of the accessibility determination code and the physical address of the confidential code are exposed by observing the address line, the confidential code can be effectively protected. This is because it is substantially difficult to specify the virtual address corresponding to the physical address unless the address conversion table is exposed.

  In addition, according to the present embodiment, since a very simple configuration called a virtual storage system is adopted, the change from the circuit configuration shown in the prior art (increase in circuit scale) is extremely small and stored in the ROM. Secure confidential code. Further, since the system configuration itself is very simple, there is little latency (waiting time) penalty when the CPU 3 accesses the ROM.

It is a block diagram which shows the structure of the memory system as embodiment of this invention. It is a figure for demonstrating an address translation buffer. It is a figure which shows the address conversion table which an address conversion buffer holds. It is a block diagram which shows the structure of the memory system in the past. It is a block diagram which shows the structure of another conventional memory system.

Explanation of symbols

1 ROM (memory)
2 (1) to 2 (n) ROM
3 CPU
4 Accessibility determination circuit 5 Register 6 Decode circuit 8 Dividing circuit 9 OR circuit 10 Memory management unit 11 Address line

Claims (3)

A first memory storing a secret code;
A processor having an address translation buffer for translating a virtual address into a physical address, and executing a program using the virtual address;
An access enable / disable determining circuit for determining whether or not the processor can access the first memory, wherein an access enable / disable determination code serving as a determination reference in the access enable / disable determination is stored in a second memory, and the access enable / disable determination is performed. When the physical address converted from the virtual address of the code is received from the processor, the access permission determination code stored at the physical address in the second memory and the determination target in the determination of the access permission An access permission determination circuit that determines whether the access is possible based on an access code output from the processor.
With a memory system.   When the access to the first memory is permitted, the processor converts the virtual address of the confidential code to the physical address using the address conversion buffer, and uses the physical address to convert the first address The memory system according to claim 1, wherein the secret code is obtained from a plurality of memories. A first memory storing a secret code; a processor having an address translation buffer for executing a program using a virtual address and converting the virtual address to a physical address; and access to the first memory by the processor In a memory system comprising: an access enable / disable determination circuit that stores an access enable / disable determination code serving as a determination criterion in the access enable / disable determination in a second memory; A memory access method for obtaining code,
The access determination circuit receiving from the processor the physical address converted from the virtual address of the access determination code;
A step of receiving, from the processor, an access code to be determined by the access permission determination circuit in the determination of access permission;
The access permission determination circuit determines whether the processor can access the first memory based on the access permission determination code stored at the physical address in the second memory and the received access code. Determining
When access to the first memory is permitted, the processor converts the virtual address of the confidential code to the physical address using the address conversion buffer, and uses the physical address to convert the first address. Obtaining the secret code from a memory of one;
A memory access method comprising:

Images