JP2005057253A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, which will enhance the throughput of an ion implantation process by forming a TFT having an Lov region [a region where an LDD (lightly doped drain) region overlaps a gate electrode through a gate insulator film] and a TFT having an Loff region [a region where an LDD region does not overlap a gate electrode through a gate insulator film] on the same substrate without providing a resist mask that is used for forming the Lov region. <P>SOLUTION: This method is used for manufacturing a semiconductor device provided with a transistor which has an active layer, a gate insulator film which is in contact with the active layer, a gate electrode which overlaps the active layer through the gate insulator film. By implanting impurities from one direction slanting to the active layer, a portion of a first region in the active layer, that overlaps the gate electrode through the gate insulator film, and a second region in the active layer excluding the first region are doped with impurities. The second region is positioned toward the one direction relative to the first region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a transistor having an LDD region, in particular, a thin film transistor, and further relates to a semiconductor device using the manufacturing method.

  In a semiconductor display device formed using an inexpensive glass substrate, as the resolution becomes higher, the ratio of the area around the pixel portion used for mounting (frame area) to the substrate tends to increase, and miniaturization tends to be hindered. . Therefore, it is considered that there is a limit to a method for mounting an IC formed using a single crystal silicon wafer on a glass substrate, and an integrated circuit including a driver circuit is integrally formed on the same glass substrate as a pixel portion. Technology, so-called system-on-panel construction, is regarded as important.

  However, since an integrated circuit formed on a glass substrate has a lower degree of integration than an integrated circuit formed on a single crystal silicon wafer, miniaturization of a semiconductor element is an important issue for practical use. . With the miniaturization of semiconductor elements, integrated circuits formed on a glass substrate can be highly integrated. Therefore, the semiconductor display device can be reduced in size, weight, power consumption, and speed. it can. In addition to the integrated circuit, high definition can be realized in the pixel portion by miniaturization of a semiconductor element.

  A semiconductor display device in which a thin film transistor (TFT) using an amorphous semiconductor film is provided in a pixel portion has advantages of high productivity and low cost. However, a TFT using the amorphous semiconductor film has mobility. Has the disadvantage of being low. Therefore, an amorphous semiconductor film is used for a driver circuit that requires high-speed operation, such as a scanning line driver circuit for selecting a pixel or a signal line driver circuit for supplying a video signal to the selected pixel. The thin film transistor used is considered unsuitable. Therefore, an IC chip on which a driving circuit is mounted is manufactured using a single crystal silicon wafer, and the IC chip is mounted around the pixel portion by a TAB (Tape Automated Bonding) method, a COG (Chip on Glass) method, or the like. The form to be used is generally adopted.

  However, the silicon wafer has a higher unit price than a glass substrate and is not suitable for providing an inexpensive IC chip, and has the advantage of low cost, which is a feature of a semiconductor display device using an amorphous semiconductor film. I ca n’t do it right now. In addition, the size of silicon wafers that are relatively large in the market is at most about 12 inches in diameter. Although silicon wafers with a size larger than 12 inches are on the market, the price per unit area further increases as the size increases. Therefore, in order to increase the number of IC chips obtained from one substrate and increase the throughput, the cost must be sacrificed.

Therefore, Patent Documents 1 and 2 below disclose a technique in which a drive circuit is formed on a glass substrate, divided into strips, and mounted on a substrate on which a pixel portion is formed.
Japanese Patent Laid-Open No. 7-014880 JP-A-11-160734

  As described in Patent Document 1 and Patent Document 2, by using a substrate of the same material as the substrate on which the pixel portion is formed (hereinafter referred to as an element substrate), a drive circuit is formed and mounted on the element substrate. The occurrence rate of defects in the contact portion of the terminal caused by the difference in thermal expansion coefficient can be suppressed, and the yield can be increased. Further, the cost of the entire semiconductor display device can be suppressed by forming the drive circuit over the glass substrate.

  By the way, as the definition of the pixel portion increases, the ratio of the region around the pixel portion (frame region) used for mounting to the substrate increases, which tends to hinder downsizing. Therefore, it is desirable that the IC chip mounted on the substrate on which the pixel portion is formed be smaller. However, an integrated circuit formed over a glass substrate has a lower degree of integration than an integrated circuit formed over a single crystal silicon wafer. Therefore, miniaturization of a semiconductor element formed over a glass substrate is an important issue in promoting downsizing of a semiconductor display device and high integration of an integrated circuit. If an integrated circuit formed over a glass substrate can be highly integrated by miniaturization of a semiconductor element, the semiconductor display device can be reduced in size, weight, power consumption, and speed.

  However, the miniaturization of a TFT, which is one of the semiconductor elements, is accompanied by a problem that reliability is reduced due to the hot carrier effect. Therefore, an LDD (Lightly Doped Drain) structure (LDD structure) has been conventionally employed as a means for suppressing the hot carrier effect. The LDD structure is a structure in which an LDD region having an impurity concentration lower than that of the source / drain region is provided between the source / drain region and the channel formation region. In particular, when the LDD region has a (Gate Overlapped Lightly Doped Drain) structure (GOLD structure) that overlaps the gate electrode via the gate insulating film, the high electric field in the vicinity of the drain is relaxed and the hot carrier effect is more effectively achieved. It is known that it can prevent and improve reliability. In this specification, a region where the LDD region overlaps with the gate electrode through the gate insulating film is referred to as a Lov region, and a region where the LDD region does not overlap is referred to as a Loff region.

Patent Document 3 listed below describes that deterioration of a transistor can be suppressed by adopting a GOLD structure.
JP-A-8-153875

  A TFT having a Loff region tends to reduce off-state current as compared with a TFT having a Lov region. Therefore, it is suitable to use a TFT having a Loff region for a switching element of a pixel in which reduction of off current is more important than high-speed driving. On the other hand, a TFT having a Lov region can be driven at a higher speed than a TFT having a Loff region. Specifically, switching can be performed at higher speed. The driving circuit has a higher operating frequency than the pixel portion, and high-speed driving is more important than reduction of off-state current. Therefore, a TFT having a Lov region is suitable. It is desirable to use a TFT having a Loff region and a TFT having a Lov region in accordance with characteristics desired for a circuit element.

  Several methods for manufacturing a TFT having a Lov region have been proposed. One of them is a method of performing ion implantation obliquely using a gate electrode as a mask. By using the above method, a dopant (impurity) can be added using an ion implantation method to a region overlapping with the gate electrode and the gate insulating film without using a resist mask and suppressing the number of steps.

  However, in order to form the Lov region on both the source region side and the drain region side, it is necessary to perform ion implantation at least twice from different implantation directions, which may hinder improvement in throughput in the ion implantation step. In addition, there is a method (tilt rotation) in which the substrate is rotated and uniformly inclined ion implantation (tilt rotation). However, this method requires precise control of the rotation of the substrate, and requires a large apparatus for performing ion implantation. become. In particular, it is not suitable for increasing the size of the substrate, and this is a factor that hinders improvement in throughput.

  Further, the above method has a problem that TFTs having a Lov region and TFTs having a Loff region cannot be made separately on the same substrate. Therefore, in the above method, when the pixel portion and the driving circuit are integrated by system-on-panel, a TFT having a Lov region and a TFT having a Loff region cannot be separately formed on the same substrate. In addition, a TFT having no LDD region itself and a TFT having a Lov region in which the source region and the drain region are in contact with the channel formation region cannot be separately formed on the same substrate.

  A TFT having a Lov region and a TFT having a Loff region can be separately formed on the same substrate by performing dopant separation using a resist mask. However, the number of resist masks and the number of processes cannot be suppressed, which increases the manufacturing cost. In addition, not only TFTs having Loff regions but also transistors having offset gate structures and transistors whose source and drain regions are in contact with the channel formation region are formed on the same substrate as TFTs having Lov regions. As a result, the number of resist masks and the number of processes cannot be suppressed, which increases the manufacturing cost.

  In view of the above problems, the present invention provides a transistor having a Lov region without forming a resist mask for forming a Lov region, a transistor having a Loff region, a transistor having an offset gate structure, and a source region and a drain region forming a channel. A method for manufacturing a semiconductor device that can be manufactured on the same substrate together with a transistor in contact with a region and the like and can improve throughput in an ion implantation process, and a cost per panel is suppressed. The present invention relates to a semiconductor device that can Furthermore, the present invention relates to a semiconductor device using a chip in which an integrated circuit is formed with a thin semiconductor film (hereinafter referred to as a thin film chip) that can reduce the cost per sheet.

  The present inventors considered that the position of the Lov region provided in the active layer of the transistor may be changed in accordance with the implantation direction instead of changing the dopant implantation direction in accordance with the position of the Lov region. In other words, the ion implantation is fixed implantation with a single implantation direction, and the positional relationship of the Lov region, the channel formation region, and the gate electrode functioning as a mask during ion implantation is determined in accordance with the implantation direction. . In this specification, the implantation direction means a direction in which a dopant is implanted from an ion source.

  Specifically, one injection direction is determined in such a direction that the dopant crosses the surface of the active layer obliquely, and an end portion of the gate electrode overlapping the active layer is directed to the injection direction side. That is, the gate electrode and the active layer are arranged so that the region where the active layer other than the region is exposed is located on the implantation direction side of the region overlapping with the gate electrode. With the above structure, the Lov region can be formed on both the source region side and the drain region side by ion implantation from one implantation direction. Therefore, in all transistors having the same polarity and in the Lov region, the Lov region is provided closer to the dopant implantation direction than the channel formation region.

  In the ion implantation for forming the Lov region, in the transistor having the Loff region, the active layer and the gate are aligned in accordance with the implantation direction so that the impurity is added only to the regions to be the source region and the drain region. The positional relationship between the electrode and the Loff region is determined. Specifically, a region serving as a Loff region and a channel formation region is covered with a resist mask, and a region overlapping with the resist mask and a region where an active layer other than the region is exposed are along the implantation direction. Arrange to touch. In other words, the end portion of the resist mask that overlaps the active layer is arranged along the implantation direction. With the above structure, a transistor having a Lov region and a transistor having a Loff region can be separately formed over the same substrate.

  In addition, in the ion implantation for forming the Lov region, in a transistor that does not have the LDD region and the source region and the drain region are in contact with the channel formation region, impurities are present only in the region that becomes the source region and the drain region. In order to be added, the positional relationship among the active layer, the gate electrode, and the LDD region is determined in accordance with the implantation direction. Specifically, the region overlapping the gate electrode and the region where the active layer other than the region is exposed are arranged so as to be in contact with each other along the implantation direction. In other words, the end portion of the gate electrode overlapping the active layer is arranged along the implantation direction. With the above structure, a transistor having a Lov region on the same substrate and a transistor in which a source region and a drain region are in contact with a channel formation region can be separately formed.

  Further, in the ion implantation for forming the Lov region, in a transistor having an offset region, an impurity is added only to a region to be a source region and a drain region, and an offset region is formed in the implantation direction. In addition, the positional relationship among the active layer, the gate electrode, and the offset region is determined. Specifically, the gate electrode and the active layer are arranged so that the exposed region of the active layer is positioned on the opposite side of the implantation direction from the region overlapping with the gate electrode other than the region. In other words, the gate electrode is overlapped with the active layer so that the end of the gate electrode is located on the side opposite to the implantation direction. With the above structure, a transistor having a Lov region and a transistor having an offset region can be formed separately on the same substrate.

  In addition to the above structure, a continuous wave laser may be used for crystallization of the semiconductor film. A semiconductor film crystallized using only pulsed laser light is formed by aggregating a plurality of crystal grains, and the positions and sizes of the crystal grains are random. Compared with the inside of a crystal grain, the interface (crystal grain boundary) of a crystal grain has innumerable recombination centers and trap centers due to an amorphous structure or crystal defects. When carriers are trapped in this trapping center, the potential of the crystal grain boundaries is increased, which becomes a barrier against the carriers, so that there is a problem that the current transport characteristics of the carriers are deteriorated. On the other hand, in the case of a continuous wave laser beam, a crystal is continuously grown in the scanning direction by irradiating the semiconductor film while scanning the irradiation region (beam spot) of the laser beam in one direction. A collection of crystal grains made of a single crystal extending along the length can be formed. Therefore, the mobility of a TFT used for a thin film chip can be increased by crystallizing the semiconductor film using a continuous wave laser.

  Note that semiconductor devices included in the category of the present invention include all kinds of semiconductor devices using transistors, such as a microprocessor, an image processing circuit, and a semiconductor display device. The thin film chip itself is also included in the category of the semiconductor device of the present invention. The semiconductor display device includes a liquid crystal display device, a light emitting device including a light emitting element typified by an organic light emitting device (OLED) in each pixel, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display). Other display devices having a circuit element using a semiconductor film in a driver circuit are included in the category.

  A transistor that can form the Lov region by using the manufacturing method of the present invention is not limited to a TFT using polycrystalline silicon, microcrystalline silicon (semi-amorphous silicon (SAS)), or amorphous silicon. A transistor formed using single crystal silicon or a transistor using SOI may be used. Further, a transistor using an organic semiconductor or a transistor using carbon nanotubes may be used. In addition, the transistor used in the semiconductor device of the present invention may have a single gate structure, a double gate structure, or a multi-gate structure having a gate electrode higher than that.

  According to the present invention, a transistor having a Lov region is replaced with a transistor having a Loff region, a transistor in which a source region and a drain region are in contact with a channel formation region, and an offset without providing a resist mask for forming the Lov region. A transistor having a region and the like can be separately formed over the same substrate. Therefore, the number of resist masks and the number of processes can be reduced, and the manufacturing cost can be reduced. In addition, an improvement in throughput in the ion implantation process can be realized.

  In the present invention, an integrated circuit using the above manufacturing method may be mounted as a thin film chip on a substrate provided with a pixel portion or another integrated circuit to form a semiconductor device. In addition to the above manufacturing method, the present invention includes, in its category, the thin film chip using the manufacturing method and a semiconductor device on which the thin film chip is mounted. Since the cost per sheet of the thin film chip of the present invention can be suppressed, the cost of the semiconductor device itself having the thin film chip can also be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

  A method for manufacturing a semiconductor device of the present invention will be described. FIG. 1A shows a top view of an active layer 101 and a gate electrode 102 functioning as a mask when ion implantation is performed to form a Lov region. A cross-sectional view along A-A ′ in FIG. 1A is shown in FIG.

  Arrows indicate the implantation direction during ion implantation, and obliquely intersect the surface of the active layer 101. Further, the active layer 101 and the gate electrode 102 overlap with each other with the gate insulating film 103 interposed therebetween. In the present invention, the region 104 exposed without overlapping the gate electrode 102 is provided closer to the dopant implantation direction than the region 105 where the gate electrode 102 of the active layer 101 overlaps. That is, the end portion 106 of the gate electrode 102 which is surrounded by a broken line and overlaps the active layer 101 is directed to the injection direction side.

  With the above structure, a dopant can be implanted into part of the region 105 where the gate electrode 102 of the active layer 101 overlaps during ion implantation, so that the Lov region 107 can be formed. Further, the source region, the drain region 108, and the channel formation region 109 can be separately formed by the ion implantation. In FIG. 1, two Lov regions 107 are formed so as to sandwich the channel formation region 109, and a source region and a drain region 108 are formed so as to sandwich the channel formation region 109 and the two Lov regions 107. .

  Note that in the case where the Lov region is formed only on one of the source region side and the drain region side, only one end portion of the gate electrode overlapping with the active layer may be directed to the implantation direction side. Alternatively, the end of the gate electrode that overlaps the active layer is directed to the implantation direction side only on one side, and the region that overlaps the gate electrode and the active layer are exposed on the other side. The region is in contact with the region along the injection direction.

  Next, the case where ion implantation is performed obliquely to manufacture a TFT having no Lov region will be described. FIG. 2A is a top view of the active layer 201 and the gate electrode 202 functioning as a mask when ion implantation is performed obliquely. A cross-sectional view taken along A-A ′ in FIG. 2A is illustrated in FIG. A cross-sectional view taken along B-B ′ in FIG. 2A is illustrated in FIG. A cross-sectional view taken along C-C ′ in FIG. 2A is illustrated in FIG.

  Arrows indicate the implantation direction during ion implantation, and obliquely intersect the surface of the active layer 201. The active layer 201 and the gate electrode 202 overlap with each other with the gate insulating film 203 interposed therebetween. In FIG. 2, the region 204 exposed without overlapping the gate electrode 202 and the region 205 where the gate electrode 202 of the active layer 201 overlaps are arranged so as to be in contact with each other along the dopant implantation direction. ing.

  With the above structure, at the time of ion implantation, a dopant can be implanted only into a region 204 that is exposed without overlapping with the gate electrode 202, and a source region or a drain region can be formed in the region 204. Further, a channel formation region can be formed in the region 205 where the gate electrode 202 of the active layer 201 overlaps by the ion implantation.

  Next, a layout of each transistor when a TFT having a Loff region and a TFT having a Lov region are formed over the same substrate will be described. FIG. 6A is a top view of the pixel portion 1301 formed over the same substrate 1300 and the signal line driver circuit 1302 and the scan line driver circuit 1303 included in the driver circuit. In FIG. 6A, the arrow indicates the direction of dopant implantation. Then, a part of the signal line driver circuit 1302 illustrated in FIG. 6A is enlarged and illustrated in FIG. Further, a part of the pixel portion 1301 illustrated in FIG. 6A is enlarged and illustrated in FIG.

  As shown in FIG. 6B, in the TFT having the Lov region used in the signal line driver circuit 1302, the end portion 1313 of the gate electrode 1312 overlapping the active layer 1311 is directed to the injection direction side. ing. Note that in the case where the Lov region is formed only on one of the source region side and the drain region side, only one end portion 1323 of the gate electrode 1322 that overlaps with the active layer 1321 needs to be directed to the implantation direction side. Alternatively, the edge of the gate electrode overlapping the active layer is directed to the injection direction side only on one of the source region side and the drain region side, and the gate electrode is overlapped on the other side. The region and the region where the active layer is exposed may be arranged so as to be in contact with each other along the implantation direction.

  FIG. 6D is a cross-sectional view taken along A-A ′ in FIG. 6B after ion implantation. As shown in FIG. 6D, the Lov region 1314 can be formed in the active layer 1311 and the Lov region 1324 can be formed in the active layer 1321 by ion implantation from an oblique implantation direction.

  As shown in FIG. 6C, the TFT 1340 used in the pixel portion 1301 and having no Lov region includes a region overlapping with the gate electrode 1333 in the active layer 1331 and an exposure of the active layer 1331. It arrange | positions so that the area | region which is doing may contact | connect along an injection | pouring direction. In other words, the end 1336 of the gate electrode 1333 that overlaps with the active layer 1331 is along the injection direction. Similarly, the TFT 1341 having no Lov region is arranged such that a region of the active layer 1332 that overlaps with the gate electrode 1334 and a region where the active layer 1332 is exposed are in contact with each other along the implantation direction. To do. In other words, the end portion 1337 of the gate electrode 1334 overlapping the active layer 1332 is along the injection direction.

  FIG. 6E shows a cross-sectional view along B-B ′ in FIG. 6C after ion implantation. As shown in FIG. 6E, only the channel formation region 1343, the source region, and the drain region 1342 can be formed in the active layer 1331 even if ions are implanted from an oblique implantation direction. Although not illustrated, also in the active layer 1332, only a channel formation region, a source region, and a drain region can be formed.

  As described above, in the semiconductor device manufactured using the manufacturing method of the present invention, the TFT having the Lov region formed on the substrate has all the positions of the Lov region implanted with respect to the channel formation region as long as the polarity is the same. It will be aligned in the direction. That is, the direction from the Lov region to the channel formation region is aligned. In the TFT in which the source region and the drain region are in contact with the channel formation region, the channel formation region and the source region or the drain region are in contact with each other as long as the polarity is the same. In addition, as long as the TFT having the Loff region has the same polarity, the channel formation region and the Loff region are in contact with each other along the implantation direction. In addition, as long as the TFTs having the offset region have the same polarity, the position of the offset region with respect to the channel formation region is aligned in the direction opposite to the implantation direction.

  Note that although FIG. 6 illustrates an example in which the TFT in which the source region and the drain region are in contact with the channel formation region is formed over the same substrate as the TFT having the Lov region, the present invention is not limited to this structure. When the TFT having the Loff region and the TFT having the Lov region are formed on the same substrate, the edge of the resist mask that overlaps the active layer in the TFT forming the Loff region may be along the implantation direction. good.

  According to the present invention, the TFT having the Lov region is replaced with the TFT having the Loff region, the TFT in which the source region and the drain region are in contact with the channel formation region, without providing a resist mask for forming the Lov region. Can be made on the same substrate. Therefore, the number of resist masks and the number of processes can be reduced, and the manufacturing cost can be reduced. In addition, an improvement in throughput in the ion implantation process can be realized.

  Next, the layout of the TFT having the Lov region in the semiconductor device of the present invention will be described.

  FIG. 8A shows a top view of a TFT having a Lov region. 401 corresponds to an active layer, 402 corresponds to a gate electrode, and 403 corresponds to a Lov region. The arrow corresponds to the dopant implantation direction when the Lov region 403 is formed. The Lov region 403 is provided only in either the source region or the drain region, and the Lov region 403 faces the dopant implantation direction side.

  FIG. 8B shows another top view of a TFT having a Lov region. Reference numeral 411 denotes an active layer, 412 denotes a gate electrode, and 413a and 413b denote Lov regions. The arrow corresponds to the dopant implantation direction when the Lov regions 413a and 413b are formed. In FIG. 8B, the Lov regions 413a and 413b face the dopant implantation direction side.

  FIG. 8C shows another top view of a TFT having a Lov region. 421 is an active layer, 422 is a gate electrode, 423a, 423b, 424a, 424b corresponds to a Lov region. The arrow corresponds to the dopant implantation direction when the Lov regions 423a, 423b, 424a, 424b are formed. In FIG. 8C, the Lov regions 423a, 423b, 424a, 424b face the dopant implantation direction side.

  FIG. 8D shows another top view of a TFT having a Lov region. Reference numeral 431 denotes an active layer, 432a and 432b denote gate electrodes, and 433a and 433b correspond to Lov regions. The arrow corresponds to the dopant implantation direction when forming the Lov regions 433a and 433b. In FIG. 8D, the Lov regions 433a and 433b face the dopant implantation direction side. The Lov region 433a overlaps with the gate electrode 432a, and the Lov region 433b overlaps with the gate electrode 432b. An end portion 435a of the gate electrode 432a overlapping the active layer 431 is along the implantation direction. An end portion 435b of the gate electrode 432b that overlaps with the active layer 431 is along the injection direction.

  As shown in FIG. 8, in the present invention, TFTs having various structures can be manufactured. Note that the layout of the TFT shown in the figure is only one embodiment, and the present invention is not limited to the structure shown in FIG.

  Next, a method for manufacturing a transistor having an offset gate structure is described.

  In the method for manufacturing a semiconductor device of the present invention, a transistor having an offset gate structure in which a gate electrode does not overlap with a source region or a drain region is a channel having a transistor having a Lov region, a transistor having a Loff region, or a source region or drain region. A transistor in contact with a formation region can be formed over the same substrate. In a transistor having an offset gate structure, a region between a source region or a drain region and a region of the active layer that overlaps with a gate electrode is referred to as an offset region. By providing the offset region on the drain region side, the electric field in the vicinity of the drain region can be relaxed and the transistor can have a high breakdown voltage.

  FIG. 5A shows a top view of an active layer 801 and a gate electrode 802 functioning as a mask when ions are implanted obliquely. 5B is a cross-sectional view taken along line A-A ′ in FIG.

  Arrows indicate the implantation direction during ion implantation, and obliquely intersect the surface of the active layer 801. The active layer 801 and the gate electrode 802 overlap with the gate insulating film 803 interposed therebetween. In the present invention, the region 805 overlapping the gate electrode 802 of the active layer 801 is provided closer to the dopant implantation direction than the region 804 exposed without overlapping the gate electrode 802. That is, the end portion 806 of the gate electrode 802 which is surrounded by a broken line and overlaps with the active layer 801 is directed to the side opposite to the implantation direction.

  With the above structure, during ion implantation, a part of the region 804 that is exposed without overlapping with the gate electrode 802 of the active layer 801 is blocked by the gate electrode 802 so that the dopant is not implanted, or other An offset region 807 can be formed in which dopant is less likely to be implanted than in the exposed region. Further, by the ion implantation, a source region and a drain region 808 can be separately formed in the exposed region 804, and a channel formation region 809 can be formed in the region 805 overlapping with the gate electrode 802. In FIG. 5, two offset regions 807 are formed so as to sandwich the channel formation region 809, and a source region and a drain region 808 are formed so as to sandwich the channel formation region 809 and the offset region 807.

  The length of the offset region in the implantation direction (offset length) can be adjusted by the incident angle of the dopant with respect to the active layer at the time of ion implantation.

  In the case where the offset region is formed only on one of the source region side and the drain region side, only one end of the gate electrode overlapping the active layer is directed to the opposite side to the implantation direction. good. At the other end, the region overlapping the gate electrode and the region where the active layer is exposed are arranged so as to be in contact with each other along the implantation direction.

  According to the present invention, a TFT having a Lov region can be formed separately from a TFT having an offset gate structure on the same substrate without providing a resist mask for forming the Lov region. Therefore, the number of resist masks and the number of processes can be reduced, and the manufacturing cost can be reduced. In addition, an improvement in throughput in the ion implantation process can be realized.

  Note that by using a continuous wave laser for crystallization of the semiconductor film used as the active layer, a collection of crystal grains including a single crystal extending in the scanning direction can be formed. Therefore, the mobility of a TFT used for a thin film chip can be increased by crystallizing the semiconductor film using a continuous wave laser.

  FIG. 3A illustrates a state in which a thin semiconductor film 1601 formed over a substrate 1600 is crystallized using continuous wave laser light. After the semiconductor film 1601 is crystallized as shown in FIG. 3A, the semiconductor film 1601 is patterned, a gate electrode, a mask, or the like is formed, and then doping is performed as shown in FIG. 3B. . Note that the semiconductor film 1601 may be patterned before crystallization with laser light or may be patterned after crystallization.

  The direction of implantation at the time of doping is determined in an oblique direction with respect to the semiconductor film (the semiconductor film 1604 after patterning in FIG. 3B) as indicated by solid arrows. Then, a plurality of integrated circuits are formed on the substrate 1600 by performing dopant activation, various insulating films, wirings, and the like thereafter. After the integrated circuit is formed, as shown in FIG. 3C, the substrate 1600 is divided to form a thin film chip 1603 in which the integrated circuits are separated.

  Next, a layout of each transistor in a thin film chip in which a TFT in which a source region and a drain region are in contact with a channel formation region and a TFT having a Lov region is formed will be described. FIG. 4A shows an external view of a thin film chip. In the thin film chip illustrated in FIG. 4A, an integrated circuit 301 formed using a thin semiconductor film and a connection terminal 302 are formed over a substrate 300. In FIG. 4A, the arrow indicates the direction of dopant implantation. In the integrated circuit 301, for example, a TFT in which a source region and a drain region are in contact with a channel formation region and a TFT having a Lov region are formed.

  FIG. 4B shows a top view of a TFT having a Lov region included in the integrated circuit 301, and FIG. 4C shows a channel formation of a source region and a drain region included in the integrated circuit 301. A top view of a TFT in contact with a region is shown.

  As shown in FIG. 4B, in the TFT having the Lov region, the end portion 313 of the gate electrode 312 overlapping the active layer 311 is directed to the injection direction side. Note that in the case where the Lov region is formed only on one of the source region side and the drain region side, only one of the end portions 323 of the gate electrode 322 overlapping the active layer 321 may be directed to the implantation direction side. Alternatively, the edge of the gate electrode overlapping the active layer is directed to the injection direction side only on one of the source region side and the drain region side, and the gate electrode is overlapped on the other side. The region and the region where the active layer is exposed may be arranged so as to be in contact with each other along the implantation direction.

  FIG. 4D is a cross-sectional view taken along A-A ′ in FIG. 4B after ion implantation. As shown in FIG. 4D, the Lov region 314 can be formed in the active layer 311 and the Lov region 324 can be formed in the active layer 321 by ion implantation from an oblique implantation direction.

  As shown in FIG. 4C, in the TFT 340 in which the source region and the drain region are in contact with the channel formation region, the region of the active layer 331 that overlaps with the gate electrode 333 and the active layer 331 are exposed. It arrange | positions so that the area | region which contacts may contact | connect along an injection | pouring direction. In other words, the end portion 336 of the gate electrode 333 overlapping the active layer 331 is along the injection direction.

  FIG. 4E shows a cross-sectional view taken along B-B ′ of FIG. 4C after ion implantation. As shown in FIG. 4E, only the channel formation region 343, the source region, and the drain region 342 can be formed in the active layer 331 even if ions are implanted from an oblique implantation direction.

  Note that although FIG. 4 illustrates an example in which the TFT in which the source region and the drain region are in contact with the channel formation region is formed over the same substrate as the TFT having the Lov region, the present invention is not limited to this structure. When the TFT having the Loff region and the TFT having the Lov region are formed on the same substrate, the edge of the resist mask that overlaps the active layer in the TFT forming the Loff region may be along the implantation direction. good. In the case where the TFT having the offset region is formed on the same substrate as the TFT having the Lov region, the end portion of the gate electrode overlapping the active layer in the TFT having the offset region is opposite to the implantation direction. Just turn to the side.

  As described above, in the semiconductor device manufactured using the manufacturing method of the present invention, the TFT having the Lov region formed on the substrate has all the positions of the Lov region implanted with respect to the channel formation region as long as the polarity is the same. It will be aligned in the direction. In the TFT in which the source region and the drain region are in contact with the channel formation region, the channel formation region and the source region or the drain region are in contact with each other as long as the polarity is the same. In addition, as long as the TFT having the Loff region has the same polarity, the channel formation region and the Loff region are in contact with each other along the implantation direction. In addition, as long as the TFTs having the offset region have the same polarity, the position of the offset region with respect to the channel formation region is aligned in the direction opposite to the implantation direction.

  According to the present invention, the TFT having the Lov region is replaced with the TFT having the Loff region, the TFT in which the source region and the drain region are in contact with the channel formation region, without providing a resist mask for forming the Lov region. Can be made on the same substrate. Therefore, the number of resist masks and the number of processes can be reduced, and the manufacturing cost can be reduced. In addition, an improvement in throughput in the ion implantation process can be realized.

  Next, a state in which the thin film chip formed using the above manufacturing method is mounted on the substrate over which the pixel portion is formed is illustrated in FIGS. In FIG. 7A, a pixel portion 6002 and a scan line driver circuit 6003 are formed over a substrate 6001. A signal line driver circuit formed on the thin film chip 6004 is mounted on the substrate 6001. Specifically, a signal line driver circuit formed in the thin film chip 6004 is attached to the substrate 6001 and electrically connected to the pixel portion 6002. Reference numeral 6005 denotes an FPC, and the power supply potential, various signals, and the like are supplied to the pixel portion 6002, the scanning line driver circuit 6003, and the signal line driver circuit formed in the thin film chip 6004 through the FPC 6005, respectively. .

  In FIG. 7B, a pixel portion 6102 and a scan line driver circuit 6103 are formed over a substrate 6101. A signal line driver circuit formed on the thin film chip 6104 is further mounted on an FPC 6105 mounted on a substrate 6101. A potential of a power source, various signals, and the like are supplied to the pixel portion 6102, the scan line driver circuit 6103, and the signal line driver circuit formed in the thin film chip 6104 through the FPC 6105.

  The mounting method of the thin film chip is not particularly limited, and a known COG method, wire bonding method, TAB method, or the like can be used. Further, the position where the thin film chip is mounted is not limited to the position shown in FIG. 7 as long as electrical connection is possible. Although FIG. 7 shows an example in which only the signal line driver circuit is formed by a thin film chip, the scanning line driver circuit may be formed by a thin film chip, and the controller, CPU, memory, etc. are formed by a thin film chip. You may make it implement. Further, instead of forming the entire signal line driving circuit and the scanning line driving circuit with a thin film chip, only a part of the circuits constituting each driving circuit may be formed with a thin film chip.

  Note that in a semiconductor display device in which a driver circuit is mounted as a thin film chip, a transistor used for a pixel portion is not limited to a TFT formed using an amorphous semiconductor film such as amorphous silicon. A TFT using a microcrystalline semiconductor film or a polycrystalline semiconductor film may be used. A transistor formed using single crystal silicon or a transistor using SOI may be used. Further, a transistor using an organic semiconductor or a transistor using carbon nanotubes may be used. By separately forming and mounting an integrated circuit such as a driver circuit with a thin film chip, the yield can be increased and the characteristics of each circuit can be improved compared to the case where all the circuits are formed on the same substrate as the pixel portion. The combined process can be easily optimized.

  Next, a specific method for manufacturing the semiconductor display device of the present invention will be described. Note that here, an n-channel TFT having a Lov region used for a driver circuit, a p-channel TFT in which a source region and a drain region are in contact with a channel formation region, and a Loff region used for a pixel portion. An n-channel TFT having n will be described as an example.

  First, as illustrated in FIG. 10A, a base film 501 is formed over the insulating surface of the substrate 500.

  As the substrate 500, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate including a SUS substrate or a silicon substrate with an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. .

  The base film 501 is provided to prevent an alkali metal such as Na or an alkaline earth metal contained in the substrate 500 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element. Therefore, the insulating film is formed using an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide that can suppress diffusion of alkali metal or alkaline earth metal into the semiconductor film. In this embodiment, a silicon nitride oxide film is formed to a thickness of 10 to 400 nm (preferably 50 to 300 nm) by a plasma CVD method.

  Note that the base film 501 may be a single layer or a stack of a plurality of insulating films. In the case of using a substrate containing an alkali metal or an alkaline earth metal, such as a glass substrate, a SUS substrate, or a plastic substrate, it is effective to provide a base film from the viewpoint of preventing impurity diffusion. However, when diffusion of impurities does not cause any problem, such as a quartz substrate, it is not necessarily provided.

  Next, a base film 501 is formed by a PCVD method, and the semiconductor film 502 is formed without being exposed to the air. The thickness of the semiconductor film 502 is 25 to 100 nm (preferably 30 to 60 nm). Note that the semiconductor film 502 may be an amorphous semiconductor or a polycrystalline semiconductor. As the semiconductor, not only silicon but also silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

  Next, as illustrated in FIG. 10A, the semiconductor film 502 is crystallized by a laser crystallization method. In the case where a polycrystalline semiconductor is used for the semiconductor film 502, an amorphous semiconductor is first formed, and the amorphous semiconductor may be crystallized using a known crystallization method. Known crystallization methods include crystallization by heating using an RTA or furnace annealing furnace, crystallization by laser light irradiation, crystallization using a catalytic metal, infrared light. And a method of crystallization using the same. Further, these crystallization methods may be combined.

In the case of using a laser, crystallization can be performed using a pulsed laser represented by an excimer laser, a YAG laser, a YVO ₄ laser, or the like. For example, when a YAG laser is used, a second harmonic wavelength that is easily absorbed by the semiconductor film is used. The oscillation frequency 30～300KHz, the energy density was 300~600mJ / cm ² (typically 350~500mJ / cm ^2), may be set the scanning speed to be irradiated by several shots to any point.

Further, when the amorphous semiconductor film is crystallized, a crystal having a large grain size can be obtained by using a solid-state laser capable of continuous oscillation and using the second to fourth harmonics of the fundamental wave. Typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light with an output of 10 W. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Preferably, the laser beam is shaped into a rectangular or elliptical shape on the irradiation surface by an optical system, and the object to be processed is irradiated. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed by moving the semiconductor film 502 relative to the laser beam at a speed of about 10 to 2000 cm / sec.

As the continuous wave laser, a known continuous wave gas laser or solid state laser can be used. Examples of gas lasers include Ar laser and Kr laser. As solid lasers, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, Y ₂ O ₃ laser, glass laser, ruby laser, alexandride laser, Ti: sapphire A laser etc. are mentioned. The harmonic with respect to the fundamental wave can be obtained by using a nonlinear optical element.

  Note that the mobility of the TFT can be further increased by aligning the scanning direction of the laser light and the direction in which carriers move in the channel formation region as much as possible.

  After the semiconductor film 502 is crystallized, it is patterned to form island-shaped semiconductor films 503 to 505 used as active layers, as shown in FIG. The film thickness of the island-shaped semiconductor films 503 to 505 is 25 to 100 nm (preferably 30 to 60 nm).

  Note that a top view corresponding to FIG. 10B is shown in a region surrounded by a broken line 600. A cross-sectional view taken along line A-A ′ and a cross-sectional view taken along line B-B ′ of the broken line 600 corresponds to FIG.

  Next, as illustrated in FIG. 10C, a gate insulating film 506 is formed so as to cover the island-shaped semiconductor films 503 to 505. Since the thickness of the gate insulating film 506 is reduced by about 10 to 20 nm in dry etching performed to form a gate electrode later, it is desirable to set the thickness in consideration of the reduction. Specifically, a gate insulating film is formed to a thickness of about 40 to 150 nm (more preferably 60 to 120 nm).

For the gate insulating film, for example, silicon oxide, silicon nitride, silicon nitride oxide, or the like can be used. As a film formation method, a plasma CVD method, a sputtering method, or the like can be used. For example, in the case where a gate insulating film using silicon oxide is formed by a plasma CVD method, a gas in which TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed is used, a reaction pressure is 40 Pa, a substrate temperature is 300 to 400 ° C., and a high frequency (13. 56 MHz) The power density is 0.5 to 0.8 W / cm ² and the film is formed.

  Aluminum nitride can be used as the gate insulating film. Aluminum nitride has a relatively high thermal conductivity and can efficiently dissipate heat generated in the TFT. In addition, after forming silicon oxide or silicon oxynitride which does not contain aluminum, a laminate of aluminum nitride may be used as the gate insulating film.

  Next, as illustrated in FIG. 10D, a conductive film 507 is formed over the gate insulating film 506. The conductive film 507 may be formed as a single layer, or may have a stacked structure including a plurality of layers such as two layers or three layers as necessary. In this embodiment, W is used and the conductive film 507 is formed so as to have a thickness of 300 nm.

  Specifically, each conductive film can be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy or compound containing the element as a main component. For example, a combination in which the first layer is Ta and the second layer is W, or the first layer is TaN, the second layer is Al, the first layer is TaN, and the second layer is Cu is also conceivable. Further, an AgPdCu alloy may be used for either the first layer or the second layer. A three-layer structure in which W, an alloy of Al and Si (Al-Si), and TiN are sequentially stacked may be employed. Tungsten nitride may be used instead of W, an alloy film of Al and Ti (Al—Ti) may be used instead of an alloy of Al and Si (Al—Si), and Ti may be used instead of TiN. It may be used. However, in the case where a plurality of conductive films are formed, a material that can secure an etching selectivity is used if it is desired to have a difference in the width in the channel length direction of the conductive films of each layer after etching.

For example, the conductive film 507 may be formed by stacking a conductive film made of TaN having a thickness of 20 to 100 nm and a conductive film made of W having a thickness of 100 to 400 nm. In this case, TaN has a purity of 99.99% as a target, the temperature in the chamber is room temperature, the flow rate of Ar is 50 ml / min, the flow rate of N ₂ is 10 ml / min, the pressure in the chamber is 0.6 Pa, Film formation can be performed at a film formation power of 1 kW and a film formation speed of about 40 nm / min. In addition, W has a purity of 99.99% as a target, the temperature in the chamber is 230 ° C., the flow rate of Ar is 100 ml / min, the pressure in the chamber is 1.5 Pa, the film formation power is 6 kW, and the film formation rate is about The film can be formed at 390 nm / min.

  Note that it is important to select an optimal etching gas as appropriate depending on the material of the conductive film. Further, the material of each conductive layer is not limited to that shown in this embodiment mode.

Next, as shown in FIG. 11A, the conductive film 507 is patterned to form gate electrodes 508 to 510. In this embodiment mode, an ICP (Inductively Coupled Plasma) etching method is used. A gas mixture of Cl ₂ and CF ₄ is used as an etching gas, and plasma is formed by applying RF (13.56 MHz) power of 3.2 W / cm ² at a pressure of 1 Pa. RF power (13.56 MHz) of 224 mW / cm ² is also applied to the substrate side (sample stage), whereby a substantially negative self-bias voltage is applied. Under this condition, the etching rate of the W film is about 100 nm / min. By the etching, the side surfaces of the gate electrodes 508 to 510 are slightly tapered. Further, when etching is performed so as not to leave a residue of the conductive film, the surface of the gate insulating film 506 that is not covered with the gate electrodes 508 to 510 may be etched by about 5 to 10 nm or more.

  Note that a top view corresponding to FIG. 11A is shown in a region surrounded by a broken line 601. A cross-sectional view taken along A-A ′ and a cross-sectional view taken along B-B ′ of the broken line 601 corresponds to FIG.

Next, as illustrated in FIG. 11B, using the gate electrodes 508 to 510 as a mask, an impurity (dopant) imparting n-type conductivity is added to the island-shaped semiconductor films 503 to 505 (first Doping process). Doping is performed by ion implantation. Doping is performed at a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 30 to 90 kV. As the impurity element imparting n-type conductivity, a Group 5 element such as P, As, or Sb that functions as a donor, or a Group 6 element such as S, Te, or Se is used. In this embodiment mode, P is used. By the first doping process, first impurity regions 511 to 515 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first impurity regions 511 to 515 in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ .

  Note that a top view corresponding to FIG. 11B is shown in a region surrounded by a broken line 602. A cross-sectional view taken along the broken line A-A ′ and a cross-sectional view taken along the B-B ′ of the broken line 602 corresponds to FIG. Reference numeral 516 denotes the implantation direction during doping. In the ion implantation shown in FIG. 11B, the implantation direction is substantially perpendicular to the substrate 500 from the upper surface of the substrate 500.

Next, as illustrated in FIG. 11C, a resist mask 520 is formed so as to cover the entire island-shaped semiconductor film 504 and a part of the island-shaped semiconductor film 505, and second doping treatment is performed. In the second doping process, the acceleration voltage is set to 50 to 150 kV, and the dose is set to 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ² .

  Note that a top view corresponding to FIG. 11C is shown in a region surrounded by a broken line 603. A cross-sectional view taken along the broken line A-A ′ and a cross-sectional view taken along the B-B ′ of the broken line 603 corresponds to FIG. Moreover, the arrow has shown the injection | pouring direction in the case of doping. In the second doping treatment, the ion implantation direction is set with respect to the surface of the island-shaped semiconductor film 503 so that impurities are added to part of a region where the gate electrode 508 and the island-shaped semiconductor film 503 overlap. Keep diagonal. Note that an end portion 521 of the gate electrode 508 which overlaps with the island-shaped semiconductor film 503 is directed to the implantation direction side. In addition, the region of the island-shaped semiconductor film 505 that overlaps with the resist mask 520 and the region that is exposed without overlapping are arranged so as to be in contact with each other along the implantation direction.

By the second doping treatment, the island-shaped semiconductor film 505 is formed by further adding impurities to the second impurity region 526 and the first impurity regions 514 and 515 in a region overlapping with the resist mask 520. A third impurity region 527 is formed. In addition, in the island-shaped semiconductor film 503, a fourth impurity region 524 is formed in a region overlapping with the gate electrode 508, and a third impurity region 525 is formed by further adding an impurity to the first impurity region 511. And are formed. An impurity element imparting n-type conductivity is added to the second impurity region 526 in a concentration range of 5 × 10 ^{17 to} 5 × 10 ¹⁹ atoms / cm ³ , and 1 × 10 ^{19 to} 5 × is added to the third impurity region 525. An impurity element imparting n-type is added in a concentration range of × 10 ²¹ atoms / cm ³ . Note that the concentration of the impurity element in the fourth impurity region 524 varies depending on the incident angle of the dopant and has a certain concentration gradient in the channel length direction, but the concentration is lower than that of the third impurity region 525. .

  The second impurity region 526 corresponds to a Loff region, and the third impurity region 527 corresponds to a source region or a drain region. The third impurity region 525 corresponds to a source region or a drain region, and the fourth impurity region 524 corresponds to a Lov region.

  Note that the island-shaped semiconductor film 504 in which the p-channel TFT is formed does not need to be doped with an n-type impurity by the first doping treatment illustrated in FIG. In this case, it may be covered with a resist mask. Further, in order to reduce the number of resist masks, a resist mask may not be provided, and the concentration of an impurity imparting p-type conductivity may be increased to invert the polarity of the island-shaped semiconductor film to p-type. In this embodiment, the case where the polarity of an island-shaped semiconductor film is reversed to p-type is described.

As shown in FIG. 12A, a resist mask 530 made of resist covers the n-channel island-shaped semiconductor films 503 and 505, and the island-shaped semiconductor film 504 is doped with an impurity imparting p-type conductivity. (Third doping process). In the third doping process, the gate electrode 509 functions as a mask, and a fifth impurity region 531 in which an impurity element imparting p-type conductivity is added to the island-shaped semiconductor film 504 used for the p-channel TFT is formed. The In this embodiment mode, an ion implantation method using diborane (B ₂ H ₆ ) is used. In the fifth impurity region 531, the p-type becomes dominant by performing the doping treatment so that the concentration of the impurity element imparting p-type becomes 2 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ^3. It functions as a source region and a drain region of the channel type TFT.

  Note that a top view corresponding to FIG. 12A is shown in a region surrounded by a broken line 604. A cross-sectional view taken along line A-A ′ and a cross-sectional view taken along line B-B ′ of the broken line 604 corresponds to FIG. Reference numeral 536 denotes an implantation direction during doping. In the ion implantation shown in FIG. 12A, the implantation direction is substantially perpendicular to the substrate 500 from the upper surface of the substrate 500. In the case of forming a Lov region also in a p-channel TFT, the ion implantation direction may be set obliquely so that an impurity is added to a region overlapping with the gate electrode 509 of the island-shaped semiconductor film 503.

  Through the above steps, impurity regions are formed in the island-shaped semiconductor films 503 to 505.

  Next, as illustrated in FIG. 12B, a first interlayer insulating film 532 is formed so as to cover the island-shaped semiconductor films 503 to 505, the gate insulating film 506, and the gate electrodes 508 to 510. As the first interlayer insulating film 532, an insulating film such as silicon oxide containing silicon, silicon nitride, or silicon oxynitride can be used, and the thickness thereof is about 100 to 200 nm.

  Next, heat treatment is performed to activate the impurity element added to the island-shaped semiconductor films 503 to 505. In this step, a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method) can be used. For example, when activation is performed by thermal annealing, it is performed at 400 to 700 ° C. (preferably 500 to 600 ° C.) in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. Further, heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor film. This step is performed for the purpose of terminating the dangling bonds with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. The activation treatment may be performed before the first interlayer insulating film 532 is formed.

  Through the above series of steps, an n-channel TFT 533 having a Lov region, a p-channel TFT 534 having a source region and a drain region in contact with a channel formation region, and an n-channel TFT 535 having a Loff region are formed over the same substrate. Can be formed.

  Note that a top view corresponding to FIG. 12B is shown in a region surrounded by a broken line 605. A cross-sectional view taken along A-A ′ and a cross-sectional view taken along B-B ′ of the broken line 605 corresponds to FIG.

  Next, as shown in FIG. 12C, a second interlayer insulating film 537 and a third interlayer insulating film 538 are formed so as to cover the first interlayer insulating film 532. As the second interlayer insulating film 537, an organic resin film, an inorganic insulating film, organic polysiloxane, or the like can be used. In this embodiment mode, the second interlayer insulating film 537 is formed using non-photosensitive acrylic which is one of organic resin films.

  Next, the gate insulating film 506, the first interlayer insulating film 532, the second interlayer insulating film 537, and the third interlayer insulating film 538 are etched to form contact holes. Then, a wiring 539 for forming a contact with the island-shaped semiconductor films 503 to 505 is formed.

  After the step shown in FIG. 12C, a step of manufacturing an element (display element) capable of displaying gradation in accordance with an electric signal such as a liquid crystal cell or a light emitting element used in a semiconductor display device is performed.

  Note that the present invention is not necessarily limited to the manufacturing method described in this embodiment mode. The manufacturing method described above is only described in detail for one embodiment of the present invention, and the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the invention are possible. It is.

  Next, how to electrically connect the wiring or terminal provided on the substrate and the thin film chip will be described.

  FIG. 9A shows a cross-sectional structure of a thin film chip connected to a wiring or terminal for routing by a wire bonding method. Reference numeral 901 corresponds to a substrate, and 902 corresponds to a thin film chip. The thin film chip 902 is attached to the substrate 901 with an adhesive 903. The thin film chip 902 is provided with a semiconductor element 906 and is electrically connected to a pad 907 functioning as a terminal formed so as to be exposed on the surface of the thin film chip 902. A wiring or terminal 904 is formed over the substrate 901 shown in FIG. 9A, and the pad 907 and the wiring or terminal 904 are connected by the wire 905.

  Next, FIG. 9B shows a state in which a thin film chip is connected to a substrate using a flip chip method. In FIG. 9B, a solder ball 913 is connected to a pad 912 formed so as to be exposed on the surface of the thin film chip 911. Therefore, the semiconductor element 914 formed on the thin film chip 911 is electrically connected to the solder ball 913 through the pad 912. The solder balls 913 are connected to wirings or terminals 916 formed on the substrate 915.

  Note that various methods such as thermocompression bonding, thermocompression bonding with ultrasonic vibration, and the like can be used for the connection between the solder ball 913 and the wiring or the terminal 916. In addition, an underfill is provided between the thin film chip 911 and the substrate 915 so as to fill the gap between the solder balls after the pressure bonding, thereby improving the mechanical strength of the connection portion and the efficiency of diffusion of heat generated in the thin film chip. You may make it raise. The underfill is not necessarily used, but connection failure can be prevented from occurring due to the stress caused by the mismatch between the thermal expansion coefficients of the substrate and the thin film chip. When crimping by applying ultrasonic waves, poor connection can be suppressed as compared to the case of simply thermocompression bonding. This is particularly effective when there are more than 300 bumps to be connected.

  In the case of the flip chip method, even if the number of pads to be connected is increased, the pitch between the pads can be relatively wide compared to the wire bonding method, which is suitable for connection of a thin film chip having a large number of terminals. ing.

  In forming the solder ball, a droplet discharge method of discharging a dispersion liquid in which metal nanoparticles are dispersed may be used.

  Next, FIG. 9C illustrates a state in which the thin film chip is connected to the substrate using an anisotropic conductive resin. In FIG. 9C, the pad 922 formed so as to be exposed on the surface of the thin film chip 921 is electrically connected to the semiconductor element 924 formed on the thin film chip 921. The pad 922 is connected to a wiring or terminal 926 formed over the substrate 925 via an anisotropic conductive resin 927.

  The mounting method is not limited to the method shown in FIG. A thin film chip may be mounted by combining the wire bonding method and the flip chip method.

  In this embodiment, the relationship between the incident angle of the dopant (impurity) and the concentration of the Lov region in the ion implantation method will be described.

FIG. 13A shows a result of a relationship between the incident angle (Tilt Angle) of the dopant with respect to the island-shaped semiconductor film and the width of the Lov region in the dopant implantation direction obtained by simulation. Note that FIG. 13A shows a simulation result when P is used as a dopant. Specifically, the dose amount of P was assumed to be 3 × 10 ¹⁵ atoms / cm ² and the acceleration voltage was assumed to be 80 kV. It is assumed that the impurity concentration in the Lov region is ¼ or more of the region exposed without being covered by the gate electrode. Similarly, in FIG. 13A, the dopant incident angle and the impurity concentration corresponding to ¼ of the region exposed without being covered by the gate electrode (the channel formation is the most in the Lov region). (Corresponding to the impurity concentration in a portion close to the region).

  As shown in FIG. 13A, as the incident angle increases, the width of the Lov region increases, and conversely, the impurity concentration in the portion of the Lov region closest to the channel formation region decreases. In FIG. 13A, even when the incident angle is 0 degree, that is, when a dopant is added from a direction perpendicular to the semiconductor film, a Lov region having a width of about 24 nm is formed. This is due to thermal diffusion of the dopant. It is due. From FIG. 13A, considering that the hot carrier effect is difficult to suppress even if the width of the Lov region is too small or the impurity concentration in the Lov region is too low, the incident angle is about 15 degrees or more and 80 degrees or less. It can be seen that it is desirable.

FIG. 13B shows the result of a simulation for the relationship between the incident angle of the dopant and the width of the Lov region in the dopant implantation direction when the dopant is B. Specifically, the dose amount of B was assumed to be 2 × 10 ¹⁶ atoms / cm ² and the acceleration voltage was assumed to be 80 kV. It is assumed that the impurity concentration in the Lov region is ¼ or more of the region exposed without being covered by the gate electrode. Similarly, FIG. 13B shows the incident angle of the dopant and the impurity concentration corresponding to ¼ of the region exposed without being covered by the gate electrode (the channel formation is the most in the Lov region). (Corresponding to the impurity concentration in a portion close to the region).

  As shown in FIG. 13B, as the incident angle increases, the width of the Lov region increases, and conversely, the impurity concentration in the portion of the Lov region closest to the channel formation region decreases. In FIG. 13B, even when the incident angle is 0 degree, that is, when a dopant is added from a direction perpendicular to the semiconductor film, a Lov region having a width of about 76 nm is formed. This is due to thermal diffusion of the dopant. It is due. From FIG. 13B, considering that it is difficult to suppress the hot carrier effect even if the width of the Lov region is too small or the impurity concentration in the Lov region is too low, the incident angle is about 15 degrees to 80 degrees. It can be seen that it is desirable.

  13A and 13B, it can be seen that the relationship between the incident angle, the width of the Lov region, and the impurity concentration of the Lov region varies depending on the type of dopant. Therefore, the relationship between the incident angle and the width of the Lov region and the impurity concentration of the Lov region is grasped, and the incident angle of the dopant at the time of ion implantation is adjusted according to the desired width of the Lov region and the impurity concentration of the Lov region. It is desirable to decide.

  In this embodiment, one mode of a semiconductor display device of the present invention will be described. FIG. 14A shows a block diagram of the semiconductor display device of this embodiment. A semiconductor display device illustrated in FIG. 14A controls a pixel portion 701 including a plurality of pixels each including a display element, a scan line driver circuit 702 that selects each pixel, and input of a video signal to the selected pixel. And a signal line driver circuit 703.

  In FIG. 14A, the signal line driver circuit 703 includes a shift register 704 and an analog switch 705. A clock signal (CLK) and a start pulse signal (SP) are input to the shift register 704. When the clock signal (CLK) and the start pulse signal (SP) are input, a timing signal is generated in the shift register 704 and input to the analog switch 705.

  A video signal (video signal) is supplied to the analog switch 705. The analog switch 705 samples the video signal in accordance with the input timing signal and supplies it to the subsequent signal line.

  Next, the configuration of the scan line driver circuit 702 is described. The scan line driver circuit 702 includes a shift register 706 and a buffer 707. In some cases, a level shifter may be provided. In the scan line driver circuit 702, a selection signal is generated by inputting a clock signal (CLK) and a start pulse signal (SP) to the shift register 706. The generated selection signal is buffered and amplified in the buffer 707 and supplied to the corresponding scanning line. The gate of the transistor of the pixel for one line is connected to the scanning line. Since the transistors of pixels for one line must be turned on all at once, a buffer 707 that can flow a large current is used.

  In the semiconductor display device illustrated in FIG. 14A, the signal line driver circuit 703 and the scan line driver circuit 702 surrounded by a broken line can be formed using a thin film chip. Note that the present invention is not limited to this, and either the scan line driver circuit or the signal line driver circuit may be formed over the same substrate as the pixel portion 701 and only the other may be formed using a thin film chip. Alternatively, only part of the signal line driver circuit 703 and part of the scan line driver circuit 702 may be formed using a thin film chip.

  14B, the scan line driver circuit 702 and the analog switch 705 of the signal line driver circuit 703 are formed over the same substrate as the pixel portion 701, and the shift register 704 of the signal line driver circuit 703 is formed using a thin film chip. An example is shown. Note that not only a driver circuit for controlling the operation of the display element, typified by a signal line driver circuit and a scanning line driver circuit, but also a controller, a CPU, a memory, and the like are formed with a thin film chip, and the thin film chip has a pixel portion. The form mounted in the board | substrate currently formed can also be taken.

  Note that the structures illustrated in FIGS. 14A and 14B merely illustrate one embodiment of the semiconductor display device of the present invention, and the structures of the signal line driver circuit and the scan line driver circuit are not limited thereto. . For example, instead of the shift registers 704 and 706, another circuit capable of selecting a signal line such as a decoder circuit may be used.

  In this example, a structure of a light-emitting device that corresponds to one embodiment of a semiconductor device of the present invention will be described. The light emitting device includes a panel in which the light emitting element is sealed, and a module in which an IC including a controller is mounted on the panel. FIG. 15A is a top view of a panel in which a transistor and a light-emitting element formed over a first substrate are sealed with a sealant between the second substrate and FIG. 15B. FIG. 15A corresponds to a cross-sectional view taken along line AA ′ of FIG.

  A sealant 4005 is provided so as to surround the pixel portion 4002, the signal line driver circuit 4003, and the scan line driver circuit 4004 which are provided over the first substrate 4001. A second substrate 4006 is provided over the pixel portion 4002, the signal line driver circuit 4003, and the scan line driver circuit 4004. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the scan line driver circuit 4004 are sealed together with the filler 4007 by the first substrate 4001, the sealant 4005, and the second substrate 4006.

  The pixel portion 4002, the signal line driver circuit 4003, and the scan line driver circuit 4004 provided over the first substrate 4001 each include a plurality of transistors. In FIG. 15B, the signal line driver circuit 4003 is provided. The transistors 4008 and 4009 included in the pixel portion and the transistor 4010 included in the pixel portion 4002 are illustrated. Note that FIG. 15B corresponds to a cross-sectional view of the panel along the direction of dopant implantation indicated by an arrow, so that it is difficult to illustrate the entire image of each transistor along the channel length direction. Although only a cross-sectional view is shown, the transistors 4008 and 4009 included in the signal line driver circuit 4003 have a Lov region, and the transistor 4010 included in the pixel portion 4002 has a Loff region.

  4011 corresponds to a light-emitting element, and a pixel electrode included in the light-emitting element 4011 is electrically connected to the drain of the transistor 4010 through a wiring 4017. In this embodiment, the counter electrode of the light emitting element 4011 and the transparent conductive film 4012 are electrically connected. Note that the structure of the light-emitting element 4011 is not limited to the structure shown in this embodiment. The structure of the light-emitting element 4011 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4011, the polarity of the transistor 4010, or the like.

  Further, various signals and potentials applied to the signal line driver circuit 4003, the scan line driver circuit 4004, or the pixel portion 4002 are not shown in the cross-sectional view in FIG. 15B, but are routed through lead wirings 4014 and 4015. It is supplied from the connection terminal 4016.

  In this embodiment, the connection terminal 4016 is formed of the same conductive film as the pixel electrode included in the light emitting element 4011. Further, the lead wiring 4014 is formed of the same conductive film as the wiring 4017. The lead wiring 4015 is formed using the same conductive film as the gate electrodes of the transistors 4010 and 4008 and 4009.

  The connection terminal 4016 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

  Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

  However, the second substrate must be transparent to the substrate positioned in the light extraction direction from the light emitting element 4011. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

  As the filler 4007, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicon resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

  The present invention can be applied not only to the light emitting device shown in this embodiment but also to other semiconductor devices.

  In this example, a structure of a light-emitting device that corresponds to one embodiment of a semiconductor display device of the present invention will be described. The light emitting device includes a panel in which the light emitting element is sealed, and a module in which an IC or the like formed of a single crystal silicon wafer is mounted on the panel. FIG. 16 is a top view of a panel in which a transistor and a light-emitting element formed over the first substrate are sealed with a sealant between the second substrate and FIG. 16B. This corresponds to a cross-sectional view taken along line AA ′ in FIG.

  A sealant 4105 is provided so as to surround the pixel portion 4102 provided over the first substrate 4101 and the scan line driver circuit 4104. A second substrate 4106 is provided over the pixel portion 4102 and the scan line driver circuit 4104. Therefore, the pixel portion 4102 and the scan line driver circuit 4104 are sealed together with the filler 4107 by the first substrate 4101, the sealant 4105, and the second substrate 4106. In addition, a signal line driver circuit 4103 formed using a thin film chip is mounted in a region different from the region surrounded by the sealant 4105 on the first substrate 4101.

  The pixel portion 4102 and the scan line driver circuit 4104 provided over the first substrate 4101 include a plurality of transistors. In FIG. 16B, only the transistor 4110 included in the pixel portion 4102 is illustrated. ing.

  4111 corresponds to a light-emitting element, and a pixel electrode included in the light-emitting element 4111 is electrically connected to the drain of the transistor 4110 through a wiring 4117. In this embodiment, the counter electrode of the light emitting element 4111 and the transparent conductive film 4112 are electrically connected. Note that the structure of the light-emitting element 4111 is not limited to the structure shown in this embodiment. The structure of the light-emitting element 4111 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4111, the polarity of the transistor 4110, or the like.

  Further, various signals and potentials applied to the signal line driver circuit 4103, the scan line driver circuit 4104, and the pixel portion 4102 which are formed using thin film chips are not illustrated in the cross-sectional view in FIG. It is supplied from a connection terminal 4116 through wirings 4114 and 4115.

  In this embodiment, the connection terminal 4116 is formed using the same conductive film as the pixel electrode included in the light-emitting element 4111. The lead wiring 4114 is formed of the same conductive film as the wiring 4117. The lead wiring 4115 is formed using the same conductive film as the gate electrode of the transistor 4110.

  The connection terminal 4116 is electrically connected to a terminal included in the FPC 4118 via an anisotropic conductive film 4119.

  Note that as the first substrate 4101 and the second substrate 4106, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

  However, the second substrate must be transparent to the substrate located in the light extraction direction from the light emitting element 4111. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

  As the filler 4107, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicon resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

  Note that FIG. 16 illustrates an example in which the signal line driver circuit 4103 is formed using a thin film chip and mounted on the first substrate 4101, but a circuit that can be formed using a thin film chip is included in the signal line driver circuit 4103. It is not limited. The scanning line driving circuit may be formed using a thin film chip, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be formed using a thin film chip.

  Further, the present invention can be applied not only to the light emitting device shown in this embodiment but also to other semiconductor devices.

  In this embodiment, an optical system used for irradiation with continuous wave laser light will be described.

  FIG. 18 illustrates the optical system of the present embodiment. The optical system shown in FIG. 18A has two cylindrical lenses 7001 and 7002. The laser beam incident from the direction of the arrow is shaped into the shape of its beam spot by two cylindrical lenses 7001 and 7002, and is irradiated to the object 7003. Note that the cylindrical lens 7002 closer to the workpiece 7003 has a shorter focal length than the cylindrical lens 7001. In order to prevent return light and perform uniform irradiation, it is desirable to keep the incident angle of the laser light on the object 7003 larger than 0 °, preferably 5 to 30 °.

  The optical system illustrated in FIG. 18B includes a mirror 7005 and a plano-convex spherical lens 7006. Then, the laser light incident from the direction of the arrow is reflected by the mirror 7005, the shape of the beam spot is formed by the plano-convex spherical lens 7006, and the object 7007 is irradiated. The radius of curvature of the plano-convex spherical lens can be set as appropriate by the designer. In order to prevent return light and perform uniform irradiation, it is desirable to keep the incident angle of the laser light on the substrate larger than 0 °, preferably 5 to 30 °.

  The optical system illustrated in FIG. 18C includes mirrors 7010 and 7011 and lenses 7012, 7013, and 7014. The laser light incident from the direction of the arrow is reflected by mirrors 7010 and 7011, and the shape of the beam spot is formed by lenses 7012, 7013 and 7014, and is irradiated to object 7015. In order to prevent return light and perform uniform irradiation, it is desirable to keep the incident angle of the laser light on the substrate larger than 0 °, preferably 5 to 30 °.

  FIG. 18D shows an optical system in the case where four beam spots are combined into one beam spot. The optical system illustrated in FIG. 18D includes six cylindrical lenses 7017 to 7022. The four laser beams incident from the direction of the arrows are incident on each of the four cylindrical lenses 7019 to 7022. The two laser beams shaped by the cylindrical lenses 7019 and 7021 are shaped again by the cylindrical lens 7017 and irradiated onto the object 7023. On the other hand, the two laser beams shaped by the cylindrical lenses 7020 and 7022 are shaped again by the cylindrical lens 7018 and irradiated onto the object 7023.

  The beam spots of the respective laser beams on the workpiece 7023 are combined by overlapping each other to form one beam spot.

  The focal length and incident angle of each lens can be set as appropriate by the designer, but the focal lengths of the cylindrical lenses 7017 and 7018 closest to the object 7023 are smaller than the focal lengths of the cylindrical lenses 7019 to 7022. To do. For example, the focal lengths of the cylindrical lenses 7017 and 7018 closest to the object 7023 are 20 mm, and the focal lengths of the cylindrical lenses 7019 to 7022 are 150 mm. The incident angle of the laser light from the cylindrical lenses 7017 and 7018 to the object 7023 is 25 ° in this embodiment, and the incident angle of the laser light from the cylindrical lenses 7019 to 7022 to the cylindrical lenses 7017 and 7018 is 10 °. Install each lens as you want. In order to prevent return light and perform uniform irradiation, it is desirable to keep the incident angle of the laser light on the substrate larger than 0 °, preferably 5 to 30 °.

  FIG. 18D shows an example of synthesizing four beam spots. In this case, four cylindrical lenses respectively corresponding to the four laser oscillation devices, two cylindrical lenses corresponding to the four cylindrical lenses, and have. The number of beam spots to be combined is not limited to this, and the number of beam spots to be combined may be 2 or more and 8 or less. When combining n (n = 2, 4, 6, 8) beam spots, n cylindrical lenses respectively corresponding to the n laser oscillation devices, and n / 2 cylindrical lenses corresponding to the n cylindrical lenses, have. When combining n (n = 3, 5, 7) beam spots, n cylindrical lenses respectively corresponding to the n laser oscillation devices, and (n + 1) / 2 cylindrical lenses corresponding to the n cylindrical lenses, have.

  When superposing five or more beam spots, considering the location of the optical system and interference, it is desirable to irradiate the fifth and subsequent laser beams from the opposite side of the substrate, and the substrate has transparency. It is necessary to do.

  In addition, if one of a surface including a short side or a surface including a long side when the shape of each beam spot is assumed to be a rectangle is defined as an incident surface, the laser beam is defined as a plane perpendicular to the irradiation surface. The incident angle θ is such that the length of the short side or the long side included in the incident surface is W, the thickness of the substrate that is installed on the irradiation surface and has translucency with respect to the laser light is d. In this case, it is desirable that θ ≧ arctan (W / 2d) is satisfied. When the locus of the laser beam is not on the incident surface, the incident angle of the projection of the locus onto the incident surface is defined as θ. If the laser light is incident at this incident angle θ, the reflected light from the surface of the substrate and the reflected light from the back surface of the substrate do not interfere with each other, and uniform laser light irradiation can be performed. In the above discussion, the refractive index of the substrate was considered as 1. Actually, in many cases, the refractive index of the substrate is around 1.5, and if this value is taken into consideration, a calculated value larger than the angle calculated in the above discussion can be obtained. However, since the energy at both ends in the longitudinal direction of the beam spot is attenuated, the influence of interference in this portion is small, and the effect of interference attenuation can be sufficiently obtained with the above calculated value.

  Note that the optical system in the laser irradiation apparatus of the present invention is not limited to the configuration shown in this embodiment.

  In the present embodiment, the shape of a beam spot obtained by combining a plurality of laser beams will be described.

  FIG. 17A shows an example of the shape of the beam spot on the object to be processed of the laser light emitted from each of the plurality of laser oscillation devices. The beam spot shown in FIG. 17A has an elliptical shape. In this embodiment, the shape of the beam spot of the laser beam oscillated from the laser oscillation device is not limited to an ellipse. The shape of the beam spot varies depending on the type of laser and can also be shaped by an optical system. For example, when a XeCl excimer laser (wavelength 308 nm, pulse width 30 ns) L3308 manufactured by Lambda is used, the shape of the laser light emitted from the laser oscillation device is a rectangular shape of 10 mm × 30 mm (both half-value width in the beam profile). It is. Further, the shape of the laser light emitted from the YAG laser is circular when the rod shape is cylindrical, and is rectangular when the rod shape is slab type. By further shaping such laser light with an optical system, laser light of a desired size can be produced.

FIG. 17B shows the energy density distribution of the laser light in the major axis Y direction of the beam spot shown in FIG. The beam spot shown in FIG. 17A corresponds to a region satisfying an energy density of 1 / e ² of the peak value of the energy density in FIG. The energy density distribution of the laser beam having a beam spot having an elliptical shape becomes higher toward the center O of the ellipse.

  Next, FIG. 17C shows the shape of the beam spot when the laser light having the beam spot shown in FIG. Note that although FIG. 17C illustrates the case where one linear beam spot is formed by superimposing the beam spots of four laser beams, the number of beam spots to be superimposed is not limited thereto.

  As shown in FIG. 17C, the beam spots of the respective laser beams are synthesized by matching the major axes of the respective ellipses and overlapping a part of the beam spots to form one beam spot. . Hereinafter, a straight line obtained by connecting the centers O of the ellipses will be referred to as a central axis of the beam spot.

FIG. 17D shows the energy density distribution of the laser beam in the direction of the central axis y of the combined beam spot shown in FIG. Note that the beam spot shown in FIG. 17C corresponds to a region satisfying an energy density of 1 / e ² of the peak value of the energy density in FIG. The energy density is added at the portion where the beam spots before synthesis are overlapped. For example, when the energy densities E1 and E2 of the overlapping beams are added as shown in the figure, the energy density peak value E3 is approximately equal, and the energy density is flattened between the centers O of the ellipses.

  Note that when E1 and E2 are added, it is ideally equal to E3, but in reality, it is not necessarily equal. The allowable range of deviation between the value obtained by adding E1 and E2 and the value of E3 can be appropriately set by the designer.

  As shown in FIG. 17A, when a beam spot is used alone, the energy density distribution follows a Gaussian distribution. Therefore, a laser beam with a uniform energy density is applied to the entire region of the semiconductor film where the active layer is formed. It is difficult to irradiate. However, as can be seen from FIG. 17D, by overlapping a plurality of laser beams and complementing each other with a portion having a low energy density, energy can be obtained rather than using a plurality of laser beams without overlapping. The region having a uniform density can be enlarged, and the restrictions on the layout of the active layer can be reduced. The crystallinity of the semiconductor film can be increased efficiently.

  A specific structure of the semiconductor device of the present invention will be described with reference to FIGS. 19A to 19C using a mobile phone which is one of electronic devices using the semiconductor device as an example.

  In a cellular phone shown in FIG. 19, a signal line driver circuit 1807, a scanning line driver circuit 1806, a controller 1801, a CPU 1802, and a memory 1811 are mounted on a substrate 1800 over which a pixel portion 1805 is formed as a single or a plurality of thin film chips. . In addition, a power supply circuit 1803, an audio processing circuit 1829 and a transmission / reception circuit 1831 provided on the printed wiring board, and other elements such as a resistor, a buffer, and a capacitor are mounted via a connector such as an FPC.

  In this embodiment, the memory 1811 includes a VRAM 1832, a DRAM 1825, a flash memory 1826, and the like. The VRAM 1832 stores image data to be displayed on the panel, the DRAM 1825 stores image data or audio data, and the flash memory stores various programs.

  In the power supply circuit 1803, a signal line driver circuit 1807, a scanning line driver circuit 1806, a controller 1801, a CPU 1802, a sound processing circuit 1829, a memory 1811, and a transmission / reception circuit 1831 are generated. Depending on the panel specifications, the power supply circuit 1803 may be provided with a current source.

  The CPU 1802 includes a control signal generation circuit 1820, a decoder 1821, a register 1822, an arithmetic circuit 1823, a RAM 1824, a CPU interface 1835, and the like. Various signals input to the CPU 1802 via the interface 1835 are once held in the register 1822 and then input to the arithmetic circuit 1823, the decoder 1821, and the like. The arithmetic circuit 1823 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 1821 is decoded and input to the control signal generation circuit 1820. The control signal generation circuit 1820 generates a signal including various commands based on the input signal, and a location designated by the arithmetic circuit 1823, specifically, a memory 1811, a transmission / reception circuit 1831, an audio processing circuit 1829, a controller 1801, and the like. Send to.

  The memory 1811, the transmission / reception circuit 1831, the audio processing circuit 1829, and the controller 1801 operate according to the received commands. The operation will be briefly described below.

  A signal input from the keyboard 1840 is sent to the CPU 1802 via the interface 1809. The control signal generation circuit 1820 converts the image data stored in the VRAM 1832 into a predetermined format according to the signal sent from the keyboard 1840 and sends it to the controller 1801.

  The controller 1801 performs data processing on a signal including image data sent from the CPU 1802 in accordance with the panel specifications, and supplies the processed signal to the signal line driver circuit 1807 and the scanning line driver circuit 1806. The controller 1801 generates an Hsync signal, a Vsync signal, a clock signal CLK, and an AC voltage (AC Cont) based on the power supply voltage input from the power supply circuit 1803 and various signals input from the CPU, and drives the signal line. The data is supplied to the circuit 1807 and the scan line driver circuit 1806.

  In the transmission / reception circuit 1831, signals transmitted / received as radio waves in the antenna 1833 are processed. Specifically, high-frequency signals such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 1831 is sent to the audio processing circuit 1829 in accordance with a command from the CPU 1802.

  A signal including audio information sent in accordance with a command from the CPU 1802 is demodulated into an audio signal by the audio processing circuit 1829 and sent to the speaker 1828. An audio signal sent from the microphone 1827 is modulated by the audio processing circuit 1829 and sent to the transmission / reception circuit 1831 in accordance with a command from the CPU 1802.

  In this embodiment, the controller 1801, CPU 1802, and memory 1811 are formed of thin film chips, but the present invention is not limited to this. The power supply circuit 1803 and the audio processing circuit 1829 may be formed using a thin film chip. The present invention is not limited to high-frequency circuits such as isolators, band-pass filters, VCOs (Voltage Controlled Oscillators), LPFs (Low Pass Filters), couplers, and baluns. Can be implemented.

  The present invention can be used for a semiconductor device of the present invention, a display portion of various electronic devices, or other signal processing circuits. As an electronic device using the semiconductor device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproducing device (car audio, audio component, etc.), a notebook type personal computer, a game device, Play back a recording medium such as a portable information terminal (mobile computer, mobile phone, portable game machine or electronic book), an image playback device (specifically a DVD: Digital Versatile Disc) equipped with a recording medium, and display the image. A device having a display capable of displaying). Specific examples of these electronic devices are shown in FIGS.

  FIG. 20A illustrates a portable information terminal, which includes a main body 2001, a display portion 2002, operation keys 2003, a modem 2004, and the like. Although FIG. 20A illustrates a portable information terminal in which the modem 2004 is removable, the modem may be incorporated in the main body 2001. The semiconductor device of the present invention can be used for the display portion 2002 or other signal processing circuits.

  FIG. 20B illustrates a mobile phone, which includes a main body 2101, a display portion 2102, a voice input portion 2103, a voice output portion 2104, operation keys 2105, an external connection port 2106, an antenna 2107, and the like. Note that the display portion 2102 can suppress current consumption of the mobile phone by displaying white characters on a black background. The semiconductor device of the present invention can be used for the display portion 2102 or other signal processing circuits.

  FIG. 20C illustrates an electronic card, which includes a main body 2201, a display portion 2202, a connection terminal 2203, and the like. The semiconductor device of the present invention can be used for the display portion 2202 or other signal processing circuits. Note that FIG. 20C illustrates a contact type electronic card; however, the semiconductor device of the present invention is also used for a non-contact type electronic card or an electronic card having both a contact type and a non-contact type function. Can do.

  FIG. 20D illustrates an electronic book, which includes a main body 2301, a display portion 2302, operation keys 2303, and the like. A modem may be incorporated in the main body 2301. The semiconductor device of the present invention can be used for the display portion 2302 or other signal processing circuits.

  FIG. 20E shows a sheet-type personal computer, which includes a main body 2401, a display portion 2402, a keyboard 2403, a touch pad 2404, an external connection port 2405, a power plug 2406, and the like. The semiconductor device of the present invention can be used for the display portion 2402 or other signal processing circuits.

  FIG. 20F illustrates a display device, which includes a housing 2501, a support base 2502, a display portion 2503, a speaker portion 2504, a video input terminal 2505, and the like. The semiconductor device of the present invention can be used for the display portion 2503 or other signal processing circuits. The display devices include all information display devices for personal computers, for receiving TV broadcasts, for displaying advertisements, and the like.

  As described above, the applicable range of the present invention is so wide that the present invention can be used for electronic devices in various fields or other signal processing circuits.

4A and 4B illustrate a method for manufacturing a TFT having a Lov region. 4A and 4B illustrate a method for manufacturing a TFT in which a source region and a drain region are in contact with a channel formation region. The figure which shows the mode of crystallization, doping, and dicing of the semiconductor film by a laser beam. The figure which shows the layout of each transistor in the thin film chip in which TFT which has a Loff area | region, and TFT which has a Lov area | region were formed. 10A and 10B illustrate a method for manufacturing a TFT having an offset region. The figure which shows the layout of each transistor in the panel in which TFT which has a Loff area | region, and TFT which has a Lov area | region were formed. 1 is an external view of a semiconductor display device on which a thin film chip is mounted. The top view of TFT which has a Lov area | region. The figure which shows the mounting method of a thin film chip. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. The figure which shows the relationship between the incident angle of a dopant, the width | variety of a Lov area | region, and impurity concentration. 1 is a block diagram illustrating a configuration of a semiconductor display device. 4A and 4B are a top view and a cross-sectional view of a light-emitting device, which corresponds to one embodiment of a semiconductor device of the present invention. 4A and 4B are a top view and a cross-sectional view of a light-emitting device, which corresponds to one embodiment of a semiconductor device of the present invention. The figure which shows distribution of the energy density of a beam spot. The figure which shows the optical system used for irradiation of a continuous wave laser beam. 1 is a block diagram of a mobile phone that is one of electronic devices. FIG. 16 is a diagram of an electronic device using the semiconductor device of the invention.

Explanation of symbols

101 active layer 102 gate electrode 103 gate insulating film 104 region 105 region 106 end 107 Lov region 108 drain region 109 channel formation region 201 active layer 202 gate electrode 203 gate insulating film 204 region 205 region 204 this region

Claims (19)

Having a plurality of transistors,
The plurality of transistors include a channel formation region and an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode,
The plurality of transistors include a transistor in which the active layer has a second impurity region between the channel formation region and the first impurity region,
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
The second impurity region has a lower impurity concentration than the first impurity region,
All the transistors having the same polarity among the transistors having the second impurity region have the same position of the second impurity region with respect to the channel formation region. Having a plurality of transistors,
The plurality of transistors include a channel formation region and an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode,
The plurality of transistors include a transistor in which the active layer has a second impurity region between the channel formation region and the first impurity region,
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
The second impurity region has a lower impurity concentration than the first impurity region,
All of the transistors having the same polarity among the transistors having the second impurity region are aligned in the direction from the second impurity region to the channel formation region. Having a plurality of transistors,
The plurality of transistors include a channel formation region and an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode,
In the plurality of transistors, the active layer includes a transistor having a second impurity region between the channel formation region and the first impurity region, and the channel formation region and the first transistor along one direction. And a transistor in contact with the impurity region of
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
The second impurity region has a lower impurity concentration than the first impurity region,
In the transistor in which the channel formation region and the first impurity region are in contact, only the channel formation region of the active layer overlaps the gate electrode with the gate insulating film interposed therebetween,
Of the transistors having the second impurity region, all transistors having one polarity have the second impurity region aligned with the channel forming region in the one direction. apparatus. Having a plurality of transistors,
The plurality of transistors include a channel formation region and an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode,
In the plurality of transistors, the active layer includes a transistor having a second impurity region between the channel formation region and the first impurity region, and the active layer includes the channel formation region and the first impurity region. And a transistor having a third impurity region.
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
In the transistor having the third impurity region, only the channel formation region of the active layer overlaps the gate electrode with the gate insulating film interposed therebetween,
The second impurity region and the third impurity region have a lower impurity concentration than the first impurity region,
Of the transistors having the second impurity region, all the transistors having one polarity have the second impurity region positioned in one direction with respect to the channel formation region,
Of the transistors having the third impurity region, all of the transistors having the one polarity are in contact with each other so that the channel formation region and the third impurity region are along the one direction. A semiconductor device. Having a transistor,
The transistor includes a channel formation region and an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode,
In the transistor, the active layer has a pair of second impurity regions between the channel formation region and the first impurity region,
Of the active layer, only the channel formation region and the pair of second impurity regions overlap the gate electrode with the gate insulating film interposed therebetween,
The pair of second impurity regions has a lower impurity concentration than the first impurity region,
A semiconductor device, wherein the pair of second impurity regions are aligned with the channel formation region. Having a plurality of transistors,
The plurality of transistors include a channel formation region and an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode,
In the plurality of transistors, the active layer includes a transistor having a second impurity region between the channel formation region and the first impurity region, and the active layer includes the channel formation region and the first impurity region. And a transistor having an offset region between
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
In the transistor having the offset region, only the channel formation region of the active layer overlaps the gate electrode with the gate insulating film interposed therebetween,
The second impurity region has a lower impurity concentration than the first impurity region,
Of the transistors having the second impurity region, all the transistors having one polarity have the second impurity region positioned in one direction with respect to the channel formation region,
Among the transistors having the offset region, all the transistors having the one polarity have the offset region with respect to the channel formation region aligned in a direction opposite to the one direction. apparatus. A first substrate, a display element formed on the first substrate, a second substrate overlapping the first substrate with the display element interposed therebetween, and controlling the operation of the display element A third substrate having an integrated circuit formed thereon,
The plurality of transistors included in the integrated circuit include a channel formation region, an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode.
The plurality of transistors include a transistor in which the active layer has a second impurity region between the channel formation region and the first impurity region,
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
The second impurity region has a lower impurity concentration than the first impurity region,
All the transistors having the same polarity among the transistors having the second impurity region have the same position of the second impurity region with respect to the channel formation region. A first substrate, a display element formed on the first substrate, a second substrate overlapping the first substrate with the display element interposed therebetween, and controlling the operation of the display element A third substrate having an integrated circuit formed thereon,
The plurality of transistors included in the integrated circuit include a channel formation region, an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode.
In the plurality of transistors, the active layer includes a transistor having a second impurity region between the channel formation region and the first impurity region, and the channel formation region and the first transistor along one direction. And a transistor in contact with the impurity region of
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
The second impurity region has a lower impurity concentration than the first impurity region,
In the transistor in which the channel formation region and the first impurity region are in contact, only the channel formation region of the active layer overlaps the gate electrode with the gate insulating film interposed therebetween,
Of the transistors having the second impurity region, all transistors having one polarity have the second impurity region aligned with the channel forming region in the one direction. apparatus. A first substrate, a display element formed on the first substrate, a second substrate overlapping the first substrate with the display element interposed therebetween, and controlling the operation of the display element A third substrate having an integrated circuit formed thereon,
The plurality of transistors included in the integrated circuit include a channel formation region, an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode.
In the plurality of transistors, the active layer includes a transistor having a second impurity region between the channel formation region and the first impurity region, and the active layer includes the channel formation region and the first impurity region. And a transistor having a third impurity region.
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
In the transistor having the third impurity region, only the channel formation region of the active layer overlaps the gate electrode with the gate insulating film interposed therebetween,
The second impurity region and the third impurity region have a lower impurity concentration than the first impurity region,
Of the transistors having the second impurity region, all the transistors having one polarity have the second impurity region positioned in one direction with respect to the channel formation region,
Of the transistors having the third impurity region, all of the transistors having the one polarity are in contact with each other so that the channel formation region and the third impurity region are along the one direction. A semiconductor device. A first substrate, a display element formed on the first substrate, a second substrate overlapping the first substrate with the display element interposed therebetween, and controlling the operation of the display element A third substrate having an integrated circuit formed thereon,
The plurality of transistors included in the integrated circuit include a channel formation region, an active layer having a pair of first impurity regions sandwiching the channel formation region therebetween, a gate insulating film, and a gate electrode.
In the plurality of transistors, the active layer includes a transistor having a second impurity region between the channel formation region and the first impurity region, and the active layer includes the channel formation region and the first impurity region. And a transistor having an offset region between
In the transistor having the second impurity region, only the channel formation region and the second impurity region of the active layer overlap the gate electrode with the gate insulating film interposed therebetween,
In the transistor having the offset region, only the channel formation region of the active layer overlaps the gate electrode with the gate insulating film interposed therebetween,
The second impurity region has a lower impurity concentration than the first impurity region,
Of the transistors having the second impurity region, all the transistors having one polarity have the second impurity region positioned in one direction with respect to the channel formation region,
Among the transistors having the offset region, all the transistors having the one polarity have the offset region with respect to the channel formation region aligned in a direction opposite to the one direction. apparatus. A first substrate, a display element formed on the first substrate, a second substrate overlapping the first substrate with the display element interposed therebetween, and controlling the operation of the display element A third substrate having an integrated circuit formed thereon,
The transistor included in the integrated circuit includes a channel formation region, an active layer having a pair of first impurity regions sandwiching the channel formation region, a gate insulating film, and a gate electrode.
The active layer has a pair of second impurity regions between the channel formation region and the pair of first impurity regions,
Of the active layer, only the channel formation region and the pair of second impurity regions overlap the gate electrode with the gate insulating film interposed therebetween,
The pair of second impurity regions has a lower impurity concentration than the first impurity region,
A semiconductor device, wherein the pair of second impurity regions are aligned with the channel formation region. A transistor having an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film interposed therebetween;
Injecting impurities from one oblique direction with respect to the active layer, a part of the active layer that overlaps the gate electrode with the gate insulating film interposed therebetween, Adding the impurity to a second region other than the first region in the active layer;
The method for manufacturing a semiconductor device, wherein the second region is positioned in the one direction with respect to the first region. A first transistor and a second transistor having an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film interposed therebetween;
In the first and second transistors, the active layer includes a first region overlapping the gate electrode with the gate insulating film interposed therebetween, and a second region other than the first region. Have
Impurities are implanted from one direction oblique to the active layer,
In the active layer of the first transistor, the second region is positioned in the one direction with respect to the first region,
The method for manufacturing a semiconductor device is characterized in that the active layer of the second transistor has the first region and the second region in contact with each other along the one direction. A first transistor and a second transistor having an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film interposed therebetween;
Forming a resist mask so as to cover the gate insulating film and the gate electrode of the second transistor;
Impurities are implanted from one direction oblique to the active layer,
The first transistor has, in the active layer, a first region overlapping the gate electrode with the gate insulating film interposed therebetween, and a second region other than the first region,
The second transistor has a third region overlapping with a resist mask in the active layer, and a fourth region other than the third region,
The second region is located in the one direction with respect to the first region;
The third region and the fourth region are in contact with each other along the one direction,
The fourth region partially overlaps with a region other than a region overlapping with the gate electrode with the gate insulating film interposed therebetween in the active layer of the second transistor. A method for manufacturing a semiconductor device. A first transistor and a second transistor having an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film interposed therebetween;
In the first and second transistors, the active layer includes a first region overlapping the gate electrode with the gate insulating film interposed therebetween, and a second region other than the first region. Have
Impurities are implanted from one direction oblique to the active layer,
In the active layer of the first transistor, the second region is positioned in the one direction with respect to the first region,
The method for manufacturing a semiconductor device, wherein the active layer of the second transistor has the first region positioned in the one direction with respect to the second region. By dividing the first substrate on which a plurality of integrated circuits are formed, a second substrate on which one integrated circuit among the plurality of integrated circuits is formed is formed,
The second substrate is bonded to a third substrate on which a semiconductor element or a display element is formed, and the one integrated circuit and the semiconductor element or the display element are electrically connected,
The transistors included in the plurality of integrated circuits are formed by injecting impurities from one oblique direction into the active layer that overlaps the gate electrode with the gate insulating film interposed therebetween. The impurity is added to a part of the first region overlapping the gate electrode with the gate insulating film interposed therebetween and to a second region other than the first region in the active layer. And
The method for manufacturing a semiconductor device, wherein the second region is positioned in the one direction with respect to the first region. By dividing the first substrate on which a plurality of integrated circuits are formed, a second substrate on which one integrated circuit among the plurality of integrated circuits is formed is formed,
The second substrate is bonded to a third substrate on which a semiconductor element or a display element is formed, and the one integrated circuit and the semiconductor element or the display element are electrically connected,
The first and second transistors included in the plurality of integrated circuits each include an active layer, a first region overlapping a gate electrode with a gate insulating film interposed therebetween, and a second region other than the first region. And having an area of
Impurities are implanted from one oblique direction with respect to the active layer,
In the active layer of the first transistor, the second region is positioned in the one direction with respect to the first region,
The method for manufacturing a semiconductor device is characterized in that the active layer of the second transistor has the first region and the second region in contact with each other along the one direction. By dividing the first substrate on which a plurality of integrated circuits are formed, a second substrate on which one integrated circuit among the plurality of integrated circuits is formed is formed,
The second substrate is bonded to a third substrate on which a semiconductor element or a display element is formed, and the one integrated circuit and the semiconductor element or the display element are electrically connected,
The first and second transistors included in the plurality of integrated circuits each include an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film interposed therebetween. Have
A resist mask is formed so as to cover the gate insulating film and the gate electrode of the second transistor, and then obliquely with respect to the active layer of the first and second transistors. Impurities are implanted,
The first transistor has, in the active layer, a first region overlapping the gate electrode with the gate insulating film interposed therebetween, and a second region other than the first region,
The second transistor has a third region overlapping with a resist mask in the active layer, and a fourth region other than the third region,
The second region is located in the one direction with respect to the first region;
The third region and the fourth region are in contact with each other along the one direction,
The fourth region partially overlaps with a region other than a region overlapping with the gate electrode with the gate insulating film interposed therebetween in the active layer of the second transistor. A method for manufacturing a semiconductor device. By dividing the first substrate on which a plurality of integrated circuits are formed, a second substrate on which one integrated circuit among the plurality of integrated circuits is formed is formed,
The second substrate is bonded to a third substrate on which a semiconductor element or a display element is formed, and the one integrated circuit and the semiconductor element or the display element are electrically connected,
The first and second transistors included in the plurality of integrated circuits each include an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film interposed therebetween. Have
In the first and second transistors, the active layer includes a first region overlapping the gate electrode with the gate insulating film interposed therebetween, and a second region other than the first region. Have
Impurities are implanted from one direction oblique to the active layer,
In the active layer of the first transistor, the second region is positioned in the one direction with respect to the first region,
The method for manufacturing a semiconductor device, wherein the active layer of the second transistor has the first region positioned in the one direction with respect to the second region.

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