JP2005057065A - Simple matrix type ferroelectric storage device, and method for designing and inspecting same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simple matrix type ferroelectric storage where a memory cell is composed only of a ferroelectric capacitor without having any cell transistors and the ferroelectric capacitor has a hysteresis loop with a superior rectangle characteristic, and to provide a method for designing the simple matrix type ferroelectric storage and a method for inspecting the simple matrix type ferroelectric storage. <P>SOLUTION: In the simple matrix type ferroelectric storage, ¾ΔPa/Cu¾≥(n-1)×ΔVBL is satisfied. In this case, n indicates the number of ferroelectric memory cells connected to each of a plurality of bit lines; and ΔPa indicates the difference between a function f(Vs) when a selection voltage Vs is applied to one selection memory cell of n ferroelectric memory cells connected to one of the bit lines and a function F(Vu) when a non-selection voltage Vu is applied to other non-selection memory cells, when a hysteresis function showing polarization quantity P(μC/cm<SP>2</SP>) in the ferroelectric memory cell is set to be P=f(V) when voltage V is applied. ΔPa Is equal to f(Vs)-f(Vu). Additionally, Cu indicates capacity (μC/cm<SP>2</SP>/V) of each of (n-1) non-selection memory cells connected to one bit line, and ΔVBL indicates the minimum input amplitude (V) that can be amplified by a sense amplifier. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a simple matrix type ferroelectric memory device in which a memory cell is configured only by a ferroelectric capacitor without a cell transistor, and a design method and an inspection method thereof.

  In recent years, research and development of thin films such as PZT and SBT, and ferroelectric capacitors and ferroelectric memory devices using the thin films have been actively conducted. The structure of the ferroelectric memory device can be roughly classified into 1T, 1T1C, 2T2C, and a simple matrix type. Among them, the 1T type has an internal electric field generated in the capacitor because of its structure, so that the retention (data retention) is as short as one month, and it is said that the 10-year guarantee required in general semiconductors is impossible. The 1T1C type and 2T2C type have almost the same configuration as the DRAM and have a transistor for selection, so that the manufacturing technology of the DRAM can be utilized and the writing speed equivalent to that of the SRAM can be realized. The following small-capacity products have been commercialized.

Up to now, Pb (Zr, Ti) O ₃ (PZT) has been mainly used as a ferroelectric material. In the case of the same material, a ridge face body having a Zr / Ti ratio of 52/48 or 40/60 is used. A mixed region of crystal and tetragonal crystals and a composition in the vicinity thereof are used, and elements such as La, Sr, and Ca are doped and used. This region is used in order to ensure the most necessary reliability of the memory element. Originally, the tetragonal region rich in Ti is good for the hysteresis shape, but Schottky defects due to the ionic crystal structure occur, which causes leakage current characteristics or imprint characteristics (so-called hysteresis characteristics). Degree of deformation) defects occur and it is difficult to ensure reliability.

On the other hand, the simple matrix type has a smaller cell size than the 1T1C type and 2T2C type, and can be multi-layered with capacitors, so that high integration and cost reduction are expected. A conventional simple matrix ferroelectric memory device is disclosed in Patent Document 1 and the like. The invention of Patent Document 1 discloses a driving method in which a voltage that is 1/3 of a write voltage is applied to an unselected memory cell when data is written to a memory cell. However, in this technique, the hysteresis loop of the ferroelectric capacitor required for operation is not specifically described. As the inventors proceeded with development, it was found that a hysteresis loop with good squareness is indispensable to obtain a simple matrix type ferroelectric memory device that can actually operate. Ti-rich tetragonal PZT is considered as a candidate for a ferroelectric material that can cope with this, but ensuring reliability is the most important issue.
JP-A-9-116107

  SUMMARY OF THE INVENTION An object of the present invention is to provide a simple matrix type ferroelectric memory device in which a memory cell does not have a cell transistor and is composed only of a ferroelectric capacitor, and the ferroelectric capacitor has a hysteresis loop with good squareness and It is to provide a design method and an inspection method.

  A simple matrix ferroelectric memory device according to an aspect of the present invention includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, the plurality of word lines, and the plurality of bit lines. It has a plurality of ferroelectric memory cells each composed of a ferroelectric capacitor formed at each intersection, and at least one sense amplifier selectively connected to the plurality of bit lines, and satisfies the following formula: is there.

| ΔPa / Cu | ≧ (n−1) × ΔVBL
n: number of the ferroelectric memory cells connected to each one of the plurality of bit lines ΔPa: hysteresis indicating the polarization amount P (μC / cm ² ) of the ferroelectric memory cell when the voltage V is applied When the function is P = f (V), the function f (Vs) when the selection voltage Vs is applied to one selected memory cell of the n ferroelectric memory cells connected to the one bit line. And the function f (Vu) when the unselected voltage Vu is applied to other unselected memory cells, and ΔPa = f (Vs) −f (Vu). Cu: The one bit line Capacity of (n-1) unselected memory cells connected to each other (μC / cm ² / V)
ΔVBL: Minimum input amplitude (V) that can be amplified by the sense amplifier
By satisfying the above formula, a simple matrix ferroelectric memory device having a hysteresis characteristic with good squareness can be realized.

  A simple matrix ferroelectric memory device design method and inspection method according to another aspect of the present invention is to design or inspect a simple matrix ferroelectric memory device using the above equations.

  An inspection method for a simple matrix ferroelectric memory device according to still another aspect of the present invention is a method for testing a simple matrix ferroelectric memory device having a ferroelectric memory cell in which a ferroelectric capacitor is arranged between electrodes. In the inspection method, the step of imprinting the simple matrix ferroelectric memory device, the coercive voltage of the ferroelectric memory cell being Vc, and the selection voltage to the ferroelectric memory cell (however, the coercive voltage and And Vs−Vc = ΔV, the step of determining whether or not ΔV ≦ Vc is satisfied after the imprint test.

  Examples of the ferroelectric thin film applicable to the present invention include the following.

(1) A ferroelectric thin film applicable to the present invention is represented by a general formula of AB _1-x Nb _x O ₃ , the A element is composed of at least Pb, and the B element is Zr, Ti, V, W And Hf, and at least one combination, and Nb is included in the range of 0.05 ≦ x ≦ 1.

Further, the ferroelectric thin film according to the present invention, A element _{consists Pb 1-y} Ln y, Ln is, La, Ce, Pr, Nd , Pm, Sm, Eu, Gd, Tb, Dy, Ho, It is composed of a combination of at least one of Er, Tm, Yb, and Lu, and can be in a range of 0 <y ≦ 0.2.

(2) A ferroelectric thin film applicable to the present invention is represented by the general formula of (Pb _1-y A _y ) (B _1-x Nb _x ) O ₃ , and the A element is La, Ce, It consists of a combination of at least one of Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, and the B element is Zr, Ti, V, W and Hf. Among them, it is composed of one or more combinations, and includes Nb in the range of 0.05 ≦ x ≦ 1.

  The ferroelectric thin film applicable to the present invention can contain Nb in the range of 0.1 ≦ x ≦ 0.3.

  (3) The ferroelectric thin film applicable to the present invention is a PZT-based ferroelectric thin film having a Ti composition higher than the Zr composition, and 2.5 mol% or more and 40 mol of the Ti composition. % Or less is substituted with Nb.

  Moreover, in the ferroelectric thin film applicable to the present invention, 10 mol% or more and 30 mol% or less of the Ti composition can be substituted with Nb.

  In the ferroelectric thin film applicable to the present invention, the PZT-based ferroelectric thin film may have a crystal structure of at least one of a tetragonal system and a rhombohedral system.

  Further, the ferroelectric thin film applicable to the present invention may contain 0.5 mol% or more of Si or Si and Ge.

  Further, the ferroelectric thin film applicable to the present invention may contain 0.5 mol% or more and less than 5 mol% of Si or Si and Ge.

(4) A ferroelectric thin film applicable to the present invention is represented by a general formula of ABO ₃ and includes Pb as a constituent element of the A site and PZT system including at least Zr and Ti as constituent elements of the B site. In the ferroelectric thin film, the amount of Pb deficiency at the A site is at most 20 mol% with respect to the stoichiometric composition of the ABO ₃ .

  In the ferroelectric thin film applicable to the present invention, the B site can contain Nb at a composition ratio corresponding to ½ of the Pb deficiency at the A site.

  Further, in the ferroelectric thin film according to the present invention, the Ti composition at the B site is higher than the Zr composition, and it can have a rhombohedral crystal structure.

  In addition, the ferroelectric thin films (3) and (4) applicable to the present invention can be formed using a sol-gel solution.

  A ferroelectric memory device according to an embodiment of the present invention will be described.

1. Capacitor of Ferroelectric Memory Device FIG. 1 is a diagram showing a ferroelectric capacitor in the ferroelectric memory device of the present embodiment. In FIG. 1, 101 is a Pb (Zr, Ti) O ₃ (PZT) or Pb (Zr, Ti, Nb) O ₃ (PZTN) ferroelectric film according to the present embodiment, 102 is a first electrode, and 103 is a second electrode. Electrode. The first electrode 102 and the second electrode 103 are made of a single noble metal such as Pt, Ir, or Ru or a composite material mainly composed of the noble metal. When the ferroelectric element diffuses into the first electrode, the composition is shifted at the interface between the electrode and the ferroelectric film, and the squareness of the hysteresis is lowered. Therefore, the ferroelectric element does not diffuse into the first electrode. High precision is required. In order to increase the density of the first electrode, a method of forming a sputter film with a gas having a heavy mass, a method of dispersing an oxide such as Y or La in the noble metal electrode, or the like is used. In FIG. 1, components (such as MOS transistors) of the substrate and other ferroelectric memory devices are omitted. These components will be described later.

  Next, an example of a film forming method when the ferroelectric film 101 is the PZTN thin film 101 will be described.

The first raw material liquid is a solution obtained by dissolving a polycondensation polymer in an anhydrous state in a solvent such as n-butanol in order to form a PbZrO ₃ perovskite crystal of Pb and Zr among the constituent metal elements of the PZTN ferroelectric phase. . The second raw material liquid is a solution obtained by dissolving a condensation polymer in an anhydrous state in a solvent such as n-butanol in order to form a PbTiO ₃ perovskite crystal of Pb and Ti among the constituent metal elements of the PZTN ferroelectric phase. . The third raw material liquid is a solution obtained by dissolving a polycondensate in an anhydrous state in a solvent such as n-butanol in order to form a PbNbO ₃ perovskite crystal of Pb and Nb among the constituent metal elements of the PZTN ferroelectric phase. .

For example, when the PbZr _0.2 Ti _0.8 Nb _0.2 O ₃ (PZTN) ferroelectric is formed using the first, second, and third raw material solutions, (first raw material solution): ( Second raw material solution) :( third raw material solution) = 2: 6: 2 is mixed, but even if this mixed solution is crystallized as it is, a ferroelectric PZTN thin film can be produced. Absent. When Nb is mixed, the crystallization temperature rises rapidly, and crystallization is impossible in the temperature range where the element can be formed at 700 ° C. or less. Therefore, 5 mol% or more of Nb has been used as a Ti substitution element so far. Has not been used and so far has not left the area of additives. In addition, there was no example of PZT tetragonal crystals containing more Ti than Zr. This is described in reference J.A. Am. Ceram. Soc, 84 (20001) 902 and Phys. Rev. Let, 83 (1999) 1347 and the like.

In the present embodiment, the above problem is solved by adding a solution obtained by dissolving a condensation polymer in a solvent such as n-butanol in an anhydrous state to form PbSiO ₃ crystals as a fourth raw material liquid, in an amount of 1 mol% or more and less than 5 mol%. It was possible to solve the problem by further adding to the above mixed solution. By using the mixed solution of the first, second, third, and fourth solutions, it becomes possible to crystallize PZTN at a temperature range in which the element can be formed at 700 ° C. or less.

  These mixed liquids are formed according to the flowchart shown in FIG. Specifically, a series of steps including a mixed solution coating step, an alcohol removing step, a drying heat treatment step, and a degreasing heat treatment step are performed a desired number of times, and finally baked to form a ferroelectric film. Examples of conditions are shown below.

  The mixed solution is applied by a coating method such as spin coating. First, the mixed solution is dropped onto a Si substrate coated with a noble metal for electrodes such as Pt. For the purpose of spreading the dropped solution over the entire surface of the substrate, spinning is performed at about 500 rpm, and then the number of rotations is reduced to 50 rpm or less and the rotation is performed for about 10 seconds. The drying heat treatment step is performed at 150 to 180 ° C. The drying heat treatment is performed using a hot plate or the like in an air atmosphere. Similarly, the degreasing heat treatment step is performed in an air atmosphere on a hot plate maintained at 300 ° C to 350 ° C. Firing for crystallization is performed using thermal rapid annealing (RTA) or the like in an oxygen atmosphere. The film thickness after sintering is about 100 to 200 nm.

  Next, after the second electrode is formed by sputtering or the like, post-annealing is performed for the purpose of forming the interface between the second electrode and the ferroelectric thin film and improving the crystallinity of the ferroelectric thin film. A ferroelectric capacitor is obtained by using RTA or the like in an atmosphere.

  FIG. 2 is a diagram schematically showing a P (polarization) -V (voltage) hysteresis curve of the ferroelectric capacitor used in the present embodiment. This ferroelectric capacitor has a polarization amount P (ten Vs) when a voltage of 10 Vs is applied, and when the voltage is 0, the polarization amount Pr is obtained, and when the voltage is −1/3 Vs, the polarization amount is obtained. P (−1 / 3Vs), the polarization amount P (−Vs) when the voltage is −Vs, the polarization amount −Pr when the voltage is 0 again, and the polarization amount P (+ 1 / Vs when the voltage is +1/3 Vs. 3Vs), and when the voltage is set to + Vs again, a hysteresis curve is drawn so that the polarization amount returns to P (+ Vs) again.

  Here, the inventor of the present application has found the following in the ferroelectric capacitor used in the present embodiment. That is, when the selection voltage Vs is once applied to obtain the polarization amount P (+ Vs), the non-selection voltage (Vs / 3) is applied, and the applied voltage is set to 0, the hysteresis loop is shown by the arrow in FIG. The amount of polarization has a stable value PO (0). Also, once the voltage −Vs is applied to obtain the polarization amount P (−Vs), a voltage of + Vs / 3 is applied, and when the applied voltage is set to 0, the hysteresis loop has a locus indicated by an arrow in FIG. The amount of polarization has a stable value PO (1).

  If the difference between the polarization amount PO (0) and the polarization amount PO (1) is sufficiently large, the simple matrix ferroelectric memory device is operated by the driving method disclosed in the above-mentioned Patent Document 1 and the like. Is possible.

According to the ferroelectric capacitor, the crystallization temperature can be lowered, the squareness of hysteresis can be improved, and Pr can be improved. A simple matrix type ferroelectric memory device having such a ferroelectric capacitor can be driven. Further, the improvement in the squareness in the hysteresis of the ferroelectric capacitor has a significant effect on the stability of disturbance, which is important for driving a simple matrix type ferroelectric memory device. In a simple matrix ferroelectric memory device, a non-selection voltage (± Vs / 3) is also applied to a cell to which writing and reading are not performed. Therefore, polarization does not change at this voltage, so-called disturb characteristics are stable. There must be. The inventor of the present application shows that when the non-selective pulse of Vs / 3 is applied 10 ⁸ times in the direction of reversing the polarization from a stable state of polarization in general PZT, the polarization amount is reduced by about 80%. According to the form, it was confirmed that the amount of decrease was 10% or less.
2. Squareness of Hysteresis Characteristics (PV Curve) FIG. 3 shows n ferroelectric capacitors C1 to Cn connected to the m-th one bit line BLm. For example, a latch-type sense amplifier SAm is connected to one end of the bit line BLm via a selection gate CT1m. In general, the sense amplifier SAm is shared by a plurality of bit lines, and is connected to the bit line BLm when the selection gate CT1m is turned on. When any one ferroelectric capacitor on the m-th bit line BLm is selected as a selected cell, for example, when data is read from the selected cell, the selection gate CT1m is turned on. At this time, in the sense amplifier SAm, the voltage accompanying the movement of charges on the bit line BLm is compared with the reference voltage Vref, and data is read out.

  The bit line MLm shown in FIG. 3 may be used as a sub-bit line, and n ferroelectric capacitors C1 to Cn may be connected to each of a plurality of sub-bit lines BLm subordinate to one main bit line. In this case, the ferroelectric memory device further includes a plurality of main bit lines, and a sense amplifier SAm that is selectively connected to the plurality of main bit lines. A plurality of sub bit lines are cascade-connected to each one main bit line via a selection gate.

  Here, in the ferroelectric memory device of the present embodiment, the following formula (1) is established.

| ΔPa / Cu | ≧ (n−1) × ΔVBL (1)
Here, n is the number of ferroelectric memory cells connected to each one (for example, BLm) of a plurality of bit lines (or sub bit lines). (N-1) in the formula (1) indicates the number of non-selected cells when one of the n ferroelectric memory cells becomes the selected cell. ΔPa is the n strong resistances connected to the bit line BLm when the hysteresis function indicating the polarization amount P (μC / cm ² ) of the ferroelectric memory cell when the voltage V is applied is P = f (V). A difference between a function f (Vs) when a selection voltage Vs is applied to one selected memory cell of the dielectric memory cell and a function f (Vu) when an unselection voltage Vu is applied to another non-selected memory cell. (See FIG. 2). That is, ΔPa = f (Vs) −f (Vu). Cu is the capacity (dP / dV; μC / cm ² / V) of each of (n−1) unselected memory cells connected to the bit line BLm. ΔVBL is the minimum input amplitude (V) that can be amplified by the sense amplifier SAm.

  Of the parameters described above, Cu can be derived from the hysteresis characteristics. If the voltage V = Vu at the time of non-selection is obtained, it can be obtained by differentiation of the hysteresis characteristics (P-V curve) at V = Vu. That is, Cu is an inclination (one index of squareness) at each point where the voltage Vu or −voltage Vu shown in FIG. 2 intersects the PV curve, and Cu = dP / dV≈ΔP / ΔV. Note that Δ is an arbitrary difference, and can be set to the sensitivity limit of the measuring device, for example.

  Further, the applied voltage Vu at the time of non-selection is set to Vu = Vs × 1 / x + α with respect to the applied voltage Vs at the time of selection. 0 <x <Vs, for example, x = 2 or x = 3 is preferable, but not limited thereto.

  As the applied voltage Vs at the time of selection, a power supply voltage is usually used. The power supply voltage used in the semiconductor device is normally Vs = 1.5V, 1.8V, 3.3V, but is not limited thereto.

  α is a voltage margin (V) determined from circuit and device characteristics. For example, α = 0.1V and 0.2V, but not limited thereto.

  Vcu is set in the range of 0 <Vu <Vc and −Vc <Vu <0. Vc is called a coercive voltage, and is a value of the V-axis when P = 0.

  As shown in FIG. 2, ΔPa is a difference between the polarization amounts of the selected cell and the non-selected cell, that is, ΔPa = f (Vs) −f (Vu). As shown in FIG. 2, when the squareness is good and the value of Cu is sufficiently small (when the inclination is almost horizontal or the like), ΔPa≈2 × Pr may be set. Note that Pr is a value of the P-axis when V = 0, and is called a dielectric polarization amount.

  The number n of ferroelectric capacitors connected to one bit line is determined by the layout configuration, redundant relief circuit configuration, switch capacitance connected to the bit line, bit line length, etc., but is not limited thereto. In Patent Document 1 described above, n = 4, 8, and 16 are cited. However, in this embodiment, n is 32 to 128 and can be practically used by improving the squareness of the hysteresis characteristic of the ferroelectric capacitor. It can be. If the number n of connections increases beyond this, the load capacity increases and the memory speed decreases.

  ΔVBL is defined by the minimum input amplitude of the sense amplifier or the sensitivity of the sense amplifier. This value preferably includes a bit line capacitance value, a bit line resistance value, a margin such as noise from an adjacent pattern or disturbance, but is not limited thereto. As an example of the value of ΔVBL, 150 to 200 mV can be given in consideration of a margin.

  The above equation (1) is derived as follows. First, when the minimum input amplitude (V) that can be amplified by the sense amplifier SAm is input to the sense amplifier SAm, the following formula is established according to the law of conservation of charge amount on one bit line BLm.

ΔPa = (n−1) × Cu × ΔVBL (2)
Here, since the right side assumes the minimum input amplitude of the sense amplifier, if ΔPa on the left side is equal to or greater than the value on the right side, the difference in polarization between the selected cell and the non-selected cell is the memory value in the sense amplifier SAm. It means that 0 and 1 are enough to be discriminated.

  Therefore, the equation (2) can be rewritten as the following equation (3).

ΔPa ≧ (n−1) × Cu × ΔVBL (3)
Further, when the Cu in the expression (3) is moved to the left side and the absolute value of the left side is taken in consideration of both the positive electric field and the negative electric field in FIG. 2, the expression (3) becomes the above-described expression (1). Can be transformed.

Here, in this embodiment, the value of Cu can be 0.1 to 15 (μC / cm ² / V). Preferably, 1 ≦ Cu ≦ 10, and more preferably 2 ≦ Cu ≦ 6.

It can be seen that the smaller the value Cu, the better the squareness of the hysteresis characteristic as the slope of the PV curve at the non-selection voltage (Vu, -Vu) point shown in FIG. The value on the left side of 1) becomes large, and the formula (1) is easily established. However, in the present embodiment, since the left side of the expression (1) is the ratio of the value ΔPa to the value Cu, the value Pa may be a large value within a certain range. For example, the value of ΔPa is 40 to 120 (μC / Cm ² ). Preferably 50 ≦ ΔPa ≦ 100, more preferably 60 ≦ ΔPa ≦ 80.

  Considering the values Cu and ΔPa, the value of | ΔPa / Cu |, which is the left side of the equation (1), can be set to 1.6 to 50 (V). Preferably 5 ≦ | ΔPa / Cu | ≦ 50, more preferably 10 ≦ | ΔPa / Cu | ≦ 50.

  The squareness of the hysteresis characteristic can also be expressed by the following formula (4).

  That is, as shown in FIG. 2, the coercive voltage of the ferroelectric memory cell is Vc, the selection voltage to the ferroelectric memory cell (however, the same polarity as the coercive voltage) is Vs, and Vs−Vc = ΔV. Then, equation (4) becomes:

ΔV ≦ Vc (4)
In the hysteresis characteristic with excellent squareness as shown in FIG. 2, ΔV ≦ Vc, which is a characteristic that cannot be seen in the conventional ferroelectric capacitor. As long as the squareness of FIG. 2 is maintained, | Vs |> | Vc |, and thus | Vs | − | Vc |> 0 always holds. In particular, it is extremely important in practice to satisfy the following formula (5) even after an imprint test (details will be described later) of the ferroelectric memory device.

| Vs |> | Vc | (5)
3. Design Method for Ferroelectric Memory Device When designing a ferroelectric memory device, the setting of various parameters, which has conventionally been a trial and error, can be referred to Equation (1). ΔPa and Cu on the left side of the equation (1) are characteristics of the ferroelectric capacitor itself. On the other hand, the right side of the equation (1) is a design item other than the ferroelectric capacitor, and the sensitivity of the number n and the sense amplifier satisfies the equation (1) based on the value of the left side of the equation (1). It may be determined as follows.

3.1 Design Method of Minimum Input Amplitude Value ΔVBL of Sense Amplifier First, the selection voltage Vs = 1.8V (power supply voltage) and the non-selection voltage Vu = Vs / x + α = 1.8 / 3 + 0.2 = 0.8V (Example of x = 3, α = 0.2).

Next, the characteristic of the ferroelectric capacitor used is measured, and the value | ΔPa / Cu | on the left side of the equation (1) is calculated. From the measurement results, when Cu = 10 μC / cm ² / V and ΔPa = 50 μC / cm ² , the value | ΔPa / Cu | = 50/10 = 5.0 V on the left side of Equation (1) is obtained.

  Next, (n-1) in the right side of the formula (1) is moved to the left side, and the formula (1) is transformed into the following formula (1-1).

| ΔPa / Cu | / (n−1) ≧ ΔVBL (1-1)
When this equation (1-1) is calculated with n = 32, | ΔPa / Cu | / (n−1) = 5 / (32−1) ≈0.16 (V) ≧ ΔVBL is obtained. Therefore, a sense amplifier having a sensitivity of ΔVBL = 150 mV may be used.

3.2 Design Method of Number of Memory Cells n Connected to Bit Line First, select voltage Vs = 1.5V (power supply voltage) and non-select voltage Vu = Vs / x + α = 1.5 / 2 + 0.1 = 0.85V (Example of x = 2, α = 0.1).

Next, the characteristic of the ferroelectric capacitor used is measured, and the value | ΔPa / Cu | on the left side of the equation (1) is calculated. From the measurement results, when Cu = 3 μC / cm ² / V and ΔPa = 100 μC / cm ² , the value | ΔPa / Cu | = 100/3 = 33.3V on the left side of Equation (1) is obtained.

  Next, Equation (1) is transformed into Equation (1-2) below so that only n remains on the right side of Equation (1).

| ΔPa / Cu | / ΔVBL + 1 ≧ n (1-2)
When this equation (2-1) is calculated with ΔVBL = 0.2 V, | ΔPa / Cu | /ΔVBL+1=33.3/0.2+1≈167.5≧n is obtained. The number n of memory cell connections is determined to be n = 128 because a power of 2 is used because of the selection using the binary system.

4). Ferroelectric Memory Device FIGS. 4A and 4B are diagrams showing a configuration of a simple matrix ferroelectric memory device in this embodiment. 4A is a plan view thereof, and FIG. 4B is a cross-sectional view taken along the line AA of FIG. 4A. In FIG. 4A, reference numerals 301 to 303 are word lines arranged in a predetermined number on the substrate 308, and reference numerals 304 to 306 are bit lines arranged in a predetermined number. The ferroelectric film 307 of this embodiment is inserted between the word lines 301 to 306 and the bit lines 304 to 306, and a ferroelectric capacitor is formed in the intersection region between the word line and the bit line.

  In the ferroelectric memory device in which the memory cells configured by this simple matrix are arranged, writing to and reading from the ferroelectric capacitor formed in the intersection region of the word line and the bit line are performed by a peripheral driving circuit (not shown) or reading. For example, these are referred to as “peripheral circuits”. This peripheral circuit may be formed by a MOS transistor on a substrate different from the memory cell array and connected to the word line and bit line, or by using a single crystal silicon substrate for the substrate 308, the peripheral circuit Can also be integrated on the same substrate as the memory cell array.

  FIG. 5 is a cross-sectional view showing an example of a ferroelectric memory device in which a memory cell array is integrated with peripheral circuits on the same substrate in the present embodiment. In the figure, a MOS transistor 402 is formed on a single crystal silicon substrate 401, and this transistor formation region becomes a peripheral circuit portion. The MOS transistor 402 includes a single crystal silicon substrate 401, source / drain regions 405, a gate insulating film 403, and a gate electrode 404. Reference numeral 406 denotes an element isolation oxide film, 407 denotes a first interlayer insulating film, and 408 denotes a first wiring layer. Reference numeral 409 denotes a second interlayer insulating film, and reference numeral 410 denotes a lower electrode (first electrode or second electrode) of the ferroelectric capacitor, which becomes a word line or a bit line. Reference numeral 411 denotes a ferroelectric film, and reference numeral 412 denotes an upper electrode (second electrode or first electrode) formed on the ferroelectric film, which becomes a bit line or a word line. The lower electrode 410, the ferroelectric film 411 including the ferroelectric phase and the paraelectric phase, and the upper electrode 412 constitute a memory cell array. Reference numeral 413 denotes a third interlayer insulating film, and reference numeral 414 denotes a second wiring layer. The second wiring layer 414 connects the memory cell array and the peripheral circuit portion. Reference numeral 415 denotes a protective film. In the ferroelectric memory device having the above configuration, the memory cell array and the peripheral circuit portion can be integrated on the same substrate. In the case of FIG. 5, the memory cell array is formed on the peripheral circuit portion. Of course, the memory cell array is not arranged on the peripheral circuit portion, and the memory cell array is in planar contact with the peripheral circuit portion. It is good also as such a structure.

  The ferroelectric capacitor used in this embodiment has a very good hysteresis squareness and a stable disturb characteristic. Furthermore, this ferroelectric capacitor has little damage to peripheral circuits and other elements due to low process temperature, and also has little process damage (especially hydrogen reduction), so it can suppress deterioration of hysteresis due to damage. it can. Therefore, by using such a ferroelectric capacitor, it is possible to drive a simple matrix type ferroelectric memory device.

  FIG. 6 shows a structural diagram of a conventional 1T1C type ferroelectric memory.

  As shown in FIG. 6, a memory element having a structure very similar to a DRAM using the ferroelectric substance of the present invention for the capacitor insulating film (1C) and comprising a transistor element for switching (1T). In this method, writing and reading can be performed at a high speed of 100 ns or less, and written data is non-volatile, so it is considered promising for SRAM replacement and the like.

5). Method for Inspecting Ferroelectric Memory Device FIG. 7 shows a method for inspecting a ferroelectric memory device according to this embodiment. In general, semiconductor device inspection includes probe inspection in a wafer state, dicing, and final sorting inspection after packaging. The inspection method described below can be performed in both the probe inspection and the final screening inspection.

  In FIG. 7, first, values n and ΔVBL obtained by the above-described design are set and inputted to the measuring apparatus (step 1). Step 1 need only be performed once for the same lot. Next, as an initial inspection, a contact is brought into contact with the external pad of the ferroelectric memory device, and an open / short inspection is performed (step 2). If a defect is found in step 2, it is determined that a defect category has occurred (step 7), the inspection for the ferroelectric memory device is terminated (step 8), and the next ferroelectric memory is stored. Transition to equipment inspection.

If no defect is found in step 2, the hysteresis characteristic specific to the ferroelectric capacitor of the ferroelectric memory device is measured, and ΔPa and Cu are measured. FIG. 8 is an example of the CV characteristic of the ferroelectric capacitor to be measured. If the non-selection voltage Vu = 0.8V, Cu = 15 μC / cm ² / V is obtained. Thus, if the value Cu is not derived from the hysteresis characteristic by calculation, but derived from the measurement of the CV curve, the time is shortened. As described above, ΔPa is a function f (Vs) when the selection voltage Vs is applied to one selected memory cell of n ferroelectric memory cells connected to the bit line BLm, and other unselected memory cells. Is obtained from the difference from the function f (Vu) when the non-selection voltage Vu is applied to, that is, ΔPa = f (Vs) −f (Vu). When Cu is sufficiently small, ΔPa≈2Pr may be set as described above. Step 3 is performed on at least one ferroelectric capacitor of the ferroelectric memory device.

  Next, the values n, ΔVBL, ΔPa and Cu obtained in steps 1 and 3 are substituted into the above-described equation (1) to determine whether the inequality of equation (1) is satisfied (step 4). ). If equation (1) does not hold, it is determined that a defect category has occurred (step 7), and the inspection of the ferroelectric memory device is terminated (step 8).

  When Expression (1) is established in Step 4, various tests (also referred to as late tests) are performed (Step 5). The various tests include a DC test, a function test, a special test, an AC test, and the like that are generally performed on a storage device. Current tests such as standby and leak are performed by the DC test, and logic operation is confirmed at a relatively low speed by the function test. The special test is a test related to items added by feedback of past defect cases, and tests other than the speed test are performed. In the AC test, the logic operation at the owned access speed is confirmed. Only when all the inspections in step 5 are determined to be normal, it is determined as non-defective (step 6), and the inspection for the ferroelectric memory device is completed.

  Here, the various tests in Step 5 required a longer time than before. For example, since the special test is performed for many items based on defects that occurred in the past, the test time is long. In addition, the DC test and AC test also take a long time because several types of test patterns are used. In the present embodiment, at least after the initial test (step 2) and before the various tests (step 5), the test in step 4 is performed, so that a functionally defective measurement object can be detected for a long time. Can be excluded before various tests that require. Therefore, compared with the conventional example in which various tests are performed on a functionally defective measurement object, the total inspection time is shortened and the total cost is reduced.

FIG. 9 shows an inspection method unique to the ferroelectric memory device. The imprint test of Step 1 in FIG. 9 is roughly classified into a static imprint test and a dynamic imprint test. Usually, it carries out about either one. The static imprint test is a test in which the selection voltage Vs is applied only once, data is written to the ferroelectric capacitor, and then left at a high temperature, for example, about 150 ° C. for a long time, for example, 40 to 150 hours, and then the data is read. It is. The dynamic imprint test is a test in which, for example, the positive selection voltage Vs is continuously applied many times, for example, 10 ⁹ to 10 ¹⁰ times in the above-described high temperature atmosphere, data is written each time, and data is finally read. .

  Both are reliability tests as to whether or not they can withstand a predetermined service life. As a result of the above-described imprint test, if the hysteresis characteristic is imprinted and the initial function cannot be achieved, it is determined as defective. In the present embodiment, whether or not the inequality of | ΔPa / Cu | ≧ (n−1) × ΔVBL (the above-described equation (4))) is satisfied as the determination item (step 2) is performed. Yes. As a result of imprinting, as long as the squareness of FIG. 2 is maintained, | Vs |> | Vc | (equation (5) described above) is always maintained. Therefore, whether or not the expression (5) is satisfied may be performed as the determination item in step 2 after the imprint test. According to the determination result in step 2, the product is sorted into a non-defective product and a defective product (steps 4 and 5).

6). PZT Tetragonal Ferroelectric Thin Film Next, the problems of the conventional PZT ferroelectric and the effectiveness of this embodiment will be described. PZT tetragonal crystals originally have squareness suitable for memory applications, but are not practical because of poor reliability.

  First, the PZT tetragonal thin film after crystallization tends to have a higher leakage current density as the Ti content is higher. In addition, when the so-called static imprint test is performed, in which data is written only once in either the + or − direction and the data is read after being heated and held at 100 ° C., for example, it is almost written after 24 hours. There is no data left. These are essential elements possessed by PZT, which is an ionic crystal, and Pb, which is a constituent element of PZT, and Ti itself, and this is the maximum that a PZT tetragonal thin film, most of which is composed of Pb and Ti, has. It has become an issue.

  It is considered that PZT perovskite is an ionic crystal and is essential for PZT.

  FIG. 10 is a list of main energies related to the bonding of each constituent element of PZT. PZT is known to contain many oxygen vacancies after crystallization. That is, it is expected from FIG. 10 that Pb—O has the smallest binding energy among the PZT constituent elements, and can be easily cut off during firing and polarization inversion. That is, it is natural that when Pb is lost, O is lost due to the principle of charge neutrality.

  Next, during heating and holding such as imprint tests, each constituent element of PZT vibrates and repeats collision, but Ti is the lightest among the PZT constituent elements, and it is easy to come off due to vibration collision at high temperature holding. It is obvious. Therefore, it is natural that O escapes from the principle of charge neutrality when Ti escapes. Further, since it contributes to bonding with the maximum valences of Pb: +2 and Ti: +4, no charge neutrality is established except for the elimination of O. That is, in PZT, two anions such as O are easily removed with respect to one cation such as Pb and Ti, and so-called Schottky defects are easily formed.

  As shown in FIG. 11, in the perovskite crystal, oxygen ions come next to the cations, so that the cation defects are less likely to cause an increase in leakage current. However, oxygen ions are connected in series with the entire PZT crystal, and when oxygen vacancies increase, the leakage current increases accordingly.

  In addition, Pb and Ti loss and accompanying O loss are so-called lattice defects, which cause the space charge polarization shown in FIG. 12, and as a result, the electric field due to ferroelectric polarization is caused by lattice defects. A counter electric field is generated and a so-called bias potential is applied. As a result, hysteresis is shifted or depolarized. In addition, this phenomenon occurs more rapidly as the temperature increases.

  The above is an essential problem of PZT, and since it is difficult to solve with pure PZT, a memory element using tetragonal PZT has not been realized. Here, we solved the above problems by using the PZTN thin film of this embodiment or improving the conventional PZT as described later in Examples 1 and 2 and the like.

In the PZTN thin film, Nb doping was performed on the Ti site. Nb is almost the same size as Ti (the ion radius is close and the same for the primitive radius), is twice the weight, and is difficult to escape during a collision. The valence is +5 and is stable, and even if Pb is lost, Nb ⁵⁺ compensates for the valence of Pb loss. In addition, even if Pb loss occurs during crystallization, it is clear that it is easier to enter small Nb than large O loss.

In addition, since Nb also has a +4 valence, Ti ⁴⁺ can be sufficiently replaced. Furthermore, in fact, Nb has a very strong covalent bond, and Pb is considered to be difficult to escape (H. Miyazawa, E. Natori, S. Miyashita; Jpn. J. Appl. Phys. 39 (2000). 5679).

  So far, Nb doping to PZT has been mainly performed in the Zr-rich rhombohedral region, but the amount is 0.2-0.025 mol% (J. Am. Ceram. Soc, 84 ( 2001) 902; Phys. Rev. Let, 83 (1999) 1347) and so on. Although this will be described in detail in the examples described later, the addition of 10 mol% of Nb increases the crystallization temperature to 800 ° C. or higher.

However, in this embodiment, it has been found that the crystallization temperature of PZTN or PZN is drastically lowered by adding 1 to 5 mol% of PbSiO ₃ silicate. The embodiment for forming the PZTN thin film is an epoch-making technique realized by simultaneously adding Nb and PbSiO ₃ silicate.

  W and V have the same effect in place of Nb. Further, in the same way of thinking, it is conceivable to substitute Pb with an element having a valence of +3 or more in order to prevent Pb loss. These candidates include lanthanoids such as La. In addition, as an additive for promoting crystallization, germanate (Ge) instead of silicate (Si), or silicate and germanate may be used as an additive.

  Hereinafter, detailed examples of the ferroelectric thin film suitably used in the present invention will be described.

In this example, a PbZr _0.35 Ti _0.65 O ₃ (PZT) ferroelectric thin film was produced.

  In the conventional method, a solution containing Pb excessively by about 20% is used. This is for the purpose of suppressing volatile Pb and reducing the crystallization temperature. However, it is unclear how excess Pb is formed in the thin film thus produced, and should be suppressed with a minimum Pb excess.

In this example, the sol-gel-MOD solution mixed solution 1 for forming PbZr _0.35 Ti _0.65 O ₃ (PZT) having a concentration of 10% by weight with an excess Pb of 2% with respect to the stoichiometric composition is the same as the chemical solution. A 10% by weight PbZr _0.35 Ti _0.65 O ₃ (PZT) -forming sol-gel-MOD solution mixed solution 2 having an excess Pb of 2% with respect to the stoichiometric composition was used.

The sol-gel-MOD solution mixed solution 1 for PZT formation uses 1-methoxy-2-propanol (CH ₃ OCH ₂ CHOHCH ₃ ) as a solvent and lead 2-ethylhexanoate (Pb (OCO (CH (C ₂ H ₅ ) C ₄ H _{9) 2),} 2- ethylhexanoate, zirconium _{(Zr (OCO (CH (C} 2 H 5) C 4 H 9) 4) and 2-ethylhexanoic acid titanium _{(Ti (OCO (CH (C} 2 H 5 ) Pb (Zr, Ti) O ₃ (PZT) thin film forming MOD solution using C ₄ H ₉ ) ₄ ) as a solute, dibutonoxy lead (Pb (OC ₄ H ₉ ) ₂ ), tetrabutoxyzirconium (Zr ( 1 mol each of the sol-gel solution for forming a PZT thin film using each metal alkoxide of OC ₄ H ₉ ) ₄ ) and tetrabutoxy titanium (Ti (OC ₄ H ₉ ) ₄ ) as a solute was obtained.

The sol-gel-MOD solution mixed solution 2 for forming PZT uses butyl acetate (CH ₃ OCOC ₄ H ₉ ) as a solvent, and uses lead oxide (PbO), zirconium oxide (ZrO ₂ ), and titanium oxide (TiO ₂ ) as solutes. PZT thin film forming MOD solution, 2-methoxyethanol (CH ₃ 0CH ₂ CH ₂ OH) as a solvent, lead acetate (Pb (OCOCH ₃ ) ₂ ), tetrabutoxyzirconium (Zr (OC ₄ H ₉ ) ₄ ) and 1 mol each of the sol-gel solution for forming a PZT thin film using tetrabutoxytitanium (Ti (OC ₄ H ₉ ) ₄ ) as a solute was obtained.

Next, a 0.1 wt% PbO-forming sol-gel solution was applied onto a Pt electrode-coated substrate using a spin coating method at 4000 rpm for 20 seconds, and then 200 ° C. in an Ar atmosphere pressurized to 5 atm. Holding for 2 hours, a PbPt ₃ alloy was formed on the outermost surface of the Pt electrode.

Using the above-mentioned PZT-forming sol-gel-MOD mixed solutions 1 and 2 on the Pt electrode-coated substrate on which the PbPt ₃ alloy is formed on the outermost surface, by spin coating, based on the following ferroelectric film formation conditions , PZT1 and PZT2 amorphous thin films were respectively formed.

Ferroelectric thin film formation conditions Step 1: Spin coating (500 rpm 5 sec → 3000 rpm 30 sec)
Step 2: Drying (150 ° C, 2 min inair)
Step 3: Temporary firing (250 ° C., 5 min in air)
Step 4: A PZT amorphous thin film was formed after repeating Steps 1 to 3 three times.

The amorphous thin films of PZT1 and PZT2 were crystallized for 10 minutes at a firing temperature of 500 ° C. with a temperature rising from room temperature to 100 ° C./second while maintaining an N ₂ mixed gas containing 1% O ₂ at 8 atm. Made. The film thicknesses of PZT1 and 2 after crystallization were 150 nm, respectively.

In addition, a 0.1 wt% PbO-forming sol-gel solution was applied to the surface of the PZT1 and PZT2 thin films using a spin coating method at 4000 rpm for 20 seconds, held in air at 150 ° C. for 2 minutes, An upper electrode (film thickness: 100 nm, diameter: 300 μm) was formed. Furthermore, it is maintained at 200 ° C. for 2 hours in an Ar atmosphere pressurized to 5 atm, and a PtPb ₃ alloy is formed on the lowermost surface of the upper Pt electrode. At the same time, a good interface is formed between the PZT thin films 1 and 2 and the upper Pt electrode. Formed.

Next, while maintaining the N ₂ mixed gas containing 1% O ₂ at 8 atm, post-annealing was performed at a firing temperature of 650 ° C. for 10 minutes from room temperature at a heating rate of 100 ° C./second, and PZT 1 and A PZT2 capacitor was fabricated and ferroelectric characteristics were evaluated.

For comparison, post-annealing for 10 minutes at a firing temperature of 650 ° C. with a heating rate of 100 ° C./second from room temperature while maintaining an N ₂ mixed gas containing 1% O ₂ at atmospheric pressure (1 atm). Then, PZT1 ′ and PZT2 ′ capacitors were produced, and ferroelectric characteristics were evaluated.

When the D-E hysteresis characteristics were evaluated, as shown in FIGS. 13 and 14, both PZT1 and PZT2 showed a good square shape at a low voltage of the selection voltage Vs = 1.5V, and the polarization when the applied voltage was 0v. Each value showed Pr = 45 μC / cm ² for both PZT1 and PZT2. The ferroelectric memory device using the ferroelectric material of Example 1 satisfied the above formulas (1), (4), and (5).

  This proves the effectiveness of this embodiment using a mixed solution of sol-gel and MOD regardless of the solute or solvent of the sol-gel and MOD solution.

  PZT1 'and PZT2', which are comparative examples, showed almost no ferroelectricity at the selection voltage Vs = 1.5V as shown in FIGS. 15 and 16, and the squareness was also inferior. In the old dielectric memory device using the ferroelectric material of the comparative example, the above formulas (1), (4), and (5) were not satisfied.

Here, since the PZT crystal is formed with a stoichiometric composition, it is necessary to form a PZT thin film by using a solution having a stoichiometric composition and a composition close to that in order to obtain good dielectric properties. It means that there is. However, since Pb has a high vapor pressure and volatilizes at a low temperature, when using a PZT forming solution with a stoichiometric composition or a composition close to it, the vapor pressure of Pb is controlled to suppress volatilization of the Pb component. It is important to. In Example 1, when the comparative PZT1 ′ and PZT2 ′ capacitors were produced, the N ₂ mixed gas containing 1% O ₂ was maintained at atmospheric pressure (1 atm), but instead, PZT1 and PZT1 ′ By setting the PZT2 capacitor to a high pressure such as 8 atm, volatilization of the Pb component could be suppressed.

In this example, a PbZr _0.4 Ti _0.6 O ₃ (PZT) ferroelectric thin film was produced.

A 10% by weight PbZr _0.4 Ti _0.6 O ₃ forming sol-gel solution (solvent: n-butanol) having an excess Pb of 0, 5, 10, 15, 20% was used, and an additional 10% by weight A sol-gel solution for forming PbSiO ₃ (solvent: n-butanol) was added in an amount of 1 mol% to form a 200 nm PbZr _0.4 Ti _0.6 O ₃ thin film using the flow of FIG. The surface morphology at this time is shown in FIGS. 18A to 18E, and the XRD patterns are shown in FIGS. 19A to 19E.

Conventionally, an excess of Pb of about 20% was required, but it was shown that crystallization progressed sufficiently with an excess of Pb of 5%. This indicates that as little as 1 mol% PbSiO ₃ catalyst has lowered the crystallization temperature of PZT, so little excess Pb is needed. Thereafter, as the PZT, PbTiO ₃ , and PbZrTiO ₃ forming solutions, all 5% Pb excess solutions are used.

Next, a 10% by weight PbZrO ₃ forming sol-gel solution (solvent: n-butanol) and 10% by weight PbTiO ₃ forming sol-gel solution (solvent: n-butanol) are mixed at a ratio of 4: 6. 200 nm-PbZr _0.4 Ti _0.6 O ₃ according to the flow of FIG. 20 using a mixed solution in which 1 mol% of a sol-gel solution (solvent: n-butanol) for forming PbSiO _{3 at a} concentration of 10% by weight was added to A ferroelectric thin film was prepared. The hysteresis characteristics at this time were excellent in squareness as shown in FIGS. However, it turned out to be leaky at the same time. The ferroelectric memory device using the ferroelectric material of Example 2 also satisfied the above formulas (1), (4), and (5).

Further, for comparison, 10% is added to a sol-gel solution (solvent: n-butanol) for forming PbZr _0.4 Ti _0.6 O ₃ having a concentration of 10% by weight using the flow shown in FIG. A 200 nm-PbZr _0.4 Ti _0.6 O ₃ ferroelectric thin film was prepared using a mixed solution to which 1 mol% of a sol-gel solution for PbSiO ₃ formation (solvent: n-butanol) having a concentration by weight of 1% was added. At this time, the hysteresis characteristic was not very good as shown in FIG.

  Then, when the degassing analysis was performed using each thin film, it was as FIG. 23 (A) (B). In the conventional thin film prepared with the PZT sol-gel solution, it was confirmed that degassing always occurred in H and C as the temperature increased from room temperature to 1000 ° C.

On the other hand, the 10% by weight PbZrO ₃ forming sol-gel solution (solvent: n-butanol) and the 10% by weight PbTiO ₃ forming sol-gel solution (solvent: n-butanol) in Example 2 were in a ratio of 4: 6. It was found that almost no degassing was observed until decomposition when using the solution mixed in (1).

This is because 10% by weight PbZrO ₃ forming sol-gel solution (solvent: n-butanol) and 10% by weight PbTiO ₃ forming sol-gel solution (solvent: n-butanol) were mixed at a ratio of 4: 6. By using the solution, PbTiO ₃ is first crystallized on Pt by a 10% by weight sol-gel solution for forming PbTiO ₃ (solvent: n-butanol) in the mixed solution, which becomes a crystal initial nucleus, and Pt and PZT It was thought that PZT crystallized easily. Moreover, it is considered that by using the mixed solution, PbTiO ₃ and PZT were continuously formed at a good interface, which led to good hysteresis squareness.

In the following examples, a mixed solution of PbZrO ₃ and PbTiO ₃ was used.

  Here, the PZTN according to the present embodiment is compared with the conventional PZT. All the film forming flows used the above-described FIG.

Pb: Zr: Ti: Nb = 1: 0.2: 0.6: 0.2, 1: 0.2: 0.7: 0.1, and 1: 0.3: 0.65: 0.5 It was. That is, the amount of Nb added was 5 to 20 mol% of the whole. To this, 0 to 1% of PbSiO ₃ was added.

  The crystallinity at this time was as shown in FIGS. 24 (A) to (C) and FIGS. 25 (A) to (C). In the case of 0%, only paraelectric pyrochlore was obtained even when the crystallization was increased to 800 ° C. In the case of 0.5%, it was a mixture of PZT and pyrochlore. In the case of 1%, a PZT (111) single alignment film was obtained. Also, the crystallinity was so good that it had never been obtained.

Next, when the film thickness was set to 120 to 200 nm with respect to the 1% -added PZTN thin film of PbSiO ₃ , the film thicknesses were as shown in FIGS. 26A to 26C and FIGS. 27A to 27C, respectively. The crystallinity was proportional to. In addition, as shown in FIGS. 28A to 28C and FIGS. 29A to 29C which are enlarged views thereof, all of the square-shaped hysteresis characteristics were obtained. In addition, as shown in FIGS. 30A and 30B, the leak characteristics are 5 to 10 ^{−8 to} 7 to 10 ⁻⁹ A / cm ² when 2 V is applied (at saturation) regardless of the film composition and film thickness. And was very good.

Next, when the fatigue characteristics and static imprint of the PbZr _0.2 Ti _0.8 Nb _0.2 thin film were measured, they were very good as shown in FIGS. 31 (A) and 31 (B). In particular, the fatigue characteristics were very good despite using Pt for the upper and lower electrodes.

Furthermore, as shown in FIG. 32, SiO ₂ coating by ozone TEOS was tried on the PZTN capacitor of this example. Conventionally, it is known that when PZT is coated with SiO ₂ by ozone TEOS, the hydrogen generated from TEOS reduces PZT through the upper Pt, and the PZT crystal breaks to such an extent that no hysteresis is exhibited.

  However, as shown in FIG. 33, the PZTN thin film according to this example hardly deteriorated and maintained good hysteresis. It was found that the PZTN thin film according to this example was also strong in reduction resistance. Further, in the tetragonal PZTN thin film according to this example, when Nb did not exceed 40 mol%, good hysteresis was obtained according to the amount of Nb added.

  As described above, the ferroelectric material of Example 3 also exhibits good squareness hysteresis characteristics, and the ferroelectric memory device using the ferroelectric material satisfies the above formulas (1), (4), and (5). Satisfied.

  Next, conventional PZT thin films were evaluated. As conventional PZT, Pb: Zr: Ti = 1: 0.2: 0.8, 1: 0.3: 0.7, and 1: 0.6: 0.4, respectively.

As shown in FIG. 34, the leak characteristic deteriorates as the Ti content increases. When Ti is 80%, the leak characteristic becomes 10 ⁻⁵ A / cm ² when 2 V is applied, which is suitable for memory applications. I found out.

Similarly, as shown in FIG. 35, the fatigue characteristics deteriorated as the Ti content increased.
Further, it was found that almost no data could be read after imprinting as shown in FIG.

  As can be seen from the above examples, the PZTN thin film according to this example has not only solved the problems of increase in leakage current and deterioration of imprint characteristics, which are considered to be caused by the essence of PZT, but has been used for the above reasons. It has become possible to use tetragonal PZT for memory purposes regardless of the type and structure of the memory. In addition, it is considered that the present material can be applied to piezoelectric element applications in which tetragonal PZT is not used for the same reason.

In the PZTN thin film according to this example, the ferroelectric properties were compared by changing the Nb addition amount to 0, 5, 10, 20, 30, and 40 mol%. In all samples, 5 mol% of PbSiO ₃ silicate was added. Further, the pH of the sol-gel solution for forming a ferroelectric thin film, which is a raw material for forming a thin film, was adjusted to 6 by adding methyl succinate. All of the film forming flows use FIG. 20 described above.

  FIGS. 37A and 37B to 39A and 39B show the hysteresis characteristics obtained at this time.

  As shown in FIG. 37A, a leaky hysteresis was obtained when the Nb addition amount was 0, but when the Nb addition amount was 5 mol% as shown in FIG. High and good hysteresis characteristics were obtained.

  Further, as shown in FIG. 38A, the ferroelectric characteristics hardly changed until the Nb addition amount was 10 mol%. Even when the amount of Nb added is 0, although it is leaky, no change is observed in the ferroelectric characteristics. Further, as shown in FIG. 38 (B), when the Nb addition amount is 20 mol%, hysteresis characteristics with very good squareness were obtained.

  As described above, the ferroelectric material of Example 4 also exhibits good squareness hysteresis characteristics, and the ferroelectric memory device using the ferroelectric material satisfies the above formulas (1), (4), and (5). Satisfied.

  However, as shown in FIG. 39 (A) and FIG. 39 (B), it was confirmed that when the Nb addition amount exceeds 20 mol%, the hysteresis characteristics greatly change and deteriorate.

  Thus, X-ray diffraction patterns were compared and it was as shown in FIG. When the amount of Nb added is 5 mol% (Zr / Ti / Nb = 20/75/5), the (111) peak position is the same as that of the conventional PZT film to which Nb is not added. As the amount increases to 20 mol% (Zr / Ti / Nb = 20/60/20) and 40 mol% (Zr / Ti / Nb = 20/40/40), the (111) peak shifts to the lower angle side. did. That is, although the composition of PZT is Ti-rich and a tetragonal region, it can be seen that the actual crystal is a rhombohedral crystal. It can also be seen that the ferroelectric properties change as the crystal system changes.

  In addition, when 45 mol% of Nb was added, the hysteresis did not open and the ferroelectric characteristics could not be confirmed (not shown).

  In addition, the PZTN thin film according to this example has already been described as having a very high insulating property, but when the conditions for PZTN being an insulator were obtained, it was as shown in FIG.

That is, the PZTN thin film according to this example has a very high insulating property, which means that Nb is added to the Ti site at a composition ratio corresponding to twice the amount of Pb deficiency. Further, as can be seen from the crystal structure of WO ₃ shown in FIG. 42, the perovskite crystal is established even if the A-site ion is 100% deficient, and WO ₃ is known to change its crystal system easily. .

  Therefore, in the case of PZTN, by adding Nb, the amount of Pb deficiency is positively controlled and the crystal system is controlled.

  This indicates that the PZTN thin film of this example is very effective for application to piezoelectric elements. In general, when PZT is applied to a piezoelectric element, a rhombohedral crystal region having a Zr rich composition is used. At this time, the Zr-rich PZT is called a soft PZT. This literally means that the crystal is soft. For example, a soft PZT is used for an ink discharge nozzle of an ink jet printer. However, since the soft PZT is too soft, an ink with a very high viscosity cannot be pushed out against the pressure of the ink.

  On the other hand, Ti-rich tetragonal PZT is called hard PZT, which means that it is hard and brittle. However, although the PZTN thin film of this example is a hard system, the crystal system can be artificially changed to a rhombohedral crystal. In addition, the crystal system can be arbitrarily changed depending on the amount of Nb added, and the Ti-rich PZT ferroelectric thin film has a small relative dielectric constant, so that the device can be driven at a low voltage. .

  This makes it possible to use a hard PZT that has not been used so far, for example, as an ink discharge nozzle of an ink jet printer. In addition, since Nb brings softness to PZT, it is possible to provide PZT that is moderately hard but not brittle.

  Finally, as described above, in this embodiment, not only Nb is added, but also silicate is added simultaneously with Nb addition, so that the crystallization temperature can be reduced.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the invention.

  For example, it is preferable that Tc ≧ 300 ° C. when the Curie temperature of the ferroelectric thin film constituting the ferroelectric capacitor is Tc. When the Curie temperature is reached, the material becomes a paraelectric, but there is a change in the properties of the ferroelectric material from the temperature before reaching the Curie temperature. This is because the compensation temperature of the ferroelectric memory device is 125 ° C., but the Curie temperature is required to be 300 ° C. or higher so that the quality of the ferroelectric material does not change at this compensation temperature.

Further, the ferroelectric material to which the present invention is applied is not limited to the above-described PZT and PZNT, but may be, for example, Bi ₄ Ti ₃ O ₁₂ as a BIT system.

The figure which showed the structure of the ferroelectric capacitor in embodiment of this invention. The figure which showed the P (polarization) -V (voltage) hysteresis curve of the ferroelectric capacitor in embodiment of this invention. FIG. 3 is a diagram showing n ferroelectric memory cells, a selection gate, and a sense amplifier that are connected to one bit line. 1A and 1B are diagrams showing a configuration of a ferroelectric memory device in which memory cells configured by a simple matrix are arranged according to an embodiment of the present invention. FIG. 1A is a plan view thereof, and FIG. Sectional drawing. 1 is a cross-sectional view showing an example of a ferroelectric memory device in which a memory cell array is integrated with a peripheral circuit on the same substrate in an embodiment of the present invention. The figure which shows the circuit diagram and structure of 1T1C type ferroelectric memory in embodiment of this invention. The flowchart which shows embodiment of the test | inspection method of this invention. The characteristic diagram of the voltage (V) -capacitance (C) of a ferroelectric capacitor. The flowchart which shows embodiment of the other test | inspection method of this invention. The figure which shows the various characteristics regarding the coupling | bonding of the PZT ferroelectric constituent element in embodiment of this invention. The figure which shows the Schottky defect in embodiment of this invention. The figure which shows the space charge polarization in embodiment of this invention. The hysteresis characteristic figure of PZT1 which concerns on Example 1 of this invention. The hysteresis characteristic figure of PZT2 which concerns on Example 1 of this invention. The hysteresis characteristic figure of PZT1 'which is a comparative example with respect to Example 1 of this invention. The hysteresis characteristic figure of PZT2 'which is a comparative example with respect to Example 1 of this invention. The figure which shows the flowchart for forming the conventional PZT thin film in embodiment of this invention by a spin coat method. (A) ~ (E) is a view showing the embodiment of the present invention, the surface morphology at the time of mixing PbSiO ₃ sol-gel solution for PZT formation. (A) ~ (E) is a view showing the embodiment of the present invention, the crystallinity when mixed with PbSiO ₃ sol-gel solution for PZT formation. The figure which shows the flowchart for forming the PZTN thin film of this invention in embodiment of this invention by a spin coat method. (A) and (B) are diagrams showing hysteresis of a tetragonal PZT thin film formed by adding PbSiO ₃ to a PbZrO ₃ and PbTiO ₃ mixed sol-gel solution in the embodiment of the present invention. The figure which shows the hysteresis of the conventional tetragonal PZT thin film in embodiment of this invention. (A) and (B) show the degassing analysis results of the tetragonal PZT thin film formed by adding PbSiO ₃ to the PbZrO ₃ and PbTiO ₃ mixed sol-gel solution and the conventional tetragonal PZT thin film in the embodiment of the present invention. FIG. (A) ~ (C) is a drawing showing the embodiment of the present invention, the surface morphology of PbSiO ₃ amount and PZTN. (A) ~ (C) is a drawing showing the embodiment of the present invention, the crystallinity PbSiO ₃ amount. (A)-(C) are the figures which show the film thickness of the PZTN thin film, and the surface morphology of PZTN in embodiment of this invention. (A)-(C) are the figures which show the film thickness and crystallinity of a PZTN thin film in embodiment of this invention. (A)-(C) are the figures which show the film thickness and hysteresis characteristic of a PZTN thin film in embodiment of this invention. (A)-(C) are the enlarged views of FIG. 28 (A)-(C). (A) and (B) are diagrams showing leakage current characteristics of a PZTN thin film in an embodiment of the present invention. (A) (B) is a figure which shows the fatigue characteristic and static imprint characteristic of a PZTN thin film in embodiment of this invention. Drawing showing an embodiment of the present invention, a capacitor structure of the SiO ₂ protective film formed by ozone TEOS. Drawing showing an embodiment of the present invention, the capacitor characteristics after SiO ₂ protective film formed by ozone TEOS. The figure which shows the leakage current characteristic of the conventional PZT thin film in embodiment of this invention. The figure which shows the fatigue characteristic of the conventional PZT capacitor in embodiment of this invention. The figure which shows the static imprint characteristic of the conventional PZT capacitor in embodiment of this invention. (A) (B) is a figure which shows the hysteresis characteristic of the PZTN thin film in embodiment of this invention. (A) (B) is a figure which shows the hysteresis characteristic of the PZTN thin film in embodiment of this invention. (A) (B) is a figure which shows the hysteresis characteristic of the PZTN thin film in embodiment of this invention. The figure which shows the X-ray-diffraction pattern of the PZTN thin film in embodiment of this invention. The figure which shows the relationship between the Pb defect | deletion amount in a PZTN crystal | crystallization, and the composition ratio of Nb in embodiment of this invention. Shows the crystal structure of WO ₃ is perovskite crystal.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 Ferroelectric film, 102 1st electrode, 103 2nd electrode, BLm mth bit line, C1-Cnn n ferroelectric capacitors, SAm sense amplifier

Claims (22)

Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of ferroelectric memory cells each comprising a ferroelectric capacitor formed at each intersection of the plurality of word lines and the plurality of bit lines;
At least one sense amplifier selectively connected to the plurality of bit lines;
Have
A simple matrix type ferroelectric memory device that satisfies the following formula.
| ΔPa / Cu | ≧ (n−1) × ΔVBL
n: number of the ferroelectric memory cells connected to each one of the plurality of bit lines ΔPa: hysteresis indicating the polarization amount P (μC / cm ² ) of the ferroelectric memory cell when the voltage V is applied When the function is P = f (V), the function f (Vs) when the selection voltage Vs is applied to one selected memory cell of the n ferroelectric memory cells connected to the one bit line. And the function f (Vu) when the unselected voltage Vu is applied to other unselected memory cells, and ΔPa = f (Vs) −f (Vu). Cu: The one bit line Capacity of (n-1) unselected memory cells connected to each other (μC / cm ² / V)
ΔVBL: Minimum input amplitude (V) that can be amplified by the sense amplifier In claim 1,
A simple matrix ferroelectric memory device in which n is 32 to 128. In claim 1 or 2,
A plurality of main bit lines are further provided,
Each of the plurality of bit lines is divided into a plurality of sub-bit lines that are selectively connected to each one of the plurality of main bit lines, and each of the plurality of sub-bit lines includes the n ferroelectrics. A simple matrix ferroelectric memory device to which memory cells are connected. In any one of Claims 1 thru | or 3,
A simple matrix ferroelectric memory device having a Cu value of 0.1 to 15 (μC / cm ² / V). In any one of Claims 1 thru | or 4,
A simple matrix ferroelectric memory device having a ΔPa value of 40 to 120 (μC / cm ² ). In any one of Claims 1 thru | or 5,
A simple matrix ferroelectric memory device having a value of | ΔPa / Cu | of 1.6 to 50 (V). Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of ferroelectric memory cells each comprising a ferroelectric capacitor formed at each intersection of the plurality of word lines and the plurality of bit lines;
Have
When the coercive voltage of the ferroelectric memory cell is Vc, the selection voltage to the ferroelectric memory cell (but the same polarity as the coercive voltage) is Vs, and Vs−Vc = ΔV, ΔV ≦ Vc is satisfied. Simple matrix type ferroelectric memory device. In claim 7,
A simple matrix ferroelectric memory device that satisfies | Vs |> | Vc | even after an imprint test of the ferroelectric memory device. In any one of Claims 1 thru | or 8.
The ferroelectric thin film constituting the ferroelectric capacitor is represented by a general formula of AB _1-x Nb _x O ₃ ,
A element consists of at least Pb,
B element consists of at least one of Zr, Ti, V, W and Hf,
A simple matrix ferroelectric memory device including Nb in a range of 0.05 ≦ x ≦ 1. In claim 9,
A element _consists of _{Pb 1-y} Ln y,
Ln is composed of at least one of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and 0 <y ≦ 0.2. A simple matrix type ferroelectric memory device in the range of In any one of Claims 1 thru | or 8.
The ferroelectric thin film constituting the ferroelectric capacitor is represented by a general formula of (Pb _1-y A _y ) (B _1-x Nb _x ) O ₃ ,
The element A is composed of at least one of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu,
B element consists of one or more of Zr, Ti, V, W and Hf,
A simple matrix ferroelectric memory device including Nb in a range of 0.05 ≦ x ≦ 1. In any one of Claims 9-11,
A simple matrix ferroelectric memory device including Nb in a range of 0.1 ≦ x ≦ 0.3. In any one of Claims 1 thru | or 8.
The ferroelectric thin film constituting the ferroelectric capacitor is a PZT ferroelectric thin film,
A simple matrix ferroelectric memory device in which a Ti composition is larger than a Zr composition, and 2.5 mol% or more and 40 mol% or less of the Ti composition is substituted with Nb. In claim 13,
A simple matrix ferroelectric memory device containing 0.5 mol% or more of Si or Si and Ge. In any one of Claims 1 thru | or 8.
The ferroelectric thin film constituting the ferroelectric capacitor is represented by a general formula of ABO ₃ and includes Pb as a constituent element of the A site, and a PZT-based ferroelectric including at least Zr and Ti as constituent elements of the B site. A simple matrix type ferroelectric memory device in which the amount of Pb deficiency at the A site in the thin film is 20 mol% or less at most with respect to the stoichiometric composition of the ABO ₃ . In any one of Claims 1 thru | or 15,
A simple matrix type ferroelectric memory device satisfying Tc ≧ 300 ° C., where Tc is a Curie temperature of a ferroelectric thin film constituting the ferroelectric capacitor. Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of ferroelectric memory cells comprising ferroelectric capacitors formed by disposing a ferroelectric material at each intersection of the plurality of word lines and the plurality of bit lines;
At least one sense amplifier selectively connected to the plurality of bit lines;
In a design method of a ferroelectric memory device having
A design method of a simple matrix type ferroelectric memory device, wherein the ferroelectric material is selected so as to satisfy the following formula, and values n and ΔVBL are designed.
| ΔPa / Cu | ≧ (n−1) × ΔVBL
n: number of the ferroelectric memory cells connected to each one of the plurality of bit lines ΔPa: hysteresis indicating the polarization amount P (μC / cm ² ) of the ferroelectric memory cell when the voltage V is applied When the function is P = f (V), the function f (Vs) when the selection voltage Vs is applied to one selected memory cell of the n ferroelectric memory cells connected to the one bit line. And the function f (Vu) when the unselected voltage Vu is applied to other unselected memory cells, and ΔPa = f (Vs) −f (Vu). Cu: The one bit line Capacity of (n-1) unselected memory cells connected to each other (μC / cm ² / V)
ΔVBL: Minimum input amplitude (V) that can be amplified by the sense amplifier Multiple word lines,
A plurality of bit lines intersecting the plurality of word lines;
A plurality of ferroelectric memory cells comprising ferroelectric capacitors formed by disposing a ferroelectric material at each intersection of the plurality of word lines and the plurality of bit lines;
At least one sense amplifier selectively connected to the plurality of bit lines;
In a method for inspecting a ferroelectric memory device having
An inspection method for a simple matrix ferroelectric memory device, comprising a step of determining whether or not the following expression is satisfied.
| ΔPa / Cu | ≧ (n−1) × ΔVBL
n: number of the ferroelectric memory cells connected to each one of the plurality of bit lines ΔPa: hysteresis indicating the polarization amount P (μC / cm ² ) of the ferroelectric memory cell when the voltage V is applied When the function is P = f (V), the function f (Vs) when the selection voltage Vs is applied to one selected memory cell of the n ferroelectric memory cells connected to the one bit line. And the function f (Vu) when the unselected voltage Vu is applied to other unselected memory cells, and ΔPa = f (Vs) −f (Vu). Cu: The one bit line Capacity of (n-1) unselected memory cells connected to each other (μC / cm ² / V)
ΔVBL: Minimum input amplitude (V) that can be amplified by the sense amplifier In claim 18,
An initial inspection process including an open / short inspection of the simple matrix ferroelectric memory device;
Late inspection process for inspecting the simple matrix ferroelectric memory device for items other than the initial inspection process,
Further comprising
The method for inspecting a simple matrix ferroelectric memory device, wherein the determination step is performed after the initial inspection step and before the late inspection step. In claim 18 or 19,
An inspection method for a simple matrix type ferroelectric memory device, wherein the value of Cu is derived by measuring a voltage-capacitance characteristic of the ferroelectric capacitor. In a testing method of a simple matrix type ferroelectric memory device having a ferroelectric memory cell in which a ferroelectric capacitor is arranged between electrodes,
Imprinting the simple matrix ferroelectric memory device; and
When the coercive voltage of the ferroelectric memory cell is Vc, the selection voltage to the ferroelectric memory cell (the same polarity as the coercive voltage) is Vs, and Vs−Vc = ΔV, the imprint test is performed. Determining whether or not ΔV ≦ Vc is satisfied;
A method for inspecting a simple matrix ferroelectric memory device. In claim 23,
An inspection method for a simple matrix ferroelectric memory device, further comprising a determination step of determining whether or not | Vs |> | Vc | is satisfied in the imprint test.