JP2005049358A - Electronic calibrating apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and a method for calibrating a VNA. <P>SOLUTION: This apparatus/method is provided with a network analyzer having at least two ports of the first port and the second port, and a multi-state transfer standard having at least one port. The one port of the multi-state transfer standard is interfaced to the one port of the network analyzer, a plurality of states is generated by the one port of the multi-state transfer standard, the plurality of states is measured by the network analyzer, and a calibration factor is drawn out based on a measured result therein. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention automatically generates multiple complex reflection coefficients, low-loss transmission coefficients, and high isolation conditions at the network analyzer port. It relates to a method and a device.

  Measurement errors in any vector network analyzer (VNA) affect the device uncertainty measured by that VNA. By quantifying these errors, their effects can be significantly reduced.

  Measurement errors in network analyzers can be divided into two categories: random errors and systematic errors. Random errors are non-repeatable measurement changes due to physical changes (eg noise or temperature changes) and are therefore not usually predictable. Systematic errors are repeatable measurement changes in the test equipment itself (eg, directivity, source match, etc.).

  In most measurements made on a “device under test” (DUT) (or device under test) in a VNA, systematic errors are the most important source of measurement uncertainty. Therefore, it is desirable to remove these errors from the VNA measurement. This is achieved through calibration of the VNA.

  In the prior art, it is known to connect several known physical standards (known as mechanical primary standards) to each of the two ports of the VNA for calibration purposes. ing. The electrical properties of a mechanical primary standard are derived from the standard's known physical properties (eg, physical dimensions, conductor material, etc.). The systematic error of the VNA can be determined by calculating the difference between the response measured with the mechanical primary standard VNA and the known electrical properties of the mechanical primary standard.

  However, the calibration performance should be checked for accuracy before measuring the DUT. Therefore, in the prior art, it has been common to check the accuracy of calibration by connecting another primary standard (verification standard) different from the calibration standard to the VNA. If the VNA is properly calibrated, the measurement of the verification standard approximately matches the known electrical characteristics of the verification standard. However, if the measurement of the verification standard does not follow the known electrical characteristics of the verification standard, the operator knows that the calibration has not been performed properly or that the VNA is not functioning properly.

  Once the verification of the VNA calibration is complete, the operator can then connect an uncharacterized DUT to the VNA for measurement. The systematic error of the measurement system can then be mathematically removed from the DUT measurement.

  The two-port DUT being measured can have any of the three possible configurations of connectors at the two ports. An “insertable” device has two connectors, which are the same kind of connectors and different sexes. That is, one connector is a male and one connector is a female. During calibration, by connecting the two ports of the VNA with the help of a cable, it is possible to establish a through connection and without having to change the configuration of the measuring device for the actual measurement of the DUT An insertable 2-port VNA is configured so that calibration can be performed.

  In contrast, the measured reversible DUT is characterized by two connectors of the same kind of the same sex (both male or both female). A reversible DUT is not “insertable” (eg, “non-insertable”). This is because, without a first adapter, the two ports of the VNA cannot be connected together to establish a feedthrough connection during calibration. However, the disadvantage of this device is that the adapter becomes part of the calibration measurement. Therefore, it is common to calibrate the VNA with a first adapter that has the same electrical characteristics as the second adapter, then switch the first adapter to the second adapter, and then perform the actual DUT measurement. Is a habit. This technique is used to test and reduce measurement uncertainty. However, if the adapter insertion loss, amplitude and phase matching, and electrical length are not equal, an error will be added during calibration. That is, any change in characteristics between these adapters increases the uncertainty in the measurement of the DUT. There is also a second non-insertable calibration technique known in the field as “adapter-removal”, which is more accurate than the “adapter-swap” method described above. This is shown in FIGS. 2 and 3 and is described below.

  The second category of “non-insertable” DUTs is a transitional device with two different types of connectors (eg, one connector is coaxial and the other connector is a waveguide). Is provided. As with reversible DUTs, a drawback to measurements made on transitional DUTs is that the DUT cannot be inserted into a measurement system that uses the same configuration used to calibrate the measurement system.

  As explained above, to determine the error factor for a given error model of a VNA, use a calibration kit that includes a set of three mechanical primary standards for the appropriate connector type and sex. Is common. These primary standards usually consist of shorted connectors, shielded open connectors, and matched load terminations, either fixed or sliding. The fixed and sliding load is generally a mechanical transfer standard. The calibration kit also typically includes a number of phase matched adapters for use in the “adapter replacement” calibration method of a non-insertable DUT as described above.

  A full two-port calibration using a 12-term error correction model to determine systematic errors in the VNA is the most comprehensive calibration procedure. In order to determine all 12 terms of the error correction model for the insertable DUT being measured, each of the three primary measurement standards for appropriate sex must be connected to the appropriate VNA port and measured. Furthermore, the two measurement ports of the VNA must be connected together using a “through” connection.

  The calibration equipment for the insertable device and the necessary connections to the primary standard are shown in FIGS. In other words, the insertable device must have a minimum of six 1-ports (short-circuited, open-circuited) that are subsequently connected to and measured at ports 114, 116 of the VNA 112 (three for each port) to determine the 12 terms of the error correction model. , Load) calibration standards 100, 102, 104, 106, 108, 110 and one feedthrough connection (B in FIG. 1).

  In addition, non-insertable devices have an adapter 144 with the same DUT and port being measured and each having the same sex connector, and a primary standard on the VNA port as shown in FIGS. You need to be connected. That is, this technique allows a minimum of 12 primary standards 120, 122, 124, 126, 128, 130 (A in FIG. 2) and 132, 134, 136, 138, 140, 142 (A in FIG. 3) to be VNA. It needs to be connected to ports 114 and 116 to be measured. Furthermore, in order to perform a full 2-port calibration, two feedthrough connections must be established (B in FIG. 2 and B in FIG. 3). That is, referring to FIGS. 2 and 3, this technique requires that an adapter 144 be alternately connected to each port 114 and 116 of the VNA 112 and that a full two-port calibration be performed using an appropriate primary standard. To do. Next, to calculate the adapter's actual S-parameters, two calibration sets are generated and used with the adapter's known electrical length, and the actual S-parameters are (like VNA port 1 and port Used to create a calibration set without an adapter (as if the two were actually connected together). That is, a non-insertable full two-port calibration requires a minimum of 12 primary standard connections and measurements and two through connections and measurements. However, since the two through connections shown in FIG. 2B and FIG. 3B can be performed in succession, the number of through connections can be reduced to one.

  In addition, sliding terminations are typically used instead of matched load terminations for more accurate calibration. The disadvantage of the sliding end is that the measurement should be performed at at least three slide positions in order to obtain a reliable measurement. Furthermore, it is common in practice to use five slide positions for the measurement of matched loads at each port, thus resulting in a total of ten matched load position measurements. That is, a minimum of 18 measurements and 7 connections are standard for broadband calibration of insertable DUTs, and a minimum of 36 measurements and 13 connections are standard for non-insertable calibrations.

  The disadvantage of the above calibration procedure is that each calibration standard must be connected and measured one at a time. This procedure involves connecting the standard to the VNA port using the appropriate hardware to ensure proper connection and, once the proper connection is made, the appropriate hardware of the VNA to make the appropriate measurements. Pressing the wear key. Furthermore, once a measurement is taken, that standard must be disconnected and another standard must be connected in the same procedure. As explained above, this procedure is repeated for a minimum of 7 connections and 18 measurements with a broadband insertable DUT, and a minimum of 13 connections and 36 measurements to measure a broadband non-insertable DUT. Is repeated. In addition, the electrical length of the adapter must be known in order to use the “adapter removal” method. Or, an equally matched adapter must be used to use the “adapter replacement” method.

  As a further disadvantage, an untrained operator may mistake the standard (standard appearance is similar) and may operate the wrong hardware key on the VNA to measure the wrong calibration standard. unknown. If a mistake is found at the end of the proofreading, the entire proofreading must be redone. Also, if the calibration is not confirmed by the operator through the use of a verification standard after a full two-port calibration, the operator typically has an invalid calibration or an incorrect DUT measurement. I don't know that.

  In addition, the continuous connection and disconnection of the calibration standard required by the calibration procedure will cause the connectors and port cables to wear, thus resulting in non-repetitiveness in the measurement of the calibration standard. This non-repetitiveness in the measurement gives an additional error term to the calibration measurement that cannot be corrected.

  A further disadvantage of the prior art calibration method is that the manual calibration procedure is cumbersome and slow. That is, a large portion of valuable test time is used daily to calibrate the VNA. If the calibration is not done correctly, the operator must try again. Furthermore, depending on the application, the troublesome calibration is accommodated by the fact that the VNA should be recalibrated at least once a day to ensure proper measurement accuracy.

  Accordingly, it is an object of the present invention to provide a method and apparatus for calibrating a VNA that, at best, requires two connections of the apparatus to any port of the VNA. It is a further object of the present invention to essentially eliminate any errors resulting from connecting the wrong calibration standard to the VNA, and to allow easy calibration of the VNA without training and to perform the calibration. It is an object of the present invention to provide a method and apparatus for reducing the time required for Calibration according to the method and apparatus of the present invention can be performed automatically.

  The present invention relates to a method and apparatus for providing a programmable, wideband, high stability, repeatable multi-state electronic transfer standard for use in determining network analyzer systematic errors.

  In a first embodiment, the multistate electronic transfer standard consists of a plurality of semiconductor switching devices interconnected through transmission lines. Each semiconductor device can be forward-biased or reverse-biased by a programmable control circuit. Thus, a number of known reflection coefficients are generated at each port of the multi-state electronic transfer standard by a selected semiconductor device that is forward biased or reverse biased through a programmable control circuit. Furthermore, all semiconductors can be reverse-biased so that the multi-state electronic transfer standard provides a low loss transparent feedthrough between the ports of the multi-state electronic transfer standard. In addition, high isolation between ports of the multi-state electronic transfer standard can be obtained by simultaneously forward biasing some or all of the semiconductor devices.

  A programmable multi-state electronic transfer standard may be connected to at least one port of the network analyzer to provide a plurality of complex impedances to the at least one port of the network analyzer. These known impedances can be used as calibration standards for at least one port of the network analyzer for one-port calibration. In addition, full two-port calibration uses a multi-state electronic transfer standard to provide multiple known complex impedances to each port of the network analyzer, and a low loss transmission through connection to the network analyzer. This can be done by providing between two ports and providing a high isolation between the two ports.

  The above and other objects and advantages of the present invention will become more apparent by referring to the following detailed description of the preferred embodiments and the drawings.

  FIG. 4 shows a measuring device according to a preferred embodiment that can be used in the present invention to calibrate the VNA. The apparatus includes a VNA 12, a two-port multistate electronic transfer standard (MSETS) 14 according to the present invention, and a computer controller 16. The computer controller 16 receives data from the VNA 12 and receives data from the VNA 12 to control the VNA 12 with the assistance of software stored in the local or permanent memory area 20 of the computer 16. -Includes line 18. The measurement device also includes a control line 22 between the interface 23 and the MSETS 14, thereby allowing the computer or VNA to control the MSETS according to control software stored in the computer's memory. In addition, the computer controller 16 includes a keyboard interface 24 for interacting with the operator. Although the computer controller 16 is shown in this embodiment, the computer functionality can be incorporated into the VNA 12 or can be incorporated into a microprocessor or other hardware and software device provided directly to the MSETS 14. Please note that.

  FIG. 5 is a diagram of the microwave circuit 25 included in the MSETS 14 of the present invention. This circuit is of the type disclosed in Applicant's US Pat. No. 5,034,708 relating to a broadband programmable electronic tuner. The teachings of this patent are hereby incorporated by reference. Microwave circuit 25 includes several pairs of PIN diodes D1-D16 and DC blocking capacitors C4-C19, each in series, which are various lengths of microstrip transmission lines T1-T17 according to this embodiment. Have been separated by. The combination of capacitors C4-C19 and PIN diodes D1-D16 in series is shunted to ground 27. DC blocking capacitors C4-C19 establish the RF connection on the cathode side of each diode D1-D16 to ground. In the preferred embodiment of the present invention, the transmission lines T1-T17 are made from a known dielectric substrate that is 10 mil thick (about 0.25 mm) and laminated with copper on both sides. Sides are etched to appropriate dimensions. Although such a transmission line is used, according to the present invention, the use of an equivalent type of transmission line that establishes a given electrical length is also contemplated. Similarly, although PIN diodes are used, the use of other types of switching semiconductor devices is also contemplated.

  Referring to FIG. 5, a DC bias current is constantly established at connection J0. This current is established by a +5 volt supply, according to a preferred embodiment. This DC bias current is supplied to the anode side of any PIN diode D1-D16 through an RF bypass network that includes an RF coil inductor L1 and an RF shunt capacitor C2. The RF bypass network prevents the interaction of RF and DC signals. Any PIN diode D1-D16 can be forward biased by providing a DC current return path to the cathode side of that diode via any of the control line connections J1-J16. By individually controlling the control line connections J1 to J16, any of the corresponding diodes D1 to D16 can be forward biased or reverse biased. Each connection of the control line also includes an RF bypass circuit including RF coils L2-L17 and shunt RF capacitors C20-C35 in series that interfere with the interaction between the RF signal and the DC bias signal.

  In FIG. 5, DC blocking capacitors C1 and C3 placed in series with the RF transmission line at the input of port 1 and port 2 allow the DC bias signal used to bias the PIN diode to exit the 2-port MSETS. Disturb.

  MSETS allows a number of states established across a wide frequency band on both its ports 1 and 2. These states include presenting multiple complex impedances at each port, low loss feedthrough connections between ports, and high isolation states. Furthermore, the length and width of the transmission lines T2-T16 are selected to ensure a unique phase relationship between each of the PIN diodes D1-D16. The selection of the electrical length of the transmission line is based on the prime number principle described in Applicant's US Pat. No. 5,034,708, which is incorporated herein by reference. This principle provides for minimizing the repetition of impedance values at any port of the MSETS. That is, by using a prime number relationship, the total length from any input port of MSETS to each diode is not evenly divisible by the line length from that input port to any other diode. ,to be certain. However, other length relationships may be used in accordance with the present invention.

  In FIG. 5, the microwave circuit allows a plurality of microwave impedances extending across the complex reflecting surface to be provided at both ports of the MSETS by controlling the signals appearing on the control lines J1-J16. . For example, it can also be considered that the microwave circuit is a symmetric circuit consisting of two equal circuits. Circuit 1 includes transmission lines T2-T8 and corresponding shunt PIN diodes D1-D8 and series capacitor C4-C10 pairs between the transmission lines. Circuit 2 includes transmission lines T10-T16 and corresponding shunt PIN diodes D9-D16 and series capacitors C12-C19 pairs. These two circuits are coupled by a DC current source connection J0 and a transmission line T9 that is supplied with current by an RF bypass network. This circuit is designed so that the transmission lines T2 to T8 and T10 to T16 are symmetrical about the transmission line T9. Accordingly, transmission line length T2 is equal to transmission line length T16, T3 is equal to T15, T4 is equal to T14, T5 is equal to T13, T6 is equal to T12, T7 is equal to T11, and T8 is equal to T10. According to this embodiment, the length of the transmission line T9 is port 1 for the situation where each diode is alternately forward biased and the electrical length is measured at the lowest frequency of operation desired. Is selected such that the phase between the round trip electrical length from port 1 to PIN diode D1 and the round trip electrical length from port 1 to PIN diode D14 is a minimum of 240 degrees. Similarly, the same phase relationship exists at the lowest frequency of operation when diodes D3 and D16 are forward biased one at a time and the connection is made to port 2.

  In FIG. 5, the PIN diode can be operated in one of two states. In the forward bias condition, the PIN diode acts as a very small resistance (substantially a short circuit). In the reverse bias condition, the PIN diode can be modeled as a very small capacitor at the RF frequency and therefore has a very high impedance (substantially open). Establishing a DC ground connection to any of the control lines J1-J16 ensures that the appropriate diode is forward biased. Also, any of the control lines J1-J16 can be set to a positive voltage substantially greater than the voltage at port J0 so that the appropriate PIN diode is reverse biased. That is, it is possible to give several different impedances to any port of the MSETS. In addition, when all control lines are connected to DC ground and all PIN diodes are forward biased, the 2-port MSETS provides a significant amount of isolation between port 1 and port 2. Acts as an attenuator. In contrast, when all control lines are set to a positive voltage and all PIN diodes D1-D16 are reverse biased, the 2-port MSETS acts as a low loss feedthrough between port 1 and port 2 .

  In the preferred embodiment, each capacitor C1-C3 has a capacitance of 200 pF, C4-C9 has a capacitance of 100 pF, and C20-C35 has a capacitor of 820 pF. Each inductor has an inductance of 40 nH. Each transmission line has a width of about 0.762 mm (0.030 ″), T1 = T17 = about 1.55 mm (0.061 ″), T2 = T16 = about 0.89 mm (0.035 ″), T3 = T15 = about 0.99 mm (0.039 ″), T4 = T14 = about 0.89 mm (0.035 ″), T5 = T13 = about 0.99 mm (0.039 ″), T6 = T12 = about 0.8. 89 mm (0.035 ″), T7 = T11 = about 5.44 mm (0.214 ″), T8 = T10 = about 6.17 mm (0.243 ″), T9 = 15.9 mm (0.627 ″) Has a physical length. Each diode has a circumference of about 0.38 mm x about 0.38 mm x about 0.127 mm (0.015 "x 0.015" x 0.005 "), a resistance of 2 ohms and a junction capacitance of 0.1 pF. Have.

FIG. 6 is a diagram of the digital circuit 29 included in the MSETS. The digital circuit 29 provides an appropriate bias to the control ports J1 to J16 according to the control signal 23 received from the computer. The computer control signal 23 is received by three commercially available Darlington transistor arrays U1, U2, and U7 (SN75468). Darlington transistor arrays U1, U2 and U7 are configured to receive a 16-bit TTL signal output by a computer. This word is transmitted on signal lines B0-B15 to pins 1-7 of U1, pins 1-7 of U2, and pins 1-2 of U7, respectively. Pins 8 of U1, U2 and U7 are connected to ground 27. A TTL logic high on any of input lines B0-B15 causes the corresponding output of Darlington array U1, U2 or U7 to provide a DC ground signal to the corresponding output control line B0 ₁ -B15 ₁ . The output control lines B0 _{1 to} B6 ₁ are connected to the respective pins 16 to ₁₀ of U1, B7 _{1 to} B13 ₁ are connected to the respective pins 16 to ₁₀ of U2, and B14 ₁ and B15 ₁ are the respective pins of U7. Connected to pins 16 and 15. Input of TTL logic low to any of the input ports of the Darlington array, without the output of the corresponding Darlington array enable, therefore, the signal level of the corresponding control lines B0 ₁ ~B15 ₁ is +50 volts Pulled up and this is applied to the control line of the corresponding PIN diode.

In FIG. 6, a pair of 68 ohm resistor networks U3 and U4 are arranged between the output control lines B0 _{1 to} B15 _{1 of} the Darlington arrays U1, U2 and U7 and the corresponding output control lines B0 _{2 to} B15 _2. , Used to limit the current that can be drawn by each diode. Further, according to this embodiment, is provided a pair of 1 megohm resistor network U5 and U6, placed at the output B0 ₂ ~B15 ₂ of 68 ohm resistor networks, they are in series with bias supply unit 33 of the +50 volt ing. The voltage supply 33 and the resistor networks U5 and U6 serve as a pull-up network for each output control not selected by the incoming TTL signal, and thus each control line for the PIN diode for which no strong reverse bias signal is selected. Ensure that J1-J16 is maintained.

  FIG. 7 is a two-port, twelve-term error correction model 35 that can be used to model systematic errors in conventional VNA devices. Reference numerals in FIG. 7 will be described. M represents the measurement made by the VNA being calibrated. A represents the actual measurement made by the VNA in a metrology laboratory. F represents a measurement in the forward direction (see 2 port MSETS from port 1) and R represents a measurement in the reverse direction (see 2 port MSETS from port 2).

  As is known in the art, several known primary standard connections to the VNA ports are required to determine the error factor of the error correction model. According to one embodiment of the present invention, only one connection to each port of the VNA is required. Such a connection is typically made to both ports simultaneously. Thereafter, the MSETS and computer controller provide several transfer standards whose characteristics are known from previous measurements to the ports of the VNA. Transfer standards include multiple impedances, low loss feedthrough connections, and high isolation connections between VNA ports. The transfer standard is measured by the VNA, compared to previous measurements of this standard, and then the error coefficient of the 12-term error model is calculated.

  Further in accordance with the present invention, the accuracy of the calibration is increased, where the number of impedances applied to both ports of the MSETS is greater than the number of impedances required to calculate the coefficients of the unknown error model. Many more impedance measurements can therefore be used to improve the accuracy of the calculated coefficients. In addition, since only one connection to the VNA port is required, any random errors associated with calibration are substantially reduced. That is, by using the present invention, it is possible to reduce random errors and systematic errors in calibration, and to improve the accuracy of DUT measurement.

  Furthermore, the present invention increases the speed of calibration, where a minimum number of connections can be made between MSETS and VNA, and the computer control program automatically performs calibration without requiring operator input. Control. A further advantage of the present invention is that any type of connector of the DUT being characterized (eg, insertable, non-insertable) can be accommodated by the present invention without changing the accuracy of the calibration. This can be accomplished by providing MSETS with a male connector at the first port and a female connector of the same type of connector at the second port, so as to provide an insertable MSETS. This insertable MSETS is then supplied with a male-to-male and female-to-female connector as part of a complete calibration kit, so that all DUTs to be measured Allow for possible insertable and non-insertable connector possibilities. The MSETS can also be customized with any connector sex and type for each of its ports.

  A further advantage of the MSETS of the present invention is that following calibration, there is no need to connect to or disconnect from further VNAs to check that calibration was performed correctly and to ensure calibration accuracy. In order to do this, a verification standard can be given to the VNA. Furthermore, the limited connection between the computer controller and MSETS and the VNA substantially eliminates the possibility of human error in calibration.

  With reference to FIGS. 5 and 8, the method in which all 12 terms, error coefficients of FIG. 7 are determined will now be described. When the DUT being measured is an insertable device, it is shown in FIG. 8 with a male connector 120 at one port (port 2) and a female connector 122 of the same type of connector at the second port (port 1). The inserted insertable MSETS is connected to the appropriate port of the VNA. Note that FIG. 8 is provided as an example, and the possible connector placement of the insertable MSETS and VNA can be reversed. For example, an insertable MSETS can be provided with a male connector at port 1 and a female connector at port 2.

First, a 16-bit digital word is input to the digital circuit of FIG. 6 and PIN diodes D15 and D16 are forward biased, thereby effectively providing a short-circuit impedance at port 2 of the insertable MSETS and port 2 Is isolated from port 1 of the insertable MSETS. Equation 1 is derived from the flow graph analysis of the 2-port, 12-term error correction model 35 of FIG. 7 to solve for the measured reflection coefficient at port 1 (S _11M ). In Equation 1, the terms S _11A , S _22A , S _21A , S _12A are the actual scattering parameters given by the insertable MSETS and measured in the metrology laboratory using VNA.

Here, a _{Det [SA] = S 11A S} 22A -S 21A S 12A.
From Equation 1, it is clear that Equation 1 becomes Equation 2 under the condition of S _21A = S _12A = 0.

This condition is achieved in particular by forward biasing diodes D15 and D16 as described above, and port 2 is isolated from port 1. In Equation 2, the coefficient S _11A is measured by the VNA in the metrology lab for various impedances provided at port 1 (when diodes D15 and D16 and at least one of the other diodes D1-D14 are “on”). Represents a predetermined reflection coefficient. Thus, by providing and measuring at least three known impedances at port 1, the three error terms in equation 2, forward directional EDF, forward reflection tracking ERF and forward source matched ESF can be solved mathematically. In addition, by measuring more than three impedances at port 1 and performing a hermitian least sum square fitting algorithm on more determined sets of equations than necessary, Improved accuracy in calculations can be achieved.

Since the circuit of FIG. 5 is symmetric, the same steps can be used at port 2. Equation 3 represents the measured reflection coefficient S _22M of the insertable MSETS derived from the error model of FIG. 7 using flow graph analysis at port 2 of the insertable MSETS.

By forward biasing PIN diodes D1 and D2 at port 1 of insertable MSETS, port 1 is isolated from port 2 of insertable MSETS. As can be seen from Equation 3, if S _21A = S _12A = 0, Equation 3 becomes Equation 4.

  Several predetermined impedances can be provided at port 2 by forward biasing diodes D1 and D2 and at least one of diodes D3-D16. These impedances are measured and can be used to calculate the three error terms of Equation 4, reverse directional EDR, reverse reflection tracking ERR, and reverse source matching ESR. Furthermore, as explained above, by measuring more than three known impedances and using a least sum square fitting algorithm, the accuracy of the calculated error term can be improved.

  Equations 5 and 6 represent the forward direction (see MSETS insertable from port 1) and reverse direction (see MSETS insertable from port 2) derived using the flow graph analysis technique in the two-port error correction model of FIG. Represents the measured transmission coefficient.

If S _21A = 0, Expression 5 becomes Expression 7 as is apparent from Expression 5 and Expression 6.

Similarly, it is clear from Equation 6 that if S _12A = 0, then Equation 6 becomes Equation 8.

These states S _12A = S _21A = 0 are achieved by forward biasing all of the PIN diodes D1-D16, and a large value of attenuation exists between port 1 and port 2 of the insertable MSETS.

By measuring the transmission coefficients S _21M and S _12M (see Equations 7 and 8) when all of the diodes D1-D16 are forward biased, the error term, forward separation EXF and reverse separation EXR can be calculated. .

Referring to the 12-term error correction model of FIG. 7, the scattering coefficients S _11A , S _21A , S _22A and S _12A are known measured in a metrology laboratory during the original characterization of the insertable MSETS. Scattering coefficient. In one measurement, these values are measured for a state in which all of the PIN diodes D1-D16 are reverse biased. The one-port error term for port 1 and port 2 was previously determined by the steps described above by measuring impedance at port 1 and port 2, where all PIN diodes are reverse biased. Thus, error terms, forward load match ELF and reverse load match ELR can be calculated from Equation 9 and Equation 10.

  In addition, when PIN diodes D1-D16 are reverse biased, measure the feedthrough from port 1 to port 2 using the signal source at port 1, and instead use the signal source at port 2 to port By measuring the feedthrough from 1 to port 2, the error term, forward transmission tracking ETF and reverse transmission tracking ETR can be calculated from equations 11 and 12.

  That is, all twelve error coefficients of the two-port error model of FIG. 7 use the steps described above, with a single connection for each port of the MSETS that can be inserted into each port of the network analyzer, It can be calculated without human intervention.

  In addition, upon completion of the calibration described above, the insertable MSETS can then be used as a verification standard for the purpose of checking the accuracy of the calibration, as well as known transmission coefficients and previously not given during the calibration procedure. It can be used to simulate the reflection coefficient. This is done immediately after calibration with the aid of software and without the need for further connection or disconnection of the insertable MSETS and without the need for human intervention. Once the insertable calibration is verified, the 2-port insertable MSETS is then removed and the insertable DUT is connected for measurement.

  When the DUT being measured is a non-insertable device, the insertable MSETS is used in conjunction with an adapter for VNA calibration. This adapter is necessary (similar to the adapters 144 in FIGS. 2A and 3B and in FIGS. 3A and 3B). This is because this device is not insertable and therefore the two ports of the VNA cannot be directly connected together with the help of a cable without an adapter. Also, a custom MSETS with the last name and type of connector required by the user at each port can be made and supplied. Next, as explained above, the error factor of the VNA is determined using the previously characterized custom MSETS and Equations 1-12.

  As explained above, the provided kit controls an insertable MSETS, a male-to-mqle connector, a female-to-female connector, and MSETS and VNA. Together with a non-insertable MSETS kit. In the method described below, the adapter used with the insertable MSETS is selected such that its connector is a replica of the shape of the connector of the DUT being measured.

  Referring to FIG. 9, an example of a VNA device is shown in which the DUT being measured has female connectors on both of its ports. In order for the VNA to couple with the non-insertable DUT, both connectors 124 and 126 of the VNA port must be male connectors. Similarly, referring to FIG. 9B, a corresponding VNA device is shown, in which the measured DUT has male connectors on both its ports. Thus, the connectors 124 and 126 of both the port 1 and port 2 of the VNA are formed into female connectors.

  A method for calibrating the VNA for the non-insertable DUT being measured will now be described. Referring to FIG. 10A, a calibration apparatus according to the first step of the method is shown. An insertable MSETS port that is associated with the selected port of the VNA is connected to the selected port. In FIG. 10A, the selected port of the VNA is shown as port 2 (116), however, the selected port may be port 1 (114). If the same port is always used, the port is simply selected for standardization in that one routine is developed by the operator. Next, as shown in FIG. 10A, the insertable MSETS is formed to operate in a 1-port mode so as to provide the VNA with a plurality of known reflection coefficients at the reference plane A. The operation in 1-port mode is equivalent to the operation described above with respect to Equations 2 and 4. Thus, several diodes of the insertable MSETS are forward biased and their impedances are measured by providing some predetermined impedances at port 2 of the VNA, and the error terms EDR, ERR of Equation 4 , Used to calculate ESR.

  Referring to FIG. 10B, the insertable MSETS is then disconnected from the VNA at the reference plane A and redirected to connect to the VNA at the reference plane C (port 1) of the VNA. Also, an adapter 128 having the same sex connectors 130 and 132 as the DUT being measured is inserted between the insertable MSETS network and port 2 of the VNA. That is, as shown in FIG. 10B, the cascaded circuit of insertable MSETS 14 and adapter 128 forms a non-insertable MSETS. Note that although a female-to-female adapter is shown as an example in FIG. 10B, this is an example for the case where the DUT has female connectors on both its ports. Also, if the DUT has male connectors on both ports, the adapter can also have male connectors on both ports, and the VNA has female connectors 124 and 126 on both ports. Can do.

Next, in the first step of the method described above, the adapter's scattering parameters are known for the insertable MSETS reflection coefficient at the reference plane B, known from previous measurements in the MSETS metrology laboratory, Calculated from the one-port error correction factor determined from the measurement of insertable MSETS at reference plane A. In other words, the scattering parameters of the adapter are determined using the following steps. As described with respect to Equations 2 and 4, the insertable MSETS is operated in one-port mode, where a known reflection coefficient at the reference plane B is given by MSETS and at the reference plane A they are by VNA. Measured. The reflection coefficient S ₂₂ ′ measured by the VNA at the reference plane A with a known reflection coefficient given by the insertable MSETS at the reference plane B is expressed as:

Here, S _11A , S _21A , S _12A and S _22A are the scattering coefficients of the adapter, and Γ _B is a known reflection coefficient of the insertable MSETS. S _11A , S _22A , S _21A , S _12A can be determined by measuring at least three reflection coefficients S ₂₂ ′ given by the insertable MSETS at the reference plane A for three known reflection coefficients Γ _B. . S _21A equals S _{12A due} to reciprocity of the adapter.

Reference is made to Equation 13. The product of S _21A × S _12A is represented by W. Given the reciprocal nature of the connector, S _21A = S _12A = (W) ^1/2 . However, W is a complex number, so its square root can have two values. There, both values have the same magnitude, but the angles are 180 degrees out of phase with each other. Therefore, W can be expressed by Equation 14 and Equation 15.

Here, | W | = the absolute value of W, and Θ = argument of W.
Therefore, a boundary condition is used to accurately determine the value of S _21A = S _12A . In order to choose the correct declination between Equations 14 and 15, a suitable boundary state is used that represents the phase of the coaxial connector in zero hertz. It is the prior art that all commercially available VNAs wrap a phase (deflection) between ± 180 degrees when the frequency is swept between the start and stop points. Are known. (That is, when the signal is not within the display range, the signal is displayed within the range of ± 180 degrees by wrapping the signal within the range of ± 180 degrees.) Cross with a frequency of ± 180 degrees By adding 360 degrees to the deflection angle as it is swept across the over point, the total phase relationship can be derived by unwrapping the deflection angle. ("Unwrap the declination" means "to derive the actual phase of the signal by subtracting the phase added to the signal to display the signal on the VNA from the signal.)" The unwrapped declination as a function of can be fitted to a polynomial as follows through a least sum square fitting algorithm.

Here, A _i = polynomial coefficient, and F = frequency.
It is also known that the phase angle of the coaxial connector must approach 0 degrees as the frequency approaches DC. Therefore, the phase expression term A ₀ for equations 14 and 15 must be selected as close to zero. That is, an appropriate value for the phase can be determined, and the adapter S-parameters can be calculated using Equation 13. Therefore, according to the present invention, it is possible to calculate the adapter's scattering parameters required for non-insertable calibration without knowing the electrical length of the adapter used as part of the calibration.

  In order to transfer the penetrating and verification scattering parameters of the insertable MSETS to the reference plane A, the adapter, the penetrating and verification scattering matrices are converted to a chain scattering matrix. This chain scattering matrix can be calculated using the following equation:

  The chain scatter matrix of insertable MSETS operating in the feedthrough state is converted to reference plane A by applying the chain matrix of insertable MSETS to the adapter's chain matrix. Similarly, the insertable MSETS chain scatter matrix operating in the verification mode is multiplied by the adapter chain scatter matrix to convert the verification state to the reference plane A. The resulting chain scattering matrix is then reconverted back into an S-parameter matrix using the following equation:

  Reference is made to FIG. Since the connector 122 of the insertable MSETS network is directly connected to the VNA port 1 (114), there is no need to convert the S-parameters provided by the insertable MSETS to the VNA port 1. Thus, the insertable MSETS S-parameters operating in one-port mode, pierce and verify states are now known at the VNA connectors 124 and 126. Next, the insertable MSETS steps the method for insertable calibration described above to determine the error correction factor for the non-insertable form as shown in FIG. 9A or B. It is operated to do. Thereafter, both the insertable MSETS and the adapter are removed and the non-insertable DUT to be measured is inserted for measurement. Thus, with the present invention, it is possible to calibrate a network analyzer for a non-insertable DUT to be measured with a minimum of two connections made to any one port of the network analyzer. In addition, all these steps are controlled by the computer, eliminating the possibility of user error. Furthermore, since the insertable MSETS simulates a verification standard, the accuracy of the non-insertable calibration is checked without having to disconnect or connect the verification standard. Further, non-insertable calibration is performed without the need to connect any primary calibration standard to the VNA.

  Please refer to FIG. A microwave circuit diagram included in the MSETS 14 'of the second embodiment of the present invention is shown. The second embodiment is used to extend the frequency of operation of MSETS. The second embodiment can be used in conjunction with the first embodiment shown in FIGS. 5 and 6 to create an ultra-wideband MSETS.

  The microwave circuit shown in FIG. 11 includes a plurality of single pole, multi-throw switches. For example, two single pole, four throw switches 134 and 136 are shown. The throws 138, 140, 142, 144 of the single pole four throw switch 134 and the throws 146, 148, 150, 152 of the single pole four throw switch 136 are connected to different impedances. For example, throws 138 and 146 are interconnected by a low loss feedthrough transmission line 154, throws 140 and 148 are connected to an open circuit, throws 142 and 150 are connected to a short circuit, and throws 144 and 152 are each a unipolar dual. Connected to poles 155 and 157 of throw switches 154 and 156. The throws 158 and 160 of the single pole double throw switch 154 and the throws 162 and 164 of the single pole double throw switch 156 are each connected to a fixed impedance. For example, throws 158 and 162 are interconnected by a 3 dB fixed attenuator, and throws 160 and 164 are each connected to a fixed 50 ohm aligned termination.

  In FIG. 11, DC blocking capacitors C1 and C2 are used to prevent the DC bias signal used to bias the single pole multiple throw switch from exiting MSETS, respectively, for input port 1 (170) and port 2 ( 172) in series with poles 166 and 168. The second embodiment of MSETS also allows multiple states to be established across the extended frequency band of operation at both port 1 (170) and port 2 (172). These states include providing multiple complex impedances at each port, including open, shorted, matched termination, and intermediate impedances including 3 dB attenuators. In addition, these states include low loss through connections between ports. A through connection can be established between port 1 and port 2 by connecting pole 166 to throw 138 and pole 168 to throw 146. Further, an open can be established between port 1 and port 2 by connecting pole 166 to throw 140 and pole 168 to throw 148. Furthermore, a short circuit can be established between port 1 and port 2 by connecting pole 166 to throw 142 and pole 168 to throw 150. In addition, by connecting pole 166 to throw 144, pole 155 to throw 160, pole 168 to throw 152, and pole 157 to throw 164, a matched termination at port 1 and port 2 is achieved. Can be given. Then, connect pole 166 to throw 144 and pole 155 to throw 158, or connect pole 168 to throw 152 and pole 157 to throw 162 to either port 1 or port 2 Impedance can be provided.

  FIG. 12 is a diagram showing a control circuit for controlling the microwave circuit of the second embodiment of MSETS. The control logic includes a number of addressable 8-bit latches 176 that are programmed to drive the single pole multiple throw switch of the circuit of FIG. 11 for any of the above combinations. The voltage output by the addressable latch is an input to the CMOS gate 178 and provides one of two voltages to each control line 182 of the single pole multiple throw switch of the circuit of FIG. For example, in the preferred embodiment of the present invention, the voltage applied to the control line of a single pole multiple throw switch is either 0 volts or -8 volts, and the slow of each switch is turned on and off, respectively. . Thus, when the CMOS gate is high, the NPN transistor 180 is biased on and the output voltage on the control line 182 is effectively connected to the -8 volt DC supply 184. Also, when the CMOS gate is low, the transistor is biased off and output 182 is connected to ground through resistor R1. In the preferred embodiment of the present invention, resistors R1, R2, and R3 are each 1.6K ohms.

  Accordingly, the circuits of FIGS. 11 and 12 include a second embodiment of MSETS according to the present invention. In order to calibrate the VNA for both the insertable and non-insertable DUT being measured, the second embodiment can be used in the same way as the first embodiment. Accordingly, the ultra-wideband calibration kit according to the present invention includes a first MSETS having a male connector at the first port and a female connector at the second port, a first connector having a male connector at the first port and a female connector at the second port. 2MSETS, a first adapter having a male connector at each of the ports, a second adapter having a female connector at each of the ports, and a software package for controlling each of the MSETS embodiments. .

In both of the methods described above, the scattering coefficients S _11A , S _21A , S _22A , S _12A are measured in the metrology lab for all possible states given by MSETS during the original characterization of MSETS. Must be measured. However, to calculate the VNA's two-port systematic error, there is another way, described below, for which all these scattering coefficients need not be known for all states given by MSETS. In contrast, it is possible to first characterize only the three reflection coefficients given by MSETS to each port of the VNA and calculate all systematic error coefficients of the VNA.

  Reference is now made to FIG. VNA two-port errors can be modeled by scatter matrices 200 and 202. The variables for this error scatter matrix are described in Equation 19.

Here, e ₁ ⁰⁰ and e ₂ ⁰⁰ are the directivity of port 1 and port 2,
e ₁ ¹¹ and e ₂ ¹¹ are port 1 and port 2 source matching,
e ₁ ⁰¹ , e ₁ ¹⁰ , e ₂ ⁰¹ , e ₂ ¹⁰ are reflection tracking of port 1 and port 2.

The unmodified transmission matrix T _m for the MSETS penetration state and the transmission matrix T _A for the actual MSETS penetration state are given by Equation 20.

The transmission matrices T ₁ and T ₂ can be calculated from the three known reflection coefficients given by MSETS to each port of the VNA. The reciprocal of MSETS, transmission matrix T _A has a unitary matrix equation (unitary determinant). Thus, Equation 20 can be written as:

Using equation 16 and the boundary conditions described above, the correct value of K can be determined without having to know the electrical length of the feedthrough. The actual scattering matrix T _A of MSETS of operations in the through state, wherein can be calculated from Equation 22.

By defining P = T ₁ ⁻¹ T _m T ₂ , the actual scattering matrix (S _Thru ) of the feedthrough can be calculated from Equation 23.

  Thus, the VNA's two-port systematic error is calculated by giving only three known reflection coefficients to each port of the VNA by MSETS. To fully characterize a VNA's two-port systematic error, no additional knowledge (eg, about penetration) is required regarding the transmission or reflection coefficient of the MSETS given to the VNA. The advantage of this method is that only six measurements of MSETS need to be made in the metrology laboratory during the initial characterization of this MSETS by the operator. This reduces the number of measurements that need to be made and the number of data that needs to be stored. In addition, this method provides a simpler insertable and non-insertable calibration, thus providing a faster calibration process.

  The MSETS embodiment described above is used to calibrate a two-port VNA. However, the device 210 having a plurality of ports 214, 216, 218, 220, 222, 224 needs to be measured by the multiport network analyzer 112 'shown in FIG. Therefore, there is a need to characterize systematic errors of the multiport network analyzer 112 '(MNA). In FIG. 15, a block diagram of a multi-port multi-state electronic transfer standard 212 (MMETS) for calibrating MNA systematic errors is shown. The advantage of MMETS is that it is not necessary to connect multiple mechanical primary standards to each port 214, 216, 218, 220, 222, 224 of the MNA. Instead, a single connection is established between each of the MMETS ports 230, 232, 234, 236, 238, 240 and the MNA ports 214, 216, 218, 220, 222, 224. Can be done. Next, the MNA systematic error is determined by analyzing the MNA as a series of two-port VNAs.

  Referring now to FIG. 16, MNA two-port pair error matrices 242 and 244, 246 and 248, 250 and 252 are shown for determining MNA systematic errors. As explained above, in order to calculate all system errors of the MNA, each MNA port 214, 216, 218, 220, 222, 224 has three known reflection coefficients of the MMETS 212, ie, each It is only necessary to give a total of six known reflection coefficients for a two-port pair. Thus, any DUT with any number of ports can be measured by the MNA after calibrating the MNA with MMETS.

  In all the methods and examples described above, once the MSETS is measured on the VNA in a metrology laboratory, it is used as a calibration standard by other vector network analyzers. Therefore, it is desirable to continue to regenerate the MSETS at that port the same state as measured in the metrology laboratory.

  Thus, according to a specific embodiment of the present invention, a heater is provided in the MSETS to ensure long-term temperature stability of the electronic circuit of the present invention. According to a preferred embodiment, the temperature is fixed at 45 ° C. (not shown) using a heating element placed in a box or other enclosure for the circuit.

  A further feature of the present invention is that MSETS can be used to perform high power calibration of VNAs using the embodiments disclosed in pending application No. 07/898204, incorporated herein by reference. That is.

  According to the present invention, a further feature of MSETS is that MSETS can be used as a verification or trust device with other devices in addition to the VNA, since the features are known. For example, the device connects an insertable MSETS between a power source and a power meter, steps through the insertable MSETS through a plurality of known attenuation values, and a power meter reading is provided by the MSETS. Can be used to verify the accuracy of the power meter by reading the power meter to see if it reflects a change in power according to a known attenuation.

  Yet another application of the MSETS of the present invention is that MSETS can be used to monitor changes in any RF instrument usage over a period of time. For example, systematic errors in the VNA can be monitored over a period of time and used as an indication of VNA status. More specifically, the MSETS of the present invention may be used periodically to monitor VNA systematic errors, and whether VNA is experiencing any problems to monitor VNA operability. The calculated error coefficient can be statistically analyzed to detect. This data can be collected in many ways. For example, an operator can collect over a telephone line using a computer with a modem connected to MSETS, thus allowing the VNA to be monitored without having to be at the location where the VNA is located. The advantage of this feature is that VNA manufacturers can use MSETS as a diagnostic and preventive maintenance tool, thus allowing problems to be detected when problems occur and, for example, time is lost This is to minimize the down time of the VNA in the production line. Also, data collection need not be by a remote operator and can be done within the organization as part of a regular maintenance program.

  Referring to FIG. 17, a flowchart of a method for controlling and calibrating the VNA is shown. First, the user inputs a frequency for DUT measurement into the computer 16 as shown in FIG. 4 (step 28). The frequency is then correlated (step 30) with the previously measured frequency of the insertable calibration network to determine at the frequency at which the calibration is to be performed. Next, to perform calibration, the VNA is set up by loading its frequency into the VNA (step 32). Next, MSETS is measured according to the method described above (step 34). Once the measurement is complete, an error term for the error model is calculated (step 36). These error terms are then used to modify the appropriate frequency for the DUT being measured (step 38). The VNA is then restored to its initial state (step 40) and the MSETS can be disconnected and the DUT can be connected for measurement.

  In one embodiment, the control routine is provided by a computer 16 (FIG. 4) that is interconnected with insertable MSETS 14 and VNA 12. For example, a model 8510 Hewlett Packard network analyzer is used, and a computer is interconnected via line 18 to a standard port using an IEEE-488 standard connector. However, as explained above, control routines and computer functions can be incorporated directly into the 2-port MSETS 14 or provided separately to the VNA 12.

  Another application of the MSETS of the present invention is that it can be placed inside a VNA test set to derive a self-calibration circuit 48 for the VNA. Referring to FIG. 18, two essentially identical MSETS 50 and 52 are placed behind the VNA couplers 54, 55, 56, 57 to provide reflection coefficients for ports 1 and 2 of the VNA test set. Controlled. These MSETSs can also be arranged before the VNA couplers 54, 55, 56 and 57. In this embodiment, it is possible to calibrate two MSETS once and then use the two MSETS as a self-calibrating VNA. That is, it is possible to first characterize the self-calibrating VNA, and then thereafter each time the VNA is used, simply by making a through connection between port 1 and port 2 of the self-calibrating VNA. It is possible to self-calibrate the VNA.

  The self-calibrating VNA embodiment is particularly advantageous as a flexible network analyzer used to measure DUT on any medium that is particularly difficult to calibrate. For example, a self-calibrating VNA can be used to calibrate a VNA for on-wafer measurement. This is done by simply placing an on-wafer probe coupled to the port of the VNA in the penetration portion of the calibration standard and running the VNA through a self-calibration routine described below. That is, self-calibrating VNAs are used to eliminate the redundant, often very difficult work of calibrating VNAs for on-wafer and stationary measurements.

  Please refer to FIG. The initial calibration procedure for characterizing the self-calibrating VNA is done by performing calibration at the reference plane 58 of the device. This is done by reverse biasing all PIN diodes in each MSETS to establish a low loss condition through each MSETS. The signal from signal source 68 is then applied to port 1 by selecting the appropriate position of switch 62. The output MSETS PIN diode is forward biased to perform through the steps for different impedances. The resulting reflection coefficient from the various impedances provided by the output MSETS 52 is measured at the reference plane 58 of the device, thereby characterizing the output MSETS 52.

  Similarly, input MSETS 50 reverse biases all PIN diodes of output MSETS, switches the position of switch 62 to send an RF signal to port 2, and steps the PIN diode of input MSETS 50 through various impedances. Characterized by measuring the reflection coefficient at the reference plane 58 of the device.

  Once the self-calibrating VNA is first characterized by the calibration steps described above, the MSETS then need not connect and disconnect from the VNA port 1 or 2 multiple times. And without the need for human intervention, the steps can be advanced through various impedances according to the steps described below to self-calibrate the VNA. As initially characterized above, the steps of the self-calibration procedure for the self-calibrating VNA are as follows according to one embodiment.

(1) Establish a feedthrough connection between port 1 and port 2 of the VNA, and (2) measure the three impedances provided by the output MSETS 52, thereby causing errors in the directional EDF, source matched ESF and reflection tracking ERF. A term is determined at port 1 and (3) an error term is calculated based on these known initial values of impedance S _11A and using equation 2 described above.

  Next, (4) step the input MSETS through the various known impedances initially characterized, and use Equation 4 to calculate the error term as described above, thereby creating a reference plane for the device. By measuring the reflection coefficient given at 58, error terms for directional EDR, source matching ESR and reflection tracking ERR are determined at port 2.

Next, (5) reverse bias all the input MSETS and output MSETS PIN diodes, and determine the forward ELF and reverse ELR load matching error terms by using Equation 9 and Equation 10 described above. To do. In Equation 9 and Equation 10, S _11A = S _22A = 0 and S _21A = S _12A = 1. This is because there is now a through connection between VNA ports instead of MSETS.

Next, (6) measure the forward S _21M and reverse S _12M transmission coefficients with all PIN diodes in both MSETS reverse biased. Here, all parameters of Equation 11 and Equation 12 are known, except for forward separation EXF and reverse separation EXR. In this network analyzer technique, it is customary not to bother calculating the error terms EXF and EXR, nor to bother measuring the isolation state between port 1 and port 2 of the VNA. Thus, the terms EXF and EXR can be set to 0, and the forward transmission tracking ETF coefficient and the reverse transmission tracking ETR coefficient can be calculated using equations 11 and 12.

  Also, the measurement of isolation between port 1 and port 2 is done by breaking through connection between port 1 and port 2 and reverse biasing all PIN diodes at input MSETS and output MSETS. . The error terms EXF and EXR can then be calculated using Equations 7 and 8 previously described. Once the error terms EXF and EXR are known, the error terms ETF and ETR can be calculated using Equations 11 and 12. That is, all error terms can be calculated in the embodiment shown in FIG. Furthermore, the technique described above does not require another step because the cable connection between port 1 and port 2 should be broken in order to make a DUT measurement.

  FIG. 19 is another embodiment of a self-calibration circuit 60 for a VNA that can be utilized in the same manner as described above with respect to the embodiment of FIG. However, conventional calibration techniques are used using single pole, double throw switches 64 and 66 configured to connect VNA ports 1 and 2 to throws 63 and 65 connected to wiring 67 from signal source 68. The initial calibration used is different. Input MSETS 72 and output MSETS 70 are each connected to ground 27 via a matched termination R having a value of 50 ohms. Thereafter, a self-calibration routine is performed using the above steps. There, a single pole double throw switch is connected to the MSETS used to establish a known impedance. In other words, the throw 73 of the single pole double throw switch 62 is connected to the signal source 68 and the pole 65 of the single pole double throw switch 64 is connected to the output MSETS 70 (slow 75) to characterize the output MSETS network 70. To do. Similarly, switch 73 of single pole double throw switch 62 is connected to signal source 68 and pole 63 of single pole double throw switch 66 is connected to input MSETS 72 (slow 77) to characterize input MSETS 72. To. Thereafter, a self-calibration routine is performed using the steps described above with respect to the embodiment of FIG.

  While several embodiments of the present invention have been described above, it will be apparent to those skilled in the art that they are exemplary and not limiting of the present invention and are provided merely as examples. is there. Numerous modifications and other embodiments are within the scope of those skilled in the art and are considered to be within the scope of the present invention as defined by the claims of this application.

1A and 1B illustrate calibration of a vector network analyzer for an insertable device measured according to a prior art method. FIGS. 2A and 2B show calibration of a vector network analyzer for a non-insertable device measured using “adapter removal” technology at each of the two ports of the VNA according to prior art methods. FIG. FIGS. 3A and 3B show calibration of a vector network analyzer for a non-insertable device measured using “adapter removal” technology at each of the two ports of the VNA according to prior art methods. FIG. FIG. 4 is a diagram of a calibration system according to the present invention. FIG. 5 is a detailed diagram of one embodiment of the microwave portion of a multi-state electronic transfer standard according to the present invention. FIG. 6 is a detailed diagram of a digital control circuit for operating the circuit of the multi-state electronic transfer standard of FIG. FIG. 7 is a flow diagram of a 2-port 12-term error correction model used with the multi-state electronic transfer standard according to the present invention. FIG. 8 shows a connection to a multi-state electronic transfer standard, where the measured DUT is an insertable device. 9A and 9B show the connections made to the multi-state electronic transfer standard, where the measured DUT is a non-insertable device. FIGS. 10A and 10B show the connections made to the multi-state electronic transfer standard to calibrate the VNA for a non-insertable device in accordance with the present invention. FIG. 11 is a diagram showing a second embodiment of the multi-state electronic transfer standard of the present invention. FIG. 12 is a diagram of a control circuit for operating the multi-state electronic transfer standard of FIG. FIG. 13 is a diagram illustrating an error matrix associated with a VNA. FIG. 14 shows the connections to and between the multiport network analyzer and the multiport multistate electronic transfer standard. FIG. 15 is a block diagram of a multi-port multi-state electronic transfer standard. FIG. 16 is a diagram showing a plurality of 2-port error matrices constituting the multi-port VNA. FIG. 17 is a flowchart showing a computer control procedure for obtaining a calibration coefficient according to the present invention. FIG. 18 is a diagram of a self-calibrating VNA using a pair of multi-state electronic transfer standards according to the present invention. FIG. 19 is another embodiment of a self-calibrating VNA according to the present invention.

Explanation of symbols

12, 112 Vector network analyzer 14 Multi-state electronic transfer standard 16 Computer controller 18 Data line 20 Memory 22 Control line 23 Interface (FIG. 4), control signals (FIG. 6)
24 Keyboard 25 Microwave circuit 27 Ground 33 Bias supply 50, 72 Input MSETS
52, 70 output MSETS
58 Reference plane 60 Self-calibration circuit 62 Switch 63, 65, 155, 157, 166, 168 Switch pole 64, 66, 154, 156 Single pole double throw switch 67 Wiring 68 Signal source 73, 75, 77, 138, 140, 142, 144, 146, 148, 150, 152, 158, 160, 162, 164 Throw of switch 100, 102, 104, 106, 108, 110, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142 Calibration standards (Fig. 1, Fig. 2, Fig. 3)
112 'Multi-port network analyzer 114, 116 Vector network analyzer 112 port 120, 122, 124, 126, 130, 132 connector (FIGS. 8, 9, 10)
128, 144 Adapter 134, 136 Single Pole Four Throw Switch 154 Transmission Line 170, 172 Port 176 Addressable 8-bit Latch 178 CMOS Gate 180 NPN Transistor 182 Control Line 184 DC Source 200, 202 Scatter Matrix 210 Device 212 Multiport Multi State Electronic Transfer Standards 214, 216, 218, 220, 222, 224 Multi-Port Network Analyzer Ports 230, 232, 234, 236, 238, 240 Multi-Port Multi-State Electronic Transfer Standard Ports 242, 244, 246, 248, 250, 252 error matrix A, B, C reference plane B0~B15 signal line _{B0 1 ~B15 1, B0 2 ~B15} 2 output control lines C1, C2, C3, C4~ C19, C20-C35 Capacitor D1-D16 PIN diode J0 connection J1-J16 Control line connection L1 RF coil inductor L2-L17 RF coil R1, R2, R3 Resistance T1-T17 Microstrip transmission line U1, U2, U7 Darlington transistor Array U3, U4, U5, U6 resistance network

Claims (36)

A calibration device comprising at least a first port that can be coupled to a port of a network analyzer,
A multi-state transfer standard for generating a plurality of states to calibrate the network analyzer against at least one reference plane, wherein the plurality of states are any port of the network analyzer during a calibration procedure Generated without the restrictions of mechanical connection or disconnection of further calibration standards to,
Calibration device.   The calibration device according to claim 1, wherein the plurality of states includes a plurality of complex reflection coefficients provided to a first port of the network analyzer for performing a one-port calibration.   2. A calibration device according to claim 1, comprising a first port and a second port connectable to a first port and a second port of the network analyzer.   4. The calibration device of claim 3, wherein the multi-state transfer standard further comprises a plurality of switching devices.   5. The calibration device according to claim 4, further comprising a controller that biases a predetermined one of the plurality of switching devices to generate the plurality of states.   6. The calibration device according to claim 5, further comprising a processor that operates the controller in response to execution of a predetermined procedure, the processor taking measurements of the network analyzer based on each of the states. A calibration device that records and derives calibration coefficients for calibrating the network analyzer therefrom.   7. The calibration device according to claim 6, wherein the control device compares a recorded value with a measured value for at least some of the states, and the measured value is determined according to the multi-state transfer standard. A calibration device that is based on the predetermined state generated.   The calibration device according to claim 3, wherein the plurality of states include a plurality of complex reflection coefficients, a low loss transmission connection, and a high isolation state.   4. The calibration device according to claim 3, wherein the plurality of states include a plurality of complex reflection coefficients provided to the first port and the second port of the network analyzer for performing two-port calibration. Calibration device.   10. The calibration device according to claim 9, wherein the plurality of complex reflection coefficients for performing the two-port calibration are coupled to each of the first port and the second port of the network analyzer. Calibration device with complex reflection coefficient.   4. A calibration device according to claim 3, wherein the multi-state transfer standard comprises at least two single pole multiple throw switches, each slow is connected to a complex impedance, each pole forms a circuit termination, A calibration device, each of which is coupled to one of the first port and the second port of the multi-state transfer standard, respectively.   The calibration device according to claim 3, wherein the plurality of states further include a verification standard.   4. The calibration device according to claim 3, wherein the multi-state transfer standard further comprises a plurality of PIN diodes, each interconnected by a transmission line of a predetermined length, the first port and the first of the calibration device. Calibration device that forms two ports.   14. A calibration device according to claim 13, wherein each transmission line comprises a microstrip transmission line, each of the predetermined lengths of the transmission line being selected based on a prime number relationship, and each length of the transmission line. A calibration device that ensures that it cannot be divided exactly by the length of any other transmission line.   4. The calibration device of claim 3, wherein the calibration device is incorporated into a network analyzer calibration system, the network analyzer calibration system further comprising the network analyzer having the first port and the second port, A network analyzer is a calibration device that measures the plurality of states.   16. The calibration device of claim 15, further comprising a second multi-state transfer standard, wherein each of the multi-state transfer standard and the second multi-state transfer standard is the first port of the network analyzer, respectively. And each of the multi-state transfer standard and the second multi-state transfer standard provides a predetermined state to each of the first port and the second port, and A calibration device that allows the network analyzer to be continuously calibrated. A calibration device according to claim 16, comprising:
At least a first port of the multi-state transfer standard is permanently coupled to one of the first port and the second port of the network analyzer;
The second port of the multi-state transfer standard is permanently coupled to a matched load to provide a self-calibrating network analyzer;
Calibration device. A calibration device according to claim 17,
The second multi-state transfer standard includes a first port and a second port;
A first port of the second multi-state transfer standard is permanently coupled to one of the first port and the second port of the network analyzer;
The second port of the second multi-state transfer standard is permanently coupled to a matched load;
Calibration device. The calibration device according to claim 3,
A first adapter having a first port and a second port, each of the first port and the second port having a male connector, and having a first port and a second port, the first port and the second port; A calibration device in combination with a second adapter, each of the second ports having a female connector, comprising a calibration kit that calibrates both insertable and non-insertable devices.   4. The calibration device of claim 3, wherein each port of the multi-state transfer standard has a specified connector sex and type.   4. A calibration device according to claim 3, comprising more than two ports, each of the more than two ports being capable of being coupled to a corresponding port of a multiport vector network analyzer. device. A method for calibrating a network analyzer having at least a first port and a second port, comprising:
Using a multi-state transfer standard, at least one reference without being restricted by mechanical connection or disconnection of further calibration standards to either the first port or the second port of the network analyzer Generating a plurality of states to calibrate the network analyzer against a surface;
Measuring the plurality of states using the network analyzer;
Deriving calibration coefficients based on measurements of the plurality of states;
A method comprising:   23. The method of claim 22, further comprising interfacing at least one of the first port and the second port of the network analyzer with the multi-state transfer standard.   23. The method of claim 22, wherein the step of generating a plurality of states comprises biasing at least one of a plurality of switching devices.   24. The method of claim 22, wherein the step of generating a plurality of states comprises a plurality of one-port calibrations for at least one of the first port and the second port of the network analyzer. Generating a complex reflection coefficient.   23. The method of claim 22, wherein the step of generating a plurality of states comprises generating a plurality of complex reflection coefficients for performing a two-port calibration.   23. The method of claim 22, wherein the step of generating a plurality of states comprises providing a verification standard that verifies the accuracy of the calibration factor. 23. The method of claim 22, wherein the step of generating a plurality of states comprises
Multiple complex reflection coefficients,
Low loss transparent connection,
Generating a high separation state. 23. The method of claim 22, wherein the step of generating a plurality of states comprises
At least three known reflection coefficients;
Generating a known low loss transparent connection.   23. The method of claim 22, wherein the step of generating a plurality of states includes at least a step of multiplexing a calibration standard having a known complex impedance with at least a single pole multiple throw switch to at least one reference plane. Including the method.   23. The method of claim 22, wherein the steps of generating a plurality of states, measuring the plurality of states, and deriving a calibration factor are each performed at a plurality of predetermined times, and Analyzing the calibration factor to monitor changes in the network analyzer instrument.   32. The method of claim 31, wherein the step of analyzing the calibration factor analyzes the calibration factor to detect whether any problems exist in the instrument of the network analyzer. A method comprising steps.   32. The method of claim 31, wherein the step of analyzing the calibration factor comprises remotely monitoring a change in the calibration factor of the network analyzer to diagnose a problem in the network analyzer. Including. A method for calibrating a network analyzer having at least a first port and a second port, comprising:
Providing three known reflection coefficients to the first port and the second port;
Providing an unknown reciprocal penetration state for each of the first port and the second port; and using the network analyzer, measuring the three previously known reflection coefficients and the penetration state;
Evaluating the unwrapped phase of the penetration state;
Calculating a calibration factor for the network analyzer;
A method comprising: 35. The method of claim 34, wherein the step of evaluating the penetrating unwrapped phase comprises:
Unwrapping the network analyzer phase declination as a function of frequency to produce an unwrapped declination;
Applying the unwrapped declination to a polynomial;
Selecting the DC term of the polynomial closest to zero to produce a correct phase shift of the feedthrough state.   35. The method of claim 34, wherein the steps of providing three previously known reflection coefficients and the step of providing an unknown reciprocal penetration state are performed using a multi-state transfer standard.

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