JP2005041341A - Method for preparing interlocking logical data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new method for preparing interlocking logical data for an interlocking device, capable of preparing interlocking logic data using a connection diagram for relay interlocking as it is when a connection diagram for an electronic interlocking device is newly prepared based on a connection diagram for the relay interlocking device. <P>SOLUTION: In this method for preparing interlocking logical data for the interlocking device, the connection diagram for interlocking device for a railroad signal consisting of a group of relay circuits is inputted in a computer by an input device such as a mouse, graphic data obtained by this is converted into node information described by nodes which collectively displays branches and anode/cathode terminals, and segments between the nodes. Every current route reaching from an anode to a cathode is searched on the basis of the node information, and after the every current route obtained by this are modified by means of considering electric characteristics, logical conversion is performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of creating interlocking logical data that can be used as interlocking conditions for interlocking devices, particularly railway signal interlocking devices.

  In order to prevent collisions or derailments of trains, etc. at railway stops, etc., signals are assigned to the trains, etc., are controlled to switch related switches, and signals to instruct or stop traveling to the trains, etc. The interlocking device which has the function to emit is used. With this interlocking device, a chain is provided between the traffic lights, between the traffic lights and the switch related to the route, between the vehicle and the traffic light or the switch, and each device such as the traffic light and the switch A so-called interlocking function is provided so that when one device is handled, the other device cannot be handled when the other device is handled.

  Conventionally, a relay interlocking device that performs interlocking processing in an electric circuit using an electromagnetic relay has been used. However, in recent years, an electronic interlocking device in which interlocking processing is performed by a computer for the purpose of saving space and using general-purpose technology. Is being introduced. In order to produce an electronic interlocking device, it is necessary to create interlocking logic data for adapting to a computer and to verify the validity of the prepared interlocking logic data. However, the creation and verification of linked logical data for computers is extremely complicated and difficult, and humans have conventionally spent a great deal of effort and time.

  In order to deal with such problems, for example, in Japanese Patent Laid-Open No. 5-16807 (Patent Document 1), a connection diagram composed of a circuit group using a relay or the like used for manufacturing a relay interlocking device is input with a mouse or the like. A logical expression based on a Boolean algebra that can be executed by the computer is created by checking all current paths from the anode to the cathode based on the graphic data obtained by inputting to the computer using the device. The link logic data that can be used for the link condition of the electronic link device was created.

In such a linked logical data creation method, it is assumed that the connection diagram (graphic data) is converted into a logical expression, but the connection diagram based on the assumption that it is converted into a logical expression is an electromagnetic relay. It cannot be exactly the same as the connection diagram for relay interlocking devices.
For example, among the circuits described in the connection diagram for the relay interlocking device, there is one that controls a plurality of relays by one circuit. Controlling a relay corresponds to setting a value (1/0) in a variable in a logical expression, but only one variable can be set in one logical expression. For this reason, in order to convert into a logical expression, it is necessary to create a circuit for each variable.

The switch control circuit for the relay interlocking device includes relays that operate differently depending on the current direction. However, since there is no concept of the current direction in the logical expression, it is necessary to create a circuit for each current direction in order to convert it into the logical expression.
Thus, conventionally, it was necessary to create a new connection diagram for the electronic interlocking device based on the connection diagram for the relay interlocking device. However, in the preceding example, the measures for the above circuit are described or suggested. It has not been.

Japanese Patent Laid-Open No. 5-16807

  The present invention was made to solve the above problems, and when a new connection diagram for an electronic interlocking device is created based on the connection diagram for a relay interlocking device, It is an object of the present invention to provide a linked logical data creation method for a new linked device that can create linked logical data using a connection diagram as it is.

Further, according to the present invention, when converting a connection diagram (graphic data) into a logical expression, even if there is a connection diagram for a relay interlocking device that controls a plurality of relays with one circuit, a logic is provided for each relay. It is an object of the present invention to provide an interlocking logical data creation method of an interlocking device capable of automatically expanding expressions.
Further, the present invention converts a connection diagram (graphic data) into a logical expression by performing a route search in consideration of the current direction, even if there are relays having different operations depending on the current direction. It is an object of the present invention to provide an interlocking logical data creation method of an interlocking device that can obtain an expression.

It is another object of the present invention to provide a linked logical data creation method for a linked device that can obtain a logical expression that is highly readable and capable of high-speed computation.
It is another object of the present invention to provide a linked logical data creation method for a linked device that ensures the reliability of a logical formula conversion process.
A further object of the present invention is to provide a method for creating interlocking logic data of an interlocking device that can easily check changes in interlocking logic on the connection diagram of the display unit when creating interlocking data.

The interlocking logic data creation method of the interlocking device according to the present invention is obtained by inputting a connection diagram of the railway signal interlocking device composed of a relay circuit group to a computer using an input device such as a mouse, and input to the computer. Converting the graphic data into node information represented by a node indicating the branch and the anode end / cathode end together and a line segment sandwiched between the nodes, and from the anode to the cathode based on the node information. It is characterized in that it comprises a step of searching for all current paths leading to, and a step of performing logical expression conversion after correcting the paths in consideration of electrical characteristics from all the current paths obtained thereby. is there.

Further, in the above-described interlocking logical data creation method of the interlocking device, in a circuit having a plurality of relays in one circuit, logical expression conversion is performed for each relay. is there.
Further, in the above-described interlocking logic data creation method of the interlocking device, in a circuit including relays that operate differently depending on the current direction, the target relay is automatically expanded into a logical expression for each current direction. Is.
Further, in the above-described interlocking logic data generation method of the interlocking device, in the circuit including unconfigurable or redundant logic among all the searched current paths, these paths are deleted. It is.

The linked logical data creation method of the linked device includes a step of collating a logical expression conversion result based on a whole route search result and a logical expression conversion result based on simplification of node information. It is.
In the linked logical data creation method of the linked device described above, the simplification of the node information is characterized in that logical expression conversion is performed by appropriately realizing parallelization and serialization of circuits.
Further, in the above-described interlocking logical data creation method of the interlocking device, the relay state is displayed on the connection diagram of the display unit by performing condition setting and performing a logical expression operation. .

According to the interlocking logic data creation method of the interlocking device according to the present invention, when creating a new connection diagram for the electronic interlocking device based on the relaying interlocking device connection diagram, the relay interlocking connection diagram is used as it is. Thus, it is possible to create linked logical data.
In addition, according to the interlocking logic data creation method of the interlocking device according to the present invention, it is possible to create highly reliable interlocking logic data with high readability that can be understood by a general engineer.

Embodiment 1 FIG.
FIG. 1 shows an example of a linked logical data creation method on which the present invention is based. FIG. 1A is a block diagram showing the basic configuration of the processing apparatus, and FIG. 1B is a flowchart showing its operation. In order to explain this method, first, an interlocking chart that shows the arrangement of traffic lights, switches, and the like in the station premises and their chain relationship is prepared. Based on such a linkage diagram, a connection diagram 105 is created in which the content is expressed by a specific connection such as a relay. A connection diagram composed of the relays and the like is input to the computer 102 using the input unit 101 such as a mouse or a keyboard. The computer includes a CPU (Central Processing Unit) and a storage device such as a memory. The input connection diagram is displayed on a display unit 103 such as a display. The input connection diagram is stored as graphic data 106 in a storage device in a computer such as a memory or an output unit 104 such as a floppy (registered trademark) disk. The computer converts the graphic data 106 into a logical expression 107 according to a predetermined conversion rule, and creates interlocking logical data 108 that can be used as interlocking conditions for the railway signal interlocking device.

  FIG. 2 is a flowchart showing an embodiment of a linked logical data creation method according to the present invention. In the first embodiment, a predetermined connection diagram is first input to the computer using a mouse or a keyboard by the method described above (step 201). An example of the connection diagram and graphic data is shown in FIGS. 3 (a) and 3 (b). The connection diagram shown in FIG. 3A includes a power source anode 301, a cathode 302, a relay 303, relay contacts 304 and 305, and the like. The relay operates when a circuit is formed and current flows from the anode to the cathode. The localization contact X (304) constitutes a circuit when the relay X is operating, and the inversion contact Y (305) constitutes a circuit when the relay Y is not operating. In this circuit, the relay R operates when the relay X is operating or when the relay Y is not operating. The connection diagram input as described above is converted into graphic data (step 202). In the example of the graphic data shown in FIG. 3 (b), for example, the connection diagram is divided into rectangles 306 of the same size (hereinafter referred to as cells), cell numbers (rows, columns), relays arranged in the cells, A connection diagram is expressed by information of components such as a relay contact and a horizontal or vertical straight line connecting them.

  Graphic data is important for security, and it is necessary to confirm that the contents of the input connection diagram are correctly reflected in the graphic data. For this reason, as a recognition number of a component arranged in a cell, for example, a character code that allows a human to intuitively recognize the meaning, such as a character “+” for a wiring intersection in a connection diagram and a character “R” for a relay. By making these correspond to each other, it becomes easy to confirm the graphic data.

In addition, CSV (Comma Separated Value) is a common data format that handles data placed in cells (rows, columns). This CSV format is a text file in which column elements are separated by commas "," and line breaks are separated by line feed characters. It can be read by a general spreadsheet program. In these programs, each cell element can be displayed as a character string. Therefore, the graphic data created by the present invention can be read and displayed by other general programs by converting the graphic data into, for example, CSV format. By doing so, it can be confirmed whether or not the graphic data can be created as intended.
By doing as described above, it is possible to prevent a failure from being included in the data at the stage of graphic data creation.

Next, the graphic data is converted into node information (step 203).
An example of this node information is shown in FIG. Here, an example of a connection diagram different from FIG. 3 is shown, and a case where three current paths are provided between the anode end B24 and the cathode end C24 is shown. Each path has two relay contacts A, B, C, D and E, F in series. The contacts A, C and E are localization contacts, and B, D and F are inversion contacts. Node information is a component of the above connection diagram in which a branch and an anode end / cathode end are collectively represented as a node (402), and a portion sandwiched between two nodes is represented as a line segment (401).
Next, based on this node information, a current path to each relay (hereinafter referred to as a path) is searched (step 204 in FIG. 2). In general, a circuit represented by a connection diagram has a plurality of paths from the anode to the cathode. FIGS. 5A and 5B show an example of an expression method based on route node information.

In the circuit of FIG. 5A, there are three paths Line1, Line2, and Line3 for the relay R, and the relay R operates if all the contacts are configured on any of these paths. Here, “all the contacts on the path are configured” means that, when expressed by a logical expression, the evaluation result obtained by taking the logical product (AND) of each contact becomes true (1).
When the path is expressed using node information, it can be expressed as a set of ordered line segments and nodes between the start node (anode) and the end node (cathode) as shown in FIG. 5B (502). ). For line segments that do not include elements such as relays and relay contacts, the preceding and following nodes are combined into one node (501). When the line segments S1, S2, S3, and S4 are expressed by logical expressions, [A] * to [B], [C] * to [D], [E] * to [F], and [G] respectively. become. Here, “[name of A, B, C, etc.]” represents a variable, “*” represents a logical product (AND), and “˜” represents a negation (NOT). The route can be expressed by the logical product of the logical expressions of the line segments that make up the route. The logical expressions of the paths Line1, Line2, and Line3 are [A] * to [B] * [G], [C] *, respectively. ~ [D] * [G], [E] * ~ [F] * [G]. Further, in order for the relay R to operate, any one of these paths only needs to be configured, and when expressed by a logical expression, a logical OR (OR) of the paths may be taken, as follows.

[A] * ~ [B] * [G] + [C] * ~ [D] * [G] + [E] * ~ [F] * [G] = [R]
Here, “+” is a logical sum (OR), and “=” is an assignment operator. In this way, the method of creating a logical expression by connecting logical expression expressions of the respective current paths to the relay by logical sum is hereinafter referred to as a standard method (207), and the procedure described above in FIG. 6 is summarized. Is a flowchart. That is, in FIG. 6, first, logical expression expressions for all line segments on the circuit are created (step 401), then all paths on the circuit are searched in line units, and a line segment list for each path is obtained. Create (step 402). Subsequently, the logical product of line segments on each path is calculated (step 403), and finally the logical sum of each path is taken to complete a logical expression for each relay (step 404).

When the entire route search by the standard method is completed, unnecessary route deletion (line pruning / error check) among all the searched routes is performed, and route classification based on the current direction is performed (step 205 in FIG. 2). ). Details will be described with reference to FIGS. FIG. 7 shows an example of a circuit that controls a plurality of relays with a single circuit. At the time of route search, there is a route 701 in which relays 702, 703, and 704 are placed in series in order to search all routes.
Ordinary relays operate at 24V, and even if such a path is configured in an actual circuit, none of the relays operate due to insufficient voltage. However, in the logical expression, the value of the relay (variable) is set to true (1) when the path is configured. Therefore, the logical expression of the path for each relay is registered, and the voltages of the anode and the cathode (see FIG. 7). In this case, the route 701 is deleted in consideration of DC 24V) and the number of relays on each route (18V per relay × the number of relays).

Next, FIG. 8 is an example of a circuit including a non-configurable path. The path 801 includes a localization contact 802 and an inversion contact (803) of the relay X, and this path is never configured.
In the logical expression, [X] * to [X] are obtained, which are falsely (0), so that the calculation result of the logical expression is not affected. However, since the logical expression becomes unnecessarily complicated, a route including both the localization contact and the inversion contact of the same relay is regarded as an unconfigurable route and is deleted from the search result.
Next, FIG. 9A shows an example of a circuit including a redundant path, and FIG. 9B shows it by a logical expression. When a full route search is performed on the circuit of FIG. 9A, a route 901 and a route 902 are registered. However, in the logical expression shown in FIG. 9 (b) corresponding to these paths, the logical sum of 903 and 904 is taken, and the final characteristic is taken into consideration when the properties of the logical expression (1+ [X] = 1, etc.) are taken into account. It can be seen that the logical expression 905 matches the logical expression of the path 901, and the path (902) is unnecessary. Such redundant paths compare the possible paths for each relay, and if all of the line segments on one path that include relay elements are line segments on other paths, the latter is a redundant path. Judge that there is. The redundant path does not affect the logical expression calculation result, but is deleted from the path in consideration of shortening the calculation time and readability of the logical expression.

Next, FIG. 10A is an example of a circuit in which the current direction has a meaning. Some relays operate differently depending on the current direction. For example, a magnetic holding relay operates differently when a current flows from left to right and from right to left on the connection diagram. On the connection diagram, two current directions are expressed by one circuit, but there is no concept of the direction in the logical expression. Therefore, in the case of a relay whose operation differs depending on the current direction, a logical expression representing the operation when current flows in each direction is created. For example, for the magnetic holding relay W1001 in the circuit, there are a path 1002 through which current flows from the anode 1004 to the cathode 1006 and a path 1003 through which current flows from the anode 1004 to the cathode 1005. Since the magnetic holding relay operates differently depending on the direction of the current, it is necessary to classify the path 1002 through which the current flows from the left to the right in the drawing and the path 1003 through which it flows in the opposite direction. In order to classify such routes, the relationship between the connection nodes Na and Nb of the line segment Sw including the relay and the current direction to the relay is examined. FIG. 10B represents this by node information. When the node Na is on the anode side of the path, the path is represented by node information in the order of Na → Sw → Nb (1007). On the other hand, when the node Nb is on the anode side of the route, the route is represented by node information in the order of Nb → Sw → Na (1008). This makes it possible to classify paths according to the current direction and create a logical expression for each current direction.
As described above, the logical expression is converted after correcting the paths in consideration of the electrical characteristics from all the searched current paths.

Embodiment 2. FIG.
Next, another method for performing logical expression conversion after correcting the paths in consideration of electrical characteristics from all the searched current paths will be described.
When a human creates a logical expression, the logical expression is created based on the following rules.
・ Logically OR the contacts inserted in parallel.
・ Logically connect the contacts inserted in series.
-Create a logical expression by repeating the above operations.

  The second embodiment simulates a method in which a human creates a logical expression while looking at a circuit. FIG. 11 is an example showing a process of performing parallelization and serialization using node information. Between the node N1 and the node N2, there are three line segments, a line segment S1, a line segment S2, and a line segment S3. Since these line segments are parallel, the logical expression representations of the line segments are connected by a logical sum (OR) and assigned to a new line segment S123 (1101). As a result, the logical expression of the line segment S123 becomes [A] * to [B] + [C] * to [D] + [E] * to [F]. After parallelization, there are two line segments, line segment S123 and line segment S4, between node N1 and node N3. Since these line segments are serial, the logical expression representation of each line segment is connected by logical product (AND) and assigned to one new line segment S1234 (1102). Thereby, the logical expression of the line segment S1234 becomes {[A] * to [B] + [C] * to [D] + [E] * to [F]} * [G].

As described above, in the example of FIG. 11, by repeating serialization and parallelization, the graph is simplified to a start point node, an end point node, and one line segment therebetween. This conversion method is hereinafter referred to as a simplified method (step 208). FIG. 12 is a flowchart showing the procedure of the simplification method. In FIG. 12, first, the reduction number counter N is set to 0 (step 1201). Next, it is checked whether parallelization is possible (step 1202). If parallelization is possible, parallelization is executed and 1 is added to the reduction counter (step 1203). When the operations in steps 1202 to 1203 are repeated and parallelization becomes impossible, it is next checked whether serialization is possible (step 1204) .If possible, serialization is performed and 1 is added to the reduction counter ( Step 1205). Next, when serialization becomes impossible, it is checked whether or not the line segment has been reduced to one (step 1206). If there is only one line segment, the simplification is completed (step 1207).
When a plurality of line segments remain, the reduction counter is checked (step 1209). If N> 0, parallelization may be possible again, and the process returns to (step 1201).
If N = 0, it is determined that simplification cannot be performed, and a standard logical expression is used (step 1208).

Now, according to a preferred embodiment of the present invention, the route search result is subjected to pruning and error checking, then the route including each relay is selected (step 206 in FIG. 2), and the standard method (step 207) and a simplified method (step 208) to convert to a logical expression. The logical expressions obtained by the standard method and the simplified method are expressed as a standard logical expression and a simplified logical expression, respectively.
The standard logical expression is a logical sum of logical expression expressions of all routes based on the result of all route search. Since it is created by a simple and logical method, a logical equation contrary to the route search result is created. Never happen. However, the relay contacts in the circuit are arranged in a logical product for each path, and one relay contact appears on the circuit as a variable in multiple places on the circuit, so the logical expression becomes long and human-readable. It will be difficult.

  On the other hand, since the simplified logical formula is created by a method of simplifying node information from the entire route search result, there is a possibility that the logical formula according to the route search result is not created. However, humans simulate the procedure of creating logical expressions while looking at the circuit, and take the form of factorization. Therefore, the expressions are shorter than the standard logical expressions and are easy for humans to read. Further, when the electronic interlocking device executes a logical expression by a program, the calculation time can be shortened. Therefore, in the preferred embodiment, the standard logical expression and the simplified logical expression are collated, and after confirming that both are logically equal (step 209), an excellent simplified logical expression is output as the logical expression. (Step 210). By doing so, it is possible to ensure reliability when creating a logical expression.

FIG. 13 shows an example of two logical expression matching flowcharts. First, a logical expression is created for the specified circuit by two conversion methods (step 1301).
Next, the left side of the logical expression is expanded (step 1302).
Next, variables and term information are registered (step 1303). At this time, registration is performed after deleting unnecessary variables included in the term. For example, the term [A] * [A] * [B] is equivalent to [A] * [B] due to the properties of the logical expression, and is registered as [A] * [B].

Next, information on a term that is not true and a redundant term are deleted (step 1304). A term that does not become true is a variable with the same name, such as [A] * to [A] * [B], where one includes the negation of the other. A redundant term is the latter term when all the variables of one term are contained in another term.
For example, the logical sum [A] + [A] * [B] of two terms [A] and [A] * [B] can be factored as [A] * {1+ [B]} Since [B] is identically true (1), [A] * [B] is a redundant term.
After deleting all the information of such terms, the remaining terms are compared one by one (step 1305). If all terms match, it is determined that the two logical expressions are logically equal (step 1306). On the other hand, if the number of terms is different or there are terms that do not match, it is determined that the two logical expressions are not logically equal (step 1307).

When the two results match, the reduced logical expression is output to the display unit 103 and the output unit 104 in FIG. 1 (step 210 in FIG. 2) and compared with the input connection diagram (step 212).
If the two results do not match, it is determined that one of the conversion methods is incorrect, and the logical expression is not output (step 211), thereby preventing the generation of a logical expression that does not match the connection diagram. it can.

  Next, for the logical expression obtained through this process, use the mouse or keyboard to set conditions and states such as relays on the connection diagram displayed on the display (step 213), Formula calculation (step 214) is performed. The cell number of the graphic data corresponding to each relay and relay contact on the connection diagram, the logical expression corresponding to the relay, and the logical operation result of the logical expression are associated with each other and stored in a storage device such as a memory. As a result, when the logical operation of the logical expression is performed, the relay symbol on the connection diagram corresponding to the logical expression according to the operation result (1/0), for example, blue for operation (1), no operation If it is (0), the operation of the relay can be confirmed by displaying it in red.

  As a method of performing a logical expression operation, for example, there is a method of converting the left side of a logical expression into a postfix notation. The postfix notation is a notation in which a variable is written first and an operator for the variable is written later, and makes it easy to perform four arithmetic operations and logical operations of an expression on a computer. For example, when the left side of the logical expression [X] + [Y] = [R] is rewritten to the postfix notation, [X] [Y] + is obtained. If the value of variable [X] is 1 and the value of variable [Y] is 0, the value is stored in memory etc., and when the corresponding operator appears, the two values are sequentially extracted and the operation is performed. Then, the result is stored again in the memory. By repeating such an operation, a logical expression is calculated.

In this case, the calculation result on the left side is 1, and the value of the variable [R] on the right side is updated to 1. The value of the variable [R] being 1 means that the relay R is in an operating state on the connection diagram, and the operation state of the relay at this time can be displayed on the connection diagram (step 215). ). This makes it possible to check whether the circuit operates as intended. Note that it is needless to say that there is a prefix notation as another method for facilitating the arithmetic operation and logical operation of an expression by a computer.
Through the above procedure, linked logical data can be created from the logical expression (step 216).

FIG. 1A is a block diagram illustrating a basic configuration of a processing apparatus, and FIG. 1B is a flowchart illustrating the operation thereof. It is a flowchart figure which shows the interlocking | linkage logical data creation method by Embodiment 1 of this invention. FIG. 3A shows an example of the connection diagram created in FIG. 2, and FIG. 3B shows an example of graphic data. It is a figure which shows an example of the node information converted from the graphic data of FIG.3 (b). It is a figure which shows the example of the expression method by the node information of a path | route. It is the figure which showed the method of producing a logical expression with a standard method with the flowchart. It is a figure which shows the cutting of the circuit which controls a some relay with one circuit. FIG. 6 is a diagram illustrating pruning a circuit including a non-configurable path FIG. 9A shows an example of a circuit including a redundant path, and FIG. 9B shows an example of logical expression conversion. FIG. 10A is a diagram showing an example of a circuit having a relay whose operation differs depending on the current direction, and FIG. It is a figure which shows the processing method of the node information by the reduction method by Embodiment 2 of this invention. It is the figure which showed the method of producing a logical expression by the simplification method with the flowchart. It is a figure which shows the flowchart which collates two logical expressions of a standard method and a reduction method.

Explanation of symbols

101 input unit 102 computer
103 Display unit 104 Output unit 105 Connection diagram 401 Line segment 402,501 Node B24 Anode end C24 Cathode end

Claims (9)

Inputting a wiring diagram of a railway signal interlocking device comprising a relay circuit group to a computer;
Converting the graphic data obtained by the input to the computer into node information represented by a node indicating a branch point and an anode end or a cathode end together and a line segment sandwiched between the nodes;
Based on this node information, searching for all current paths from the anode to the cathode;
An interlocking logic data generation method for an interlocking device, comprising: a step of performing logical expression conversion after correcting a path in consideration of electrical characteristics from all current paths obtained in this way. 2. The interlocking logic data creation method for an interlocking device according to claim 1, wherein in a circuit having a plurality of relays in one circuit, logical expression conversion is performed for each relay. 2. The interlocking logic data creation method for an interlocking device according to claim 1, wherein in the circuit including relays that operate differently depending on the current direction, logical expression conversion is performed for each current direction with respect to the target relay. 2. The interlock of the interlocking device according to claim 1, wherein in the circuit including unconfigurable or redundant logic among all searched current paths, logical expression conversion is performed after these paths are deleted. Logical data creation method. 2. The interlocking logical data creation method of the interlocking device according to claim 1, wherein logical expression conversion is performed by taking a logical sum of logical expression expressions of all paths based on a result of searching all paths. The logical expression conversion is performed by performing parallelization and serialization of the inter-node circuit based on the result of the entire path search, and repeating the process until it is reduced to one line segment. How to create interlocking logical data for interlocking devices. Based on the result of all-path search, logical expression conversion result by logical sum of logical expressions of all paths and parallelization and serialization of inter-node circuits are performed as appropriate, and simplified to one line segment. The interlocking logic data creation method of the interlocking device according to claim 1, further comprising a step of collating the logical expression conversion result obtained by repeating the process up to. 8. The interlocking logic data creation method for an interlocking device according to claim 7, wherein when the two logical expression conversion results are collated, if both are logically equal, a simplified logical expression is employed. The interlock device according to any one of claims 5 to 8, wherein the relay state is displayed on the connection diagram of the display unit by performing condition setting and performing a logical expression operation. How to create linked logical data.

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