JP2005040406A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To recognize a communication fault between a game control means and a put-out control means, to surely receive control signals from the game control means when starting power supply, and to prevent disadvantages to a player by a switch operation at the time of error cancellation. <P>SOLUTION: When the power supply to a game machine is started, reset signals are inputted to the reset terminal of a CPU (central processing unit) for put-out control and the CPU for the put-out control is turned to be in an operable state. Also, the reset signals are delayed in a delay circuit and then inputted to the reset terminal of a main CPU and the main CPU is turned to be in the operable state later than the CPU for the put-out control. When turned to the operable state, the main CPU executes a software delay processing and then starts an initialization processing and a game control processing. Also, when detecting the communication fault with the main CPU, the CPU for the put-out control reports it by an LED (light emitting diode). Also, in a prescribed error state, when signals are inputted from an error cancellation switch, the error state is canceled. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is a pachinko gaming machine, a slot machine, etc. that allows a player to play a predetermined game using a game medium and pays out a prize game medium as a prize based on the fact that a payout condition is established by the game Related to the gaming machine.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, there is provided a variable display unit capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display mode. is there.

  Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. Or a condition where the winning ball payout condition is easily established.

  In a pachinko gaming machine, the combination of a predetermined display mode with a display result of a variable display unit that displays a special symbol is usually referred to as “big hit”. When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state in which a hit ball is easy to win.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game is performed by the game control means mounted on the main board. Since it is controlled, the number of winning balls based on winning is determined by the game control means, and as described in Patent Document 1, a control signal indicating the number of winning balls is transmitted to the payout control board by unidirectional communication. Then, the payout control means performs a process of paying out the number of prize balls based on the winning based on the control signal from the game control means. For example, as described in Patent Document 2, when the winning ball detection switch provided in the winning ball processing device that holds the winning ball detects the winning ball, the game control means controls the control signal indicating the number of winning balls. Is sent to the payout control means, and when the payout of the winning ball based on the control signal indicating the number of winning balls is completed, the winning ball is discharged from the winning ball processing device so that the next winning ball can be detected.

JP 2000-202126 A (paragraphs 0061 to 0065, FIG. 5) Japanese Patent Laid-Open No. 11-244491 (paragraphs 0125 to 0135, FIG. 15)

  When the winning ball detection switch detects a winning ball, the game control means transmits a control signal indicating the number of winning balls to the payout control means, and when the winning ball payout based on the control signal indicating the number of winning balls is completed, the winning ball processing device When the winning ball is discharged so that the next winning ball can be detected, the payout control is performed from the game control means for the occurrence of the winning when the winning is continuously generated. Transmission of the control signal indicating the number of prize balls to the means is delayed. As a result, there is a possibility that the point at which the prize ball payout is actually started is delayed with respect to the occurrence of the winning. In addition, since a control signal indicating the number of winning balls is transmitted to the payout control board by unidirectional communication, a signal is missed or misrecognized in the payout control means, and the number of winning balls based on the winning is not paid out accurately. there is a possibility.

  In addition, when there is a failure in communication between the game control means and the payout control means, it may not be possible to accurately pay out a prize ball. There is also a problem that the game may continue even though the ball cannot be paid out.

  Further, in general, each control means is constituted by a microcomputer, and this microcomputer starts its operation by releasing the reset state after a predetermined reset period after turning on the power. For this reason, there is a problem that, when the game control means transmits a control signal when the power is turned on, the signal may be missed if other control means such as the payout control means are not ready for reception. .

  In addition, a clear switch for clearing the RAM backed up in the payout control means is provided for convenience of the game store, etc., but the clear switch is operated to cancel an error related to payout of the game media. If this is done, the information regarding unpaid prize balls will be cleared, causing a disadvantage to the player.

  Therefore, the present invention can recognize that a failure has occurred in communication between the game control means and the payout control means in the gaming machine in which the game control means and the payout control means are provided separately. When the power supply to the gaming machine is started, the payout control means can reliably receive the control signal from the game control means, and the player is disadvantaged by the switch operation for error release It is an object of the present invention to provide a gaming machine that can prevent the player from being played.

  The gaming machine according to the present invention allows a player to play a predetermined game using a game medium, and as a prize based on the fact that a payout condition is established by the game (for example, a game ball has won a winning area). A gaming machine that pays out premium game media and executes a game control process for controlling the progress of the game (for example, the process after step S5 in the main process, the timer interrupt process shown in FIG. 14). A game control means (for example, the main board 31) including (for example, the CPU 56), a payout means (for example, a ball payout device 97) for paying out premium game media, and a payout control process for controlling the payout means (for example, FIGS. 36 to 38). The payout control means (for example, the payout control board 37) including the payout control microcomputer (for example, the payout control CPU 371) that executes the processing shown in FIG. , Communication abnormality detection means (for example, step S552 in the payout control means, step S552) for detecting an abnormality (for example, main control unconnected error, prize ball REQ signal error) related to signal communication between the game control means and the payout control means S564, the portion that executes step S815), and when the communication abnormality detecting means detects an abnormality, the internal state is an error occurrence state (for example, a prize ball REQ signal error bit is set, a main control unconnected error) When the error is detected by the error control means (for example, the part that executes step S553, step S566, and step SS816 in the payout control means) and the communication abnormality detection means detects that the bit is set) Communication error notification means (for example, an error display LED 374) and error according to human operation. An error canceling operation means (for example, an error canceling switch 375) for outputting a canceling signal (for example, an operation signal corresponding to the operation), an error canceling signal from the error canceling operating means is monitored in an error occurrence state, and an error canceling signal is input. Error canceling means (for example, a portion of the payout control means for executing steps S802 to S807) that releases the error occurrence condition on the condition that the game control means is detected, and the game control means receives the prize based on the establishment of the payout condition. The payout control means includes payout command signal transmission means (for example, a part for executing the prize ball transmission processing in step S232 in the game control means) for transmitting a payout command signal (for example, a prize ball control signal) for designating the number of game media payouts. Is a prize game medium with the number of payouts specified by the payout command signal from the payout command signal transmitting means in the game control means. A prize game medium payout control means for executing a payout process for controlling the payout means to pay out the body (for example, a portion of the payout control means for executing the award ball lending control process in step S545 and step S766); Including a signal transmission means (for example, a portion executing step S546 in the payout control means) for transmitting a signal (for example, a prize ball BUSY signal) related to payout processing by the game medium payout control means to the game control means. However, when power supply to the gaming machine is started and the game control process becomes executable, the execution of the game control process is started (specifically, for example, the control command output process in steps S14, S94, etc. is included) At least pay from the start of the game control process. Until the start of execution of the control process (specifically, it may be after the process for receiving the control command from the main board 31 is executable), for example, after the interrupt is permitted in step S715 Can be delayed. ) Is delayed for a predetermined period (for example, steps S81 to S86). In the delay process, the control signal transmission process (for example, steps S14 and S94) after the game control process is started is started at least when the game control process is ready to be executed. May be delayed for a predetermined period of time until the execution of the control signal is started and the control signal can be received (for example, after the interrupt is permitted in step S715).

  Provided with an allowance signal output means (eg, a power supply monitoring circuit 920) for outputting an allowance signal (eg, a reset signal) that makes the game control microcomputer ready to execute the game control process when power supply to the gaming machine is started. Further, delay means (for example, a delay circuit 69) for delaying the allowance signal from the allowance signal output means and supplying it to the game control microcomputer may be provided.

  The allowance signal (for example, reset signal) from the allowance signal output means is supplied to the payout control microcomputer, and the allowance signal output means is executed before the game control microcomputer completes the execution of the delay process (for example, in step S86). It may be configured to output an allowable signal before it is determined as Y).

  The allowable signal from the allowable signal output means is branched and supplied to the game control microcomputer and the payout control microcomputer (for example, as shown in FIG. 7, the reset signal output line from the power supply monitoring circuit 920 The reset signal may be branched and supplied to each board. That is, the allowable signal output at the same timing may be branched and supplied to the game control microcomputer and the payout control microcomputer, respectively.

  The allowance signal output means is a board provided separately from the game control board (for example, main board 31) on which the game control means is mounted and the payout control board (for example, payout control board 37) on which the payout control means is mounted. It is preferable to be mounted on a power supply board 910 (for example).

  It is preferable that the communication abnormality detecting means and the communication abnormality notifying means are mounted on a payout control board (for example, the payout control board 37) on which the payout control means is mounted.

  The game control means transmits a connection confirmation signal (for example, a connection confirmation signal) to the payout control means when power supply to the gaming machine is started and the game control process becomes executable (for example, when the main board 31 rises). Then, the communication abnormality detection means is configured to monitor the state of the connection confirmation signal (for example, step S815) and detect an abnormality related to signal communication between the game control means and the payout control means (for example, step S816). It may be.

  The signal related to the payout process transmitted by the signal transmitting means may include a command reception signal (for example, a prize ball BUSY signal) indicating that the payout command signal has been received.

  The gaming machine can communicate with a recording medium processing device (for example, card unit 50) that performs processing for converting a value specified by information recorded on the recording medium into a gaming usage value that can be used for gaming on the gaming machine. Connected and provided with external device abnormality detection means (for example, a part for executing steps S825 and S826 in the payout control means) for detecting an abnormality relating to communication between the recording medium processing device and the gaming machine, The abnormality detected by the abnormality detection unit and the abnormality detected by the external device abnormality detection unit are notified in a distinguishable manner (for example, as shown in FIG. 54, “1” and “5” are displayed for the abnormality detected by the communication abnormality detection unit. (8 and 9 are displayed for the abnormality detected by the display and external device abnormality detecting means).

  An error release signal from the error release operation means is input to the payout control means (for example, FIG. 5), and the error release means is included in the payout control means (for example, steps S801 to S807 are executed in the payout control means). May be.

  The error release signal from the error release operation means may be input to the payout control means, and the error release means may be included in the payout control means.

  According to the first aspect of the present invention, when the communication abnormality detecting means detects an abnormality, the communication abnormality notifying means for informing the fact, and the error releasing signal from the error releasing operation means in the error occurrence state are monitored. And an error canceling means for canceling the error occurrence state on the condition that the input of the error cancel signal is detected, and the game control microcomputer is in a state where power supply to the gaming machine is started and the game control process can be executed. A delay process is executed to delay the start of execution of the game control process for a predetermined period from when the game control process becomes executable to at least the start of execution of the payout control process. Therefore, it is possible to recognize that a failure has occurred in communication between the game control means and the payout control means, and the power supply of the gaming machine has been started. The payout control means can surely receive the control signal from the game control means and can prevent the player from being disadvantaged by the switch operation for canceling the error. effective.

  In the second aspect of the invention, since the start of the game control process is also delayed by hardware, the versatility of the delay process by software can be left in preparation for when the specification is changed, and by the software Delay processing can be simplified, and the data capacity of software for delay processing can be reduced.

  According to the third aspect of the present invention, since the permission signal is output to the payout control microcomputer prior to the game control microcomputer, the payout control process is started prior to the game control process. Can be.

  In the invention of claim 4, since the allowable signal from the allowable signal output means is branched and supplied to the game control microcomputer and the payout control microcomputer, the allowable signal is output from the allowable signal output means. Since they are output at the same timing, the payout control process can be surely started before the game control process by the delay means.

  In the invention according to claim 5, since the allowance signal output means is mounted on a board provided separately from the game control board and the payout control board, even if there are a plurality of boards that require the allowance signal, One permissible signal output means can cope with this.

  According to the sixth aspect of the present invention, since the communication abnormality detecting means and the communication abnormality notifying means are controlled by the same substrate, the communication abnormality can be notified more reliably.

  In the invention according to claim 7, since the communication abnormality detection means monitors the state of the connection confirmation signal from the game control means and detects an abnormality related to signal communication between the game control means and the payout control means, The control means can reliably detect that an abnormality relating to signal communication with the game control means has occurred.

  In the invention described in claim 8, since the command reception signal is included in the signal related to the payout process transmitted by the signal transmitting means, the game control means easily grasps that the payout process is started by the payout control means. be able to.

  In the ninth aspect of the invention, the communication abnormality notification means is configured to notify the abnormality detected by the communication abnormality detection means and the abnormality detected by the external device abnormality detection means in a distinguishable manner. It is possible to easily identify which abnormality has occurred between the abnormality relating to communication with the communication device and the abnormality relating to communication of the signal between the game control means and the payout control means.

  In the invention described in claim 10, since the error release signal from the error release operation means is input to the payout control means, and the error release means is included in the payout control means, it is possible to detect an error related to the payout of the game medium and the error state. The cancellation can be executed by the payout control means, and the configuration for detecting the error and canceling the error state can be simplified.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Below the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the game balls. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. Further, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, the symbol display area and the start memory display area are provided separately, so that the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. Further, the display of the start memory number may be interrupted during variable display. In this example, the start memory display area is provided in the variable display device 9, but a display (special symbol start memory display) for displaying the start memory number may be provided separately from the variable display device 9. Good.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning opening 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. In addition, a variable winning ball apparatus 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An opening / closing plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing a large winning opening (variable winning ball apparatus). Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area: special area) is detected by the V count switch 22, and the winning ball from the opening / closing board 20 is counted. 23. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (a symbol can be visually recognized when the lamp is lit). For example, if the right lamp is lit when the variable display ends, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increments the LED to be turned on by one. Then, every time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Decorative lamps 25 blinking and displayed during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a game ball that has not won a prize is provided at the bottom. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is lit while paying out a prize ball is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the refill ball is cut is provided in the vicinity of the top frame lamp 28a. It has been. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Furthermore, a prepaid card unit (hereinafter referred to as a card unit) that enables lending of a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown).

  The card unit includes, for example, a use indicator lamp that indicates whether or not the card unit is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, When checking the card insertion indicator lamp that indicates that a card has been inserted, the card insertion slot into which a card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock is provided to release the unit.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, the special symbol starts variable display (fluctuation) in the variable display device 9 if the variable display of the symbol can be started. If variable display of symbols is not possible, the starting memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When a game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stoppage is a combination of jackpot symbols (probability variation symbols) with probability fluctuation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 are increased when the stop symbol of the normal symbol is a winning symbol, or when the stop symbol of the special symbol is a probabilistic symbol. Change to an advantageous state. It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 2, on the back side of the gaming machine, a game in which a variable display control unit 49 including an effect control board 80 on which an effect control means for controlling the variable display device 9 is mounted, a game control microcomputer, and the like are mounted. A control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. The production control means includes a variable display device 9 provided on the game board 6, various decoration LEDs, a normal symbol start memory display 41, a decoration lamp 25, a top frame lamp 28a provided on the frame side, and a left frame. The lamp 28b and the right frame lamp 28c are controlled to be turned on, and sound generation from the speaker 27 is controlled.

  The effect control means is realized by one effect control microcomputer mounted on the effect control board 80, but various decoration LEDs, normal symbol start memory display 41, and decoration lamp 25 provided on the game board 6. The drive circuit for driving the top frame lamp 28a, the left frame lamp 28b and the right frame lamp 28c provided on the frame side is mounted on a lamp driver board electrically connected to the effect control board 80. Yes. The drive circuit for driving the speaker 27 is mounted on a sound control board that is electrically connected to the effect control board 80.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Although most of the power supply substrate 910 overlaps with the main substrate 31, there is an exposed portion that is exposed so as to be visible from the outside without overlapping the main substrate 31. In the exposed portion, power supply to the main board 31 and each electric component control board (the effect control board 80 and the payout control board 37) in the gaming machine 1 and each electric component provided in the gaming machine is executed or cut off. Data stored in a power switch as a power supply permitting unit and a storage content holding unit included in the main board 31 and the payout control board 37 (for example, a backup RAM capable of holding the contents even when power supply is stopped) And a clear switch as an operation means for clearing. Furthermore, a replaceable fuse is provided inside the power switch in the exposed portion (inside the substrate).

  An electrical component control means including an electrical component control microcomputer is mounted on the electrical component control board. The electric component control means is an electric component (game device: ball payout device 97, variable display device 9, light emitter such as a lamp or LED) provided in the gaming machine in accordance with a command signal (control signal) from the game control means. ) To control. Hereinafter, description may be made by including the main board 31 in the electric component control board. In that case, the electric component control means mounted on the electric component control board indicates each of the game control means and the means for controlling the electric components provided in the gaming machine in accordance with a command signal from the game control means. . A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting prize ball information (prize ball number signal) and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. Near the center, an information terminal board (information output board) 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and reach the ball payout device covered with the payout case 40A through the curve rod. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage. In the vicinity of the head). When the ball break detection switch 167 detects a shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize and game balls based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball passage. When the game ball is further paid out, a sensing lever (not shown) presses a full tank switch (not shown) as a storage state detection means, and the full tank switch as a storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 3 is a front view (FIG. 3 (A)) and a cross-sectional view (FIG. 3 (B)) showing the ball dispensing device 97 covered with the dispensing case 40A. The ball payout device 97 is fixed to the lower part of the passage body installed between the ball break switch 187 and the ball payout device 97. The passage body has a ball passage for flowing down two rows of game balls in which the flow direction is changed to the left and right directions by the curve saddle. A ball break switch 187 is installed on the upstream side of the ball passage. In practice, a ball break switch is installed in each ball passage. The ball break switch 187 detects the presence or absence of a game ball in the ball passage. When the ball break switch 187 stops detecting a game ball, the ball discharge device 97 has a payout motor (not shown in FIG. 3). The rotation is stopped and the payout of the game ball is immobilized.

  The ball break switch 187 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball path.

  In the ball payout device 97, a payout motor (not shown) using a stepping motor rotates, for example, a cam, thereby paying out one winning ball or one game ball based on a ball lending request. Also, below the ball payout device 97, for example, a payout number count switch 301 using a proximity switch is provided. Each time one game ball falls from the ball payout device 97, the payout number count switch 301 is turned on. That is, the payout number count switch 301 detects a game ball actually paid out from the ball payout device 97. Therefore, the payout control means can count the number of game balls actually paid out by the detection signal of the payout number count switch 301.

  In this embodiment, the ball payout device 97 is configured to perform both prize ball payout and ball lending. However, a ball payout device for paying out a prize ball and a ball payout device for lending a ball may be provided separately. When provided separately, a payout means is constituted by a ball payout device for paying out a prize ball and a ball payout device for lending a ball. Further, for example, the configuration may be such that the prize ball payout and the ball lending are separated by changing the rotation direction of the cam or sprocket, or the ball payout device 97 exemplified in the present embodiment (the cam is rotated by the motor). The present invention can be applied to any structure other than the structure).

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 4 also shows a payout control board 37, an effect control board 80, and the like. On the main board 31, a basic circuit (corresponding to a game control microcomputer: game control means) 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V count switch 22, and a count switch 23 The input driver circuit 58 for supplying signals from the winning opening switches 29a, 30a, 33a, 39a and the clear switch 921 to the basic circuit 53, the solenoid 16 for opening / closing the variable winning ball apparatus 15, and the solenoid 21 for opening / closing the opening / closing plate 20. And a solenoid circuit 59 for driving the solenoid 21A for switching the route in the special winning opening in accordance with a command from the basic circuit 53.

  The gate switch 32a, the start port switch 14a, the V count switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, and other switches may be referred to as sensors. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball. Each of the start port switch 14a, the V count switch 22, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a for performing the winning detection is also a winning detection means. Note that the winning detection means may be configured to collectively detect the respective game balls that have won separately a plurality of winning openings. In addition, even if a passing gate such as the gate switch 32a is used, if a prize ball is to be paid out, a game ball entering the passing gate becomes a win, and a switch ( For example, the gate switch 32a) serves as a winning detection means. Further, in this embodiment, since the game balls won in the V winning area are detected only by the V count switch 22, the number of game balls won in the big winning opening is the number detected by the V count switch 22 and the count switch 23. It becomes the sum with the number of detection by. However, the game ball that has won the V winning area may be detected by the V count switch 22 and also by the count switch 23. In that case, the number of game balls won in the big winning opening corresponds to the number detected by the count switch 23.

  A switch common voltage (for example, + 12V) is supplied to each of the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a. A switch common monitoring circuit 71 for monitoring the voltage is mounted. When the switch common monitoring circuit 71 detects that the switch common voltage has dropped to a predetermined value, the switch common monitoring signal input to the basic circuit 53 is turned off.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  A basic circuit 53 realized by a game control microcomputer includes a ROM 54 for storing a game control (game progress control) program and the like, and storage means used as a work memory (variable data storage means for storing variable data). RAM 55, CPU 56 for performing control operations in accordance with programs, and I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 built in, and the ROM 54 and the I / O port unit 57 may be externally attached or built in. Since the CPU 56 executes control according to the program stored in the ROM 54, the CPU 56 executes (or performs processing) hereinafter, specifically, when the CPU 56 executes control according to the program. is there. The same applies to CPUs mounted on boards other than the main board 31. The game control means is realized by a basic circuit 53 realized by a game control microcomputer, but is mainly realized by a CPU 56 that executes control according to a program in the game control microcomputer.

  The RAM 55 is a backup RAM as a non-volatile storage means that is partially or entirely backed up by a backup power source created on the power supply substrate 910. In other words, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the power supply of the backup power supply is disabled). In particular, at least data (special symbol process flag or the like) corresponding to the game state, that is, the control state of the game control means, and data indicating the number of unpaid winning balls are stored in the backup RAM. Note that the data according to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power supply is restored after a power failure or the like. . In this embodiment, it is assumed that the entire RAM 55 is backed up.

  The reset signal from the power supply board 910 is input to the reset terminal of the CPU 56, but the reset signal from the power supply board 910 is delayed by the delay circuit 69 in the main board 31. Further, a power-off signal output from the power supply substrate 910 is input to the basic circuit 53 (specifically, an input port).

  The hitting ball launching device for hitting and launching the game ball includes a launch motor 94 controlled by a circuit on the payout control board 37, and the game ball is launched toward the game area 7 by the rotation of the launch motor 94. A drive signal for driving the firing motor 94 is transmitted to the firing motor 94 via the touch sensor substrate 91. The touch sensor detects that the player is touching the operation knob (hitting ball handle) 5 and a signal from the touch sensor is mounted on the touch sensor substrate 91 (the player touches the operation knob 5). Is transmitted to the payout control board 37 via a circuit including a detection circuit for detecting whether or not it is touched. The circuit on the payout control board 37 stops the driving of the firing motor 94 when the signal from the touch sensor circuit indicates an off state. Note that the operation knob 5 is provided with a touch ring that adjusts the resilience and is a part that the player contacts. In the gaming machine, the touch sensor substrate 91 is disposed between the touch ring and the payout control substrate 37, and is disposed in the vicinity of the touch ring. Specifically, the wiring length between the touch ring and the touch sensor substrate 91 is shorter than the wiring length between the touch sensor substrate 91 and the payout control substrate 37.

  In this embodiment, the effect control means mounted on the effect control board 80 controls the display of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board 6, and the frame side The display control of the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c provided in is performed. The effect control means mounted on the effect control board 80 also performs display control of the variable display device 9 that variably displays special symbols and the normal symbol display 10 that variably displays normal symbols.

  In addition, the CPU 56 used in this embodiment includes a non-maskable interrupt terminal (NMI terminal) used for generating a non-maskable interrupt (NMI) that cannot be set to interrupt prohibition by software, And an interrupt terminal (INT terminal) used for generating an external interrupt (external interrupt; maskable interrupt that can be disabled by software). However, this embodiment does not use non-maskable interrupts and external interrupts. Therefore, the NMI terminal and the INT terminal are pulled up to Vcc (+5 V) through resistors. Therefore, the input levels of the NMI terminal and the INT terminal are always at a high level, and there is a possibility that the input level of the NMI terminal and the INT terminal falls due to noise or the like, and an interrupt is generated, as compared with the terminal open state. To reduce.

  FIG. 5 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, the payout control board 37 is equipped with a payout control microcomputer (an example of an electric component control microcomputer) including a payout control CPU 371. In this embodiment, the payout control microcomputer is a one-chip microcomputer and has at least a built-in RAM. Further, the RAM is backed up in the same manner as the RAM 55 in the main board 31. The payout control CPU 371, the RAM, the ROM (not shown) storing the payout control program, the I / O port, etc. constitute payout control means. Accordingly, the payout control means is realized by a payout control CPU 371, a payout control microcomputer including a RAM, a ROM, and an I / O port, but is mainly realized by a payout control CPU 371 that executes control according to a program.

  Detection signals from the full tank switch 48 and the payout number count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. Further, detection signals from the ball break switch 187 and the payout motor position sensor 295 are input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . The payout control CPU 371 of the payout control board 37 performs a ball payout process when the detection signal from the ball break switch 187 indicates a ball shortage state or when the detection signal from the full tank switch 48 indicates a full tank state. Stop. Further, when the detection signal from the full tank switch 48 indicates a full tank state, the ball launching from the ball striking device is stopped.

  When there is a win, the output circuit 67 of the main board 31 receives a prize ball REQ signal (prize ball request signal) for making a prize ball payout request and a prize ball control indicating the number of prize balls to be paid out as a payout command signal. A signal is output (turns on). The prize ball control signal is composed of 4-bit data (binary 4-digit data) and is output through four signal lines. Note that the on state of the signal, that is, the output state is a state where the signal is significant, and turning on means that the signal receiving side is instructed to start some processing based on the signal. To do. For example, when the prize ball control signal indicating the number of prize balls and the prize ball REQ signal are turned on, this means that the dispense control means is instructed to recognize the number of prizes indicated by the prize ball control signal. To do. The prize ball control signal is input to the I / O port 372e via the input circuit 373A. When the winning ball REQ signal and the winning ball control signal are input via the I / O port 372e, the payout control CPU 371 drives the ball paying device 97 to pay out the number of game balls indicated by the winning ball control signal. I do. A power supply confirmation signal (connection confirmation signal) indicating that the main board 31 is connected is also output from the output circuit 67 of the main board 31. The prize ball REQ signal and the prize ball control signal correspond to a payout command signal for designating the number of payouts.

  Further, when the payout control means accepts a payout command signal, it sends a command acceptance signal to the main board 31. The command acceptance signal is transmitted to the main board 31 via the output port 372b of the payout control board 37 and the output circuit 373B. Then, in the main board 31, the data is input to the CPU 56 via the input circuit 68 and the I / O port 57. In this embodiment, the command acceptance signal is transmitted when the prize ball BUSY signal is turned on.

  The payout control CPU 371 receives a prize ball information signal indicating the number of prize balls to be paid and a ball lending number signal indicating the number of lent balls via the output port 372b as a terminal board (frame external terminal board and board external terminal board). Output) 160. A driver circuit is provided outside the output port 372b, but is not shown in FIG. In addition, door opening information switches 161A and 161B are connected to the terminal board 160 (frame external terminal board).

  Further, the payout control CPU 371 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. In this example, as shown in FIG. 5, the error display LED 374 is mounted on the payout control board 37. Further, a signal for instructing lighting / extinguishing is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. A driver circuit (motor drive circuit) is installed outside the output port 372a, but is not shown in FIG. A drive signal from the payout control board 37 to the firing motor 94 is transmitted to the firing motor 94 via the output port 372 a and the touch sensor board 91.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp 151, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155. The interface board (relay board) 66 is connected to a frequency display LED 60, a ball lending LED 61, a ball lending switch 62 and a return switch 63 provided in the vicinity of the hitting ball supply tray 3.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control CPU 371 determines the connected / unconnected state of the card unit 50 based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, when a BRDY signal from the card unit 50 is not in an ON state, a prize ball payout control is executed when a payout command signal is received from the game control means. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  The power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in the AC 24V power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  The payout control CPU 371 used in this embodiment generates a non-maskable interrupt terminal (NMI terminal) used to generate a non-maskable interrupt (NMI) and a maskable interrupt. And an interrupt terminal (INT terminal) used for the purpose. However, this embodiment does not use non-maskable interrupts and external interrupts. Therefore, the NMI terminal and the INT terminal are pulled up to Vcc (+5 V) through resistors.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even when a game ball corresponding to the amount of money is lent out in accordance with coin insertion.

  FIG. 6 is a block diagram illustrating a circuit configuration example of the effect control board 80, the lamp driver board 35, and the sound control board 70. The lamp driver board 35 and the voice control board 70 are not equipped with a microcomputer. In the effect control board 80, the effect control CPU 101 in the effect control microcomputer (an example of an electric component control microcomputer) operates in accordance with a program stored in a ROM (not shown), and a strobe signal from the main board 31. In response to (symbol control INT signal), a symbol control command is received via the input driver 102 and the input port 103. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD, based on the symbol control command. The VDP 109 is sometimes called a GCL (graphic controller LSI).

  Further, the production control CPU 101 outputs sound number data to the sound control board 70 via the output port 104 and the output driver 110. A bus (including an address bus, a data bus, and a control signal line such as a writing / reading signal) input / output to / from the effect control CPU 101 is extended to the lamp driver board 35 via the bus driver 105.

  In the lamp driver board 35, a bus that is input to and output from the effect control CPU 101 is connected to the output port 352 and the expansion port 353 via the bus receiver 351. A signal for driving each lamp output from the output port 352 is amplified by the lamp driver 354 and supplied to each lamp. A signal for driving each LED output from the output port 352 is amplified by the LED driving circuit 355 and supplied to each LED. A signal for driving the effect driving means 61 is amplified by the drive circuit 356 and supplied to each lamp.

  In this embodiment, lamps / LEDs and effect driving means provided in the gaming machine are controlled by effect control means including effect CPU 101 mounted on effect control board 80. Further, data for controlling the variable display device 9, the normal symbol display 10, the lamp / LED, and the like are stored in the ROM. The effect CPU 101 controls the variable display device 9, the normal symbol display 10, the lamp / LED, and the like based on the data stored in the ROM. Then, the lamp / LED and the effect driving means are driven via the output port 352 and each drive circuit mounted on the lamp driver board 35. Therefore, when changing the model, it is necessary to make a design change such as changing the number of ports for the lamp driver board 35, but for the production control board 80, it is only necessary to replace the ROM storing the program. There is no need to make design changes.

  Although the production control board 80, the lamp driver board 35, and the sound control board 70 are independent boards, they are installed in a single box on the back of the gaming machine, for example. The expansion port 353 is installed in consideration of the case where the number of lamps / LEDs and the like is increased when the model is changed, but it may not be installed. The drive circuit 356 may not be provided when there are no movable members for production. However, considering the case where the movable member for production is installed when changing the model, the movable circuit for production is performed. It is preferably provided even when no member is present.

  In the voice control board 70, the sound number data from the effect control board 80 is input to the voice synthesis IC 703 by a digital signal processor, for example, via the input driver 702. The voice synthesis IC 703 reads data corresponding to the sound number data from the voice data ROM 704 mounted on the voice data board 70 </ b> A, generates voice and sound effects corresponding to the read data, and outputs them to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. In this embodiment, the voice data ROM 704 is mounted on the voice data board 70A, which is a board different from the voice control board 70, but the voice data ROM 704 may be mounted on the voice control board 70. Good. In that case, the audio data board 70A is unnecessary.

  The data corresponding to the sound number data stored in the sound data ROM 704 is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a special symbol fluctuation period). When the voice number IC 703 receives the sound number data, the voice synthesis IC 703 performs sound output control according to the corresponding data in the voice data ROM 704. The sound output control according to the corresponding data is continued until the next sound number data is input. When the next sound number data is input, the speech synthesis IC 703 performs sound output control according to the data in the sound data ROM 704 corresponding to the newly input sound number data.

  In this embodiment, the sound and sound output from the speaker 27 are controlled by the effect control means including the effect control CPU 101, but the effect control means outputs the sound number data to the sound control board 70. . In the voice control board 70, the voice data ROM 704 stores a large amount of data for realizing voice and sound effects that can appear as the game progresses, and these data are associated with the sound number data. . Therefore, the production control means can realize sound output control only by outputting the sound number data. Note that the sound number data is, for example, 1-byte data and is transferred to the sound control board 70 via a serial signal line or a parallel signal line.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), an AC power supply (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply board 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911.

  The power supply board 910 is installed independently of the electric component control board (the main board 31, the payout control board 37, and the effect control board 80), and generates a voltage used by each board and mechanism component in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow preventing diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 914. VSL is a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of regulator ICs (two regulator ICs 924A and 924B are shown in FIG. 7), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 7, AC24V output from the transformer 911 is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. The cable connected to the connector 922B is connected to the payout control board 37. Therefore, VBB is also supplied to the connectors 922A and 922B. The cable connected to the connector 922C is connected to the lamp driver board 36. Each voltage is supplied to the effect control board 80 via the lamp driver board 36.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the main board 31 and the payout control board 37 via the connectors 922A and 922B. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided other than the power supply board 910 in the gaming machine.

  Further, the power supply board 910 generates a reset signal for the microcomputer mounted on the electric component control board, amplifies the reset signal from the power supply monitor circuit 920 that outputs a power-off signal, and the power supply monitor circuit 920. And an output driver circuit 925 that amplifies the power-off signal and outputs it to the connectors 922A and 922B. The reset signal for the effect control microcomputer is transmitted to the effect control board 80 via the lamp driver board 36.

  The power supply monitoring circuit 920 is a circuit that realizes power supply monitoring means for outputting a power-off signal and reset signal generation means for generating a reset signal. As the power supply monitoring circuit 920, a commercially available power failure monitoring reset module IC should be used. Can do. The power supply monitoring circuit 920 outputs a power-off signal when a period during which a predetermined voltage (for example, + 24V) used in a gaming machine becomes equal to or lower than a predetermined value (for example, + 5V) continues for a predetermined time (for example, 56 ms). . Specifically, the power-off signal is turned on (low level). Further, the power supply monitoring circuit 920 enters a state in which the reset signal can be set to a low level, for example, when VCC becomes +4.5 V or less.

  When the power supply to the gaming machine is stopped, the power supply monitoring circuit 920 sets the reset signal to a low level on condition that a predetermined period has elapsed since the power-off signal was output (set to a low level). The predetermined period is a time sufficient for the microcomputer mounted on the main board 31 and the payout control board 37 to execute power-off processing described later. In addition, when the power supply to the gaming machine is started and Vcc exceeds +4.5 V, for example, the reset signal is set to high level. ) The reset signal is set to high level on condition that a predetermined period has elapsed. Therefore, when the microcomputer mounted on each electrical component control board (including the main board 31) starts the control operation according to the program in response to the reset signal becoming high level, the power-off signal is always turned off. It is in a state.

  A reset signal from the power supply monitoring circuit 920 is branched into three for the three substrates 31, 37, and 35 and is input to the output driver circuit 925. Then, the three reset signals amplified by the output driver circuit 925 are output to the three substrates 31, 37, and 35, respectively. In this way, the reset signal output at the same timing is branched and supplied to the game control microcomputer and the payout control microcomputer, so that delay processing (software delay processing, delay by the delay circuit 69) in the main board 31 is performed. By the process, the payout control process can be surely started before the game control process.

  A power-off signal from the power monitoring circuit 920, that is, a detection signal from the power monitoring means is input to the CPU 56 via the input port 572 in the main board 31. Therefore, the CPU 56 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 572. Further, the power-off signal from the power supply monitoring circuit 920 is input to the payout control CPU 371 via the input port 372g on the payout control board 37 (see FIG. 5). Therefore, the payout control CPU 371 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 372g.

  As described above, in this embodiment, since the power supply monitoring circuit 920 is mounted on the power supply board 910 which is a board different from the main board 31 and the payout control board 37, there is no board that requires a reset signal. A plurality of power supply monitoring circuits 920 can cope with them.

  In this embodiment, the power supply monitoring means monitors the output of the power supply of a predetermined potential, and the voltage from the outside of the gaming machine (this implementation) In this embodiment, it is used that the predetermined DC voltage created from AC24V) is lower than the predetermined value. However, the detection condition is not limited to this, and if it is possible to detect that the power from the outside is cut off, Other conditions may be used. For example, the AC wave itself may be monitored and the AC wave may be detected as a detection condition, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be stopped when the digital signal becomes flat. May be used as a detection condition.

  In this embodiment, a reset signal is output from the power supply monitoring circuit 920 to each of the three substrates 31, 37, and 35 at the same timing, and thereafter, a reset signal input to the CPU 56 on the main substrate 31 is output. Although the configuration is delayed, the power supply monitoring circuit 920 may output a reset signal at a separate timing toward the main board 31 and the sub boards 37 and 35. In this case, the power supply monitoring circuit 920 may be configured to output the reset signal first toward the sub-boards 37 and 35 and then output the reset signal toward the main board 31. At least before the delay processing (software delay processing, delay processing by the delay circuit 69) in the main substrate 31 is completed (for example, before it is determined as Y in step S86), the sub substrates 37 and 35 are started up. At such timing, a reset signal may be output to the sub-boards 37 and 35 first. In this way, the power supply monitoring circuit 920 is configured to output a reset signal before the delay processing in the main board 31 is completed so that the sub boards 35 and 37 rise before the main board 31. However, the payout control process can be started before the game control process.

  8 and 9 are explanatory diagrams showing examples of output port assignment in the game control means. As shown in FIG. 8, the output port 0 is an output port for a payout control signal transmitted to the payout control board 37. Further, 8-bit data of the symbol control command transmitted to the effect control board 80 is output from the output port 1.

  Further, from the output port 2, a solenoid (large winning port door solenoid) 21 for opening and closing the opening / closing plate 2 of the large winning port, a solenoid (large winning port guide plate solenoid) 21A for switching the path in the large winning port and a variable A drive signal is output to a solenoid (normal electric accessory solenoid) 16 for opening and closing the winning ball apparatus 15. Further, a symbol control INT signal (strobe signal) for the symbol control command transmitted to the effect control board 80 is also output. The symbol control INT signal is a signal for instructing the effect control means to capture 8-bit data of the symbol control command.

  Then, various information output signals from the output ports 3 and 4 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 10 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 10, the detection signals of the V count switch 22, the count switch 23, the gate switch 32a, the winning port switches 33a, 24a, 29a, and 30a, and the start port switch 14a are respectively input to bits 0 to 7 of the input port 0. Is entered. In addition, bits 0 to 3 of the input port 1 respectively include a power-off signal from the power supply monitoring board 910, a detection signal of the clear switch 921 from the power supply board 910, a prize ball BUSY signal from the payout control board 37, and a switch common. A monitoring signal is input. Note that the detection signal and the prize ball BUSY signal from each switch are logically inverted in the input driver circuit 58.

  Next, the operation of the gaming machine will be described. 11 and 12 are flowcharts showing main processing executed by the game control means on the main board 31. When the gaming machine is turned on and the input level of the reset terminal to which the reset signal is input becomes high, the CPU 56 performs a security check process that is a process for confirming whether the contents of the program are valid. After the execution, main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4).

  Next, a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software is executed. Specifically, first, the initialization wait number designation value 1 is set in the wait counter 1 (step S81). Also, the initialization wait number specification value 2 is set in the wait counter 2 (step S82). As the wait counters 1 and 2, general-purpose registers built in the CPU 56 are used. Then, the value of the wait counter 2 is decremented by 1 until the value of the wait counter 2 becomes 0 (steps S83 and S84). When the value of the weight counter 2 becomes 0, the value of the weight counter 1 is decremented by 1 (step S85). When the value of the weight counter 1 is not 0 (step S86), the process returns to step S82. If the value of the wait counter 1 is 0, the software delay process is terminated.

  By the software delay processing as described above, the software delay processing is not executed substantially by [(initialization wait number specification value 1) × (initialization wait number specification value 2) × (processing time of steps S83, S84)]. Compared to the case, the start timing of the game control process can be delayed. In other words, the initialization weight count designation values 1 and 2 are determined so that the start timing of the game control process can be delayed by a desired time. Note that the values of the initialization wait times designation values 1 and 2 are set in the ROM 54. Further, the software delay processing described here is an example, and the software delay processing may be realized by other methods.

  The predetermined period to be delayed by the software delay process ensures at least a period from when the power supply to the gaming machine is started to the operable state until after the payout control process is started. That is, a predetermined period of time to be delayed by the software delay process is determined so that the game control process by the game control means is started after the payout control process by the payout control means is started. With this configuration, the payout control means can reliably receive a control signal from the game control means when power supply to the gaming machine is started. Note that when the power supply of the gaming machine is started, the payout control unit only needs to ensure that the control signal from the game control unit can be received. Therefore, the predetermined period delayed by the software delay processing is at least the sub-board. After the control state in which the control signal can be received is started in 37 and 35 (for example, after execution of step S715), the control signal transmission operation (for example, steps S14 and S94) in the main board 31 is performed. It only has to be adjusted. The same applies to the case where delay processing is performed using a hardware circuit.

  When the software delay processing ends, the CTC (counter / timer) and PIO (parallel input / output port), which are built-in devices (built-in peripheral circuits), are initialized (step S5), and then the RAM 55 is set in an accessible state. (Step S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform processing for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes a normal initialization process (steps S10 to S15). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the clear switch signal is on at a high level. Further, for example, the game clerk can easily execute the initialization process by starting the power supply to the gaming machine (for example, turning on the power switch 914) while turning the clear switch 921 on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. If it is confirmed that such protection processing has been performed, the CPU 56 determines that there is a backup. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

  Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 2). Note that such a confirmation method is merely an example. For example, a flag indicating that the data protection process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that there is a backup, it may be determined that there is a backup.

  If it is determined that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power outage or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S15) executed when the power is turned on, not when the power supply is stopped. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S81), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S82). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processes in steps S81 and S82, the saved contents of the work area that should not be initialized remain. The portion that should not be initialized is, for example, a portion in which data indicating a gaming state before stopping power supply (a special symbol process flag or the like) or data indicating the number of unpaid prize balls is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S83), and power is supplied to the sub-boards (the payout control board 37 and the effect control board 80) according to the contents. Control is performed so that a control command indicating the recovery is transmitted (step S84). Then, the process proceeds to step S15.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by an unauthorized means. Therefore, it is difficult to aim at a timing at which the count value of the counter for matching the jackpot determination value. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12). Through the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, a ball break An initial value is set to a flag for selectively performing processing according to the control state, such as a flag or a payout stop flag.

  Further, the CPU 56 sets the initial address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and sends an initialization command for initializing the sub board according to the contents of the sub board. The process to transmit to is executed (step S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  In step S15, the CPU 56 sets a CTC register built in the CPU 56 so that a timer interrupt is periodically generated every predetermined time (for example, 4 ms). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18). The CPU 56 disables the interrupt when the display random number update process and the initial value random number update process are executed (step S16), and interrupts when the display random number update process and the initial value random number update process are finished. The permitted state is set (step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. It is. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a jackpot (a jackpot determining random number generation counter). Game control processing described later (a game control microcomputer controls a game device such as a variable display device 9, a variable winning ball device, a ball payout device, etc. provided in the gaming machine, or other In the process of transmitting a command signal to cause the microcomputer to control, also referred to as a gaming device control process), when the count value of the big hit determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process and the initial value random number update process are executed, the interrupt disabled state is caused by the timer interrupt process described later. This is to avoid conflict with the processing in the timer interrupt processing. That is, if a timer interrupt occurs during the processing of steps S17 and S18 and the count value of the counter for generating the display random number and the initial value random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt disabled state is set during the processes of steps S17 and S18.

  FIG. 13 is a timing chart showing how the microcomputer operates when power supply to the gaming machine is started and when power supply is stopped. When power supply to the gaming machine is started and the voltage of the DC + 24V power supply exceeds a predetermined value, the power-off signal is turned off. When the value of VCC exceeds a predetermined value, the reset signal becomes high level. As described above, the power supply monitoring circuit 920 sets the reset signal to high level after turning off the power-off signal. The reset signal is input to the main board 31 and the payout control board 37 and is input to the effect control board 80 via the lamp driver board 36. Then, it is input to the reset terminal of the payout control CPU 371 mounted on the payout control board 37 and the effect control CPU 101 mounted on the effect control board 80. The payout control CPU 371 and the effect control CPU 101 become operable when the reset signal becomes high level. When in the operable state, first, initialization processing is executed, and thereafter, production control processing and payout control processing are started.

  The reset signal input to the main board 31 is delayed by the delay circuit 69 and then input to the reset terminal of the CPU 56. Therefore, the time when the CPU 56 becomes operable is later than the time when the CPU of the sub-board becomes operable. Further, when the CPU 56 becomes operable, the CPU 56 executes security check processing based on the security check program. And when the security check process is finished, after executing the software delay process, the initialization process and the game control process are started.

  As described above, the CPU 56 performs a process of transmitting a command (command signal) to the CPU of the sub board in the initialization process. Due to the delay by the delay circuit 69 (delay by the hardware circuit) and the execution of the security check process, the time when the CPU 56 starts the initialization process is later than the time when the CPU of the sub-board completes the initialization process. That is, since the execution time of the security check process is determined according to the frequency of the clock signal supplied to the CPU 56, the time when the CPU 56 starts the initialization process is more than the time when the CPU of the sub-board completes the initialization process. The delay amount of the delay circuit 69 is set so as to be delayed.

  In this embodiment, software delay processing is also executed before the CPU 56 starts initialization processing. Therefore, it is more certain that the time when the CPU 56 starts the initialization process is later than the time when the CPU of the sub-board completes the initialization process. Further, for example, when the CPU of the sub board is changed to an inexpensive CPU having a slow operation (that is, when the CPU of the sub board completes the initialization process is delayed), the delay amount of the delay circuit 69 Otherwise, the time when the CPU 56 starts the initialization process may be earlier than the time when the CPU of the sub-board completes the initialization process. However, if it is configured to execute software delay processing as in this embodiment, the time when the CPU 56 starts initialization processing is relative to the execution time of the security check processing and the delay time by the delay circuit 69. Further, since the time of the software delay process is added, the CPU 56 delays the initialization process without changing the configuration of the delay circuit 69 even when the CPU of the sub-board completes the initialization process. It is possible to prevent the time at which the CPU starts from being earlier than the time at which the CPU of the sub-board completes the initialization process.

  The delay time (specific period) by the delay circuit 69 is, for example, the execution time of the security check process from the time until the sub-board using the slowest CPU among the sub-boards that may be adopted starts. The time is set slightly shorter (eg, 700 ms) than the subtracted time. Then, the delay time due to the software delay processing is adjusted according to the operation speed of the sub-board actually used, and the time when the CPU of the sub-board completes the initialization processing is the time when the CPU 56 starts the initialization processing. It should be slow. In this way, if it is configured to be delayed not only by software but also by a hardware circuit, the versatility of delay processing by software can be left in preparation for when a specification change such as a change of a sub board is made, and software Thus, the delay process can be simplified, and the data capacity of the software for the delay process can be reduced.

  When the power supply to the gaming machine is stopped, the voltage of the DC + 24V power supply also gradually decreases. However, when the voltage of the DC + 24V power supply falls below a predetermined value, the power supply monitoring circuit 920 outputs a power-off signal (set to a low level). ). The power-off signal is input to the main board 31 and the payout control board 37. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37, according to the power-off signal being output, the power supply stop process (both power-off control process) Say). The power supply monitoring circuit 920 sets the reset signal to a low level when VCC falls below a predetermined value. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 are system reset in response to the reset signal becoming low level. That is, the CPU 56 and the payout control CPU 371 are not operated. Note that the power supply monitoring circuit 920 sets the reset signal to a low level when a predetermined time elapses from the time when the power supply cutoff signal is output when the power supply voltage decreases.

  Next, the game control process will be described. FIG. 14 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, during the execution of the loop process of steps S16 to S19, the CPU 56 performs a timer interrupt process that is activated in response to the occurrence of the timer interrupt. A game control process is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-on signal is turned on) (step S20). Subsequently, detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a are input via the switch circuit 58, and their state is determined (switch) Process: Step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one. Moreover, the short circuit alerting | reporting process which performs a predetermined alerting | reporting process based on a switch common monitoring signal is performed (step S22).

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S27). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting a symbol control command related to the special symbol in a predetermined area of the RAM 55 and sending the symbol control command (special symbol command control process: step S28). Further, the symbol control command related to the normal symbol is set in a predetermined area of the RAM 55, and the symbol control command is transmitted (normal symbol command control processing: step S29).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on detection signals from the prize opening switches 29a, 30a, 33a, 39a and the like (step S31). Specifically, a payout control signal such as a prize ball control signal indicating the number of prize balls is output to the payout control board 37 in response to detection of a winning based on the winning opening switch 29a, 30a, 33a, 39a being turned on. . The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in accordance with a payout control signal such as a prize ball control signal indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start winning memory | storage number (step S32). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, but the CPU 56 relates to the solenoid in the RAM area of the output port 3 (see FIG. 8). Is output to the output port (step S34: solenoid output processing). Thereafter, the interrupt permission state is set (step S35), and the process is terminated.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 4 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed. Further, the processing of steps S21 to S34 (except for steps S30 and S33) corresponds to a game control process for controlling the progress of the game.

  15 and 16 are flowcharts illustrating an example of the power-off process in step S20. In the power-off process, the CPU 56 first checks whether or not a power-off signal is output (whether it is in an on state) (step S450). If not on, the value of the backup monitoring timer formed in the RAM 55 is cleared to 0 (step S451). If it is on, the value of the backup monitoring timer formed in the RAM 55 is incremented by 1 (step S452). If the value of the backup monitoring timer matches the determination value (for example, 2) (step S453), the power supply stop processing after step S454, that is, the preparation processing for power supply stop is executed. That is, the state shifts from the state in which the progress of the game is controlled to the state in which the power supply stop process (the power-off control process) for saving the game state is executed.

  By using the backup monitoring timer and the determination value, if the power-off signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even when the power-off signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer formed in the RAM 55 is stored by the backup power source for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, in step S8 in the main process, it is possible to confirm that the processing result of the power supply stop process is stored because the value of the backup monitoring timer is the same value as the determination value.

  In the power supply stop process, the CPU 56 creates parity data (steps S454 to S463). That is, first, clear data (00) is set in the checksum data area (step S454), and the checksum calculation start address corresponding to the start address of the RAM area in which the contents are to be stored even when power supply is stopped is set in the pointer. (Step S455). Further, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (step S456).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S457). The calculation result is stored in the checksum data area (step S458), the value of the pointer is incremented by 1 (step S459), and the value of the checksum calculation count is decremented by 1 (step S460). Then, the processes in steps S457 to S460 are repeated until the value of the checksum calculation count becomes 0 (step S461).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S462). Then, the inverted data is stored in the checksum data area (step S463). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the output ports for the number of processes are sequentially set.

  The CPU 56 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data of the address pointed to by the pointer (that is, the address of the output port) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479), and if the number of processes is not 0, the process returns to step S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (step S481) and the loop process is started.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (step S482). When the power-off signal is turned off, the execution address at power-on (address in step S1) is set as a return address and a return command is executed (step S483). That is, the process returns to the main process. Specifically, a state in which a gaming device provided in the gaming machine is controlled (a concept including both controlling by itself and sending a command signal to cause another microcomputer to control). Return.

  When the power supply is stopped by the above process, the power supply stop process in steps S454 to S481 is executed, and data indicating that the power supply stop process has been executed (specified value with backup and checksum) Is stored in the backup RAM, the RAM access is disabled, the output port is cleared, and the timer interrupt for executing the game control process is disabled.

  In this embodiment, the entire area of the RAM 55 is backed up by a backup power source (the contents of the RAM 55 are preserved for a predetermined period even when power supply to the gaming machine is stopped). Therefore, the checksum based on the contents of the RAM 55 when the power-off signal is output is stored in the RAM 55 together with the value of the backup monitoring timer by the processing in steps S452 to S479. After the power supply to the gaming machine is stopped, when the power supply is restored within a predetermined period, the game control means performs data stored in the RAM 55 (immediately before the power supply is stopped) by the processing of steps S91 to S94 described above. In accordance with the data indicating the game state that is the control state by the game control means (for example, including the process flag state, the big hit flag state, the probability change flag state, the output port output state, etc.) It is possible to return to the state immediately before the supply is stopped. If the power supply stop period exceeds the predetermined period, the value of the backup monitoring timer and the checksum should be different from the regular values. In this case, the initialization process of steps S10 to S14 is executed. The

  As described above, the power supply stop process (preparation process for stopping the power supply) ensures that the data for returning the gaming state to the state immediately before the power supply stopped is the fluctuation data storage means (in this example) Stored in the entire area of the RAM 55). Therefore, even if the power is cut off due to a power failure or the like, if the power is restored within a predetermined period, the gaming state can be returned to the state immediately before the power supply is stopped. The entire area of the RAM 55 may not be backed up by power, but only the area for storing data for returning the gaming state to the state immediately before the power supply is stopped may be backed up.

  If the power-off signal is turned off, the process returns to step S1. In this case, since data indicating that the power supply stop process has been executed is set, the game state recovery process of steps S91 to S94 is executed. Therefore, when the detection signal from the power supply monitoring unit is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  The connection confirmation signal transmitted to the payout control board 37 is set to the off state by the process of clearing the output port. In the setting of the work area in steps 82 and S12, the content of the output port buffer corresponding to the connection confirmation signal is set to a value corresponding to the ON state of the connection confirmation signal. When the prize ball processing in step S31 is executed, the contents of the output port buffer are output to the output port, so that the connection confirmation signal to the payout control board 37 is turned on. Therefore, the connection confirmation signal is output (turned on) when the main board 31 rises. Note that a connection confirmation signal is also output when the power supply is recovered from an instantaneous power interruption or the like.

  Next, the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 17 is an explanatory diagram showing each 1-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer in which the contents of port 0 inputted this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected.

  FIG. 18 is a flowchart illustrating a processing example of the switch process in step S21 in the game control process. In the switch process, the CPU 56 first inputs data input to the input port 0 (see FIG. 10) (step S101), and sets the input data in the port buffer (step S102). Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter becomes 0, the data of the input port 0 is input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer (step S106). S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S14 and S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S14 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the CPU 56 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The CPU 56 further performs a logical product for each bit between the operation result of the exclusive OR and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the CPU 56 sets the operation result of the logical product in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the operation result in step S108 is set in the previous port buffer (step S112). .

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Next, payout control signals transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 19 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means and a payout control signal input from the payout control means to the game control means. In this embodiment, a plurality of types of control signals are transmitted and received between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 19, the connection confirmation signal is output when the main board 31 rises (when the game control means starts the game control process), indicating that the main board 31 has risen with respect to the payout control board 37. This is a signal for notification (connection confirmation signal for the main board 31). The connection confirmation signal indicates that the winning ball can be paid out.

  The prize ball REQ signal is a signal that is in an output state (= ON state) when a prize ball payout request is made (that is, a trigger signal for a prize ball payout request). Further, the award ball REQ signal becomes a stopped state (off state) when the award ball BUSY signal is turned on after being turned on from the payout control means. The award ball control signal is a signal (award ball number command) output for designating the number (1 to 15) of game balls for which a payout request is made.

  The prize ball BUSY signal is a signal that is turned on when the payout control means confirms the on state of the prize ball REQ signal, and is turned off after a predetermined period. That is, it corresponds to an acceptance confirmation signal for the prize ball REQ signal. Therefore, the state in which the prize ball BUSY signal is OFF corresponds to a state of waiting for a prize ball number command reception.

  FIG. 20 is a block diagram showing signal lines and the like used for transmission / reception of each control signal shown in FIG. As shown in FIG. 20, the connection confirmation signal, the prize ball REQ signal, and the prize ball control signal are output by the CPU 56 via the output circuit 67 and input to the payout control CPU 371 via the input circuit 373A. The prize ball BUSY signal is output via the output circuit 373B by the payout control CPU 371 and input to the CPU 56 via the input circuit 68. Each of the connection confirmation signal, the prize ball REQ signal, and the prize ball BUSY signal is 1-bit data, and is transmitted through one signal line. Since 1 to 15 prize ball control signals are designated, it is composed of 4-bit data and transmitted through four signal lines.

  FIG. 21 is a timing chart showing an example of how to output the payout control signal, and FIG. 22 is a timing chart showing an enlarged part of FIG. As shown in FIG. 21, when the winning detection switch detects the winning of a game ball, the game control means turns on the winning ball REQ signal and pays out the output state of the winning ball control signal according to the winning. A state corresponding to the number of prize balls is set. In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any of the prize port switches 33a, 39a, 29a, 30a. Seven prize balls are paid out. When a game ball is detected by the V count switch 22 or the count switch 23, 15 prize balls are paid out. Further, as described above, the prize ball control signal is composed of 4 bits, and therefore, the lower 4 bits of the prize ball number commands of 00 (H) to 0F (H) represented by 8 bits are A prize ball control signal is transmitted from the main board 31 to the payout control board 37. Hereinafter, the prize ball control signal may be expressed as “00 (H) to 0F (H) prize ball control signal”, but actually, the prize ball control signal is represented by 8 bits. This corresponds to the lower 4 bits of 0F (H).

  When the payout control means confirms reception of the prize ball BUSY signal within the time of the prize ball BUSY signal on waiting time (A) shown in FIG. 22, the prize ball BUSY signal is kept on only for the prize ball BUSY signal on time. When the award ball BUSY signal on time elapses, the award ball BUSY signal is turned off. The award ball BUSY signal on waiting time (A) is a time from when the payout control means turns on the award ball REQ signal to confirm the receipt of the award ball REQ signal (for example, MAX2). .783 ms). The award ball BUSY signal ON time is a time for causing the game control means to recognize the ON state of the award ball BUSY signal, and is a fixed time (for example, 20.870 ms).

  When the game control means confirms that the prize ball BUSY signal has changed to the OFF state, the game control means turns the prize ball BUSY signal to the OFF state after the award ball REQ signal OFF waiting time (C) has elapsed. At that time, the output state of the prize ball control signal is cleared and turned off. That is, the prize ball control signal is set to a state indicating 0 (a state in which an invalid command is output). Accordingly, since the prize ball control signal is in an invalid command output state when the prize ball REQ signal is in an on state, a case where the on state of the prize ball BUSY signal is detected by noise or the like in the payout control means. However, there is no such thing as accidentally paying out a prize ball. The award ball REQ signal off waiting time is a time for providing an interval between the on periods of a plurality of award ball REQ signals when the award ball payout is continuously executed (for example, MAX49.391 ms). . Further, the times A, B, and C become different values when the frequency of the clock signal supplied to the CPU 56 and the payout control CPU 371 changes. That is, when the frequency of the clock signal supplied to the CPU 56 and the payout control CPU 371 changes, the value becomes different.

  As shown in FIG. 21, when a new winning is detected when the winning ball REQ signal is on, the turning on of the winning ball REQ signal and the output of the winning ball control signal based on the winning are waited. Specifically, when a new winning is detected when the winning ball REQ signal is on, the number of winning balls to be paid out based on the winning is the content of the total winning ball buffer formed in the RAM 55. Is added to Then, when the game control means turns off the prize ball REQ signal, if the content of the total prize ball number buffer is not 0, the number of prize balls indicated by the contents of the total prize ball number buffer is set to 15 as the upper limit. In order to instruct a prize ball payout, the prize ball REQ signal is turned on and a prize ball control signal is output.

  As shown in FIG. 23, when the prize ball BUSY signal is turned on even though the prize ball REQ signal is not turned on, the game control means turns the connection confirmation signal off. When the connection confirmation signal is in the OFF state, even if the winning detection switch detects the winning of the game ball, the winning ball REQ signal is not turned ON. Therefore, the number of prize balls to be paid out based on the winning is simply added to the contents of the total prize ball number buffer, and no prize ball control signal is output. When the prize ball BUSY signal is turned off, the connection confirmation signal is turned on. At that time, if the content of the total prize ball number buffer is not 0, the prize ball REQ signal is turned on in order to instruct the payout of the number of prize balls indicated by the content of the total prize ball number buffer with an upper limit of 15. At the same time, a prize ball control signal is output.

  FIG. 24 is a flowchart showing an example of the prize ball processing in step S31. In the prize ball process, the CPU 56 executes a prize ball number addition process (step S201) and a prize ball control process (step S202). Then, the contents of the port 0 buffer formed in the RAM 55 are output to port 0 (step S203). The contents of the port 0 buffer are updated in the prize ball control process.

  In the prize ball number adding process, a prize ball number table shown in FIG. 25 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “7”) is set in the top address of the winning ball number table, and then the lower address of the switch-on buffer, and each switch of the winning opening that will pay out the winning ball by winning. The switch input bit determination value and the number of winning balls are sequentially set corresponding to each switch of the winning opening. The switch input bit determination value is a value corresponding to the bit to which the detection signal of each switch at the input port 0 is input (see FIG. 10). The upper address of the switch-on buffer is a fixed value (for example, 7F (H)). In the prize ball number table, the same data is set in each of the lower addresses of the seven switch-on buffers.

  FIG. 26 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the CPU 56 sets the start address of the winning ball number table in the pointer (step S211). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S212). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S213).

  Then, the value of the pointer is incremented by 1 (step S214), the prize ball number table data pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S215), The pointer value is incremented by 1 (step S216). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S217), and the loaded contents and the data of the prize ball number table pointed to by the pointer (in this case, the switch input bit judgment value) ) And the logical product (step S218). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is incremented by 1 (step S219).

  If the calculation result in step S218 is 0, that is, if the detection signal of the switch to be inspected is on, the prize ball number table data pointed to by the pointer (in this case, the prize ball number) is used as the prize ball addition value. (Steps S220 and S221), and the prize ball addition value is added to the contents of the 16-bit total prize ball number storage buffer formed in the RAM 55 (step S222). The total winning ball number storage buffer is formed in the backup RAM. If a carry occurs as a result of the addition, the content of the total number of winning balls storage buffer is set to 65535 (= FFFF (H)) (steps S223 and 224). Further, “formed in RAM” means an area in the RAM.

  In step S225, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S214 (step S226). In step S220, when it is confirmed that the calculation result in step S218 is 0, that is, the detection signal of the switch to be inspected is in the OFF state, the process proceeds to step S225.

  FIG. 27 is a flowchart showing the prize ball control process in step S201. In the prize ball control process, the CPU 56 executes any one of steps S231 to S234 according to the value of the prize ball process code.

  FIG. 28 is a flowchart showing the prize waiting process 1 (step S231) executed when the value of the prize ball process code is zero. In the award ball waiting process 1, the CPU 56 checks whether or not the award ball BUSY signal is turned on (step S241). At this stage, since the prize ball BUSY signal should not be in the on state, when the prize ball BUSY signal is in the on state, the prize ball abnormal state output value (20 (H)) is stored in the port 0 buffer. To complete the processing (step S242). When the prize ball abnormal state output value is set in the port 0 buffer, the contents of the port 0 buffer are outputted to port 0 in step S203 (see FIG. 24), so that the prize ball REQ signal, connection confirmation signal and All the prize ball control signals are turned off (see FIG. 8).

  If the prize ball BUSY signal is off, the prize ball standby output value (30 (H)) is set in the port 0 buffer (step S243). When the output value during waiting for a prize ball is set in the port 0 buffer, the contents of the port 0 buffer are output to port 0 in step S203, whereby the prize ball REQ signal is turned off, and the connection confirmation signal The on state is maintained (see FIG. 8). In addition, the prize ball control signal enters an invalid command (00 (H)). Next, it is confirmed whether or not the prize ball timer is 0 (step S244). If the prize ball timer is not 0, the value of the prize ball timer is decreased by 1 (step S245), and the process is terminated. The prize ball timer is a timer for measuring the time required for prize ball processing. At this stage, if the value of the prize ball timer is not 0, the next prize ball after the previous payout process is completed. Waiting time until the REQ signal is turned on (time for providing an interval between ON periods of a plurality of prize ball REQ signals when prize ball payout is continuously executed, 00 (H ) Means that the prize ball control signal is being output). The prize ball timer is set in step S275 of the prize ball waiting process 3 described later. In addition, after the execution of the prize ball process 3 in step S234 is completed and the previous payout process is completed, the process of steps S243 to S245 sets the prize ball REQ signal to the OFF state and the invalid command as the prize ball control signal. This is a process for outputting (00 (H)).

  If the value of the prize ball timer is 0, the CPU 56 then checks the contents of the total prize ball number storage buffer (step S247). If the value is 0, the process ends. If not, the value of the prize ball process code is set to 1 (step S248), and the process ends.

  FIG. 29 is a flowchart showing a prize ball transmission process (step S232) executed when the value of the prize ball process code is 1. In the prize ball transmission process, the CPU 56 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step S251). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S252). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S253).

  Thereafter, the output value (10 (H)) during the prize ball REQ is set in the output port 0 buffer (step S254). When the output value in the prize ball REQ is set in the output port 0 buffer, the contents of the output port 0 buffer are outputted to the port 0 in step S203, so that the prize ball REQ signal is turned on and the connection confirmation is made. The on state of the signal is maintained (see FIG. 8). Further, the contents of the winning ball number buffer are set in the lower 4 bits of the output port 0 buffer (step S255). Thereafter, the value of the prize ball process code is set to 2 (step S256), and the process is terminated.

  In this embodiment, the maximum value of the prize ball command is “15”. Accordingly, a prize ball control signal designating the maximum number of payouts of “15” is transmitted to the payout control board 37.

  FIG. 30 is a flowchart showing the winning ball waiting process 2 (step S233) executed when the value of the winning ball process code is 2. In the award ball waiting process 2, the CPU 56 checks whether or not the award ball BUSY signal output (turned on) by the payout control means in response to the award ball REQ being turned on (turned on) ( Step S261). When the on-state is not turned on, a BUSY start determination time value (for example, 2) is set in the prize ball timer (step S262). The BUSY start determination time value is a value for the game control means to confirm that the prize ball BUSY signal has been output (turned on) if the prize ball BUSY signal is on for the time indicated by the value. is there.

  Accordingly, the CPU 56 confirms the value of the prize ball timer when the prize ball BUSY signal is turned on (step S263). If the value is not 0, the CPU 56 decrements the value of the prize ball timer by 1 (step S264). Exit. When the value of the prize ball timer becomes 0, it is determined that the prize ball BUSY signal is turned on, and the contents of the prize ball number buffer are changed from the contents of the total prize ball number storage buffer (the number of prize balls paid out to the payout control means). Is subtracted (step S265). Then, the value of the prize ball process code is set to 3 (step S266), and the process is terminated.

  In the prize ball transmission process shown in FIG. 29 and the prize ball waiting process 2 shown in FIG. 30, the game control means sends a prize ball BUSY signal from the payout control means within a predetermined period after sending the prize ball control signal. When the game is not received, it may be configured to perform control for stopping the progress of the game. Specifically, in the award ball transmission process shown in FIG. 29, the CPU 56 turns on the award ball REQ signal (step S255), and then monitors the award ball BUSY on monitor value (here, the monitor timer is , A timer for detecting the occurrence of a communication abnormality, and the prize ball BUSY ON monitoring value has a margin for the time until the prize ball BUSY signal is turned ON when the payout control means and the communication line are normal. Is a value corresponding to the set time). Then, in the award ball waiting process 2 shown in FIG. 30, the CPU 56 confirms whether or not the award ball BUSY signal is turned on (step S261). To do. When the value of the monitoring timer becomes 0, the CPU 56 assumes that an abnormality has occurred in communication with the payout control means. Specifically, the game 56 assumes that the prize ball BUSY signal has not been turned on. Control to stop the progress of.

  The game control means clears the output state of the output port after saving the current control state, for example, the output state of the output port, in the RAM 55 before stopping the progress of the game. Then, the progress of the game is stopped until the abnormality of communication with the payout control means is resolved. That is, even if a new event (game ball winning or the like) occurs, processing corresponding to the new event is not performed, for example, a newly generated event is stored. Note that the game control means transmits a communication error display command to the effect control means of the effect control board 80 in order to notify the occurrence of communication abnormality using the variable display device 9 or the like before stopping the progress of the game. It may be configured. When the communication abnormality is resolved, the game control means can restore the output port based on the control state stored in the RAM 55.

  FIG. 31 is a flowchart showing the prize waiting process 3 (step S234) executed when the value of the prize ball process code is 3. In the award ball waiting process 4, the CPU 56 checks whether or not the award ball BUSY signal is turned off (step S271). When not in the off state, a BUSY end determination time value (for example, 3) is set in the prize ball timer (step S272). The BUSY end determination time value is a value for creating the period C shown in FIG.

  Therefore, the CPU 56 checks the value of the prize ball timer when the prize ball BUSY signal is turned off (step S273). If the value is not 0, the CPU 56 decrements the value of the prize ball timer by 1 (step S274). Exit. When the value of the prize ball timer becomes 0, that is, when the period C shown in FIG. 22 ends, the prize ball REQ waiting time is set in the prize ball timer (step S275). Then, the value of the prize ball process code is set to 0 (step S276), and the process is terminated. As described above, the award ball REQ waiting time is the waiting time until the next award ball REQ signal is turned on (when award ball payout is continuously performed, the on periods of a plurality of award ball REQ signals are Is a time for providing an interval).

  Through the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. The total award ball number storage buffer corresponds to a prize game medium number storage means for storing stored contents for at least a predetermined period by a backup power source as a variable data storage means when power supply to the gaming machine is stopped. Further, the game control means transmits a payout command signal for designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls stored in the total prize ball number storage buffer. Here, the predetermined number is 15 if the number of prize balls stored in the total prize ball number storage buffer is 15 or more, and is stored in the total prize ball number storage buffer if it is less than 15. The number of prize balls. When a predetermined condition is satisfied, a subtraction process is performed for subtracting the number of payouts specified by the payout command signal from the number of prize balls stored in the total prize ball number storage buffer.

  In this embodiment, the predetermined condition for executing the subtraction process is when a command acceptance signal is received from the payout control means, specifically when the prize ball BUSY signal is turned on. When the prize ball BUSY signal is turned on, the payout control means has not yet paid out the number of prize balls instructed by the payout command signal. If configured to perform subtraction processing of the total prize ball number storage buffer when the winning ball payout is completed, an illegal act of restoring the power supply after illegally stopping the power supply of the gaming machine during paying the winning ball As a result, a large number of prize balls are illegally paid out. For example, when 15 prize ball payouts are instructed by a payout command signal, when 10 prize ball payouts are made, if the power supply is restored after illegally stopping the power supply of the gaming machine, Since the contents of the total number of winning balls storage buffer are not subtracted at all, it is assumed that the ten winning balls are not paid out even though ten winning balls are actually paid out. Control will continue.

  However, in this embodiment, when the prize ball BUSY signal is turned on, that is, when the payout control means accepts a payout command signal and transmits a command acceptance signal, the total prize ball number storage buffer subtraction process is executed. Therefore, the above fraud can be prevented.

  In this embodiment, as the prize game medium number storage means for storing the total number of prize game media to be paid out based on the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of prize game media in an identifiable manner stores the number of prizes received in each prize area, or the number of prizes for each prize area (for example, 6). The number of winning holes 14 corresponding to the number of winning balls, the number of winning holes 33, 39, 29, 30 corresponding to the number of 10 winning balls, and the number of winning prizes corresponding to the number of 15 winning balls, , The number of winning prizes for which the winning ball payout has not ended yet) may be stored.

  Next, the operation of the payout control means (the payout control CPU 371 and peripheral circuits such as ROM and RAM) will be described. FIG. 32 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 32, the output port 0 is an output port for outputting a signal of each phase supplied to the firing motor 94 by the stepping motor and a signal of each phase supplied to the payout motor 289 by the stepping motor. It is. Further, the output port 1 outputs a ball-out LED 52, a prize ball LED 51, a prize ball BUSY signal, a prize ball signal, prize ball information, ball rental information, and a gaming machine error status signal output to the outside of the gaming machine. Output port.

  The output port 2 is an output port for outputting each segment of the error display LED 374 using a 7-segment LED. The output port 3 is an output port for outputting an EXS signal and a PRDY signal to the card unit 50.

  FIG. 33 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 33, a 4-bit prize ball control signal is input to bits 0 to 3 of the input port 0, and a connection confirmation signal from the main board 31 and the main board 31 are respectively input to bits 4 to 7. The award ball REQ signal, the ball break switch 187 detection signal, and the payout motor position sensor 295 detection signal are input. Bits 0 to 3 of the input port 1 respectively include a touch sensor signal (launch control signal) from the touch sensor, a detection signal from the payout count switch 301, an operation signal from the error release switch 375, and a full switch 48. The detection signal is input. The VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 4 to 6 of the input port 1, respectively. An output signal and a power-off signal from the clear switch 921 from the power supply board 910 are input to the input port 2.

  FIG. 34 is a timing chart for explaining the communication between the payout control means of the gaming machine and the card unit 50. The payout control means turns on the PRDY signal when power supply to the gaming machine is started and a payout operation is possible. When the power supply is started, the card unit 50 turns on the VL signal as a connection signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit 50 outputs a BRDY signal to the payout control means. That is, the BRDY signal is turned on. When a predetermined delay time elapses from this point, the card unit 50 outputs a BRQ signal to the payout control means. That is, the BRQ signal is turned on.

  Then, when the payout control means turns on the EXS signal for the card unit 50 and detects the fall (off) of the BRQ signal from the card unit 50, the payout control unit 289 drives the payout motor 289 to set a predetermined number (for example, 25). Pay out the rental balls to the player. Then, when the payout is completed, the payout control means causes the EXS signal to the card unit 50 to fall. That is, the EXS signal is turned off.

  Next, the operation of the payout control means will be described. FIG. 35 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706). . Further, 0000 (H) is set as an initial value of the award ball unpaid number counter (step S707).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 0.7 ms, a value corresponding to 0.7 ms is set in a predetermined register (time constant register) as an initial value.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase.

  Next, the state of the output signal of the clear switch 921 input via the input port 2 is confirmed only once (step S708). In the confirmation, when the on is detected, the payout control CPU 371 executes an initialization process (steps S712 to S715). If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirmation is made (step S709). Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 10). Note that such a confirmation method is an example. For example, a flag indicating that data protection processing has been executed is set in the backup flag area in the power supply stop processing, and the flag is set in step S709. If it is confirmed that there is a backup, it may be determined that there is backup.

  If it is determined that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area (step S710). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S710, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power outage or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state at the time of stopping the power supply, the payout control state restoration processing is not executed, and the initialization processing (steps S712 to S715) is executed.

  If the check result is normal, the payout control CPU 371 performs payout control state recovery processing. Specifically, the value of the award ball unpaid number counter formed in the backup RAM is set as the initial value of the award ball unpaid number counter (step S711). And then. The process after step S712 is executed.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S712). In addition, initial values are set in the flags and counters of the RAM area (step S713). The process of step S713 includes a process of setting an initial value of the award ball unpaid number counter in the award ball unpaid number counter. Therefore, when the payout control state recovery process (step S711) is executed, the value of the unsold prize ball number counter stored in the backup RAM is set again in the unsold prize ball number counter. In other words, the value of the award ball unpaid number counter stored in the backup RAM is used as it is.

  Then, the CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically received (step S714). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S715). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 sets a timer interrupt flag in the timer interrupt process. In the loop process in the main process, when it is detected that the timer interrupt flag is set, the processes after step S750 are executed.

  In step S750, the payout control CPU 371 executes a power-off process for monitoring whether or not a power-off signal is output. Thereafter, a payout control process after step S751 is executed. In the payout control process, the payout control CPU 371 first performs an excitation pattern output process for the firing motor 94 (output of the patterns of the firing motors φ1 to φ4 to the output port 0) (step S750). In the firing motor control process in step S763, the excitation pattern is stored in the excitation pattern buffer which is a RAM area. In step S750, the payout control CPU 371 outputs the contents of the excitation pattern buffer to the lower 4 bits of the output port 0. Perform the process.

  The power-off process is a process similar to the power-off process executed by the game control means (see FIGS. 15 and 16). That is, if the power-off signal from the power supply board 910 is on for a predetermined time counted by the backup monitoring timer, the power supply stop process is executed. In the process when power supply is stopped, the check code (specifically, checksum) is calculated for the RAM area that you want to save even when the power supply is stopped, the check code is stored in the backup RAM area, RAM access is prohibited, and the output port After clearing, loop processing starts. When it is detected that the power-off signal is turned off in the loop processing, the state of the payout control means is the same as when the game control means returns to the state of executing the game control processing (at least from the main board). This includes a process of driving the ball payout device 97 in response to a command signal related to award ball payout, and may include a process of driving the ball payout device 97 in response to a ball lending request. Specifically, for example, the process returns to step S701 of the main process shown in FIG.

  Next, the payout control CPU 371 executes one of task 1 to task 6 according to the value of the switch counter formed in the RAM. In task 1, 3 is set as the number of inputs to be detected in the number of switch checks (step S781), and the address of the firing control signal timer is set in the pointer (step S782). Then, a switch check process is executed (step S761).

  The switch check process is a process for checking the states of the bits 0, 1, and 2 of the input port 1, that is, checking the states of the detection signals of the firing control signal, the payout number count switch, and the error release switch. Specifically, switch timers (launch control signal timer, payout number count switch timer, error release switch timer) corresponding to each of them are formed in the RAM, and it is detected in the switch check process that they are in the ON state. Then, the value of the corresponding switch timer is incremented by 1, and when it is detected that the switch is off, the value of the corresponding switch timer is cleared. In Task 1, since the number of switch checks is set to 3, the status of the detection signal of the firing control signal, the payout number count switch, and the error release switch is checked. In other tasks, one of them is checked. There may be only one or two status checks. Further, the value of the switch timer is determined based on the state of the detection signal of the firing control signal, the payout number count switch, and the error release switch (for example, launch motor control processing, prize ball lending control processing, error processing described later, error In the processing), if the value of the switch timer has reached a predetermined value, it is determined that the switch timer has been turned on.

  Also, the payout control CPU 371 performs input determination processing (step S762). In the input determination process, the states of bits 4 to 6 of input port 0 and bits 3 to 6 of input port 1 (see FIG. 33) are detected, and the detection result is a predetermined 1 byte of RAM (referred to as an input state flag). It is a process to reflect on. In the payout control process, when control is performed based on the states of bits 4 to 6 of input port 0 and bits 3 to 6 of input port 1, the state of the input port is not directly checked, but the input state is checked. Check the status of the flag.

  Next, the payout control CPU 371 executes a firing motor control process (step S763). In the firing motor control process, the patterns of the firing motors φ1 to φ4 are stored in the excitation pattern buffer. When the firing motor 94 should be disabled, the patterns of the firing motors φ1 to φ4 that do not rotate the firing motor 94 are stored in the excitation pattern buffer. Then, control goes to a step S790.

  In task 2, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S764). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S765). Further, a prize ball lending control process for performing a control for paying out a lending ball in response to a ball lending request from the card unit 50 and a control for paying out the number of award balls indicated by a prize ball control signal from the main board. Is executed (step S766). Then, control goes to a step S790.

  In task 3, the payout control CPU 371 sets 1 as the number of inputs to be detected in the switch check number (step S783), and sets the address of the firing control signal timer in the pointer (step S784). Then, a switch check process is executed (step S761). Therefore, in task 3, only the state check of the firing control signal is executed. Next, a firing motor control process is executed (step S763). Also, a payout motor control process is executed (step S768). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed. Then, the payout control CPU 371 executes error processing for detecting various errors (step S769). Also, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S770). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S771). In the display control process, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball REQ signal is on. Further, when the prize ball REQ signal is turned off, control for turning off the prize ball LED 51 is performed.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer, output port 2 buffer) corresponding to the output state of the output port is provided. The contents of the port 0 buffer, output port 1 buffer, and output port 2 buffer are output to the output port (step S772: output processing). However, since the lower 4 bits (fire motors φ1 to φ4) of the output port 0 are executed in step S751, the output of the lower 4 bits of the output port 0 is not performed in the output process. The output port 0 buffer, the output port 1 buffer, and the output port 2 buffer include a payout motor control process (step S768), a prepaid card control process (step S764), a main control communication process (step S765), and an information output process (step S770). And it is updated by the display control process (step S771). Then, control goes to a step S790.

  In task 4, the payout control CPU 371 sets 2 as the number of inputs to be detected in the switch check number (step S785), and sets the address of the payout number count switch timer in the pointer (step S786). Then, a switch check process is executed (step S761). Therefore, in task 4, only the status check of the detection signals of the payout number count switch 301 and the error release switch 375 is executed. Next, input determination processing is executed (step S762), and the process proceeds to step S790.

  In task 5, the payout control CPU 371 sets 1 as the number of inputs to be detected in the switch check number (step S787), and sets the address of the firing control signal timer in the pointer (step S788). Then, a switch check process is executed (step S761). Therefore, in task 3, only the state check of the firing control signal is executed. Next, a firing motor control process is executed (step S763). Further, a prepaid card unit control process is executed (step S764). Next, the payout control CPU 371 executes main control communication processing (step S765). Further, a prize ball lending control process is executed (step S766). Then, control goes to a step S790.

  In task 6, the payout control CPU 371 executes a payout motor control process (step S768). Further, error processing is executed (step S769). Further, an information output process is executed (step S770). Further, display control processing is executed (step S771). Further, output processing is executed (step S772), and the process proceeds to step S790.

  In step S790, after the task counter value is incremented by 1, the process returns to step S716. When the value of the task counter reaches 6, it is reset to 0.

  As described above, in this embodiment, when a timer interrupt occurs, all processes in the payout control process (switch check process, input determination process, firing motor control process, payout motor control process, prepaid card unit control) Process, main control communication process, prize ball lending control process, error process, display control process, output process), depending on the value of the task counter when the timer interrupt occurs Only the part is executed. Therefore, by making the timer interrupt generation period relatively short (for example, 0.7 ms), the process to be executed in a short period (for example, the process in step S751) can be repeatedly executed in a short period. Become. In addition, there is a possibility that processing that cannot be executed if all processing in the payout control processing is executed within the timer interruption period, but processing that cannot be executed occurs by executing only a part. Can be prevented.

  FIG. 39 is a flowchart showing the firing motor control process in step S763. In the firing motor control process, the payout control CPU 371 performs when the VL signal from the card unit 50 is in an off state (no prepaid card is connected) or when the full tank switch 48 is in an on state (bottom plate full). Shifts to step S518 (steps S511, S513). If the prepaid card is not connected and the lower pan is not full, the process proceeds to step S514. In step S514, the payout control CPU 371 checks whether or not the touch sensor signal (launch control signal) is on. If it is in the on state, the process proceeds to step S515, and if it is not in the on state, the process proceeds to step S518.

  In step S515, the payout control CPU 371 increments the firing motor excitation pattern counter by one. Then, data corresponding to the value of the excitation pattern counter is read from the firing motor excitation pattern table stored in the ROM (step S516). Further, the read data is set in the firing motor excitation pattern buffer (step S517). As described above, the contents of the firing motor excitation pattern buffer are output to the output port in step S750. In the firing motor excitation pattern table, the excitation pattern data (shooting motors φ1 to φ4) for each step for rotating the firing motor 94 is sequentially set.

  In step S518, non-rotation data (excitation pattern for preventing the firing motor 94 from rotating) is set in the firing motor excitation pattern buffer.

  As described above, the firing motor 94 is disabled when the prepaid card is not connected or when the lower tray is full, so that the game does not proceed even though they are generated. . It should be noted that the firing motor 94 can also be used when a communication error (connection confirmation signal is off) or a prize ball REQ signal error occurs when the prize ball REQ signal is turned on or off at an incorrect timing. May be disabled so that the game ball cannot be launched into the game area 7.

  FIG. 40 is a flowchart showing the payout motor control process in step S768. In the payout motor control process, the payout control CPU 371 executes any one of steps S521 to S526 in accordance with the value of the payout motor control code.

  In the payout motor normal process (step S521) executed when the value of the payout motor control code is 0, the payout control CPU 371 sets the pointer at the head address of the table stored in the ROM. The payout motor normal process setting table stores a payout motor excitation pattern table in which data of excitation patterns (payout motors φ1 to φ4) of each step for rotating the payout motor 289 at the time of ball payout is sequentially set. Yes.

  In the payout motor start preparation process (step S522) executed when the value of the payout motor control code is 1, the payout control CPU 371 sets bits 4 to 7 of the output port 0 buffer corresponding to the output state of the output port 0. Performs processing such as setting the initial value of the excitation pattern.

  In the payout motor slow-up process (step S523) executed when the value of the payout motor control code is 2, the payout control CPU 371 starts the rotation of the payout motor 289 more smoothly than in the case of the constant speed process. Bit 4 of the output port 0 buffer corresponding to the output state of the output port 0 by reading the contents of the payout motor excitation pattern table at a long interval and gradually approaching the time interval in the case of constant speed processing. Set to ~ 7. At the time of reading, the contents of the payout motor excitation pattern table at the address pointed to by the pointer are read and the value of the pointer is incremented by one.

  In the payout motor constant speed process (step S524) executed when the value of the payout motor control code is 3, the payout control CPU 371 periodically reads the content of the payout motor excitation pattern table and outputs the output state of the output port 0. Are set in bits 4 to 7 of the output port 0 buffer corresponding to.

  In the payout motor brake process (step S525) executed when the value of the payout motor control code is 4, the payout control CPU 371 has a longer interval than in the case of the constant speed process in order to stop the payout motor 289 smoothly. In addition, the contents of the payout motor excitation pattern table are read at a time interval gradually moving away from the time interval in the case of constant speed processing, and bits 4 to 7 of the output port 0 buffer corresponding to the output state of the output port 0 Set to.

  In the ball biting payout motor brake process (step S526) executed when the value of the payout motor control code is 5, the payout control CPU 371 smoothes the payout motor 289 in the case of rotation for releasing the ball biting. The payout motor excitation pattern is longer than the rotation of the payout motor 289 for releasing the ball biting, and gradually away from the time interval in the case of constant speed processing. The contents of the table are read and set in bits 4 to 7 of the output port 0 buffer corresponding to the output state of output port 0.

  FIG. 41 is a flowchart showing the main control communication process in step S765. In the main control communication process, the payout control CPU 371 executes any one of steps S531 to S533 according to the value of the main control communication control code.

  FIG. 42 is an explanatory diagram showing conditions for inputting a prize ball control signal via the input port in the main control communication normal process. As shown in FIG. 42, the main control unconnected error (connection confirmation signal is turned off) in the 1-byte error flag formed in the RAM, the prize ball REQ signal error (the prize ball REQ signal is turned on or off at an incorrect timing) ) Is not in the set state and the BRDY signal from the card unit 50 is not in the on state, the payout is made when the connection confirmation signal is in the on state and the prize ball REQ signal is in the on state. The control means inputs a prize ball control signal via the input port. The error bit is a bit in an error flag that is set when it is detected that various errors have occurred.

  FIG. 43 is a flowchart showing a main control communication normal process (step S531) executed when the value of the main control communication control code is zero. In the main control communication normal processing, when the error bit (main control unconnected error bit or prize ball REQ signal error bit) is on, the payout control CPU 371 ends the processing without executing the subsequent processing. (Step S541). In step S541, if any one of the two bits in the error flag is set, it is determined that the error bit is set.

  If the BRDY signal is on, the payout control CPU 371 ends the process without executing the subsequent processes (step S542). That the BRDY signal is on means that a ball lending request is generated from the card unit 50. That is, when a ball lending request is generated, communication with the game control means of the main board 31 (communication relating to prize ball payout) does not proceed.

  If the conditions of steps S541 to S542 are not satisfied and the connection confirmation signal is on, the payout control CPU 371 confirms whether or not the prize ball REQ signal is on (steps S543 and S544). . If it is in the on state, the number of prize balls indicated by the prize ball control signal is added to the contents of the prize ball unpaid-out number counter (step S545), and processing for turning on the prize ball BUSY signal is performed. (Step S546). Specifically, the bit corresponding to the prize ball BUSY signal in the output port 1 buffer corresponding to the output state of the output port 1 is set to the on state. Then, a prize ball BUSY signal output time (10 in this example) is set in the main control communication control timer (step S547), the value of the main control communication control code is set to 1 (step S548), and the process is terminated. The main control communication control timer is a timer used for monitoring the time related to communication with the game control means of the main board 31. At this stage, the main control communication control timer is used to set a timing for turning off the award ball BUSY signal. The sphere BUSY signal output time is set. The prize ball unpaid-out number counter is formed in a non-volatile (power-backed up in this example) RAM area.

  FIG. 44 is a flowchart showing main control communication processing (step S532) executed when the value of the main control communication control code is 1. In the main control communication process, the payout control CPU 371 checks the state of the prize ball REQ signal if the connection confirmation signal is in the on state (step S551) (step S552). If the prize ball REQ signal is off, the prize ball REQ signal error bit in the error flag is set (step S553). This is because it is strange that the prize ball REQ signal is immediately turned off at this stage.

  Next, the payout control CPU 371 checks the value of the main control communication control timer (step S554), and if not 0, subtracts 1 from the value of the main control communication control timer (step S555) and ends the process. If the value of the main control communication control timer is 0, processing for turning off the prize ball BUSY signal is performed. Specifically, the bit corresponding to the prize ball BUSY signal in the output port 1 buffer corresponding to the output state of the output port 1 is set to the OFF state (step S556). Also, a prize ball REQ signal OFF monitoring time (24 in this example) is set in the main control communication control timer (step S557). Then, the value of the main control communication control code is set to 2 (step S558), and the process ends.

  FIG. 45 is a flowchart showing a main control communication end process (step S533) executed when the value of the main control communication control code is 2. In the main control communication process, when the error bit (main control unconnected error bit or prize ball REQ signal error bit) is on, the payout control CPU 371 proceeds to step S567 (step S561). Moreover, also when a connection confirmation signal is an OFF state, it transfers to step S567 (step S562). If both error bits are off and the connection confirmation signal is on, it is checked whether or not the prize ball REQ signal is off (step S563). When it is turned off, the process proceeds to step S567.

  If the prize ball REQ signal is not turned off, the value of the main control communication control timer is confirmed (step S564). If the value of the main control communication control timer is not 0, the value of the main control communication control timer is decremented by 1 (step S565). If the value of the main control communication control timer is 0, it is determined that the prize ball REQ signal has not been turned off within the monitoring time, and the prize ball REQ signal error bit is set in the error flag (step S566). Transition.

  In step S567, the value of the main control communication control code is set to 0, and the process ends.

  FIG. 46 is a flowchart showing the prize ball lending control processing in step S766. In the winning ball lending control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S601). The value is decremented by 1 (steps S602 and S604), and if the ball is not being lent, the value of the unpaid prize ball counter is decremented by 1 (steps S602 and S603). Next, the payout ball detection bit of the payout control state flag formed in the RAM is set (step S605). The payout ball detection bit is a game regardless of whether the payout motor 289 is driven in one payout ball payout process (up to 15 balls) or one ball lending process (25 payouts) in the payout passing waiting process. This is used to detect that no sphere has passed through the payout number counting switch 301. Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  FIG. 47 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if the error bit is set (step S621). The error bit in the error flag includes a main board non-connection error bit. The main board non-connection error is set when the connection confirmation signal from the main board 31 is in the OFF state. Therefore, the payout control means starts substantial control on condition that the connection confirmation signal is turned on after power supply to the gaming machine is started.

  On the other hand, if the BRDY signal is not in the on state, processing for paying out a prize ball after step S631 is executed. If the BRDY signal is on and the BRQ signal that is a ball lending request signal is on, a ball lending operation flag is set (steps S623 and S624). Then, “25” is set in the unpaid ball lending number counter (step S625), and “25” is set in the payout motor rotation number buffer (step S626).

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S768). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. It is set (step S627), the value of the payout control code is set to 1 (step S628), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the value of the award ball non-payout counter is 0 (step S631). If 0, the process ends. The prize ball unpaid-out counter is a value other than 0 (the number indicated by the prize ball control signal) when the prize ball REQ signal is received from the game control means of the main board 31 in step S546 in the main control communication normal process. ) Is added. If the value of the award ball unpaid number counter is not 0, it is confirmed whether it is 15 or more (step S632). If it is less than 15, the value of the award ball unpaid number counter is set in the payout motor rotation count buffer (step S633), and if it is 15 or more, “15” is set in the payout motor rotation count buffer. Then, a winning ball operating flag is set (step S635), and the process proceeds to step S637.

  FIG. 48 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (step S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and whether the payout operation is completed by checking the flag in step S641. You can check whether or not.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  49 to 51 are flowcharts showing the payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, when a prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is zero. If the value of the award ball unpaid-out counter is not 0, if it is not in an error state, a re-payout operation of one game ball is tried up to 2 times. In the re-payout operation, when it is detected by the payout number count switch 301 that the game ball is actually paid out, it is determined that the payout has been completed normally. In this embodiment, the maximum number of game balls to be paid out in one prize ball payout operation is 15, and if a prize ball control signal is received during the prize ball payout, the value of the prize ball unpaid number counter Therefore, even when the payout is completed normally, the value of the award ball non-payout number counter may not be 0.

  Further, when the ball lending is being paid out, it is determined that the payout has been completed normally if the value of the ball lending unpaid-out counter is 0. If the value of the ball lending unpaid number counter is not 0, and if it is not in an error state, a re-payout operation of one game ball or the remaining number of ball lending (corresponding to the value of the ball lending unpaid number counter) Try. In this embodiment, the number of game balls to be paid out in one ball lending and payout operation is 25 (fixed value), and the payout motor 289 is rotated so that 25 game balls are paid out. Therefore, when the value of the unpaid ball lending counter is not 0, the payout has not been completed normally.

  In the payout waiting process, the payout control CPU 371 first checks the value of the payout control timer, and if the value is 0, the process proceeds to step S653 (step S650). If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S651). If the value of the payout control timer is not 0 (step S652), that is, if the payout control timer has not timed out, the process is terminated. Note that the process of step S650 is a process that takes into account when a game ball payout retry operation to be described later is started. When the process of step S807 described later is executed, a retry operation is started through a route that moves from step S650 to S653.

  If the payout control timer has timed out (step S652), it is confirmed whether or not the ball lending payout process (ball lending operation) has been executed (step S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation in progress flag in the payout control state flag formed in the RAM is set. When the ball lending operation is not executed, that is, when the prize ball payout process (prize ball operation) is executed, the payout control CPU 371 checks the value of the award ball unpaid number counter (step S654). ). When the value of the winning ball unpaid-out counter is 0, it is determined that the winning ball payout process has been completed normally, and the payout ball detection bit in the payout control state flag, 1 bit during re-payout operation, and during re-payout operation 2 bits, the winning ball operating flag and the ball lending operating bit are reset (step S655), the payout control code is set to 0 (step S656), and the process is terminated. This bit is set when the switch 301 is turned on, and indicates that the payout number counting switch 301 has detected at least one game ball during the payout operation. Further, 1 bit during the re-payout operation and 2 bits during the re-payout operation are control bits used when executing a re-payout process including two re-payout operations.

  The payout control CPU 371 determines that an error flag (specifically, a payout switch error error 1 bit, a payout switch error error 2 bit, and a payout case error bit when the value of the award ball unpaid number counter is not 0. (One or a plurality of bits) is not set (step S658), and if the payout ball detection bit is not set (step S661), the re-payout operation is executed. To do. If the error flag is set, the re-payout operation is not executed.

  As described above, in this embodiment, even when the payout is completed normally, the value of the unpaid prize ball number counter may not be 0. Therefore, if the payout ball detection bit is set, that is, if the payout number count switch 301 detects the payout of at least one game ball during the prize ball payout process, it is assumed that the prize ball payout process is normally completed. The process proceeds to step S655. For example, when 15 game balls should be paid out in one prize ball payout process, when only 14 game balls are actually paid out (the number of payout count switch 301 is 14 game balls). In this case, the payout ball detection bit is set, so it is considered that the award ball payout process has been completed normally. It should not have been done, and the shortage will be paid out in the next prize ball payout process, so there will be no disadvantage to the player.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not 2 bits during re-payout operation are set (step S662). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S663). If 1 bit is not set during the re-payout operation, 1 is set as the number of re-payout operations to execute the first re-payout operation (step S664), and 1 bit is set during the re-payout operation (step S665). ) The value of the re-payout operation number or the ball lending unpaid-out number counter is set in the payout motor rotation number buffer (step S666). The payout motor rotation frequency buffer is referred to in the payout motor control process (step S768). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer. In step S666, the value of the unpaid ball lending number counter is also handled because step S666 is used in the re-payout process in the lend-out process. That is, in step S666, the payout control CPU 371 sets the re-payout operation number in the re-payout process in the prize ball payout process, and sets the value of the ball lending unpaid-out number counter in the re-payout process in the ball lending payout process. . Thereafter, the payout control code is set to 1 (step S667), and the process is terminated.

  In step S663, when it is confirmed that 1 bit is set during the re-payout operation, the payout control CPU 371 sets 1 as the re-payout operation number in order to execute the second re-payout (step S668). Then, 1 bit is reset during the re-payout operation (step S669), and 2 bits are set during the re-payout operation (step S670). Then, control goes to a step S666.

  When it is confirmed in step S662 that 2 bits are set during the re-payout operation, the payout control CPU 371 does not pay out the game ball even if the re-payout process is executed twice (payout number count switch). 301 has not detected a game ball), a payout case error bit in the error flag is set (step S672). At that time, 2 bits are reset during the re-payout operation (step S671). Then, the process ends.

  As described above, if no game balls are paid out even if two re-payout operations are performed in the re-payout process (corrected payout process), it is assumed that the game ball payout operation is defective and the payout number count switch is not A passing error bit (payout case error bit) is set.

  Therefore, in this embodiment, the prize game medium payout control means in the payout control means indicates that the prize game medium has not been paid out based on the detection signal from the payout number count switch 301 as the payout detection means. When it is detected, control is performed so that the payout means pays out one prize game medium up to a predetermined number of times (in this example, twice) as a limit. In this embodiment, if the prize game medium is not paid out even if the retry operation for paying out the prize game medium is performed twice, the payout case error bit is set and an error is being generated. (Step S672), the payout case error bit may be set when it is first detected that the premium game medium has not been paid out.

  In the winning ball lending control process, the error bit is checked to determine whether or not to perform a payout operation (one winning ball payout or one ball lending). The payout start shown in FIG. Only in the waiting process. In the payout motor stop waiting process shown in FIG. 48 and the payout passing wait process shown in FIG. 49 and the like, the error bit is not checked. Note that the error bit is also checked in step S658 and the like in the payout passing waiting process, but this check is for determining whether or not to perform a payout operation again, and is a payout operation (single prize ball payout or 1 This is not to determine whether or not to start ball lending. Therefore, after the process of step S626, S633, or step S634 is performed and the game ball payout process is started, the payout process is not interrupted even if an error occurs. In other words, when an error occurs, the game ball payout process is continued until a point at which the game ball can be cut well (at the time when one prize ball payout or one ball lending ends). The error bits in the error flag checked in step S621 include an error bit indicating that the connection confirmation signal from the main board 31 has been turned off. Therefore, even when the connection confirmation signal is turned off, the game ball payout process is stopped at a time when it is best to turn it off.

  Upon confirming that the ball lending / dispensing process (ball lending operation) has been executed in step S653, the payout control CPU 371 confirms whether or not the value of the unlapped ball lending number counter is 0 (step S657). . If it is 0, it is determined that the ball lending / dispensing process is normally completed, and the process proceeds to step S655.

  If the value of the ball lending unpaid number counter is not 0, an error flag (specifically, any one bit of the payout switch abnormal error 1 bit, the payout switch abnormal error 2 bit, and the payout case error bit) On the condition that (multiple bits) is not set (step S675), the re-payout process is executed. If the error flag is set, the re-payout process is not executed.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not 2 bits during re-payout operation are set (step S676). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S677). If 1 bit is not set during the re-payout operation, 1 is set as the number of re-payout operations to execute the first re-payout operation (step S678), and 1 bit is set during the re-payout operation (step S669). ) After further resetting the payout ball detection bit (step S680), the process proceeds to step S666.

  In step S677, when it is confirmed that 1 bit is set during the re-payout operation, the payout control CPU 371 performs a process for re-executing the re-payout operation. Specifically, 1 bit is reset during the re-payout operation (step S681). If the payout ball detection bit is set, that is, if the game ball is paid out in the first re-payout operation, the process proceeds to step S683. If the payout ball detection bit is not set, the process proceeds to step S684 to execute the second re-payout operation.

  In step S683, the payout ball detection bit is reset, and then the process proceeds to step S666. Therefore, in this case, since 1 bit remains set during the re-payout operation, the first (first) re-payout operation is performed again. In step S684, 1 is set as the number of re-payout operations (step S684), 2 bits during re-payout operation are set (step S685), and the process proceeds to step S666.

  In step S676, when it is confirmed that the 2 bits during re-payout operation are set, the payout control CPU 371 resets 2 bits during the re-payout operation (step S686), and if the payout ball detection bit is set, That is, if the game ball is paid out by the re-payout operation, the process proceeds to step S683 to try to eliminate the remaining unpaid out. If the payout ball detection bit is not set, it is determined that the game ball has not been paid out even if the re-payout process is executed twice (the payout number count switch 301 has not detected a game ball). A payout case error bit is set (step S688). Then, the process ends.

  As described above, if one game ball is not paid out even if two re-payout operations are continuously performed in the re-payout process (corrected payout process) related to the ball lending process, a game ball payout operation is performed. As a failure, a payout count switch non-passing error bit (payout case error bit) is set.

  FIG. 52 is a timing chart for explaining the ball biting detection process executed in the payout motor control process (step S768). In the payout motor constant speed process (step S524) in the payout motor control process, the payout control CPU 371 monitors the detection signal of the payout motor position sensor 295. The detection signal of the payout motor position sensor 295 is turned on twice, for example, every time the cam that rotates in conjunction with the payout motor 289 rotates once. In order for the detection signal to be output twice each time the cam rotates once, the cam has two locations in the portion that receives light from the light emitting portion in the payout motor position sensor 295 (positions symmetrical with respect to the axis). Is provided with a reflector. The output of the light receiving unit in the dispensing motor position sensor 295 is used as a detection signal.

  Therefore, even if the payout control CPU 371 gives an excitation pattern having a step number of 1/2 rotation or more to the payout motor 289, the detection signal of the payout motor position sensor 295 does not turn on. Actually, the payout motor 289 does not rotate due to foreign matter such as dust adhering to the cam portion and the like, and the game ball is clogged (ball biting has occurred). As a result, the cam rotates. It can be judged that it is not.

  In this embodiment, when the payout motor 289 receives an excitation pattern for 16 steps (2.087 ms per step), it makes one rotation and pays out one game ball. For example, as shown in FIG. 52, the payout control CPU 371 checks the detection signal of the payout motor position sensor 295 every time the payout motor 371 gives an excitation pattern for 8 steps to the payout motor 289. Thus, it is determined whether or not the payout motor 289 is rotating. Then, if the same state is detected five times continuously (the detection signal of the dispensing motor position sensor 295 is turned off five times continuously or turned on five times continuously), it is determined that ball engagement has occurred. A ball biting release process is executed.

  As shown in FIG. 53, the payout control CPU 371 repeats a process of rotating the payout motor 289 at a high speed and a process of rotating at a low speed a predetermined number of times (for example, 9 times). Each time an excitation pattern for 8 steps is given to the payout motor 289, the detection signal of the payout motor position sensor 295 is checked to determine whether or not the payout motor 289 is rotating. If it is determined by the detection signal that the rotation of the payout motor 289 has been restored, the ball biting release process is terminated, and the normal ball payout process returns.

  If there is no change in the detection signal of the payout motor position sensor 295 even if the high speed rotation process and the low speed rotation process are executed a predetermined number of times, a ball biting error bit (payout case error bit) in the error flag Set. When the payout case error bit is set, the payout control CPU 371 does not drive the payout motor 289. When the payout case error bit is reset (see step S807 in FIG. 55), the payout control CPU 371 returns to a state in which the payout motor 289 can be driven.

  Thus, the payout control means includes a drive state monitoring means for monitoring the operating state of the payout means, and a drive stop means for stopping the driving of the payout means when the drive state monitoring means detects a malfunction of the payout means. Including.

  Next, error processing will be described. FIG. 54 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 54, when the connection confirmation signal from the main board 31 is turned off, the payout control CPU 371 displays “1” on the error display LED 374 as a main board non-connection error. I do. When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above. When the prize ball REQ signal is turned on at an improper timing or when the prize ball REQ signal is turned off at an improper timing, “5” is displayed in the error display LED 374 as a prize ball REQ signal error. Control to display. A specific method for detecting that the prize ball REQ signal is turned on or off at an incorrect timing is as described above.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit unconnected error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S764).

  Among the above errors, after the occurrence of a payout switch abnormality detection error 2, a payout case error or a prize ball REQ signal error, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (becomes turned on). The payout control means returns to the state before the error occurred.

  FIG. 55 is a flowchart showing the error processing in step S769. In the error processing, the payout control CPU 371 checks the error flag, and the set bits are only payout switch abnormality detection error 2, payout case error and prize ball REQ signal error (any one of the three). It is confirmed whether it is only a bit, or only two bits out of three, or only these three bits (step S801). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (step S802). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S803). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S804). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S808. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S805). If the pre-error recovery timer value becomes 0 (step S806), the payout switch of the error flag is set. The bits of the abnormality detection error 2, the payout case error and the prize ball REQ signal error are reset (step S807), and the process proceeds to step S808.

  When the processing of step S807 is executed, there may be an error bit that is not in the set state among the bits of the payout switch abnormality detection error 2, the payout case error, and the prize ball REQ signal error. There is no problem resetting error bits that are not in the state. As described above, in this embodiment, when an error (see FIG. 54) that causes the setting of the payout switch abnormality detection error 2, the payout case error, or the prize ball REQ signal error bit occurs, an error occurs. The error is released when the release switch 375 is pressed.

  When the process of step S807 is executed and the payout case error bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 49 to 51), and the prize ball When the value of the unpaid-out number counter or the value of the ball-lending unpaid-out number counter is not 0, a retry operation for game ball payout is started. That is, when the award ball lending control process of step S766 is executed next, when the payout passing waiting process of step S612 is executed, the repayment process is performed again. For example, if a prize ball payout process has been performed and the value of the prize ball unpaid number counter is not 0, the process proceeds from step S654 to step S659, and it is confirmed in step S659 that the error bit is in a reset state. Therefore, the process for starting the re-payout process after step S662 is executed again, and the re-payout process is executed. Regarding the payout case error bit reset by pressing the error release switch 375, when the bit is set (when step S672 is executed), the payout control timer has already expired. Therefore, when the process in step S807 is executed and the payout case error bit is reset, the payout control timer = 0 is determined in the determination in step S652 when the payout passage waiting process is executed next. Further, when the payout case error bit is set, the payout ball detection bit is 0 (since step S672 is not executed unless the payout ball detection bit is 0 according to the determination in step S661). Therefore, step S662 is always executed whenever it is confirmed in step S659 that the error bit is in the reset state. That is, the re-payout process is always executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When it is detected (see step S661 and thereafter in FIG. 50), the control state related to payout is shifted to an error state, and corrected payout control is performed again on condition that an error release signal is output from the error release switch 375 in the error state. A correction payout control restart process for executing

  Further, even during execution of the re-payout process in the error state (specifically, during the re-payout process before setting the payout case error and during the re-payout process after the error release switch 375 is pressed), steps S601 to S601 shown in FIG. The process of S604 is being executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the award ball unpaid number counter or the ball lending unpaid number counter is subtracted. Therefore, the value of the award ball unpaid number counter or the ball lending unpaid number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Further, in the payout passing waiting process shown in FIGS. 49 to 51, even when it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) (steps S802 and S807). That is, the state of the payout case error (payout shortage error) is not automatically canceled based on the fact that the game ball has passed the payout number count switch 301, etc. The error is not cleared. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred.

  When the error cancel switch 375 is operated so as to be reset in hardware (reset to the payout control CPU 371), the error cancel switch 375 is operated, for example, a prize ball has not been paid out. The value of the number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S808, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (step S809). If the detection signal of the full tank switch 48 is in the OFF state, the full tank error bit is reset (step S810).

  Also, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S811). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S812). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (step S813). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port 1 buffer is set to a value corresponding to the lighting state in the display control processing in step S771.

  Further, the payout control CPU 371 checks the state of the connection confirmation signal from the main board 31 (step S815). If the connection confirmation signal is not output (if it is in the off state), the main board unconnected error bit is set. Set (step S816). If the connection confirmation signal is output (if it is on), the main board non-connection error bit is reset (step S817).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 240 ") (step S818), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S819). If the value of the switch timer corresponding to the payout number count switch 301 is less than the switch-on maximum time, the bit of the payout switch abnormality detection error 1 is reset (step S820). Note that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the switch check processing of step S761, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371, when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (eg, “2”) (step S821), the ball lending operation flag and the winning ball operation If both the middle flags are in the reset state, the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 in the error flag is set (steps S822 and S823). . If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S824).

  Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S825). If the VL signal is not input (if it is in the OFF state), the prepaid card unit not yet out of the error flags is displayed. A connection error bit is set (step S826). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S827).

  In the display control process of step S771, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374. In this embodiment, the game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 perform bi-directional communication with respect to prize ball payout, but a communication error is indicated by an error display LED 374. Can be notified.

  Further, since the communication error is detected on the payout control means side, even if the game control means and the payout control means perform bi-directional communication with respect to the prize ball payout, the communication without increasing the burden on the game control means. Can detect errors.

  In this embodiment, the main board unconnected error is automatically eliminated when the connection confirmation signal is turned on (see steps S815 and S817), but the condition that the error cancel switch 375 is further operated is added. Thus, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit unconnected error and a prepaid card unit communication error) and other errors (see FIG. 54). ). Therefore, a communication error between the game control unit and the payout control unit is easily identified.

  In this embodiment, the error display LED 374 mounted on the payout control board 37 installed on the back side of the gaming machine is informed that an error relating to the payout has occurred. You may mount an alerting | reporting means in other locations (For example, the payout unit in which the ball payout apparatus 97 etc. were concentratedly arranged). Furthermore, you may make it alert | report by the indicator (for example, prize ball LED51) installed in the front side of the gaming machine. In the display control process, the payout control CPU 371 performs control for turning on the prize ball LED 51 when the prize ball REQ signal is on. When the prize ball REQ signal is off, the prize ball LED 51 is displayed. Control for turning off the light is performed. When an error relating to payout occurs, for example, the prize ball LED 51 is blinked to notify that an error related to payout has occurred. If an error is notified by a display device installed on the front side of the gaming machine, the game shop clerk can more easily recognize the occurrence of the error. Moreover, you may use together the alerting | reporting by error display LED374, and the alerting | reporting by the indicator installed in the front side of the gaming machine.

  FIG. 57 (A) is a timing chart showing a state of occurrence of a payout case error (payout shortage error), and FIG. 57 (B) is a timing chart showing a state when the error release switch 375 is operated.

  As shown in FIG. 57 (A), the payout motor 289 is rotated in order to pay out a predetermined number of game balls, and after the stop of the rotation, the game ball that should have been paid out last has passed through the payout number count switch 301. Later (after 402.087 ms in this example), it is confirmed whether or not there is an unpaid game ball (corresponding to the determination in step S654), and if there is an unpaid game ball, a re-payout operation is executed. FIG. 57 (A) shows an example in which two re-payout operations are executed. When two re-payout operations are executed, it is determined as a payout case error (corresponding to the determination in step S672), and “4” is displayed on the error display LED 374 by the display control processing in step S771 (FIG. 54).

  As shown in FIG. 57B, when the error release switch 375 is operated, the re-payout operation is started again after the error release time has elapsed. As shown in FIG. 57B, when the re-payout operation is started again, the display of “4” on the error display LED 374 is erased. That is, when the corrected payout control is performed after the operation of the error release switch 375, a notification indicating an insufficient payout error is not performed.

  58 and 59 are flowcharts showing the display control process (step S771). In the display control process, the payout control CPU 371 adds 1 to the value of the 1-byte blinking timer formed in the RAM (step S571). If the ball break error bit is set in the error flag (step S572), the ball break LED output bit in the output port 1 buffer is set (step S573). If the ball break error bit is not set, the ball break LED output bit in the output port 1 buffer is reset (step S574). Note that the contents of the output port 1 buffer are output to the output port 1 in the output process of step S772.

  Further, when the main control unconnected error bit is not set (step S575), the payout control CPU 371 determines that the winning ball is being paid out (the winning ball operating flag in the payout control state flag is set) (step S575). In step S576, the prize ball LED output bit in the output port 1 buffer is set (step S577). If no prize ball is being paid out, the prize ball LED output bit in the output port 1 buffer is reset (step S578).

  Further, the payout control CPU 371 has set bits other than the respective bits of the payout switch abnormality detection error 2, the payout case error, and the winning ball REQ signal error (error that can be canceled by the error cancel switch 375) in the error flag. In step S585, the process proceeds to step S585. If bit 7 of the blinking timer is “1” when the bit set in the error flag is one or more of payout switch abnormality detection error 2, payout case error and prize ball REQ signal error ( In step S580), a prize ball LED output bit in the output port 1 buffer is set (step S581). If bit 7 of the blinking timer is not “1”, the prize ball LED output bit in the output port 1 buffer is reset (step S582). When an error that can be corrected by an artificial operation has occurred by the processing of steps S579 to S581, that effect is notified from the player or the like so as to be visible. In this embodiment, the prize ball LED 51 is notified by blinking. Therefore, the player or the game store clerk can easily recognize that an error has occurred so that the error can be canceled by a manual operation and the gaming machine can be returned to the normal state.

  Further, the payout control CPU 371 loads an error flag (step S585), determines an error code (7SEG display code; see FIG. 54) corresponding to the error bit in the error flag (step S586), and determines the determined error code. The output port 2 is set in the output buffer (step S587).

  FIG. 60 is a flowchart showing a portion related to output of prize ball information (prize ball signal) as a prize ball number signal in the information output process (step S770). The prize ball signal is output from the payout control board 37 to the outside of the gaming machine via the terminal board 160.

  In the information output process, the payout control CPU 371 checks whether or not the value of the signal output timer is 0 (step S831). The signal output timer is a timer for setting an ON period of one pulse prize ball signal. That is, that the value of the signal output timer is not 0 indicates that a prize ball signal is being output. When the value of the signal output timer is not 0, the value of the signal output timer is subtracted (step S841). When the value of the signal output timer becomes 0 (step S842), the prize ball signal is turned off (step S842). Step S843).

  If the value of the signal output timer is 0, it is confirmed whether or not the ball lending operation flag is set (step S832). When the ball lending operation flag is not set, if the payout number count switch 301 is turned on (if the game ball passes), the value of the prize ball payout number counter is incremented by 1 (steps S833 and S834). The prize ball payout number counter is a counter formed in the RAM.

  When the value of the prize ball payout number counter reaches 10 (step S835), the value of the prize ball payout quantity counter is cleared, the prize ball signal is turned on (step S837), and the signal output timer is set to the prize output timer. The on period value of the sphere signal is set (step S838). As a result of the above processing, one prize ball signal is output every time ten game balls as prize balls are paid out. As described above, when the payout control means detects that a predetermined number (10 in this example) of game balls have been paid out based on the detection signal of the payout count switch 301, the payout control means indicates the number. The prize ball signal is output to the outside of the gaming machine. In this embodiment, the predetermined number is 10. However, other numbers may be used as the predetermined number. Further, there may be a plurality of predetermined numbers. For example, when 10 game balls are instructed to be paid out and 10 game balls have been paid out, a first prize ball signal is output, and 15 game balls are instructed from the game control means. The predetermined number is 10 and 15 when the second prize ball signal is output when the game balls are paid out.

  In the information output process, error bit checking is not executed. Therefore, even in an error state related to payout of game balls, a prize ball signal is output every time 10 game balls as prize balls are detected by the payout number count switch 301. Therefore, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed outside the gaming machine. In addition, when the error cancel switch 375 is operated and the hardware is reset (reset to the payout control CPU 371), the payout of the winning ball is performed by operating the error cancel switch 375. The value of the number counter is also cleared. However, in this embodiment, the payout control means is configured such that the error can be released by operating the error release switch 375, and the winning ball payout number counter is not cleared when the error is released. Therefore, the game ball actually paid out is accurately reflected in the prize ball signal. In addition, even in an error state related to payout, the number of game balls actually paid out can be ascertained outside the gaming machine, so that an illegal act that causes an error related to payout and illegally pays out game balls is performed. This is easily detected.

  Also, the prize ball payout number counter is incremented by 1 when the payout number count switch 301 detects a game ball in a state where the ball lending operation flag is not set. Therefore, not only when the winning ball operating flag is set (pending a winning ball), but also when the winning ball operating flag or the lending ball operating flag is not set (both winning or paying a ball) When the payout number count switch 301 detects a game ball, the value is incremented by one. In other words, when the payout number counting switch 301 detects a game ball when it is neither paying out a ball nor lending a ball, it is considered that a game ball has been paid out by paying out a prize ball, and is outside the gaming machine (for example, a hall computer). It is reflected in the output prize ball signal. In this way, the game balls actually paid out are always reflected in the signal output to the outside of the gaming machine, and are therefore always reflected in the total result of the number of payouts at the game store, for example. Note that when the payout number count switch 301 detects a game ball when it is neither paying out a prize ball nor lending a ball, it may be considered that a game ball has been paid out based on a lending ball request.

  In the above-described embodiment, the game control means relates to the transmission of the payout command signal (specifically, the prize ball BUSY signal is turned on in response to the transmission of the payout command signal). Since the subtraction process (see steps S261, S263, and S265 in FIG. 30) is performed, even if an unexpected power supply stoppage occurs due to a power failure or the like, it is possible to minimize the disadvantage given to the player and to perform illegal acts. It can be effectively prevented. In other words, the total award ball number storage buffer in which the number of unpaid prize game media is set is formed in the backup RAM in the game control means, so even if the power supply to the gaming machine is stopped, a predetermined period (backup power supply The content is saved within the duration), and when the power supply is restored, the game control means can resume the winning ball processing based on the saved content of the total number of winning balls stored. That is, if the content of the stored total number of winning balls is not 0, a payout command signal can be output to the payout control means.

  For example, if the subtraction process for the number of unpaid prize game media is executed based on the receipt of the payout completion signal, the payout control means starts illegal payout after sending a prize ball payout based on the payout command signal. The number of unpaid prize game media that have not been subtracted if an action is made to restore the power supply after the power supply is stopped or the game control means is illegally reset once. Based on this, the prize ball payout is executed twice. However, if the subtraction process for the number of unpaid prize game media is executed based on the receipt of the payout completion signal, the prize ball payout is not executed twice even if such an illegal act is performed.

  Furthermore, in the above embodiment, the output of the payout number count switch 301 is input only to the payout control board 37. Therefore, compared with the case where the output of the payout number count switch 301 is supplied to both the main board 31 and the payout control board 37, the circuit configuration is simplified and the cost can be reduced.

  In addition, the game control means is configured to output a control signal (connection confirmation signal) indicating that power supply to the gaming machine has started to the payout control means at the start of power supply. The payout control means can recognize that the supply has started and the control operation of the game control means has started.

  In the above embodiment, the payout request is made by the prize ball REQ signal and the number of payouts is specified by the prize ball control signal. However, the payout request and the number of payouts are designated by the prize ball control signal. May be. In this case, the payout control means may determine that the payout request is made at the same time when the prize ball control signal is output. According to such a configuration, it is not necessary to use the prize ball REQ signal.

  In the above embodiment, the software delay processing and the delay by the delay circuit 69 (delay by the hardware circuit) are used in combination. However, the software delay processing may be delayed by either software or hardware. .

  Further, in the above embodiment, the payout control means monitors the state of the connection confirmation signal from the game control means, and the payout control indicates that an abnormality has occurred with respect to signal communication between the game control means and the payout control means. Since the means is configured to detect, the payout control means can reliably detect that an abnormality has occurred with respect to signal communication with the game control means.

  In the above embodiment, since the payout control means outputs the prize ball BUSY signal in response to receiving the prize ball control signal, the game control means indicates that the payout process is started by the payout control means. It can be easily grasped.

  Further, in the above embodiment, when the payout control means is in an error state due to the occurrence of a predetermined abnormality, it monitors an error release signal (for example, an operation signal corresponding to the operation) from the error release switch 375 to detect an error. Since the error state is canceled when the input of the release signal is detected, the payout control means recognizes the error release signal, the error is released, and the memory content of the payout control means can be prevented from being cleared. As a result, it is possible to prevent the player from being disadvantaged by the switch operation for canceling the error.

  In the above embodiment, the error cancel signal from the error cancel switch 375 is input to the payout control means, and the payout control means executes the error cancel processing. And the cancellation of the error state can be executed by the payout control means, and the configuration for detecting the error and canceling the error state can be simplified.

  In the above embodiment, an error display is displayed when an abnormality relating to communication between the game control means and the payout control means occurs and when an abnormality relating to communication with the card unit 50 occurs. Since the LED 374 is used to make a distinction notification, any one of the abnormality related to the communication of the signal between the game control means and the payout control means and the abnormality related to the communication with the card unit 50 is selected. A game store clerk or the like can easily recognize whether or not this has occurred.

  In the above embodiment, the payout control means determines that the prize ball payout has ended when it detects that the payout motor 289 has rotated by the planned payout number. However, the number of times detected by the payout motor position sensor is the expected payout number. If it reaches, it may be determined that the prize ball payout has ended. That is, the payout control means is configured to determine whether or not the payout has been completed by detecting the operation amount of the payout means (in this example, the rotation amount of the payout motor 289 or the number of detections by the payout motor position sensor). May be.

  Further, in the above embodiment, the payout control means confirms that the game ball has been paid out based on the detection signal of the payout count switch 301, but the game ball is based on the output signal of the payout motor position sensor. You may make it confirm that was paid out.

  Also, the payout control means detects the operation amount of the drive means (for example, payout motor 289, cam, etc.) of the payout means, and determines whether or not an abnormality related to payout (payout unit error) has occurred based on the detected amount. It may be configured to. With such a configuration, it is possible to reliably detect an abnormality relating to payout.

  In the above embodiment, the ball payout device 97 is configured to execute both ball lending and prize ball payout. However, even if the mechanism for lending the ball and the mechanism for paying the prize ball are independent, The invention can be applied.

  In the above-described embodiment, the payout is prohibited when the ball is out of the ball or the lower pan is full. However, when it is not preferable to perform another payout or when the payout cannot be performed, You may set it in a payout prohibition state. For example, the payout prohibition state may be set also when the glass door frame 2 is in an open state and a detection signal is output from a door opening switch for detecting this.

The above-described embodiment includes the following configuration.
Communication abnormality detecting means for detecting an abnormality related to game medium payout (for example, payout switch abnormality detection error 1, payout switch abnormality detection error 2, payout case error), and when the communication abnormality detection means detects an abnormality, A gaming machine including error control means for setting an error occurrence state and communication abnormality notification means for notifying that when the communication abnormality detection means detects an abnormality.

  In each of the above-described embodiments, the recording medium used in the recording medium processing apparatus (card unit 50) is a magnetic card (prepaid card). However, the recording medium is not limited to a magnetic card, and is a non-contact type or a contact type. An IC card may be used. In addition, when the recording medium processing device is configured to be able to identify the recording information based on the identification code, the recording medium can be read at least by the recording medium processing device such as an identification code that can identify the recording information It may be something that can be recorded on. Further, the recording medium may be a medium on which a predetermined information recording symbol such as a barcode is printed so as to be readable. The shape of the recording medium is not limited to a card shape, and may be any shape such as a disk shape, a spherical shape, or a chip shape.

  The pachinko gaming machine of each of the above embodiments mainly gives a player a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display unit 9 based on the start winning is a combination of the predetermined symbols. It was a first type pachinko game machine that can be used, but if there is a prize in a predetermined area of an electric game that is released based on a start prize, a second type pachinko game that can give a predetermined game value to a player 3rd type pachinko game where a predetermined right is generated or continued when there is a prize for a predetermined electric game that is released when the stop symbol of the pattern variably displayed based on the machine or the start winning combination becomes a combination of the predetermined pattern The present invention can be applied even to a machine. Furthermore, the present invention is not limited to pachinko gaming machines in which the game medium is a game ball, and the present invention can also be applied to slot machines and the like.

  In each of the above embodiments, a game ball is used as an example of the game medium. However, other game media such as coins and medals may be used.

  The present invention can be applied to games such as pachinko machines, and in particular, in a gaming machine in which game control means and payout control means are provided separately, for communication between game control means and payout control means. A game by recognizing that a failure has occurred, and that the payout control means reliably receives a control signal from the game control means when the power supply of the gaming machine is started, and further operates a switch for error release This is useful for preventing disadvantages to the user.

It is the front view which looked at the pachinko game machine from the front. It is the rear view which looked at the gaming machine from the back. It is the front view and sectional drawing which show a ball dispensing apparatus. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram showing a configuration example of an effect control board, a lamp driver board and a sound control board. It is a block diagram which shows the structural example of a power supply board. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows the main process which CPU in a main board | substrate performs. FIG. 6 is a timing chart showing how the microcomputer operates when power supply to the gaming machine is started and when power supply is stopped. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a power-off process. It is a flowchart which shows a power-off process. It is explanatory drawing which shows the buffer used by switch processing. It is a flowchart which shows an example of a switch process. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal wire | line etc. which are used for transmission / reception of a control signal. It is a timing diagram which shows an example of how to output a payout control signal. It is a timing diagram which expands and shows a part in FIG. It is a timing diagram which shows an example of how to output a payout control signal. It is a flowchart which shows a prize ball process. It is explanatory drawing which shows the structural example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball waiting processing 1. It is a flowchart which shows a prize ball transmission process. It is a flowchart which shows the winning ball waiting process 2. FIG. It is a flowchart which shows prize ball waiting processing 3. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a timing diagram for demonstrating communication between a prepaid card unit and a game machine. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows a discharge motor control process. It is a flowchart which shows a payout motor control process. It is a flowchart which shows a main control communication process. It is explanatory drawing which shows the conditions for inputting a prize ball control signal via an input port in main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a timing diagram for explaining a ball biting detection process. It is a timing diagram for demonstrating a ball biting cancellation | release process. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a timing diagram which shows the mode of occurrence of the payout case error. It is a flowchart which shows a display control process. It is a flowchart which shows a display control process. It is a flowchart which shows the part in connection with the output of the prize ball signal of an information output process.

Explanation of symbols

1 Pachinko machine 31 Game control board (main board)
37 Payment control board 50 Prepaid card unit (card unit)
56 CPU
66 Interface board (relay board)
80 Production Control Board 91 Touch Sensor Board 94 Launching Motor 97 Ball Dispensing Device 301 Dispensing Number Count Switch 371 Dispensing Control CPU
374 LED for error display
375 Error release switch 917 Capacitor (backup power supply)
920 Power supply monitoring circuit

Claims (10)

A gaming machine in which a player can play a predetermined game using a game medium and pays out a prize game medium as a prize based on the fact that a payout condition is established by the game,
Game control means including a game control microcomputer for executing a game control process for controlling the progress of the game;
A payout means for paying out the prize game medium;
A payout control means including a payout control microcomputer for executing a payout control process for controlling the payout means;
A communication abnormality detecting means for detecting an abnormality relating to signal communication between the game control means and the payout control means;
An error control means for setting an internal state to an error occurrence state when the communication abnormality detection means detects an abnormality;
When the communication abnormality detecting means detects an abnormality, a communication abnormality notifying means for notifying that effect,
An error canceling operation means for outputting an error canceling signal in response to a human operation;
An error canceling means for monitoring the error canceling signal from the error canceling operation means in the error generating state, and canceling the error generating state on condition that the input of the error canceling signal is detected;
The game control means includes
A payout command signal transmitting means for sending a payout command signal designating the number of payouts of the prize game medium based on the establishment of the payout condition;
The payout control means includes:
A prize game medium payout control means for executing a payout process for controlling the payout means to pay out premium game media of a payout number specified by a payout command signal from the payout command signal transmission means in the game control means; ,
Signal transmitting means for transmitting a signal related to a payout process by the prize game medium payout control means to the game control means,
When the game control microcomputer enters the state in which the game control process is executable when the power supply to the gaming machine is started and the game control process is in an executable state, the game control microcomputer The game machine is characterized by executing a delay process for delaying at least a predetermined period from when the payout control process starts to be executed. When the power supply to the gaming machine is started, the apparatus includes an allowance signal output means for outputting an allowance signal for allowing the game control microcomputer to execute the game control process.
The gaming machine according to claim 1, further comprising delay means for delaying an allowance signal from the allowance signal output means and supplying the allowance signal to the game control microcomputer. The permissible signal from the permissible signal output means is supplied to the payout control microcomputer,
The gaming machine according to claim 2, wherein the permission signal output means outputs a permission signal before the game control microcomputer completes execution of the delay process. The gaming machine according to claim 2, wherein the permission signal from the permission signal output means is branched and supplied to the game control microcomputer and the payout control microcomputer. The allowance signal output means is mounted on a board provided separately from the game control board on which the game control means is mounted and the payout control board on which the payout control means is mounted. Gaming machine. The gaming machine according to any one of claims 1 to 5, wherein the communication abnormality detecting means and the communication abnormality notifying means are mounted on a payout control board on which the payout control means is mounted. The game control means transmits a connection confirmation signal to the payout control means when the power supply to the gaming machine is started and the game control process becomes executable,
The communication abnormality detection means monitors the state of the connection confirmation signal, and detects an abnormality related to signal communication between the game control means and the payout control means. The gaming machine described. The gaming machine according to any one of claims 1 to 7, wherein the signal related to the payout process transmitted by the signal transmission means includes a command reception signal indicating that the payout command signal has been received. The gaming machine is communicably connected to a recording medium processing device that performs processing for converting a value specified by information recorded in the recording medium into a gaming usage value that can be used for gaming in the gaming machine,
An external device abnormality detecting means for detecting an abnormality relating to communication between the recording medium processing apparatus and the gaming machine;
The gaming machine according to any one of claims 1 to 8, wherein the communication abnormality notifying unit notifies the abnormality detected by the communication abnormality detecting unit and the abnormality detected by the external device abnormality detecting unit in a distinguishable manner. The error release signal from the error release operation means is input to the payout control means,
The game machine according to any one of claims 1 to 9, wherein the error canceling means is included in the payout control means.

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