JP2005039636A - Duty correction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly accurate duty correction circuit with a wide range for a correcting amount of a duty ratio. <P>SOLUTION: The duty correction circuit includes: a delay circuit for receiving a clock signal and outputting a plurality of delay output signals whose delay times differ from each other; a first selector for receiving a plurality of the delay output signals, selecting any of them in response to a first select signal and providing an output of a delayed clock signal; a first duty correction circuit for receiving the clock signal and the delayed clock signal, ANDing both the signals, and outputting a first duty correction signal; a second duty correction circuit for receiving the clock signal and the delayed clock signal, ORing both the signals, and outputting a second duty correction signal; and a second selector for selecting either of the first and second duty correction clock signals in response to a second select signal and outputting the selected signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a duty correction circuit.

  If the duty ratio of the system clock signal of the digital system (in this specification, the ratio (%) in which the H level period of the signal occupies one period) is unstable, the operation margin becomes insufficient and the system malfunctions. May occur. In particular, a circuit that operates using both rising and falling edges of a clock signal requires high accuracy with respect to the duty ratio.

  The duty correction circuit is a circuit that corrects and outputs the duty ratio of the input clock signal. A conventional duty correction circuit will be described with reference to FIGS. FIG. 5 is a circuit diagram of a conventional duty correction circuit. The conventional duty correction circuit includes a NOT circuit 501, an inverter 510, an inverter 520, and a selector 530. Inverter 510 includes a p-channel MOS transistor 511 and an n-channel MOS transistor 512. Inverter 520 includes a p-channel MOS transistor 521 and an n-channel MOS transistor 522. The input signal X is inverted by the NOT circuit 501, and the output signal a is input to the inverter 510 and the inverter 520.

  The W / L ratio (the ratio of the channel width to the channel length) of the p-channel MOS transistor 511 is larger than the p-channel MOS transistor of a normal NOT circuit (for example, the NOT circuit 501). Therefore, the threshold voltage of the inverter 510 is higher than usual. The W / L ratio of n channel MOS transistor 522 is larger than the n channel MOS transistor of a normal NOT circuit (for example, NOT circuit 501). Therefore, the threshold voltage of the inverter 520 is lower than usual.

  The selector 530 includes NAND circuits 531, 533, and 534 and a NOT circuit 532. The output signal Z1 of the inverter 510 and the output signal Z2 of the inverter 520 are connected to the input terminal of the selector 530. The selector 530 selects the output signal Z2 when the select signal B0 is at the H level, and selects the output signal Z1 when the select signal B0 is at the L level, and outputs it as the output signal Y. The select signal B0 is, for example, an external signal that is H level when the duty ratio of the input signal X is 50 or more and L level when the duty ratio is less than 50.

  FIG. 6 is a timing chart showing the operation of the conventional duty correction circuit. A clock signal with a duty ratio greater than 50 and having a signal H level period longer than the L level period is defined as an input signal X. The output signal a of the NOT circuit 501 is a signal in which the falling edge is delayed by THL and the rising edge is delayed by TLH due to the wiring load and the input load of the next stage. Since the threshold voltage of the inverter 510 is higher than usual, the inverter 510 outputs a signal Z1 obtained by delaying the falling edge of the input signal X by TLH. Since the threshold voltage of the inverter 520 is lower than normal, the inverter 520 outputs a signal Z2 obtained by delaying the rising edge of the input signal X by THL.

On the other hand, since the duty ratio of the input signal X is larger than 50, the select signal B0 is set to H level. Therefore, the selector 530 selects the signal Z2 and outputs it as the output signal Y. The output signal Y has a smaller duty ratio than the input signal X.
FIG. 7 is a timing chart showing the operation of the conventional duty correction circuit when the input signal X is a clock signal having a shorter H level period than the L level period and a duty ratio smaller than 50. . Select signal B0 is set to L level. As a result, the selector 530 selects the signal Z1 and outputs it as the output signal Y. The output signal Y has a larger duty ratio than the input signal X.

  The duty ratio of the output signal Y of the duty correction circuit shown in FIG. 5 is determined by the rising and falling delay times (TLH and THL) of the NOT circuit 501 and the threshold voltages of the inverter 510 and the inverter 520. The duty correction circuit shown in FIG. 5 can only select the correction amount of the duty ratio from two stages (increase or decrease).

  The duty correction circuit disclosed in Japanese Patent Laid-Open No. 10-28036 uses delay circuits having different rising delay times and falling delay times, and uses both delay times for signal duty correction. Therefore, the correction amount of the duty ratio can be set finely.

Japanese Patent Laid-Open No. 10-28036

The conventional duty correction circuit uses the rising delay time and the falling delay time of the NOT circuit 501 or the delay circuit for correcting the duty ratio. However, since the settable range of the rise delay time and the fall delay time is limited, the correction amount of the duty ratio has a limit. Also, since it is difficult to realize an integrated circuit with good delay time accuracy, the duty ratio correction accuracy is poor.
SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a highly accurate duty correction circuit with a wide range of duty ratio correction amounts.

  In order to solve the above problems, the present invention has the following configuration. According to the first aspect of the present invention, a delay circuit that inputs a clock signal and outputs a plurality of delayed output signals having different delay times, and a plurality of the delayed output signals are input, and any one of them is a first one. A first selector that selects and outputs a delayed clock signal in response to a select signal of 1; inputs the clock signal and the delayed clock signal; performs an AND operation on both signals; and outputs a first duty correction clock signal A first duty correction circuit that inputs the clock signal and the delayed clock signal, performs a logical OR operation on both signals, and outputs a second duty correction clock signal, and the first duty correction circuit. And a second selector that selects and outputs one of the second duty correction clock signals according to the second select signal. It is an I correction circuit.

  According to a second aspect of the present invention, in the delay circuit, a plurality of delay elements that delay an input signal for a predetermined time are connected in series, and the clock signal is input to the first stage of the plurality of delay elements, and each of the delay elements The duty correction circuit according to claim 1, wherein a delay output signal is output from.

  According to a third aspect of the present invention, in the delay circuit, a plurality of delay elements having different delay times are connected in parallel, the clock signal is input to each of the plurality of delay elements, and a delay output is output from each of the delay elements. 2. The duty correction circuit according to claim 1, wherein the duty correction circuit outputs a signal.

  The present invention has an effect that a duty correction circuit with a wide range of duty ratio correction can be realized and a highly accurate duty correction circuit can be realized.

According to the duty correction circuit of the present invention, there is an effect that the duty ratio of the clock signal can be accurately corrected regardless of the correction amount.
The duty correction circuit of the present invention is useful as a circuit for correcting the duty ratio of a system clock signal incorporated in an analog / digital mixed integrated circuit system.
Since the duty correction circuit of the present invention can correct the duty ratio of the input clock signal to a predetermined value (for example, 50) and output it, a circuit that operates using both the rising edge and the falling edge of the clock signal is mounted. Enables high-speed operation of digital systems.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments that specifically show the best mode for carrying out the present invention will be described below with reference to the drawings.

<< Embodiment >>
The duty correction circuit according to the embodiment of the present invention will be described with reference to FIGS. 1 and 2 are a block diagram and a circuit diagram, respectively, of the duty correction circuit 100 according to the embodiment of the present invention. The duty correction circuit 100 includes a delay circuit 110, a first selector 120, a first duty correction circuit 130, a second duty correction circuit 140, and a second selector 150.

  The delay circuit 110 includes three stages of delay elements 111, 112, and 113 connected in series. The delay circuit 110 propagates the input signal X while delaying the input signal X by a predetermined delay time (T) by the delay elements 111 to 113, and inputs the delayed output signals D1, D2, and D3 from the delay elements 111 to 113, respectively. The signal X itself is output to the first selector 120. Specifically, the delay elements 111 to 113 are buffer circuits.

  The first selector 120 includes NAND circuits 121 to 125. The first selector 120 selects one signal as the delayed clock signal DS from the input signal X and the delayed output signals D1, D2, and D3 according to the first select signals A0 to A3, and performs the first duty correction. This is output to the circuit 130 and the second duty correction circuit 140. The first duty correction circuit 130 includes a logical product circuit 131, performs a logical product operation of the delayed clock signal DS and the input signal X, and outputs a logical product operation result as a first duty correction signal Z1. The second duty correction circuit 140 includes a logical sum circuit 141, performs a logical sum operation on the delayed clock signal DS and the input signal X, and outputs a logical sum operation result as a second duty correction signal Z2.

  The second selector 150 includes a NOT circuit 152 and NAND circuits 151, 153, and 154. The input terminal of the selector 150 is connected to the first duty correction signal Z1 and the second duty correction signal Z2. The second selector 150 selects the first duty correction signal Z1 or the second duty correction signal Z2 according to the second select signal B0 and outputs the output signal Y.

  FIG. 3 is a timing chart showing the operation of the duty correction circuit according to the embodiment of the present invention. A clock signal with a duty ratio greater than 50 and having a signal H level period longer than the L level period is defined as an input signal X. A case will be described in which the first select signal A2 is at the H level, A0, A1 and A3 are at the L level, and the second select signal B0 is at the L level. Delayed output signals D1, D2, and D3 from the delay elements 111, 112, and 113 are delayed by T, 2T, and 3T, respectively, with respect to the input signal X. Since the first select signal A2 is at the H level, the first selector 120 selects the delayed output signal D2 and outputs it as the delayed clock signal DS. The first duty correction circuit 130 calculates the logical product of the delayed clock signal DS and the input signal X, and outputs the logical product result as the first duty correction signal Z1. The first duty correction signal Z1 is a signal having a rising edge immediately after the rising edge of the delayed clock signal DS and a falling edge immediately after the falling edge of the input signal X. The second duty correction circuit 140 calculates the logical sum of the delayed clock signal DS and the input signal X, and outputs the logical sum result as the second duty correction signal Z2. The second duty correction signal Z2 is a signal having a rising edge immediately after the rising edge of the input signal X and a falling edge immediately after the falling edge of the delayed clock signal DS. Since the second select signal B0 is at the L level, the second selector 150 selects the first duty correction signal Z1 as the output signal Y. The output signal Y is a signal that has a rising edge obtained by delaying the rising edge of the input signal X by 2T and a falling edge that has substantially the same timing as the input signal X, and has a duty ratio corrected to be smaller than that of the input signal X.

  FIG. 4 shows the operation of the duty correction circuit according to the embodiment of the present invention when the input signal X is a clock signal in which the H level period of the signal is shorter than the L level period and the duty ratio is less than 50. It is a timing chart which shows. A case will be described in which the first select signal A2 is at the H level, A0, A1 and A3 are at the L level, and the second select signal B0 is at the H level. Since the first select signals A0 to A3 are the same as those in the timing chart shown in FIG. 3, the first and second duty correction signals Z1 and Z2 are the same as those in FIG. Since the second select signal B0 is at the H level, the second selector 150 selects the second duty correction signal Z2 as the output signal Y. The output signal Y has a rising edge with substantially the same timing as the input signal X and a falling edge obtained by delaying the falling edge of the input signal X by 2T, and is a signal in which the duty ratio is corrected to be larger than that of the input signal X.

  In the embodiment, the delay circuit 110 includes three delay elements 111 to 113 connected in series. However, the number of delay elements may be two or more. Alternatively, a plurality of delay elements having different delay times may be connected in parallel, each delay element may receive the input signal X, and each delay element may output delay output signals D1 to D3 having different delay times.

  Unlike the conventional duty correction circuit, the duty correction circuit of the embodiment does not require adjustment of the ratio between the channel length and the channel width of the MOS transistor. The duty correction circuit according to the embodiment corrects the duty ratio by delaying the rising edge and the falling edge of the input clock signal by a delay element. Therefore, the correction amount of the duty ratio can be accurately adjusted using the value on the data sheet of the delay element. Furthermore, the range of the duty ratio correction amount is not limited to a narrow width.

  A system clock signal of a digital system or the like and first and second select signals that make the duty ratio of the system clock signal a predetermined value may be input to the duty correction circuit of the present invention. As a result, a system clock signal with a stable duty ratio can be obtained, so that a digital system or the like can be operated at high speed.

  The duty correction circuit according to the present invention is useful as a duty correction circuit used in various digital systems (including a microcomputer).

Block diagram of a duty correction circuit according to an embodiment of the present invention Circuit diagram of duty correction circuit according to an embodiment of the present invention Timing chart showing the operation of the duty correction circuit of the embodiment of the present invention Timing chart showing the operation of the duty correction circuit of the embodiment of the present invention Circuit diagram of conventional duty correction circuit Timing chart showing operation of conventional duty correction circuit Timing chart showing operation of conventional duty correction circuit

Explanation of symbols

110 delay circuit 120 first selector 130 first duty correction circuit 140 second duty correction circuit 150 second selector 111, 112, 113 delay element (buffer circuit)
121-125, 151, 153, 154 NAND circuit 131 AND circuit 141 OR circuit

Claims (3)

A delay circuit for inputting a clock signal and outputting a plurality of delayed output signals having different delay times;
A first selector that inputs a plurality of the delayed output signals, selects any one of them according to the first select signal, and outputs a delayed clock signal;
A first duty correction circuit that inputs the clock signal and the delayed clock signal, performs a logical AND operation on both signals, and outputs a first duty correction clock signal;
A second duty correction circuit that inputs the clock signal and the delayed clock signal, performs a logical OR operation on both signals, and outputs a second duty correction clock signal;
A second selector that selects and outputs one of the first and second duty correction clock signals according to a second select signal;
A duty correction circuit comprising: The delay circuit includes a plurality of delay elements that delay the input signal for a predetermined time in series, inputs the clock signal to the first stage of the plurality of delay elements, and outputs a delay output signal from each of the delay elements. The duty correction circuit according to claim 1, wherein The delay circuit includes a plurality of delay elements having different delay times connected in parallel, inputs the clock signal to each of the plurality of delay elements, and outputs a delay output signal from each of the delay elements. The duty correction circuit according to claim 1.

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