JP2005039125A - Semiconductor variable-capacitance diode and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor variable-capacitance diode which can work at a low voltage and a high frequency and has less variation in an initial capacitance value. <P>SOLUTION: The semiconductor variable-capacitance diode has an n<SP>+</SP>region 2 as a standard concentration n region wherein n-type impurity is contained, a p<SP>+</SP>region 12 as a standard concentration P region in contact with the n<SP>+</SP>region 2 wherein p-type impurity is contained at a first concentration and a p<SP>++</SP>region 13 as a high concentration p region in contact with the p<SP>+</SP>region 12 wherein p-type impurity is contained at a second concentration higher than the first concentration. The concentration distribution of p-type impurity remaining active in the p<SP>+</SP>region 12 is almost fixed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor variable capacitance diode. The present invention also relates to a method for manufacturing a semiconductor device.

  In the present specification, P and N basically represent conductivity types. When P + and N + are written as compared to P and N, it means that the impurity concentration in each conductivity type is higher. Furthermore, the notation P ++ and N ++ means that the impurity concentration is higher than that of P + and N +.

  Many conventional semiconductor variable capacitance diodes use a relationship between a capacitance Cmax when a reference bias voltage is applied to a PN junction and a capacitance Cmin when a reverse bias voltage is applied as an operating voltage. When used in a circuit such as a VCO (Voltage Controlled Oscillator), a larger variable capacitance ratio Cmax / Cmin is preferable because the degree of freedom in design increases. In order to increase the variable capacitance ratio, a method of forming a junction between a layer having a high impurity concentration and a thin layer so that the depletion layer is likely to spread, that is, a method of forming a step junction is common. In reality, a step junction is often formed using a junction between the P + region in the anode extraction region and the N-type epitaxial layer.

  Further, in order to increase the variable capacitance ratio, the initial capacitance value is increased by forming an N + region having an impurity concentration higher than that of the epitaxial layer at the junction interface between the P + region and the N-type epitaxial layer. Patent Documents 1 and 2 disclose structures similar to the super staircase junction.

  As described above, an example of the structure of the semiconductor variable capacitance diode including the N + region as the initial capacitance layer in order to increase the initial capacitance value will be described. In this semiconductor variable capacitance diode, an N + buried layer is formed on the upper surface of a P-type substrate, and a P + buried layer is formed on the side of the N + buried layer. N-type epitaxial layers collectively cover these upper sides. The upper surface of this epitaxial layer is partitioned by a field oxide film. As the compartment, there are at least a cathode extraction region and an anode extraction region. In the cathode extraction region, a sinker N + region is formed so as to penetrate the inside of the epitaxial layer and reach the N + buried layer. In the anode extraction region, a P + region is formed by implantation from the upper surface of the epitaxial layer. Impurities are implanted to aim at the interface between this P + region and the region remaining as the original N-type epitaxial layer, thereby forming an N + region as an initial capacitance layer.

  An interlayer insulating film covers the upper side of these, and contact holes are disposed so as to penetrate the interlayer insulating film at positions of the anode extraction region and the cathode extraction region, and an aluminum electrode is formed through the contact hole. .

In addition, examples of varactor diodes and variable capacitance diodes are also disclosed in Patent Documents 3 to 5.
JP-A-11-68124 Japanese Patent Application Laid-Open No. 11-233797 JP-A-4-287978 Japanese Patent Laid-Open No. 5-206486 JP-A-3-41779

  The semiconductor variable capacitance diode having the above-described structure is not suitable for handling a high frequency because a resistance component in a portion with a low impurity concentration becomes large. In particular, it is difficult to use it for products that handle high frequencies on the order of more than recent GHz. In addition, since the depletion layer cannot be fully expanded unless a voltage of a certain level, for example, 5 V or more, is applied, it is inconvenient to use in a product with a low power supply voltage such as a recent IC (Integrated Circuit). It is. Further, in the structure in which the N + region exists at the interface between P + and N, a junction is formed at a portion where the concentration gradient of the impurity is steep, so that there is a problem that the initial capacitance value varies greatly.

  After all, when a semiconductor variable capacitance diode is built into the latest high-frequency analog LSI (Large Scale Integration), it is required to operate properly at low voltage and high frequency, and the variable capacitance ratio must be increased. It is more important that the initial capacitance value has a smaller variation.

  Accordingly, an object of the present invention is to provide a semiconductor variable capacitance diode that can operate at a low voltage and a high frequency and has little variation in initial capacitance value. Furthermore, it aims at providing the manufacturing method of the semiconductor device which incorporates such a semiconductor variable capacitance diode.

  In order to achieve the above object, a semiconductor variable capacitance diode according to the present invention includes a standard concentration N region containing an N-type impurity and a P-type impurity at a first concentration in contact with the standard concentration N region. A standard concentration P region, and a high concentration P region in contact with the standard concentration P region and containing a P-type impurity at a second concentration higher than the first concentration. However, the concentration distribution of active P-type impurities in the standard concentration P region is substantially constant.

  According to the present invention, operation at a low voltage and high frequency is possible, and since the concentration distribution of active P-type impurities in the standard concentration P region is substantially constant, variation in initial capacitance value can be reduced. it can.

(Embodiment 1)
(Production method)
With reference to FIGS. 1-14, the semiconductor variable capacitance diode in Embodiment 1 based on this invention is demonstrated. Note that the meanings of notations such as “P +” and “N +” in the layers of each figure are as described at the beginning of the “Prior art” column. Furthermore, “P-sub” means a P-type substrate, and “N-epi” means an N-type epitaxial layer. In each figure, the aspect ratio may be exaggerated for convenience of explanation.

As shown in FIG. 1, antimony or arsenic is implanted into the upper surface of a P-type substrate 1 at a rate of 30 to 50 keV at about 5 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² and heat treatment is performed at 1180 ° C. for about 2 hours. N + region 2 is formed as a buried N + layer. CVD (Chemical Vapor Deposition) is performed on this upper surface, and as shown in FIG. 2, an N type epitaxial layer 3 having a thickness of 1 to 2 μm and a specific resistance of about 0.1 to 1 Ω · cm is grown.

Next, a trench isolation process is performed. This process is performed as follows. A TEOS (Tetraethyl orthosilicate Tetraethoxysilane) oxide film (not shown) is deposited on the upper surface by 5000 mm, and a resist film (not shown) is formed thereon. The isolation region is patterned into a resist film by photolithography, and the TEOS oxide film is anisotropically etched using this resist film as a mask. After removing the resist film, the substrate is etched by 5 to 10 μm using the TEOS oxide film as a mask, thereby forming a trench 4 for isolation as shown in FIG. The side wall of the trench 4 is thermally oxidized by 500 to 1500 to form a thermal oxide film 5 so as to cover the inner surface of the trench 4. Further, boron is implanted into the bottom of the trench 4 in order to prevent inversion from P-type to N-type at the bottom of the trench 4. This implantation is performed at 30 to 50 keV so as to be about 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² . Thus, a boron implantation region 6 which is a P + region is formed at the bottom of the trench 4. Next, 8000 to 12000 of polysilicon is deposited on the entire surface, and the trench 4 is filled with polysilicon. Etching is performed to planarize the upper surface, thereby forming a polysilicon portion 7 in the trench 4 as shown in FIG.

  Next, a field oxide film forming step is performed. This step is performed as follows. An underlay oxide film (not shown) is formed in a thickness of 100 to 500 mm by thermal oxidation. A nitride film of 1000 to 1500 is deposited on this upper side. Patterning is performed to fit the element region by photolithography. The nitride film and the oxide film are simultaneously anisotropically etched. Thereafter, thermal oxidation is performed at 1100 ° C. for about 30 minutes, and a field oxide film 8 is formed to have a thickness of 4000 to 6000 mm as shown in FIG. At this time, the nitride film used as a mask is removed by anisotropic etching, and the underlying oxide film is removed by wet etching. Thus, as shown in FIG. 6, a structure in which the region of each element is partitioned by the field oxide film 8 can be obtained.

In order to extract the buried N + layer as the cathode (cathode) of the semiconductor variable capacitance diode, phosphorus is 350 × 500 keV and 1 × 10 ¹⁴ to 1 × 10 ¹⁵ / cm ^{2 using the} resist film 9 as a mask as shown in FIG. Inject to a degree. Thus, the sinker N + region 10 is formed.

  As shown in FIGS. 8 and 9, the anode (anode) region is patterned by photolithography to form a P + region 12 and a P ++ region 13. These forming steps will be described in detail.

  First, the P + region 12 is formed by boron implantation using the resist film 11 as a mask. In the implantation for forming the P + region 12, as shown in FIG. 10, the acceleration energy is set so that the depth of the implantation peak is shallower than the PN junction depth and as close as possible to the PN junction depth. To do. FIG. 10 is a graph showing the change in impurity concentration with respect to the depth at the position of the broken line 43 in FIG. Note that the “PN junction depth” refers to the P-type impurity concentration when attention is paid to the change in the impurity concentration in the depth direction in the state after the formation of the P + region, as indicated by a broken line in FIG. The depth at which the magnitude relationship with the N-type impurity concentration is reversed is assumed.

  Since the depth at which the N + region 2 exists varies depending on the thickness of the N-type epitaxial layer 3, the acceleration energy should be determined in consideration of the thickness of the N-type epitaxial layer 3. For example, it is determined in the range of 200 to 350 keV. After the implantation, a heat treatment is performed at 900 ° C. for about 60 minutes to activate the impurities. As a result of activation, the P + region 12 and the N + region 2 have the same concentration gradient in the vicinity of the PN junction depth, so that the P and N impurities cancel each other. Only the difference between the density curves of the N + region 2 remains active. That is, since the gradients of the concentration curves are equal, as shown in FIG. 11, P-type impurities remain in the P + region 12 in an active state at a substantially constant concentration regardless of the depth.

Next, in order to form the P ++ region 13, as shown in FIG. 9, BF ₂ is implanted at 30 to 60 keV to a high concentration of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . This implantation is performed so that the impurity distribution becomes a curve shown as “P ++” in FIG. FIG. 12 is a graph showing the change in impurity concentration with respect to the depth at the position of the broken line 47 in FIG. After the injection of BF ₂ , heat treatment is performed at a low temperature of 800 to 850 ° C. for about 30 minutes. Thus, the P ++ region 13 is formed. Since this implantation is highly concentrated and the heat treatment is cold, the boron in BF ₂ is not fully activated. Further, since the heat treatment is performed at a low temperature, proliferation and diffusion occur. Therefore, the distribution of the active impurities implanted for forming the P ++ region 13 is actually as shown by “P ++” in FIG. That is, the tail is widened toward the P + region 12 adjacent to the lower side. The shape that is cut off at the right end in FIG. 13 as compared to FIG. 12 is due to the fact that the region of the impurity having a concentration higher than a certain concentration is activated only to a certain amount.

  The amount of impurities in the portion where the tail of the curve of “P ++” spreads is added to the reverse gradient of the boron curve previously implanted for the P + region 12, whereby the P + region 12 The concentration of the actually active P-type impurity becomes substantially constant.

  After the formation of the P ++ region 12 and the P ++ region 13, as shown in FIG. 14, an interlayer oxide film 14 is deposited by CVD to a thickness of 3000 to 10,000 mm, a contact hole is opened, and an aluminum wiring 15 is connected. To do.

(Constitution)
By the manufacturing method described above, it is possible to obtain a semiconductor variable capacitance diode in which the P ++ region 13, the P + region 12, and the N + region 2 are arranged in this order, and the active impurity concentration in the P + region 12 is substantially constant.

  The concentration of the P-type impurity in the P + region 12 is regarded as the “first concentration”, the P + region 12 is regarded as the “standard concentration P region”, and the concentration of the P-type impurity in the P ++ region 13 is regarded as the “second concentration”. Then, since the impurity concentration in the P ++ region 13 is higher than that in the P ++ region 12, the second concentration is higher than the first concentration. The semiconductor variable capacitance diode (see FIG. 14) obtained in the present embodiment is in contact with the standard concentration N region containing the N-type impurity and the standard concentration N region, and has the P-type impurity at the first concentration. And a high concentration P region that is in contact with the standard concentration P region and contains a P-type impurity at a second concentration higher than the first concentration. The P ++ region 13 corresponds to the high concentration P region. N + region 2 corresponds to the standard concentration N region. Further, due to the action described in the description of the manufacturing method described above, the concentration distribution of active ones of the P-type impurities in the standard concentration P region is substantially constant.

(Action / Effect)
In this semiconductor variable capacitance diode, since the concentration distribution of active P-type impurities in the P + region serving as the standard concentration P region is substantially constant, variations in the initial capacitance value can be reduced.

  A case where an operating voltage is applied between the aluminum wiring 15 and the P ++ region 13 and the sinker N + region 10 will be described with reference to FIG. When an operating voltage is applied, the region 16 which is the P + region 12 is completely depleted, and the depletion layer enters the P ++ layer 13 as shown in the region 17. However, as shown in FIG. 15, when the P ++ region 13 is entered, the impurity concentration increases rapidly as it advances upward, so that the depletion layer grows slowly and stops at an appropriate point. For example, by setting the operating voltage to an appropriate value, the depletion layer can stop growing in the region 17. As described above, the depletion layer stably stops growing at a certain position, so that the variation in the capacitance value when the operating voltage is applied can be reduced.

Note that there is an inactive portion 18 in a portion close to the surface of the P ++ region 13. This is the portion that was not activated because of the high concentration of BF ₂ injection and the low temperature of the heat treatment.

  Increasing the amount of P-type impurity implanted to form the P + region 12 increases the initial capacitance value as shown in FIG. Moreover, since the width of the P + region 12 is wider than the current region 16, the variable capacitance ratio is also increased as shown in FIG. When the implantation amount of the P-type impurity is increased, the PN junction depth further comes to a portion where the slope of the impurity concentration curve is gentle, so that the variation in the variable capacitance ratio is reduced as shown in FIG.

  On the other hand, the breakdown voltage as the variable capacitance diode is determined by the likelihood of an avalanche breakdown phenomenon occurring at the junction of the P + region 12 and the N + region 2. When the implantation amount of the P-type impurity is increased, the impurity concentration at the junction is high, so that the avalanche breakdown phenomenon is likely to occur, the breakdown voltage is lowered and the leakage current is increased as shown in FIG. Therefore, in order to avoid the avalanche breakdown phenomenon, the implantation amount of the P-type impurity is made as large as possible within the allowable range according to the value of the operating voltage. In this way, it is possible to reduce variations in the variable capacitance ratio without reducing the breakdown voltage as much as possible.

  In this semiconductor variable capacitance diode, the concentration of the active P-type impurity in the P + region serving as the standard concentration P region is the concentration of the P-type impurity implanted to form the P + region, and the concentration of the P-type impurity implanted to form the P ++ region. As a result, the concentration of active P-type impurities in the P + region itself increases as a whole. Since the impurity concentration is high, the resistance component becomes small, and operation under high frequency becomes possible. This is shown in FIG. The “Q value” on the vertical axis in FIG. 20 indicates the ratio of operating as a capacitor. In FIG. 20, the line 19 is shifted to the line 20 by increasing the implantation amount of the P-type impurity. That is, it can operate correctly as a capacitor even at a higher frequency.

  In this semiconductor variable capacitance diode, the standard concentration N region is preferably covered with an epitaxial layer on the upper side. That is, the N + region 2 is a so-called buried layer. Furthermore, both the standard concentration P region and the high concentration P region are formed by implanting a P-type impurity into the N-type epitaxial layer 3 that is an epitaxial layer covering the upper side of the standard concentration N region. Providing this configuration facilitates manufacturing.

  In this semiconductor variable capacitance diode, preferably, the implantation for forming the P + region 12 is performed with acceleration energy so that the depth of the implantation peak is shallower than the PN junction depth and as close to the PN junction depth as possible. Since this is carried out by setting, the depth of the peak of the distribution of the P-type impurity implanted as the standard concentration P region is the standard concentration P region and the standard concentration N region at the PN junction depth. It is shallower than the interface. With this configuration, the P and N impurities cancel each other, and only the P-type impurities remain at a substantially constant concentration regardless of the depth as active impurities. Further, in the distribution curves in which the depth and the concentration are drawn as coordinate axes, the bottom of the distribution curve of the P-type impurity implanted into the P + region 12 as the standard concentration P region and the P ++ region 13 as the high concentration P region are shown. It overlaps with the bottom of the distribution curve of the existing P-type impurity. By providing this configuration, the concentration of the actually active P-type impurity in the P + region 12 is preferably substantially constant.

(Embodiment 2)
(Production method)
With reference to FIGS. 21 to 33, a semiconductor device manufacturing method according to the second embodiment of the present invention will be described. A semiconductor device obtained by this manufacturing method is formed on the surface of a P-type substrate 1 and includes an NPN diode, an NMOS (N-channel Metal-Oxide Semiconductor) transistor, and a PMOS (P-channel Metal-Oxide Semiconductor). A transistor, a substrate take-out part, a variable capacitance diode, and an L-PNP (lateral PNP) diode are included. In order to facilitate understanding of the progress of the process in each of these areas, these areas are displayed side by side in order from the left in FIGS. The display of NPN, NMOS, PMOS, Sub, variable capacitance diode, and L-PNP displayed at the top of the figure represents each of these areas. In practice, the arrangement of each element is arbitrary, and the arrangement is not limited to one in which the elements are arranged one by one.

  In each figure, “Sb +”, “P +”, and “B +” displayed with an arrow in the air mean that antimony, phosphorus, and boron are implanted at a slightly higher concentration, respectively.

As shown in FIG. 21, antimony (Sb) as an N-type impurity is implanted into the upper surface of a P-type substrate 1 at a rate of 30 to 50 keV at about 1 × 10 ^{14 to} 5 × 10 ¹⁴ / cm ² , and 1 to 10 at 1000 to 1200 ° C. Heat treatment for 3 hours is performed. By doing so, the N + region 2 is activated.

As shown in FIG. 22, a resist film 21 is formed by photolithography, and boron (B) is implanted as a P-type impurity at 20 to 40 keV so as to be about 1 × 10 ^{14 to} 5 × 10 ¹⁴ / cm ² . Thus, the P + region 22 is formed.

  The resist film 21 is removed, and as shown in FIG. 23, an N-type epitaxial layer 3 having a thickness of 1 to 3 μm and a specific resistance of about 0.3 to 2 Ω · cm is grown on the upper surface.

  As shown in FIG. 24, a TEOS oxide film (not shown) is formed and patterned, and the silicon (Si) layer is etched using this TEOS oxide film as a mask. Thus, a trench is formed. Boron is implanted into the bottom of each trench. Thermal oxidation is performed on the inner surface of the trench. Further, polysilicon is buried in the trench. A polysilicon portion 7 is formed by planarizing the upper surface.

  A nitride film pattern is formed on the upper surface, and an oxidation treatment at 900 to 1200 ° C. is performed for 30 minutes to 1 hour, thereby forming a field oxide film 8 as shown in FIG.

  As shown in FIG. 26, a resist film 24 is formed. Using this resist film 24 as a mask, phosphorus (P) as an N-type impurity is implanted into the PMOS area. Thus, the N well region 23 is formed. In this phosphorus implantation step, phosphorus is also implanted in the variable capacitance diode region at the same time, and an N well region 25 to be a sinker N + region is formed.

  The resist film 24 is removed, and a resist film 44 is formed as shown in FIG. Using this resist film 44 as a mask, boron (B) as a P-type impurity is implanted into the NMOS transistor area. Thus, the P well region 26 is formed. In this boron implantation process, boron is implanted also in the variable capacitance diode region, and a region 27 to be a P + region is formed. Further, in this implantation step, boron is implanted also into the substrate take-out portion, and a P region 35 is formed.

  As shown in FIG. 28, gate electrodes 28 and 29 are formed in the substrate exposed regions in the NMOS transistor area and the PMOS transistor area, respectively.

  As shown in FIG. 29, a resist film 45 is formed. Antimony as an N-type impurity is implanted using the resist film 45 as a mask. As a result, source / drain regions 30, 31 of the NMOS transistor, collector region 34 of the NPN diode, base lead region 32 of the variable capacitance diode, and base lead region 33 of the L-PNP diode are simultaneously formed.

The resist film 45 is removed, and a resist film 46 is formed as shown in FIG. Using this resist film 46 as a mask, BF ₂ as a P-type impurity is implanted. As a result, the source / drain regions 36 and 37 of the PMOS transistor, the emitter region 39 of the variable capacitance diode, and the P + region 40 to be the emitter region and collector region of the L-PNP diode are formed. BF ₂ is simultaneously injected into the external base of the NPN diode.

  The resist film 46 is removed, and an opening 41 is provided in the base region of the NPN diode as shown in FIG. Impurities are implanted into the opening 41.

  As shown in FIG. 32, an emitter electrode of an NPN diode is formed.

  As shown in FIG. 33, an interlayer oxide film 14 is formed, a contact hole is opened in the interlayer oxide film 14, and an aluminum wiring 15 is formed.

  In this way, a semiconductor device is obtained. This semiconductor device includes an NPN diode, an NMOS transistor, a PMOS transistor, a substrate take-out part, a variable capacitance diode, and an L-PNP diode. Of these, the variable capacitance diode has basically the same configuration as the semiconductor variable capacitance diode described in the first embodiment.

(Action / Effect)
According to the semiconductor device manufacturing method described above, the N + region 2 as the buried layer containing the N-type impurity disposed below the MOS transistor and the N + region 2 as the standard concentration N region of the semiconductor variable capacitance diode are the same. These are simultaneously formed by the impurity implantation step. Therefore, the semiconductor variable capacitance diode can be manufactured in parallel without increasing the number of extra steps as compared with the conventional method for manufacturing the MOS transistor.

  Further, in the above-described semiconductor device manufacturing method, the P well region 26 as the P-type well region of the MOS transistor and the P well region 27 as the standard concentration P region of the semiconductor variable capacitance diode are formed by the same impurity implantation process. Formed simultaneously. Therefore, the semiconductor variable capacitance diode can be manufactured in parallel without increasing the number of extra steps as compared with the conventional method for manufacturing the MOS transistor.

  In addition, the said embodiment disclosed this time is an illustration in all the points, Comprising: It is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

It is explanatory drawing of the 1st process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing of the 2nd process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing of the 3rd process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing of the 4th process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing of the 5th process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing of the 6th process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing of the 7th process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing of the 8th process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing of the 9th process among the manufacturing methods of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is the graph which displayed the change with respect to the depth of the total impurity concentration in the broken-line position of FIG. It is the graph which displayed the change with respect to the depth of the density | concentration of the active impurity after performing activation of an impurity. 10 is a graph displaying changes with respect to the depth of the total impurity concentration at the position of the broken line in FIG. 9. It is the graph which displayed the change with respect to the depth of the density | concentration of the active impurity after performing low temperature heat processing. It is sectional drawing of the semiconductor variable capacitance diode in Embodiment 1 based on this invention. It is explanatory drawing which shows the relationship between the density | concentration distribution of the impurity at the time of applying an operating voltage to the semiconductor variable capacitance diode in Embodiment 1 based on this invention, and the breadth of a depletion layer. It is a graph which shows the relationship between the implantation amount of a P-type impurity, and an initial stage capacitance value. It is a graph which shows the relationship between the implantation amount of a P-type impurity, and a variable capacitance ratio. It is a graph which shows the relationship between the implantation amount of a P-type impurity, and the dispersion | variation in variable capacitance ratio. It is a graph which shows the relationship between the implantation amount of a P-type impurity, and a proof pressure. It is a graph which shows the relationship between a frequency and Q value. It is explanatory drawing of the 1st process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 2nd process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 3rd process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 4th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 5th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 6th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 7th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 8th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 9th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 10th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 11th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 12th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 13th process among the manufacturing methods of the semiconductor device in Embodiment 2 based on this invention.

Explanation of symbols

  1 P-type substrate, 2 N + region, 3 N-type epitaxial layer, 4 trench, 5 thermal oxide film (on the sidewall of the trench), 6 boron implanted region, 7 polysilicon portion, 8 field oxide film, 9, 11, 21, 21 24, 44, 45, 46 Resist film, 10 sinker N + region, 12 P + region, 13 P ++ region, 14 interlayer oxide film, 15 aluminum wiring, 16, 17 region, 18 inactive portion, 19, 20 wire, 22 P + region , 23 N well region, 25 (becomes sinker N + region), N well region, 26 P well region, 27 (corresponding to P + region in variable capacitance diode), P well region, 28, 29 Gate electrode, 30, 31 (NMOS Source / drain region of transistor, 32 Base extraction region of variable capacitance diode, 33 (L-PNP diode) Ode) base extraction region, 34 (NPN diode) collector region, 35 (substrate extraction portion) P region, 36, 37 (PMOS transistor) source / drain region, 38 (substrate extraction region) P + region, 39 Emitter region (for variable capacitance diode), 40 (for L-PNP) P + region, 41 opening, 42 side wall insulating film, 43, 47 (showing position for displaying concentration distribution) broken line.

Claims (5)

A standard concentration N region containing N-type impurities;
A standard concentration P region in contact with the standard concentration N region and containing a P-type impurity at a first concentration;
A high concentration P region in contact with the standard concentration P region and containing a P-type impurity at a second concentration higher than the first concentration;
A semiconductor variable capacitance diode, wherein a concentration distribution of active P-type impurities in the standard concentration P region is substantially constant.   The standard concentration N region is covered with an epitaxial layer on an upper side, and the standard concentration P region and the high concentration P region are formed by implanting a P-type impurity into the epitaxial layer. Semiconductor variable capacitance diode. The standard concentration P region is implanted with the P-type impurity,
The depth at which the peak of the distribution of the P-type impurity implanted as the standard concentration P region is shallower than the interface formed by the standard concentration P region and the standard concentration N region,
In a distribution curve drawn with the depth and the concentration as coordinate axes, respectively, the tail of the distribution curve of the P-type impurity implanted as the standard concentration P region and the distribution curve of the P-type impurity existing as the high concentration P region The semiconductor variable capacitance diode according to claim 1, wherein the semiconductor variable capacitance diode overlaps with a skirt portion of the semiconductor variable capacitance diode. A manufacturing method for obtaining a semiconductor device comprising a MOS transistor and the semiconductor variable capacitance diode according to claim 1,
A method for manufacturing a semiconductor device, comprising: forming a buried layer including an N-type impurity disposed below the MOS transistor and the standard concentration N region of the semiconductor variable capacitance diode in the same step.   The P-type well region of the MOS transistor and the standard concentration P region of the semiconductor variable capacitance diode are formed in the same process, and the source / drain region of the MOS transistor and the high concentration P of the semiconductor variable capacitance diode are formed. The method for manufacturing a semiconductor device according to claim 4, wherein the region is formed in the same step.

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