JP2005038150A - Transmission line analysis system - Google Patents
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- JP2005038150A JP2005038150A JP2003274055A JP2003274055A JP2005038150A JP 2005038150 A JP2005038150 A JP 2005038150A JP 2003274055 A JP2003274055 A JP 2003274055A JP 2003274055 A JP2003274055 A JP 2003274055A JP 2005038150 A JP2005038150 A JP 2005038150A
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本発明は、電気回路設計やプリント基板設計における伝送線路解析、特に、クロック信号と制御信号とバス信号を含めた電気回路やプリント基板全体のタイミングとノイズを同時に解析する伝送線路解析システムに関するものである。 The present invention relates to transmission line analysis in electrical circuit design and printed circuit board design, and more particularly to a transmission line analysis system that simultaneously analyzes the timing and noise of an entire electrical circuit and printed circuit board including clock signals, control signals, and bus signals. is there.
近年、電気機器のプリント基板の高密度化や高速化が進んでおり、プリント基板の機能を正確に実現できるように、電気回路設計やプリント基板設計において、伝送線路解析を実施している。伝送線路解析は、ノイズがないクロック信号を実現する電子部品の選定や伝送線路を設計するため、さらには、複数の電子部品間でタイミングを合わせて、バス信号を伝播する電子部品の選定や伝送線路を設計する視点から実施される。 In recent years, the density and speed of printed circuit boards of electrical devices have been increased, and transmission line analysis has been carried out in electrical circuit design and printed circuit board design so that the functions of the printed circuit board can be accurately realized. In transmission line analysis, in order to select electronic parts that realize clock signals without noise and to design transmission lines, it is also necessary to select and transmit electronic parts that propagate bus signals at the same timing among multiple electronic parts. It is implemented from the viewpoint of designing the track.
従来、これら2つの視点を同時に解析する方法として、例えば、実際に配線した配線長をもとに算出した配線遅延を配線許容遅延と比較することで、タイミングを考慮した電子部品の配置や電子部品を接続する配線の設計が行われている(例えば、特許文献1参照)。 Conventionally, as a method for analyzing these two viewpoints simultaneously, for example, by comparing the wiring delay calculated based on the actually wired wiring length with the wiring allowable delay, the arrangement of the electronic components in consideration of the timing and the electronic components are considered. A wiring for connecting the two is designed (for example, see Patent Document 1).
図6に従来の解析システムで扱う電気回路の概要を示す。図6において、バス信号を伝播する伝送線路66は、1つのドライバの電子部品62と、1つのレシーバの電子部品63を接続している。電子部品61から伝送線路64と伝送線路65を通じて、バス信号のタイミングを制御するクロック信号が伝播される。この電気回路では、伝送線路64と伝送線路65の電気特性を、伝送線路66の伝送線路解析に利用することで、バス信号とクロック信号のタイミングとノイズを同時に解析できる。
しかし、従来の電気回路では、伝送線路の電気特性を利用するのは、ドライバとレシーバの2つの電子部品へのクロック信号に限定されているため、それ以外にデータを一時保存するためのバッファの電子部品と制御信号を含む電気回路を解析することはできない。 However, in the conventional electric circuit, the electrical characteristics of the transmission line are limited to the clock signal to the two electronic components of the driver and the receiver, and other than that, a buffer for temporarily storing data is used. It is not possible to analyze an electrical circuit including electronic components and control signals.
本発明は、複数の電子部品から構成されるクロック信号と制御信号と多接続のバス信号を含む電気回路全体に対するタイミングとノイズを同時に解析することができる伝送線路解析システムを提供することを目的とする。 It is an object of the present invention to provide a transmission line analysis system that can simultaneously analyze timing and noise for an entire electric circuit including a clock signal, a control signal, and a multi-connection bus signal composed of a plurality of electronic components. To do.
この課題を解決するために、本発明の伝送線路解析システムは、解析対象の電気回路の伝送線路解析モデルを生成する手段と、電子部品の電気特性を蓄積する手段と、伝送線路の電気特性を蓄積する手段と、蓄積された電子部品の電気特性と伝送線路の電気特性とから、伝送線路の解析モデルに対して伝送線路のタイミングを補正する手段と、タイミング補正した解析モデルから、伝送線路解析ソフトを用いて伝送線路解析をする手段と、伝送線路解析の結果から、伝送線路の電気特性を抽出する手段とからなることを特徴とするものであり、本発明の伝送線路解析システムは、また、電子部品の電気特性は、バス信号を出力するタイミングであり、伝送線路の電気特性は、伝送線路を伝播する制御信号であり、蓄積された電子部品の電気特性と伝送線路の電気特性とから、伝送線路の解析モデルに対して、伝送線路を伝播するバス信号のタイミングを補正することを特徴とするものである。 In order to solve this problem, the transmission line analysis system of the present invention includes means for generating a transmission line analysis model of an electrical circuit to be analyzed, means for storing electrical characteristics of electronic components, and electrical characteristics of the transmission line. The means for accumulating, the means for correcting the transmission line timing with respect to the analysis model of the transmission line from the electrical characteristics of the stored electronic components and the electrical characteristics of the transmission line, and the transmission line analysis from the analysis model corrected for the timing The transmission line analysis system of the present invention is characterized by comprising means for performing transmission line analysis using software and means for extracting the electrical characteristics of the transmission line from the result of the transmission line analysis. The electrical characteristics of electronic components are the timing at which bus signals are output, and the electrical characteristics of transmission lines are control signals that propagate through the transmission lines. From the electrical characteristics of the transmission line, with respect to the analysis model of the transmission line, it is characterized in that to correct the timing of the bus signals propagating through the transmission line.
本発明によると、蓄積した電子部品の電気特性と、蓄積した伝送線路の電気特性とを用いて、解析モデルに対してバス信号のタイミングを補正して、伝送線路解析をするように構成したので、複数の電子部品から構成されるクロック信号と制御信号と多接続のバス信号を含む電気回路全体に対するタイミングとノイズを同時に解析することができる。 According to the present invention, the transmission line analysis is performed by correcting the timing of the bus signal with respect to the analysis model using the accumulated electrical characteristics of the electronic components and the accumulated electrical characteristics of the transmission line. The timing and noise of the entire electric circuit including a clock signal, a control signal, and a multi-connection bus signal composed of a plurality of electronic components can be analyzed simultaneously.
本発明によれば、電子部品の電気特性蓄積部に蓄積した電気特性と、伝送線路の電気特性蓄積部に蓄積した電気特性とを用いて、解析モデルに対して、タイミングを補正して伝送線路解析することにより、複数の電子部品から構成されるクロック信号と制御信号と多接続のバス信号を含む電気回路全体に対するタイミングとノイズを同時に解析することができる。 According to the present invention, using the electrical characteristics accumulated in the electrical property accumulation unit of the electronic component and the electrical characteristics accumulated in the electrical property accumulation unit of the transmission line, the transmission line is corrected by correcting the timing with respect to the analysis model. By analyzing, it is possible to simultaneously analyze timing and noise for the entire electric circuit including a clock signal, a control signal, and a multi-connection bus signal composed of a plurality of electronic components.
以下、本発明の実施の形態について、図1から図5を用いて説明する。
(実施の形態1)
図1は本発明のタイミング伝送線路解析システムの構成ブロック図である。図において、11は伝送線路の解析モデルの生成部、12は解析モデルのタイミング補正部、13は伝送線路解析ソフト、14は伝送線路の電気特性の抽出部、15は電子部品の電気特性蓄積部、16は伝送線路解析の結果、17は伝送線路の電気特性蓄積部である。
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
(Embodiment 1)
FIG. 1 is a configuration block diagram of a timing transmission line analysis system of the present invention. In the figure, 11 is a transmission line analysis model generation unit, 12 is an analysis model timing correction unit, 13 is a transmission line analysis software, 14 is a transmission line electrical characteristic extraction unit, and 15 is an electronic component electrical characteristic storage unit. , 16 is a result of the transmission line analysis, and 17 is an electrical characteristic storage unit of the transmission line.
図2は本発明のタイミング伝送線路解析システムで扱う電気回路の1例である。21はクロック信号と制御信号のドライバの電子部品、22はバス信号のドライバの電子部品、23はバス信号のレシーバの電子部品、24と25はバス信号のバッファの電子部品、26と27はクロック信号を伝播する伝送線路、28と29はバス信号を伝播する伝送線路、210と211は制御信号を伝播する伝送線路である。 FIG. 2 shows an example of an electric circuit handled by the timing transmission line analysis system of the present invention. 21 is an electronic component of the driver of the clock signal and control signal, 22 is an electronic component of the driver of the bus signal, 23 is an electronic component of the receiver of the bus signal, 24 and 25 are electronic components of the buffer of the bus signal, and 26 and 27 are clocks Transmission lines that propagate signals, transmission lines 28 and 29 that propagate bus signals, and transmission lines 210 and 211 that propagate control signals.
電気回路の動作を次に示す。電子部品22から伝送線路28を通じて、電子部品24にバス信号が伝播される。一方、電子部品22から伝送線路29を通じて、電子部品25にバス信号が伝播される。一方、電子部品21からそれらのバス信号を出力するタイミングのクロック信号が伝送線路26を通じて伝播される。その後、電子部品21から伝送線路210を通じて、電子部品24にバス信号を出力するタイミングの制御信号が伝播され、電子部品21から伝送線路211を通じて、電子部品25にバス信号の制御信号が伝播される。各々に伝播された制御信号に応じて、電子部品24から伝送線路28を通じて、電子部品23へバス信号が伝播され、電子部品25から伝送線路29を通じて、電子部品23へバス信号が伝播される。その後、電子部品21から伝送線路27を通じて伝播されたクロック信号に応じて、各々伝播されたバス信号が電子部品23に取り込まれる。 The operation of the electric circuit is as follows. A bus signal is propagated from the electronic component 22 to the electronic component 24 through the transmission line 28. On the other hand, a bus signal is propagated from the electronic component 22 to the electronic component 25 through the transmission line 29. On the other hand, a clock signal for outputting those bus signals from the electronic component 21 is propagated through the transmission line 26. Thereafter, a control signal at a timing of outputting a bus signal to the electronic component 24 is propagated from the electronic component 21 through the transmission line 210, and a control signal of the bus signal is propagated from the electronic component 21 to the electronic component 25 through the transmission line 211. . A bus signal is propagated from the electronic component 24 to the electronic component 23 through the transmission line 28 and the bus signal is propagated from the electronic component 25 to the electronic component 23 through the transmission line 29 according to the control signal propagated to each. Thereafter, in accordance with the clock signal propagated from the electronic component 21 through the transmission line 27, each propagated bus signal is taken into the electronic component 23.
次に、図3を用いて伝送線路解析について説明する。31は伝送線路の入力波形、32は伝送線路の出力波形、33はレシーバの電子部品の0/1の閾値、34は伝送線路の電気特性である。本発明の特長は、多接続のバス信号のタイミングとノイズを同時に解析するために、伝送線路の電気特性34を、バス信号のタイミング補正に利用する点にある。 Next, transmission line analysis will be described with reference to FIG. 31 is an input waveform of the transmission line, 32 is an output waveform of the transmission line, 33 is a threshold value of 0/1 of the electronic components of the receiver, and 34 is an electrical characteristic of the transmission line. The feature of the present invention is that the electrical characteristic 34 of the transmission line is used for correcting the timing of the bus signal in order to simultaneously analyze the timing and noise of the bus signal of multiple connections.
図1の構成ブロック図の働きを、図2の電気回路を例にして詳しく説明する。本発明は、図2に例示する電気回路全体のタイミングとノイズを同時に解析することを、目的とするものである。図2に示す電気回路において、伝送線路210、211から伝播される制御信号が異なるため、電子部品24と電子部品25でバス信号を出力するタイミングが異なる。そのため、伝送線路210と伝送線路211に対して、事前に伝送線路解析することにより、各々の伝送線路の電気特性を伝送特性抽出部14にて抽出し、蓄積部17に蓄積しておく。次に、伝送線路28と伝送線路29に対して、解析モデル生成部11にて、各々の解析モデルを作成し、事前に電気特性蓄積部17に蓄積された伝送線路210と伝送線路211の電気特性と、電子部品の電気特性蓄積部15に蓄積された制御信号に応じて、電子部品の内部遅延である電子部品24と電子部品25の電気特性とを加算して、タイミング補正部12により、伝送線路28と伝送線路29を伝播するバス信号のタイミングを補正する。それに対して、伝送線路解析ソフト13を用いて、伝送線路解析の結果16を得る。これにより、多接続のバス信号のタイミングとノイズを同時に解析することができる。 1 will be described in detail by taking the electric circuit of FIG. 2 as an example. The object of the present invention is to simultaneously analyze the timing and noise of the entire electric circuit illustrated in FIG. In the electric circuit shown in FIG. 2, since the control signals propagated from the transmission lines 210 and 211 are different, the timing at which the electronic component 24 and the electronic component 25 output the bus signal is different. Therefore, by performing transmission line analysis on the transmission line 210 and the transmission line 211 in advance, the electrical characteristics of each transmission line are extracted by the transmission characteristic extraction unit 14 and stored in the storage unit 17. Next, the analysis model generation unit 11 creates each analysis model for the transmission line 28 and the transmission line 29, and the electrical characteristics of the transmission line 210 and the transmission line 211 stored in the electrical characteristic storage unit 17 in advance. Depending on the characteristics and the control signal stored in the electrical property storage unit 15 of the electronic component, the electrical characteristics of the electronic component 24 and the electronic component 25 that are internal delays of the electronic component are added, and the timing correction unit 12 The timing of the bus signal propagating through the transmission line 28 and the transmission line 29 is corrected. On the other hand, the transmission line analysis result 16 is obtained by using the transmission line analysis software 13. As a result, the timing and noise of the bus signal with multiple connections can be analyzed simultaneously.
さらに、伝送特性抽出部14にて、解析結果16から伝送線路28と伝送線路29の電気特性を抽出することにより、他の電気回路を伝送線路解析することが可能になる。なお、伝送線路の電気特性を蓄積部17で蓄積するので、伝送線路26や伝送線路27や伝送線路210や伝送線路211が、複数部品で構成された電気回路であっても、伝送線路の電気特性を加算すれば同様の解析ができる。 Furthermore, by extracting the electrical characteristics of the transmission line 28 and the transmission line 29 from the analysis result 16 in the transmission characteristic extraction unit 14, it becomes possible to analyze the transmission line of other electrical circuits. In addition, since the electrical characteristics of the transmission line are stored in the storage unit 17, even if the transmission line 26, the transmission line 27, the transmission line 210, and the transmission line 211 are electric circuits composed of a plurality of parts, The same analysis can be performed by adding the characteristics.
次に、タイミング補正部12の機能を図4と図5を用いて説明する。通常、バス信号は単一の電子部品から供給されるため、図4のバス信号41とバス信号42をそのまま伝送線路解析する。しかし、本発明では、複数の電子部品や多接続のバス信号を扱うため、図5に示すように、タイミング補正量53を用いて、タイミングを補正して、バス信号41をバス信号51にし、タイミング補正量54を用いて、タイミングを補正して、バス信号42をバス信号52にする。これにより、バス信号間のクロストークも実際の動作と同じ状態で伝送線路解析できる。タイミング補正量53とタイミング補正量54は、ドライバやバッファの電子部品に対するクロック信号や制御信号の伝送線路の電気特性として抽出される。図1と図2において、電気特性蓄積部17に蓄積された伝送線路210と伝送線路211の電気特性が、タイミング補正量53とタイミング補正量54である。 Next, the function of the timing correction unit 12 will be described with reference to FIGS. Since the bus signal is normally supplied from a single electronic component, the bus signal 41 and the bus signal 42 in FIG. However, in the present invention, in order to handle a plurality of electronic components and multi-connection bus signals, as shown in FIG. 5, the timing correction amount 53 is used to correct the timing, and the bus signal 41 is changed to the bus signal 51. Using the timing correction amount 54, the timing is corrected and the bus signal 42 is changed to the bus signal 52. As a result, the crosstalk between the bus signals can be analyzed in the same manner as the actual operation. The timing correction amount 53 and the timing correction amount 54 are extracted as electrical characteristics of the transmission line of the clock signal and control signal for the electronic components of the driver and the buffer. In FIG. 1 and FIG. 2, the electrical characteristics of the transmission line 210 and the transmission line 211 stored in the electrical characteristic storage unit 17 are the timing correction amount 53 and the timing correction amount 54.
11 解析モデル生成部
12 タイミング補正部
13 伝送線路解析ソフト
14 伝送特性抽出部
15 電子部品の電気特性蓄積部
16 伝送線路解析の結果
17 伝送線路の電気特性蓄積部
21 電子部品(クロック信号と制御信号のドライバ)
22 電子部品(バス信号のドライバ)
23 電子部品(バス信号のレシーバ)
24 電子部品(バス信号のバッファ)
25 電子部品(バス信号のバッファ)
26 伝送線路(クロック信号の伝播)
27 伝送線路(クロック信号の伝播)
28 伝送線路(バス信号の伝播)
29 伝送線路(バス信号の伝播)
210 伝送線路(制御信号の伝播)
211 伝送線路(制御信号の伝播)
31 伝送線路の入力波形
32 伝送線路の出力波形
33 電子部品の0/1閾値
34 伝送線路の電気特性
41 バス信号
42 バス信号
51 タイミング補正後のバス信号
52 タイミング補正後のバス信号
53 バス信号のタイミング補正量
54 バス信号のタイミング補正量
61 電子部品(クロック信号のドライバ)
62 電子部品(バス信号のドライバ)
63 電子部品(バス信号のレシーバ)
64 伝送線路(クロック信号の伝播)
65 伝送線路(クロック信号の伝播)
66 伝送線路(バス信号の伝播)
DESCRIPTION OF SYMBOLS 11 Analysis model production | generation part 12 Timing correction | amendment part 13 Transmission line analysis software 14 Transmission characteristic extraction part 15 Electrical characteristic storage part 16 Electronic line result of transmission line analysis 17 Transmission line electrical characteristic storage part 21 Electronic parts (clock signal and control signal) Driver)
22 Electronic components (bus signal driver)
23 Electronic components (bus signal receiver)
24 Electronic components (buffer for bus signals)
25 Electronic components (bus signal buffer)
26 Transmission line (clock signal propagation)
27 Transmission line (Clock signal propagation)
28 Transmission line (Bus signal propagation)
29 Transmission line (Bus signal propagation)
210 Transmission line (propagation of control signal)
211 Transmission line (propagation of control signal)
31 Transmission Line Input Waveform 32 Transmission Line Output Waveform 33 Electronic Component 0/1 Threshold 34 Transmission Line Electrical Characteristics 41 Bus Signal 42 Bus Signal 51 Bus Signal After Timing Correction 52 Bus Signal After Timing Correction 53 Bus Signal Timing correction amount 54 Bus signal timing correction amount 61 Electronic component (clock signal driver)
62 Electronic components (bus signal driver)
63 Electronic components (bus signal receiver)
64 Transmission line (Propagation of clock signal)
65 Transmission line (clock signal propagation)
66 Transmission line (Bus signal propagation)
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JP2010238170A (en) * | 2009-03-31 | 2010-10-21 | Nec Corp | System, method and program for verifying wiring |
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JP2010238170A (en) * | 2009-03-31 | 2010-10-21 | Nec Corp | System, method and program for verifying wiring |
US8312411B2 (en) | 2009-03-31 | 2012-11-13 | Nec Corporation | Wiring verification system, wiring verification method, and wiring verification program product |
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