JP2005037498A - Driving device of light emitting display panel and driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving device for a light emitting display panel capable of reducing the horizontal cross talk caused by a lighting state (the lighting rate of light emitting elements by each of scanning lines and dimmer set rate) of the light emitting elements. <P>SOLUTION: A scanning driver 3 acts to successively scan the scanning lines K1 to Km arrayed at the display panel A at a prescribed period to light and drive the light emitting elements E 11 to Enm made to correspond to the scanning lines of a scanning state and to supply a reverse bias voltage VM from a reverse bias voltage source 5 to the scanning line of a non-scanning state. A time constant control means where the output time constant (a resistor R254 alone or the parallel connection of the resistors R25 and R26) from the reverse bias voltage source is controlled according to, for example, the dimmer set value in the display panel 1 is provided between the reverse bias voltage source 5 and the scanning driver 3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a drive device for a light-emitting display panel using, for example, an organic EL (electroluminescence) element as a light-emitting element, and in particular, due to a lighting state of the light-emitting element (an element lighting rate and a dimmer value for each scanning line). The present invention relates to a driving device and a driving method for a light-emitting display panel that can reduce horizontal crosstalk generated by the above.
[0002]
[Prior art]
Development of a display panel in which light emitting elements are arranged in a matrix has been widely promoted, and organic EL elements using an organic material for a light emitting layer are attracting attention as light emitting elements used in such display panels. . This is also due to the fact that the use of an organic compound that can be expected to have good light-emitting characteristics for the light-emitting layer of the device has led to higher efficiency and longer life that can withstand practical use.
[0003]
The above-described organic EL element can be replaced with a configuration of a light emitting element having an electrically diode characteristic and a parasitic capacitance component coupled in parallel to the light emitting element. The organic EL element is a capacitive light emitting element. It can be said.
[0004]
When a light emission driving voltage is applied to the organic EL element, first, a charge corresponding to the electric capacity of the element flows into the electrode as a displacement current and is accumulated. Subsequently, when a certain voltage specific to the element (light emission threshold voltage = Vth) is exceeded, current begins to flow from one electrode (the anode side of the diode component) to the organic layer constituting the light emitting layer, and the intensity proportional to this current Can be considered to emit light.
[0005]
On the other hand, the current / luminance characteristics of organic EL elements are stable with respect to temperature changes, whereas the voltage / luminance characteristics are unstable with respect to temperature changes. In general, constant current driving is performed for reasons such as severe deterioration when received and shortening the light emission life. As a display panel using such an organic EL element, a passive drive display panel in which elements are arranged in a matrix has already been put into practical use.
[0006]
FIG. 1 shows an example of a conventional passive matrix display panel and its driving circuit. There are two methods for driving the organic EL element in this passive matrix driving system: cathode line scanning / anode line driving and anode line scanning / cathode line driving. The configuration shown in FIG. The form of an anode wire drive is shown. That is, anode lines A1 to An as n drive lines are arranged in the vertical direction, and cathode lines K1 to Km as m scan lines are arranged in the horizontal direction, and each intersecting portion (total n × m locations) ), The organic EL elements E11 to Enm indicated by diode symbol marks are arranged to constitute the display panel 1.
[0007]
Each EL element E11 to Enm constituting the pixel has one end (anode in an equivalent diode of the EL element) corresponding to each intersection position of the anode lines A1 to An along the vertical direction and the cathode lines K1 to Km along the horizontal direction. The terminal is connected to the anode line, and the other end (the cathode terminal in the equivalent diode of the EL element) is connected to the cathode line. Further, each anode line A1 to An is connected to an anode line drive circuit 2 as a data driver, and each cathode line K1 to Km is connected to and driven by a cathode line scanning circuit 3 as a scanning driver.
[0008]
The anode line drive circuit 2 includes constant current sources I1 to In and drive switches Sa1 to San that operate using a drive voltage VH provided from a booster circuit 4 in a DC-DC converter to be described later. When the switches Sa1 to San are connected to the constant current sources I1 to In, the currents from the constant current sources I1 to In are supplied to the individual EL elements E11 to Enm arranged corresponding to the cathode lines. Acts as supplied. The drive switches Sa1 to San are configured to connect the anode line to the ground side as a reference potential point when the current from the constant current sources I1 to In is not supplied to the individual EL elements. Yes.
[0009]
Further, the cathode line scanning circuit 3 is provided with scanning switches Sk1 to Skm corresponding to the cathode lines K1 to Km, and a reverse bias voltage generating circuit (which is described later as a reverse bias voltage) for preventing crosstalk light emission. It is also referred to as a source.) It acts to connect either the reverse bias voltage VM from 5 or the ground potential as the reference potential point to the corresponding cathode line. Accordingly, the EL elements are selectively emitted by connecting the constant current sources I1 to In to desired anode lines A1 to An while setting the cathode lines to the reference potential point (ground potential) at a predetermined cycle. It works to let you.
[0010]
On the other hand, the DC-DC converter described above is configured to generate a DC drive voltage VH using PWM (pulse width modulation) control as the booster circuit 4 in the example shown in FIG. The DC-DC converter can use well-known PFM (pulse frequency modulation) control or PSM (pulse skip modulation) control instead of PWM control.
[0011]
This DC-DC converter is configured such that a PWM wave output from a switching regulator 6 constituting a part of the booster circuit 4 turns on the MOS power FET Q1 as a switching element with a predetermined duty cycle. That is, the power energy from the DC voltage source B1 on the primary side is accumulated in the inductor L1 by the on operation of the power FET Q1, and the power energy accumulated in the inductor L1 with the off operation of the power FET Q1 is passed through the diode D1. Is stored in the capacitor C1. Then, by repeating the on / off operation of the power FET Q1, the boosted DC output can be obtained as the terminal voltage of the capacitor C1.
[0012]
The DC output voltage is divided by the thermistor TH1 that performs temperature compensation and the resistors R11 and R12, and is supplied to the error amplifier 7 in the switching regulator 6. The error amplifier 7 compares the voltage with the reference voltage Vref. This comparison output (error output) is supplied to the PWM circuit 8 and feedback control is performed so as to maintain the output voltage at a predetermined drive voltage VH by controlling the duty of the signal wave provided from the oscillator 9. Therefore, the output voltage from the DC-DC converter, that is, the drive voltage VH can be expressed as follows.
[0013]
[Expression 1]
VH = Vref × [(TH1 + R11 + R12) / R12]
[0014]
On the other hand, the reverse bias voltage generation circuit 5 used for preventing the crosstalk light emission is configured by a voltage dividing circuit that divides the drive voltage VH. That is, this voltage dividing circuit is constituted by resistors R13 and R14 and an npn transistor Q2 functioning as an emitter follower, and obtains a reverse bias voltage VM at the emitter of the transistor Q2. Therefore, if the base-emitter voltage in the transistor Q2 is expressed as Vbe, the reverse bias voltage VM obtained by this voltage dividing circuit can be expressed as follows.
[0015]
[Expression 2]
VM = VH × [R14 / (R13 + R14)] − Vbe
[0016]
Note that a control bus is connected to the anode line drive circuit 2 and the cathode line scan circuit 3 from a light emission control circuit 11 including a CPU, and the scan switches Sk1 to Skm and the drive are driven based on a video signal to be displayed. The switches Sa1 to San are operated. Thus, the constant current sources I1 to In are connected to the desired anode line while setting the cathode scanning line to the ground potential at a predetermined cycle based on the video signal. Accordingly, each light emitting element selectively emits light, and an image based on the video signal is displayed on the display panel 1.
[0017]
In the state shown in FIG. 1, the first cathode line K1 is set to the ground potential to be in the scanning state. At this time, the non-scanning cathode lines K2 to Km are supplied from the reverse bias voltage generation circuit 5 described above. A reverse bias voltage VM is applied. Therefore, each EL element connected to the intersection of the driven anode line and the cathode line not selected for scanning acts to prevent crosstalk light emission.
[0018]
By the way, the organic EL element has a parasitic capacitance as described above. For example, in the case where dozens of EL elements are connected to one anode line, each parasitic capacitance is viewed from the anode line. The combined capacity of several tens of times is connected to the anode line as a load capacity.
[0019]
Therefore, the current from the anode line at the beginning of the scanning period is consumed to charge the load capacitance, and a time delay occurs to charge until the light emitting threshold voltage of the EL element is sufficiently exceeded. There arises a problem that the rise of light emission of the element is delayed. In particular, when the constant current sources I1 to In are used as the drive sources as described above, the constant current source is a high-impedance output circuit on the principle of operation, so that the current is limited and the emission rise of the EL element is suppressed. There is a noticeable delay.
[0020]
Therefore, a cathode reset method is generally employed in this type of drive circuit. This cathode reset method acts so as to accelerate the light emission rise of the EL element driven to emit light corresponding to the next scanning line when the scanning line is switched.
[0021]
FIGS. 2A to 2D illustrate the cathode reset operation. For example, from the state in which the EL element E11 connected to the first anode line A1 is driven to emit light, The state where the EL element E12 connected to the first anode line A1 is driven to emit light is shown. In FIG. 2, EL elements driven to emit light are shown as diode symbol marks, and the others are shown as capacitor symbol marks as parasitic capacitances.
[0022]
FIG. 2A shows a state before the cathode reset operation, and shows a state in which the cathode line K1 is scanned and the EL element E11 emits light. The EL element E12 is caused to emit light in the next scanning. Before the EL element E12 is caused to emit light, the anode line A1 is connected to the ground via the switch Sa1, as shown in FIG. Although not provided, all the cathode lines are also connected to the ground via the scanning switches Sk1 to Skm. As a result, a reset operation for discharging all the electric charges of each EL element is executed.
[0023]
Next, in order to cause the EL element E12 to emit light, the cathode line K2 is brought into a scanning state. That is, the cathode line K2 is connected to the ground, and the reverse bias voltage VM is applied to the other cathode lines. At this time, the drive switch Sa1 is switched to the constant current source I1 side.
[0024]
Therefore, since the charge of the parasitic capacitance in each element is discharged at the time of the above-described reset, as shown in (c) at this moment, the parasitic capacitance by the elements other than the element E12 that emits light next is indicated by an arrow. As shown, reverse charging is performed with the reverse bias voltage VM. The charging current for these flows into the EL element E12 that emits light next through the anode line A1, and charges the parasitic capacitance of the EL element E12. At this time, the constant current source I1 connected to the anode line A1 is basically a high impedance output circuit as described above, and does not affect the movement of the charging current.
[0025]
In this case, it is assumed that, for example, 64 EL elements are arranged on the anode line A1, and the reverse bias voltage VM is, for example, 10 (V). Since the potential V (A1) of the line A1 is so small that the wiring impedance in the panel is negligible, the potential V (A1) instantaneously rises to the potential based on the following Equation 3.
[0026]
[Equation 3]
V (A1) = (VM × 63 + 0V × 1) /64=9.84V
[0027]
Thereafter, the EL element E12 enters a light emitting state as shown in (d) by the drive current from the constant current source I1 flowing through the anode line A1. As described above, the above-described cathode reset method uses the parasitic capacitance of the EL element that is originally an obstacle to driving and the reverse bias voltage VM for preventing crosstalk light emission, so that the forward voltage of the EL element that is next driven to be lit is used. It works to instantly start up.
[0028]
As described above, the passive drive type display panel having the configuration shown in FIG. 1 and its drive circuit are disclosed in the following Patent Document 1 already filed by the present applicant. The cathode reset method shown in FIG. 2 is disclosed in Patent Document 2.
[0029]
[Patent Document 1]
Japanese Patent Laying-Open No. 2003-76328 (paragraphs 0007 to 0020, FIG. 6)
[Patent Document 2]
Japanese Patent Laid-Open No. 9-232974 (paragraphs 0018 to 0033, FIGS. 1 to 4)
[0030]
[Problems to be solved by the invention]
However, the drive circuit that performs the cathode reset operation described above has a problem that horizontal crosstalk occurs due to the lighting state of the display panel (the lighting rate of the light emitting element for each scanning line and the dimmer setting value). ing. FIG. 3 schematically shows the lighting state of the display panel 1 in which the horizontal crosstalk described above can occur. Here, the display pattern shown in FIG. 3 indicates a region where the A portion with double hatching is controlled to be in a non-lighting state, and the B portion and the C portion indicate regions that are controlled to be in a lighting state.
[0031]
As shown by A in FIG. 3, when the ratio of non-lighting elements is large as seen for each scanning line, the combined parasitic capacitance due to the EL elements arranged in the display panel 1 becomes large. The phenomenon that the rise characteristic of the light emission becomes slow occurs. In the description of the cathode reset operation described above, this point is not mentioned, but in reality, it is unavoidable that such a phenomenon occurs due to the influence of the wiring impedance in the display panel.
[0032]
For example, when a display panel having 128 anode lines as drive lines and 64 scan lines is taken as an example and the parasitic capacitance of one EL element is Cp, all the EL elements are turned off during the scan. In this case, the combined parasitic capacitance value in the display panel viewed from the reverse bias voltage generation circuit 5 side is 63 Cp per drive line. This corresponds to the number of EL elements in the non-scanning state. Accordingly, since there are 128 drive lines in this state as described above, the combined parasitic capacitance value in the display panel is 63 Cp × 128 = 8064 Cp.
[0033]
On the other hand, when all the EL elements are turned on in the scanning, the combined parasitic capacitance value in the display panel viewed from the reverse bias voltage generation circuit 5 side is parallel parasitic capacitance due to 63 EL elements in one drive line, It becomes a series circuit of parasitic capacitance by one EL element to be lit. This means that the parasitic capacitance per drive line is approximately Cp. Since there are 128 drive lines in this state as described above, the combined parasitic capacitance value in the display panel at this time is about 128 Cp. Therefore, comparing the combined parasitic capacitance when all the lights are turned off with the combined parasitic capacitance when all the lights are turned on, 8064 Cp / 128 Cp = 63, and a difference of 63 times in capacitance value occurs.
[0034]
Therefore, the greater the number of EL elements that are controlled to be turned off during scanning, the greater the combined parasitic capacitance value as viewed from the reverse bias voltage generation circuit 5 side for the reason described above. FIG. 5A is a diagram for explaining the rising characteristic of the luminance corresponding to the above-described combined parasitic capacitance value, and shows the luminance characteristic corresponding to the reference clock (CLK) as the scanning signal. Here, as shown in the left half of FIG. 5 (a), when scanning a line with few non-lighted portions (that is, when scanning a region indicated by C in FIG. 3), in synchronization with the reference clock, A characteristic that light emission (luminance) rises relatively steeply can be obtained. This is because the combined parasitic capacitance value is small as described above.
[0035]
On the other hand, as shown in the right half of FIG. 5A, when scanning a line with many non-lighted portions (that is, when scanning the areas indicated by A and B in FIG. 3), the reference clock is used. The rising characteristics of synchronized light emission (luminance) become slow. This is because it is influenced by a large synthetic parasitic capacitance as described above. On the other hand, when scanning a line with many non-lighted portions, as shown in the right half of FIG. 5A, a phenomenon occurs in which the potential of the anode line to be lit increases and the instantaneous luminance of the EL element increases. In addition, the inventor of the present application knows empirically.
[0036]
The area indicated by the product of luminance and time due to the above phenomenon can be recognized as brightness on the display screen by human eyes. Therefore, as shown in the right half of FIG. 5A, even if the rise of light emission is slow, the horizontal luminance increases due to the increase in the instantaneous luminance of the element due to the increase in the potential of the anode line to be lit. In some cases, crosstalk hardly occurs. That is, in this case, the brightness of the areas indicated by B and C in FIG. 3 is made equal.
[0037]
On the other hand, depending on the display pattern and time constant in the display panel, the area corresponding to the cathode line with many non-lighted parts as shown in FIG. 5B has an area indicated by the product of luminance and time. In some cases, the image becomes larger and brightly displayed on the display screen. That is, in this case, the region indicated by B is displayed brighter than C in FIG. 3, resulting in “bright crosstalk”. Furthermore, when dimmer control is performed in addition to the above-described phenomenon, “dark crosstalk” may occur on the contrary depending on the degree of dimmer control.
[0038]
FIG. 4 shows an example of the case where the above-described dimmer control is executed. In this example, by changing the supply time (lighting time) of the drive current applied to the EL element in one scanning period, The example which controls substantial light-emitting luminance is shown. That is, as shown in FIG. 4, the cathode reset operation Rs is executed in synchronization with the line sync signal Ls indicating one line of display, and the dimmer control is executed in the remaining period following the cathode reset operation Rs. The
[0039]
Here, in the dimmer control period indicated as DRn, as shown in FIG. 4, the EL element is controlled to be turned on by time division. In other words, the lighting possible period in one scanning line period is divided into 0 to 15, and by controlling lighting of these periods with 4 bits, 16-stage dimmer control can be realized. Therefore, in the dimmer control shown in FIG. 4, when the dimmer value is “15”, the drive current is supplied from the constant current sources I1 to In in the anode line drive circuit 2 to the EL elements in the entire dimmer control period. The display screen is in the brightest state. On the other hand, when the dimmer value is “0”, the drive current is supplied from the constant current sources I1 to In to the EL element only during the period “0” in FIG. Made into a state.
[0040]
Incidentally, as described above, there are many non-lighting portions corresponding to the cathode lines in the display panel, and when the dimmer control as described above is executed, the electrical characteristics thereof are as shown in FIG. To be made. That is, the left half of FIG. 5C shows the luminance characteristics in a line with few non-lighting parts, as in the example already described. In order to receive the dimmer control, the reference clock is controlled to fall after a period of t2 shorter than the total lighting period t1 corresponding to the dimmer value “15”. As a result, the luminance of the EL element that is turned on also suddenly declines and is turned off.
[0041]
On the other hand, in the line having many non-lighted portions as shown in the right half of FIG. 5C, the luminance rises slowly in synchronization with the rise of the reference clock as described above, and the luminance is increased after the period of t2. Falls. As a result, as shown in the right half part of FIG. 5B, it is impossible to obtain an increase characteristic of the instantaneous luminance of the element due to an increase in the potential of the anode line to be lit. As a result, the “B” area shown in FIG. 3 is darker than the area indicated by “C”, resulting in “dark crosstalk”.
[0042]
In the above description, the case where the scanning lines in the display panel are arranged in the horizontal direction is taken as an example, and the phenomenon that occurs in this case is referred to as horizontal crosstalk. Therefore, when the scanning lines in the display panel are arranged in the vertical direction, crosstalk due to the phenomenon described above occurs in the vertical direction. In the following description, these are both horizontal crosstalk. I will call it.
[0043]
As described above, the present invention provides a light emitting display panel that can effectively reduce the horizontal crosstalk generated due to the lighting rate of the light emitting elements for each scanning line and the lighting state of the light emitting elements such as dimmer control. An object of the present invention is to provide a driving device and a driving method.
[0044]
[Means for Solving the Problems]
The light emitting display panel driving apparatus according to the present invention, which has been made to achieve the above object, includes a plurality of drive lines and a plurality of scanning lines intersecting each other, and each of the drive lines and A driving device for a light-emitting display panel comprising capacitive light-emitting elements each having a diode characteristic connected between each drive line and each scan line at each intersection position with the scan line, A reverse bias voltage source for applying a reverse bias voltage to the scanning line in the non-scanning state in a state where the light emitting element is driven to emit light by scanning the light emitting element at a predetermined cycle, And a time constant control means for controlling an output time constant from the reverse bias voltage source.
[0045]
According to another aspect of the present invention, there is provided a driving method for a light emitting display panel according to the present invention, wherein a plurality of drive lines and a plurality of scanning lines intersecting each other, and each of the drive lines. And a method of driving a light emitting display panel comprising capacitive light emitting elements having diode characteristics respectively connected between the drive lines and the scan lines at each of the intersections with the scan lines, In a state where the scanning line is scanned at a predetermined period and the light emitting element is driven to emit light, a reverse bias voltage is applied to the scanning line in the non-scanning state, and according to the lighting state of the light emitting element in the light emitting display panel, It is characterized in that the output time constant of the reverse bias voltage is switched.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
A light emitting display panel driving apparatus according to the present invention will be described below based on the embodiment shown in FIG. In FIG. 6, portions corresponding to the components shown in FIG. 1 already described are denoted by the same reference numerals, and thus detailed description thereof is omitted. The reverse bias voltage generation circuit (reverse bias voltage source) 5 in the embodiment shown in FIG. 6 is configured by a series circuit of a Zener diode ZD1 connected to the booster circuit 4 and a resistor R14. That is, the reverse bias voltage generation circuit 5 obtains the reverse bias voltage VM as the terminal voltage of the capacitor C2 by dropping the Zener voltage of the diode ZD1 from the drive voltage VH provided from the booster circuit 4.
[0047]
On the other hand, as already described based on the embodiment shown in FIG. 1, the light emission control circuit 11 is driven by the scanning switches Sk1 to Skm in the cathode line scanning circuit 3 and the drive in the anode line drive circuit 2 by the video signal supplied thereto. It operates so as to switch the switches Sa1 to San. In addition, the embodiment shown in FIG. 6 is configured such that a control output from the dimmer control circuit 12 is supplied to the light emission control circuit 11.
[0048]
That is, the light emission control circuit 11 receives the control output from the dimmer control circuit 12, and sets the supply period of the drive current supplied from the constant current sources I1 to In to the EL elements in the anode line drive circuit 2 by time-sharing control. It is configured as follows. This is equivalent to the form of the dimmer control described with reference to FIG. 4, and thereby, 16-stage dimmer control with dimmer values “0” to “15” is realized. In the embodiment shown in FIG. 6, the cathode reset operation Rs is also executed as shown in FIG. 4 just before the lighting period by the dimmer control. The details of the cathode reset operation Rs are as described with reference to FIG.
[0049]
The light emission control circuit 11 is configured to supply a control signal to the time constant switching circuit 13 in order to obtain an optimal time constant based on the dimmer control from the dimmer control circuit 12. Yes. In the embodiment shown in FIG. 6, the switch S1 is configured to be opened and closed by a command signal from the time constant switching circuit 13. When the switch S1 is in an open (off) state, a reverse bias voltage source is provided. A resistor R25 constituting a time constant is interposed between 5 and the cathode ray scanning circuit 3. When the switch S1 is closed (ON), a resistor R26 is further connected in parallel with the resistor R25 forming a time constant between the reverse bias voltage source 5 and the cathode ray scanning circuit 3. Acts to be.
[0050]
Here, a combination of the dimmer control circuit 12, the switch S1, and the resistors R25 and R26 constitutes a time constant control means. A specific example of this time constant control means is indicated by reference numeral 15 in FIG. Has been. 7 indicates the reverse bias voltage generation circuit shown in FIG. 6.
[0051]
The time constant control means 15 is provided with a logic input terminal L3, and a series circuit of resistors R31 and R32 is connected to the terminal L3. The base of an npn transistor Q3 whose emitter is grounded is connected to the midpoint of connection between the resistors R31 and R32. The reverse bias voltage is generated via the resistor R35 at the collector of the transistor Q3. The reverse bias voltage VM from the circuit 5 is supplied.
[0052]
Similarly, the collector of the transistor Q3 is connected to the base of an npn transistor Q4 whose emitter is ground-connected, and the collector of the transistor Q4 is reverse-biased via resistors R36 and R37 connected in series. The reverse bias voltage VM from the voltage source 5 is supplied. Further, the base of a pnp type transistor Q5 whose emitter is connected to the reverse bias voltage source 5 is connected to the connection midpoint of the resistors R36 and R37.
[0053]
The resistor R25, one end of which is connected to the reverse bias voltage source 5, is configured such that a resistor R26 is connected in parallel through the emitter and collector of the transistor Q5. That is, the transistor Q5 shown in FIG. 7 is configured to function as the switch S1 shown in FIG.
[0054]
Here, as described above, the dimmer value given from the dimmer control circuit 12 is controlled by 4 bits in 16 steps from the dimmer value “15” (bright) to the dimmer value “0” (dark). Yes. The most significant bit of the dimmer signal is supplied to the terminal L3 shown in FIG. 7, and low (low) is supplied for the dimmer value from “0” to “7”, and high for the dimmer value from “8” to “15”. It works so that (High) is supplied.
[0055]
Therefore, when the dimmer value is in the range of “0” to “7”, the transistor Q5 is turned on as a result, and the parallel connection body of the resistors R25 and R26 is connected to the reverse bias voltage source 5, the cathode line scanning circuit 3, and the like. It will be interposed between. Thereby, the output time constant from the reverse bias voltage source 5 formed between the parallel connection body of the resistors R25 and R26 and the parasitic capacitance of the EL element in the display panel 1, in other words, to the parasitic capacitance. The charging time constant is controlled to be small.
[0056]
When the dimmer value is in the range of “8” to “15”, the transistor Q5 is turned off as a result, and the resistor R25 is interposed between the reverse bias voltage source 5 and the cathode line scanning circuit 3. Become. Thereby, the output time constant from the reverse bias voltage source 5 formed between the resistor R25 and the parasitic capacitance of the EL element in the display panel 1, in other words, the charging time constant for the parasitic capacitance is increased. Controlled.
[0057]
FIG. 8 illustrates the operation when the charging time constant to the parasitic capacitance is changed as described above based on the dimmer value. The waveform shown in FIG. 8 shows an example in the case where the dimmer control is executed in the same manner as the waveform shown in FIG. That is, as shown in the right half of FIG. 8, in a line with many non-lighted portions, the combined parasitic capacitance increases, so that the rising characteristic of luminance synchronized with the rising of the reference clock becomes slow. Then, the luminance falls after the t2 period elapses due to the execution of the dimmer control. As a result, as described above, it is not possible to obtain an increase characteristic of the instantaneous luminance of the element due to an increase in the potential of the anode line to be lit, and as a result, the region B shown in FIG. A “dark crosstalk” that is darker than the region occurs.
[0058]
By the way, in the case where the countermeasure for changing the time constant based on the dimmer control is taken as described above, when the dimmer value is controlled to a certain degree or less (controlled darkly), the time constant is reduced. . As a result, the charging response to the parasitic capacitance of the EL element is enhanced. This is indicated by a broken line in FIG. 8, and the rising characteristic of luminance is greatly corrected in the right half rather than the left half. As a result of the steep rise characteristics, even in a line with many non-lighted portions, the same characteristics as the lighting luminance of a line with few non-lighted portions can be obtained, and the occurrence of the aforementioned “dark crosstalk” can be prevented. Can do.
[0059]
On the contrary, when the dimmer value is controlled to a certain degree or more (brightly controlled), the time constant described above is increased. As a result, the charging response to the parasitic capacitance of the EL element is reduced and the rise in luminance is returned to a slow characteristic. In this case, however, the instantaneous luminance of the element due to an increase in the potential of the anode line to be lit is increased. Ascending characteristics can be obtained. As a result, for example, as shown in FIG. 5 (a), the area as the product of the luminance and the light emission time can be made substantially equal regardless of the line with few non-lighted parts and the line with many non-lighted parts. The occurrence of horizontal crosstalk can be suppressed.
[0060]
In the embodiment described above, the dimmer value is divided into two stages, “bright” and “dark”, and the time constant is similarly controlled in two stages. The time constant can be controlled in multiple stages in the same way. In this case, as shown in FIG. 6 and FIG. 7, in addition to using the resistors constituting the time constant in the configuration of the parallel connection, a plurality of resistors are alternatively selected and used, Alternatively, it is possible to adopt a configuration in which they are connected in series with each other.
[0061]
In the embodiment described above, the output time constant from the reverse bias voltage source 5 (time constant for charging the parasitic capacitance of the EL element) is changed based on the dimmer value. In addition to the change of the time constant, it is desirable to add information on the lighting rate of the light emitting element for each scanning line to change the time constant.
[0062]
In this case, ideally, for example, as shown in FIG. 9, a lookup table is constructed in a non-volatile memory such as an EEPROM using the lighting rate of the light emitting element for each scanning line and the set dimmer value as parameters. By referring to this look-up table, the output time constant is obtained. That is, “Line No. 01” in FIG. 9 is a table to be referred to when scanning the first scanning line (cathode line K1), and thereafter “Line No. 02”, “Line No. 03”,. It is constructed up to line No. m ″.
[0063]
Then, the light emission control circuit 11 shown in FIG. 6 reads this from the two-dimensional table shown in FIG. 9 based on the lighting rate of the line and the dimmer value set at that time immediately before the scanning of each scanning line. The optimum resistance value (R11... Rxx) corresponding to is read out. By switching to the time constant based on the resistance value for each scanning line, ideal compensation characteristics can be obtained, and the occurrence of horizontal crosstalk as already described can be greatly reduced.
[0064]
When the degree of variation in the parasitic capacitance of each element or the impedance of the cathode line in each light emitting display panel is large, a lookup table is constructed by measurement for each scanning line as shown in FIG. Is desirable. However, when the above-described variation tendency is converged, a lookup table that can be used in common may be constructed and used for each specification of the light emitting display panel.
[Brief description of the drawings]
FIG. 1 is a connection diagram illustrating a conventional display panel drive circuit;
FIG. 2 is an equivalent circuit diagram for explaining a cathode reset method used in a drive circuit of a passive drive type display panel.
FIG. 3 is a schematic diagram of a display panel for explaining a situation of occurrence of horizontal crosstalk.
FIG. 4 is a timing diagram illustrating an example of dimmer control.
FIG. 5 is a timing chart showing light emission luminance characteristics of EL elements according to the lighting rate of each scanning line.
FIG. 6 is a connection diagram showing a display panel drive circuit according to the present invention;
7 is a connection diagram showing an example of time constant control means in the drive circuit shown in FIG. 6. FIG.
FIG. 8 is a timing chart for explaining light emission luminance characteristics of an EL element formed by a display panel drive circuit according to the present invention;
FIG. 9 is a schematic diagram showing a construction example of a lookup table for determining a time constant made to reduce the occurrence of horizontal crosstalk.
[Explanation of symbols]
1 Luminescent display panel
2 Data driver
3 Scan driver
4 Booster circuit
5 Reverse bias voltage generation circuit (reverse bias voltage source)
11 Light emission control circuit
12 Dimmer control circuit
13 Time constant switching circuit
15 Time constant control means
A1 to An drive line (anode line)
B1 DC voltage source
D1 diode
E11-Enm Light emitting element (organic EL element)
I1 to In constant current source
K1-Km Scanning line (cathode line)
L1 inductor
Q1 Power FET
S1 switch
Sa1-San drive switch
Sk1-Skm scan switch
Vref reference voltage
ZD1 Zener diode

Claims (10)

A plurality of drive lines and a plurality of scan lines intersecting each other, and diode characteristics connected between the drive lines and the scan lines at each of the intersection positions of the drive lines and the scan lines. A drive device for a light emitting display panel comprising a capacitive light emitting element,
A reverse bias voltage source for applying a reverse bias voltage to a scanning line in a non-scanning state in a state in which the scanning line is scanned at a predetermined period to drive the light emitting element, and lighting of the light emitting element in the light emitting display panel A drive device for a light-emitting display panel, comprising: time constant control means for controlling an output time constant from the reverse bias voltage source according to a state. 2. The drive device for a light emitting display panel according to claim 1, wherein the output time constant controlled by the time constant control means is changed at least according to a setting state of a dimmer value. The time constant control means is configured to control the output time constant by changing a resistance value of a resistor interposed between the reverse bias voltage source and the scanning line of the light emitting display panel. The drive device of the light emission display panel of Claim 1 or Claim 2 characterized by these. The time constant control means is provided with a look-up table describing the data of the time constant corresponding to the lighting state of the light emitting element, and the output time constant is obtained by referring to the look-up table. 4. The drive device for a light emitting display panel according to claim 1, wherein the drive device is configured. The time constant switching means is configured to obtain output time constant data from a look-up table constructed using a lighting rate of a light emitting element for each scanning line and a set dimmer value as parameters. The drive device of the light emission display panel in any one of Claims 1 thru | or 4. 6. The drive device for a light emitting display panel according to claim 4, wherein the look-up table is constructed in a nonvolatile memory. The light-emitting display panel driving device according to claim 1, wherein the light-emitting elements constituting the light-emitting display panel are organic EL elements. A plurality of drive lines and a plurality of scan lines intersecting each other, and diode characteristics connected between the drive lines and the scan lines at each of the intersection positions of the drive lines and the scan lines. A driving method of a light emitting display panel comprising a capacitive light emitting element,
In a state where the scanning line is scanned at a predetermined cycle to drive the light emitting element to emit light, a reverse bias voltage is applied to the scanning line in the non-scanning state, and the light emitting element in the light emitting display panel is turned on. A method for driving a light emitting display panel, wherein the output time constant of the reverse bias voltage is switched. 9. The driving method of a light emitting display panel according to claim 8, wherein an output time constant of the reverse bias voltage is changed at least according to a setting state of a dimmer value. 10. The light emitting display according to claim 8, wherein an output time constant is obtained by referring to a look-up table describing the time constant data corresponding to the lighting state of the light emitting element. Panel drive method.

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