JP2005033103A - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device and its manufacturing method with a high reliability, wherein a breakage of data due to an electric field generated between neighboring capacitive elements is prevented, thereby preventing a malfunction of memory cells. <P>SOLUTION: A capacitive element 62 comprises a lower electrode 59 formed on a first insulating film 57, a capacitance insulating film 60 formed so as to cover the first insulating film 57 and the lower electrode 59, and an upper electrode 61 formed so as to cover the capacitance insulating film 60. A part of the capacitance insulating film 60 on the first insulating film 57 between the lower electrodes 59, whereby a slit 63 is formed so as not to come into contact with the lower electrode 59. Further, the upper electrode 61 is formed so as to bury the inside of the slit 63, whereby a shield which intercepts the electric field generated between the neighboring capacitive elements 62 is provided. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device including a capacitive element using a capacitive insulating film made of a ferroelectric film or a high dielectric film, and a manufacturing method thereof.

  A conventional semiconductor memory device using a ferroelectric material as a capacitive insulating film of a capacitive element and utilizing hysteresis characteristics will be described with reference to the drawings. FIG. 1 is a diagram of a memory cell of a conventional semiconductor memory device using a ferroelectric material as a capacitive insulating film. As shown in FIG. 1, the memory cell 1 includes a source / drain region 11 and a gate electrode 12 constituting a transistor formed on a semiconductor substrate 10, one source / drain region 11a, and the other source / drain region 11b. An element isolation layer 13 for isolating layers, an interlayer insulating film 14 formed on the semiconductor substrate 10, and a contact plug 15 formed on the interlayer insulating film 14 so as to be electrically connected to the source / drain regions 11a and 11b. And a lower electrode 16 formed on the interlayer insulating film 14 so as to be electrically connected to the contact plug 15 and a ferroelectric material formed so as to cover the lower electrode 16 and the interlayer insulating film 14. The capacitor insulating film 17 and the upper electrode 18 formed so as to cover the capacitor insulating film 17 are configured (see, for example, Patent Document 1). Here, the capacitive element 19 includes a lower electrode 16, a capacitive insulating film 17, and an upper electrode 18. The lower electrode 16 is connected via a bit line (not shown) to a sense amplifier (not shown) for detecting / amplifying the polarization amount of the capacitive element 19 in order to determine the stored information held by the capacitive element 19. Has been. The upper electrode 18 is connected to a cell plate line (not shown) capable of applying a voltage for each memory cell 1. The gate electrode 12 of the transistor is connected to a word line (not shown), and the ON / OFF of the transistor is controlled using the word line (not shown).

  An operation principle in a semiconductor memory device using the capacitor element 19 will be described with reference to the drawings. FIG. 2 is a diagram showing an applied electric field at the time of data writing in the semiconductor memory device. FIG. 3 is a diagram showing the polarization state of the capacitive element in FIG. The same components as those in FIG.

A semiconductor memory device comprising a capacitor element 19A and the capacitor 19B of FIG. 2, as shown in FIG. 3 (a), (c) , the capacitive element 19A holds the polarization amount P _A, capacitive element 19B is polarized A case where data is written to the capacitive element 19A and data is not written to the capacitive element 19B in a state where the amount P _B is held will be described.

In the memory cell 1A, a voltage is applied to the gate electrode 12 through the word line to turn on the transistor. Further, the voltage V (V) is applied to the bit line, and the voltage 0 (V) is applied to the cell plate line. That is, in FIG. 2, the voltage 0 (V) is applied to the upper electrode 18 and the voltage V (V) is applied to the lower electrode 16A, whereby the applied voltage to the capacitive element 19A becomes V (V). Thus, as shown in FIG. 3 (a), the electric field E is generated between the upper electrode 18 and the lower electrode 16A of the capacitor 19A, the polarization amount of the capacitor 19A is changed from P _A to Q _A. Thereafter, when the voltage of the lower electrode 16A is returned to 0 (V) and the applied voltage of the capacitive element 19A is changed from V (V) to 0 (V), the electric field E of the capacitive element 19A becomes zero, and FIG. ), The polarization amount of the capacitive element 19A changes from Q _A to R _A. Thus, by the polarization amount of the capacitor 19A is changed from P _A to R _A, data is written to the capacitor 19A.

On the other hand, when new data is not written in the memory cell 1B, the voltage of the cell plate line and the bit line is 0 (V). At this time, the polarization amount P _B of the capacitive element 19B does not change.
Japanese Patent No. 3322031 (page 4-5, FIG. 3)

  However, in the case described above, the capacitive insulating film 17 between the capacitive element 19A and the capacitive element 19B is connected between the lower electrode 16A and the lower electrode 16B, and therefore, between the capacitive element 19A and the capacitive element 19B. When the distance is close, the data is erroneously written in the capacitive element 19B due to the electric field E generated in the capacitive element 19A. The mechanism by which such a phenomenon occurs will be described below.

FIG. 4 is a schematic diagram of a mechanism in which an electric field generated in the capacitive element 19A affects the capacitive element 19B and erroneous writing occurs. The polarization state before applying a voltage to the capacitive element 19A is as shown in FIG. In such a state, when the voltage V (V) is applied to the capacitive element 19A, an electric field E is generated in the capacitive element 19A. At this time, as shown in FIG. 4B, the polarization direction of the capacitive element 19A changes in a direction from the lower electrode 16A toward the upper electrode 18. That is, as shown in FIG. 3A, the polarization amount of the capacitive element 19A changes from P _A to Q _A. At this time, an electric field is also generated between the lower electrode 16A and the lower electrode 16B via the capacitive insulating film 17. When the distance between the lower electrode 16A and the lower electrode 16B is short, the electric field changes the polarization direction of the capacitive insulating film 17 between the lower electrode 16A and the lower electrode 16B. Therefore, as shown in FIG. 4B, the direction of polarization in the region D of the capacitive element 19B changes in a direction from the upper electrode 18 toward the lower electrode 16B. That is, as shown in FIG. 3C, the polarization amount of the capacitive element 19B changes by the amount of polarization in the region D and changes from P _B to Q _B.

Thereafter, when the applied voltage of the capacitive element 19A is set to 0 (V), the electric field E ′ generated in the capacitive element 19B becomes zero, and the polarization amount of the capacitive element 19B is Q _{B as} shown in FIG. reducing the amount of polarization R _B from. Thus, although the capacitive element 19B originally has to hold the polarization amount P _B , since the data is written to the capacitive element 19A, the polarization amount of the capacitive element 19B changes from P _B to R _B. To decrease. For this reason, when reading the data of the capacitive element 19B, the data of the capacitive element 19B cannot be read accurately, and a malfunction occurs in the memory cell 1B.

  Thus, in the semiconductor memory device in which the capacitive insulating film formed so as to cover the lower electrode is connected between the lower electrode and the lower electrode, when the distance between adjacent capacitive elements approaches, Due to the electric field generated in one capacitor element, a part of the data of the other capacitor element is destroyed, causing a malfunction of the memory cell.

  In view of the above-described conventional problems, the present invention provides a highly reliable semiconductor memory device while preventing malfunction of a memory cell by cutting at least one portion of a capacitive insulating film between the lower electrode and the lower electrode. The purpose is to do.

  In order to solve the above problems, the present invention is characterized in that at least one portion of the capacitive insulating film between the lower electrode and the lower electrode along the cell plate line direction is cut. Therefore, a part of the first insulating film between the lower electrode and the lower electrode is not covered with the capacitive insulating film. For this reason, the electric field generated in one capacitive element including the lower electrode, the capacitive insulating film, and the upper electrode does not propagate to the other capacitive element through the capacitive insulating film between the lower electrodes. As a result, the amount of polarization held by the other capacitive element does not change due to the electric field generated in one capacitive element.

  In order to solve the above problems, the present invention provides a second insulating film formed between the plurality of lower electrodes so as to be substantially the same height as the upper surface of the lower electrode, a plurality of lower electrodes, And a capacitive insulating film formed on the insulating film, and is characterized by cutting at least one portion of the capacitive insulating film between the lower electrode and the lower electrode. Accordingly, since a part of the second insulating film between the lower electrode and the lower electrode is not covered with the capacitive insulating film, the electric field generated in one capacitive element passes through the capacitive insulating film between the lower electrodes. Does not propagate to the other capacitor element. Therefore, the amount of polarization held by the other capacitive element does not change due to the electric field generated in one capacitive element. In addition, since the upper surface of the lower electrode and the upper surface of the second insulating film are formed at substantially the same height, the capacitor insulating film can be formed on a flat base, resulting in variations in film thickness. Can be suppressed.

  In addition, a shield is provided in a portion where the capacitive insulating film is cut. By providing this shield, an electric field generated between the lower electrode and the lower electrode can be weakened or the electric field can be blocked. That is, the polarization amount held by the other capacitive element does not change due to the electric field generated in one capacitive element.

  The shield is made of an insulating film having a dielectric constant lower than that of the capacitive insulating film. Therefore, since the parasitic capacitance of the shield made of the insulating film having a lower dielectric constant than the capacitive insulating film is smaller than the parasitic capacitance of the capacitive insulating film, the lower electrode of one capacitive element and the lower electrode of the other capacitive element Since the electric field generated during this period is concentrated on the shield, the electric field applied to the other capacitor element becomes weak. Therefore, the polarization amount held by the other capacitive element does not change.

  The shield made of a conductive material has a ground potential or a fixed potential. That is, the potential of the shield embedded in the portion where the capacitive insulating film is cut is fixed. Therefore, when a voltage is applied to one capacitive element and a potential difference is generated between the lower electrode of one capacitive element and the lower electrode of the other capacitive element, the voltage is between the shield and the lower electrode of the other capacitive element. No electric field is generated. Therefore, the amount of polarization held by the other capacitive element does not change.

  A third insulating film formed so as to fill a space between the lower electrode and the lower electrode so as to be substantially the same height as the upper surface of the capacitive insulating film formed on the lower electrode; The insulating film is an insulating film having a dielectric constant lower than that of the capacitor insulating film, and an upper electrode formed in contact with the upper surface of the third insulating film and the upper surface of the capacitor insulating film is provided. As a result, the upper surface of the capacitive insulating film formed on the lower electrode and the upper surface of the third insulating film are almost the same height, and the upper electrode is placed on the flat capacitive insulating film and the third insulating film. Can be formed. Therefore, it is possible to prevent disconnection. In addition, since the parasitic capacitance of the third insulating film is smaller than the parasitic capacitance of the capacitive insulating film, the electric field generated between the lower electrode of one capacitive element and the lower electrode of the other capacitive element is Therefore, the electric field applied to the other capacitor element is weakened.

  The shield and the upper electrode are integrated. Thereby, it is not necessary to provide a shield separately from the upper electrode, and the manufacturing process of the semiconductor memory device can be reduced.

  Further, a portion where the capacitive insulating film is cut is used as a slit, and the slit is provided at a position away from the peripheral portion of the lower electrode by a distance larger than the thickness of the capacitive insulating film so as not to contact the lower electrode. Further, the slit is provided in the capacitor insulating film by etching. Therefore, the capacitor insulating film in the slit portion where the crystallinity is disturbed by etching and the insulating property is lowered is not included in the region contributing to the storage capacity of the capacitor. Therefore, it is possible to prevent a leakage current that is generated when the insulating property of the capacitor insulating film is lowered.

  Further, the long side of the slit is made substantially equal to the width of the lower electrode. Accordingly, a slit is formed at the shortest distance between the lower electrode and the lower electrode, and the capacitive insulating film between the lower electrode and the lower electrode is cut. Therefore, the electric field generated in one capacitive element does not propagate to the other capacitive element through the capacitive insulating film between the lower electrodes. In addition, an electric field generated in one capacitor can be blocked.

  In addition, slits are provided between all lower electrodes. Therefore, the capacitive insulating film between the lower electrode and the lower electrode is cut. By providing the slits between all the lower electrodes, the electric field generated in the adjacent capacitive elements can be blocked or weakened for all the capacitive elements.

  The distance between the lower electrode and the lower electrode is greater than 0 nm and not greater than 300 nm. Therefore, when the distance between the lower electrode and the lower electrode where the influence of the electric field between adjacent capacitive elements becomes remarkable is 300 nm or less, malfunction of the capacitive element can be reliably prevented.

  The distance between the lower electrode and the lower electrode is the shortest distance among the plurality of lower electrodes and the lower electrode. Therefore, at least between the lower electrodes having the shortest distance between the lower electrode and the lower electrode, the electric field generated in the adjacent capacitor element can be blocked or weakened.

  In order to solve the above problem, the present invention is characterized in that it includes a step of forming an upper electrode so as to cover the capacitor insulating film and a portion not covered with the capacitor insulating film. Accordingly, since the upper electrode is formed so as to fill the portion where the capacitive insulating film is cut, the shield and the upper electrode that block or weaken the electric field can be formed at a time.

  In order to solve the above problems, the present invention is characterized in that it includes a step of forming a second insulating film between a plurality of lower electrodes. Accordingly, since the upper surface of the lower electrode and the upper surface of the second insulating film are formed at substantially the same height, the capacitive insulating film can be formed on a flat base, and as a result, variations in film thickness and suppression are achieved. can do.

  In order to solve the above-described problem, the present invention forms a capacitor insulating film so as to cover a plurality of lower electrodes, then forms an upper electrode so as to cover the capacitor insulating film, and thereafter, the lower electrode and the lower electrode And a step of cutting the capacitive insulating film and the upper electrode between them. Therefore, the capacitor insulating film and the upper electrode can be removed at a time by etching using one mask pattern.

  In order to solve the above problems, the present invention is characterized in that it includes a step of etching only the slit region when forming the slit. Accordingly, the etched area does not include a wide surface width and a narrow surface width, so that variations in the etching rate due to the micro-rotating effect can be suppressed. Therefore, variations in the shape of the slit can be suppressed.

  In order to solve the above problems, the present invention is characterized in that it includes a step of forming a third insulating film so as to fill a space between the lower electrode and the lower electrode. Therefore, since the upper surface of the capacitive insulating film formed on the lower electrode and the upper surface of the third insulating film are formed at substantially the same height, the upper electrode can be formed on a flat base.

  As described above, according to the present invention, the capacitance insulating film between the lower electrode and the lower electrode is cut, and a slit is formed in the cut portion, so that the capacitance caused by the voltage generated between adjacent capacitive elements. A highly reliable semiconductor memory device can be provided while preventing destruction of data of elements and malfunction of memory cells.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
A semiconductor memory device and a manufacturing method thereof according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 5 is a plan view of a principal part of a plurality of memory cells constituting the memory cell array in the first embodiment. FIG. 6 is a cross-sectional view of a principal part of the semiconductor memory device in the direction of the line XX ′ in FIG. FIG. 7 is a process sectional view of the method of manufacturing the semiconductor memory device according to FIG.

  First, the element isolation layer 56 is selectively formed on the surface portion of the semiconductor substrate 50 made of silicon. Next, a gate electrode 52 is formed through a gate insulating film 54 in a direction perpendicular to the semiconductor substrate 50. The direction perpendicular to the semiconductor substrate 50 is hereinafter referred to as “up” or “up”. Using the gate electrode 52 as a mask, low-concentration impurity implantation is performed on the semiconductor substrate 50 to form an extension region (no symbol). Next, a sidewall insulating film 55 is formed on the side surfaces of the gate electrode 52 and the gate insulating film 54. Subsequently, high-concentration impurity implantation is performed on the semiconductor substrate 50 using the gate electrode 52 and the sidewall insulating film 55 as a mask, and source / drain regions 53 that are impurity diffusion layers are formed in regions on both sides of the gate electrode 52. As a result, as shown in FIG. 7A, a plurality of transistors 51 insulated from each other by the element isolation layer 56 are formed on the semiconductor substrate 50. In the present specification, the description has been made on the premise of the LDD structure, but other structures may be used.

Next, silicon oxide (SiO ₂ ) is deposited over the entire surface of the semiconductor substrate 50 on which the plurality of transistors 51 are formed by a CVD (Chemical Vapor Deposition) method. Subsequently, the upper surface of the deposited silicon oxide is planarized by a CMP (Chemical Mechanical Polishing) method. As a result, a first insulating film 57 which is an interlayer insulating film having a thickness of 500 nm or more and 700 nm or less is formed on the semiconductor substrate 50.

  Next, a photoresist is applied to the entire surface of the first insulating film 57. Then, holes are formed in the photoresist above one source / drain region 53 of each transistor 51 by lithography. Using the hole-shaped resist pattern as a mask, the first insulating film 57 is dry etched. Thereafter, the resist pattern is removed. As a result, a contact hole is formed above one source / drain region 53.

  Next, a conductive material made of polysilicon is deposited over the entire surface of the first insulating film 57 so as to bury the contact holes by CVD. Subsequently, the conductive material is removed by CMP until the upper surface of the first insulating film 57 is exposed. As a result, a contact plug 58 is formed on one source / drain region 53. The upper surface of the contact plug 58 and the upper surface of the first insulating film 57 are flattened so as to have substantially the same height. Here, the height is a direction perpendicular to the semiconductor substrate 50 with respect to the semiconductor substrate 50.

Next, titanium aluminum nitride (TiAlN) is deposited on the upper surfaces of the plurality of contact plugs 58 and the first insulating film 57 by sputtering to form a titanium aluminum nitride film having a thickness of 40 nm to 100 nm. . Subsequently, iridium (Ir) is deposited on the titanium aluminum nitride film by sputtering to form an iridium film having a thickness of 50 nm to 100 nm. Subsequently, iridium dioxide (IrO ₂ ) is deposited on the iridium film by sputtering to form an iridium dioxide film having a thickness of 50 nm to 100 nm. Thus, a conductive barrier layer composed of a titanium aluminum nitride film, an iridium film, and an iridium dioxide film is formed on the upper surfaces of the plurality of contact plugs 58 and the upper surface of the first insulating film 57.

  The titanium aluminum nitride film can prevent diffusion of oxygen and hydrogen generated in the process after the formation of the conductive barrier layer. In addition, the iridium film and the iridium dioxide film can prevent diffusion of oxygen generated in the process after the formation of the conductive barrier layer. Thereby, the conductive barrier layer can prevent diffusion of oxygen and hydrogen into the contact plug 58. Further, it is possible to prevent the contact resistance of the contact plug 58 from increasing and the capacitance insulating film 60 from being reduced by hydrogen.

  Subsequently, platinum (Pt) is deposited over the entire upper surface of the conductive barrier layer by sputtering. Thereby, a platinum layer having a thickness of 50 nm or more and 100 nm or less is formed. Here, the platinum layer is a conductive layer. In this way, a conductive layer is formed on the conductive barrier layer. Thereafter, a resist pattern is formed on the surface of the conductive layer above the contact plug 58. Using this resist pattern as a mask, dry etching is performed on the conductive layer and the conductive barrier layer. Thereafter, the resist pattern is removed. As a result, a lower electrode 59 having a laminated structure including a conductive layer and a conductive barrier layer is formed above the contact plug 58. That is, the lower electrode 59 is formed so as to be electrically connected to one of the source / drain regions 53 via the contact plug 58. Further, as shown in FIG. 5, a plurality of lower electrodes 59 are formed at equal intervals along the X-X ′ line direction which is the cell plate line direction. Further, as shown in FIG. 7A, the lower electrode 59 has a quadrangular shape in the cross-sectional view. As shown in FIG. 7A, the lower electrode 59A is a first lower electrode, and the lower electrode 59B is a second lower electrode.

Next, a ferroelectric material is formed of a metal oxide so as to cover the upper surface and side surfaces of the lower electrode 59 and the upper surface of the first insulating film 57 by MOCVD (Metal Organic Chemical Vapor Deposition). Deposit strontium bismuth tantalum niobate (SrBi ₂ (Ta _x Nb _{1 -x} ) ₂ O ₉ ) (hereinafter referred to as SBTN) (where x is 0 ≦ x ≦ 1) having a bismuth layered perovskite structure. . As a result, as shown in FIG. 7B, an SBTN film having a thickness of 50 nm to 250 nm is formed. This SBTN film is a capacitive insulating film 60 formed so as to cover the lower electrode 59 and the first insulating film 57. As described above, when the MOCVD method is used, it is possible to form the capacitive insulating film 60 having excellent coverage at the step portion between the lower electrode 59 and the first insulating film 57.

  Next, a characteristic configuration of the semiconductor memory device according to the present invention will be described in detail below.

  Next, the capacitive insulating film 60 formed on the first insulating film 57 between the lower electrode 59A and the lower electrode 59B is thicker than the thickness of the capacitive insulating film 60 from the peripheral edge a of the lower electrode 59. A resist pattern having openings at positions separated by a distance is formed on the upper surface of the capacitor insulating film 60. Here, in this embodiment, since the shape of the lower electrode 59 is a square, the side surface of the lower electrode 59 is the peripheral edge a. Using this resist pattern as a mask, the capacitive insulating film 60 is removed by dry etching until the upper surface of the first insulating film 57 is exposed. Here, a gas containing fluorine (F) is used as the etching gas. Thereafter, the resist pattern is removed. In this way, as shown in FIG. 7C, the capacitive insulating film 60 between the lower electrode 59A and the lower electrode 59B is cut. As a result, a portion not covered with the capacitive insulating film 60 is formed between the lower electrode 59A and the lower electrode 59B. A portion that is not covered with the capacitive insulating film 60 is a slit 63. That is, the capacitive insulating film 60 has a substantially L shape on the side surface of the lower electrode 59. The slit 63 is formed at a position away from the peripheral edge a of the lower electrode 59 by a distance larger than the thickness of the capacitive insulating film 60. This is because the capacitor insulating film 60 needs to be formed so as to cover the entire lower electrode, so that the slit 63 must not be formed so that the lower electrode 59 is exposed, and the film thickness of the capacitor insulating film 60 is equal. This is because if the slit 63 is formed at a distance, the insulating property of the capacitive insulating film 60 covering the lower electrode 59 is lowered.

  That is, as shown in FIG. 6, the capacitor insulating film 60 has a shape that protrudes in the direction along the surface of the first insulating film 57 at the end of the lower electrode 59. Thus, the end face whose crystallinity is disturbed at the time of etching for forming the slit 63 in the capacitive insulating film 60 is not included in the region contributing to the storage capacity of the capacitive element 62. For this reason, it is possible to prevent the occurrence of a leakage current resulting from the deterioration of the insulating property of the capacitor insulating film 60. Therefore, the reliability of the capacitive element 62 can be increased.

  Here, the slit 63 is preferably formed at an equal distance between the lower electrode 59 and the lower electrode 59 in the X-X ′ line direction as shown in FIG. The width of the slit 63 is, for example, 150 nm.

  Since the slit 63 is used to block the electric field between the lower electrodes, even when the long side of the slit 63 is equal to or smaller than the width of the lower electrode 59, an effect of blocking the electric field is produced as compared with the case where the slit 63 does not exist.

  Further, by providing the slits 63 in all the parts of the shortest distance between the lower electrode and the lower electrode, a further effect can be obtained. In this case, when the opposing surfaces of the lower electrodes are parallel as shown in FIG. 5, the long side of the slit 63 needs to be equal to or larger than the width of the lower electrode 59. At this time, if the long side of the slit 63 is equal to the width of the lower electrode 59, the slit 63 can be provided in all the shortest distances between the lower electrode and the lower electrode. It is desirable to have

  Furthermore, by setting the long side of the slit 63 to be equal to or larger than the width of the lower electrode 59, it is possible to block an electric field in a portion other than the shortest distance between the lower electrode and the lower electrode, and the effect can be further obtained.

  Here, a manufacturing method using a resist pattern having a slit shape will be described. In the present embodiment, only the portion of the slit 63 in which the region to be etched is very narrow is etched. Therefore, there is no variation in the etching rate that occurs when the region to be etched is wide and narrow. Therefore, variation in shape after etching can be suppressed, and a plurality of slits 63 with uniform shapes can be easily formed.

  Next, a process for forming the upper electrode 61 will be described. As shown in FIG. 7D, the entire surface of the capacitive insulating film 60 is deposited by sputtering so as to fill the slits 63 with platinum. Thereby, a platinum film having a thickness of 20 nm to 100 nm is formed. That is, the upper electrode 61 made of a platinum film is formed so as to cover the capacitive insulating film 60. As shown in FIG. 5, the upper electrode 61 is formed in the X-X ′ line direction that is the cell plate line direction. Further, since the upper electrode 61 is also formed in the slit 63, the upper electrode 61 serves as a shield to block the electric field between the lower electrodes, like the slit 63.

  Next, a protective insulating film (not shown) is deposited over the entire surface of the upper electrode 61 by CVD. Subsequently, a photoresist is applied to the entire surface of the protective insulating film. Then, holes are formed above the other source / drain region 53 that is not electrically connected to the lower electrode 59 by lithography. The protective insulating film and the first insulating film 57 are dry-etched using the resist pattern having holes as a mask. Thereafter, the resist pattern is removed. As a result, a contact hole is formed above the other source / drain region 53.

  Next, a conductive film (not shown) is deposited over the entire surface of the protective insulating film so as to fill the contact hole by CVD. Subsequently, a resist pattern is formed only on the surface of the conductive film above the contact hole. Using this resist pattern as a mask, the conductive film is dry etched. Thereafter, the resist pattern is removed. Thereby, a bit line (not shown) as a wiring layer is formed so as to be electrically connected to the other source / drain region 53.

  Next, the semiconductor memory device formed as described above will be described in detail below. A capacitive element 62 is composed of the lower electrode 59, the capacitive insulating film 60, and the upper electrode 61 described above. Further, the transistor 51, the contact plug 58, and the capacitor 62 constitute a memory cell 64. Further, as shown in FIG. 5, a memory cell array is constituted by a plurality of memory cells 64. FIG. 8 is a circuit schematic diagram of the cell block shown in FIG. The same components as those in FIGS. 5 and 6 are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 8, a plurality of word lines WL and a plurality of bit lines BL are formed so as to be orthogonal to each other, and memory cells 64 are arranged at the intersections. A plurality of cell plate lines CP are formed in parallel with the word lines WL, and a capacitive element 62 is connected to the cell plate lines CP. The direction parallel to the word line WL and the cell plate line CP is the X-X ′ line direction in FIG. 5, and the direction parallel to the bit line BL is the Y-Y ′ line direction in FIG. 5. The lower electrode 59 is electrically connected to the source / drain region 53 via the contact plug 58 and further connected to a sense amplifier (not shown) from the source / drain region 53 via the bit line BL. The sense amplifier detects / amplifies the amount of polarization held by the capacitive element 62 in order to determine the data stored in the capacitive element 62. The upper electrode 61 is electrically connected to a cell plate line CP to which a voltage can be applied for each memory cell 64. The gate electrode 52 is connected to a word line WL that controls ON / OFF of the transistor 51 by applying a voltage. In the first embodiment, the upper electrode 61 also serves as the cell plate line CP.

  In the semiconductor memory device using the capacitive element 62 configured as described above, a case where data is written to one capacitive element and data is not written to the other capacitive element will be described with reference to the drawings. FIG. 9 is an operation diagram of the semiconductor memory device. The same components as those in FIG.

In the state where the capacitive element 62A holds the polarization amount P _A and the capacitive element 62B holds the polarization amount P _B , in the capacitive element 62A, a voltage is applied to the gate electrode 52A via the word line to turn on the transistor 51A. . Thereafter, the voltage V (V) is applied to the bit line, and the voltage 0 (V) is applied to the cell plate line. On the other hand, voltage 0 (V) is applied to the cell plate line and the bit line in the capacitive element 62B. That is, as shown in FIG. 9, when a voltage 0 (V) is applied to the upper electrode 61 of the capacitive element 62A and a voltage V (V) is applied to the lower electrode 59A, an electric field E is generated between the upper electrode 61 and the lower electrode 59A. appear. The electric field E changes the polarization direction of the capacitive element 62A, and data is written to the capacitive element 62A. At this time, since the slit 63 is formed in the capacitive insulating film 60 between the lower electrode 59A and the lower electrode 59B, the electric field E generated in the capacitive element 62A is blocked by the slit 63, and the capacitive insulating film of the capacitive element 62B. 60 is not transmitted.

Therefore, the polarization direction of the capacitive element 62B does not change. That is, since the polarization amount P _B of the capacitive element 62B does not change, data destruction of the capacitive element 62B that occurs in the conventional example does not occur. Thereby, the data of the capacitive element 62B can be read accurately, and malfunction of the memory cell 64 can be prevented.

  Next, the distance between the capacitive elements and the amount of polarization will be described. FIG. 10 is a relationship diagram between the distance between the capacitive elements and the amount of polarization in the present invention and the conventional example. As the semiconductor memory device is miniaturized, the distance between the capacitive element 62A and the capacitive element 62B becomes shorter. For example, when the capacitive insulating film 60 between the lower electrode 59A and the lower electrode 59B is connected as in the conventional case, when the distance between the capacitive element 62A and the capacitive element 62B is 300 nm or less, the dotted line in FIG. As shown, the amount of polarization of the capacitive element 62B is reduced by about 30% due to the influence of the electric field E generated in the capacitive element 62A. However, in the present embodiment, when the distance between the capacitive element 62A and the capacitive element 62B is 300 nm or less, the slit 63 is formed in the capacitive insulating film 60 between the lower electrode 59A and the lower electrode 59B. The electric field E generated in the capacitive element 62A is blocked, and the polarization amount of the capacitive element 62B does not change as shown by the solid line in FIG. Therefore, even if the data of the capacitive element 62A is rewritten, the data of the capacitive element 62B is not destroyed, so that the data of the capacitive element 62B can be read accurately. That is, malfunction of the memory cell 64 can be prevented. Here, the distance between the capacitive element 62A and the capacitive element 62B is the distance between the lower electrode 59A and the lower electrode 59B.

  Further, even when the electric field E generated in the capacitive element 62A is increased by increasing the voltage applied to the capacitive element 62A, in this embodiment, the capacitive insulating film 60 between the lower electrode 59A and the lower electrode 59B is used. As a result, the electric field E generated in the capacitive element 62A does not propagate to the capacitive element 62B but is blocked by the slit 63. That is, the polarization amount of the capacitive element 62B does not change regardless of the distance between the capacitive element 62A and the capacitive element 62B. Accordingly, since the data of the capacitor 62B is not destroyed, accurate data reading of the capacitor 62B can be performed. That is, malfunction of the memory cell 64 can be prevented.

  In the configuration in this embodiment, the potential difference between the lower electrode 59A and the lower electrode 59B is V (V), and an electric field is generated between the lower electrode 59A and the lower electrode 59B. However, since the upper electrode 61 to which a voltage of 0 (V) is applied is embedded in the slit 63 between the lower electrode 59A and the lower electrode 59B, it is generated between the lower electrode 59A and the lower electrode 59B. The applied electric field is blocked by the upper electrode 61. Therefore, an electric field is not generated between the upper electrode 61 and the lower electrode 59B, and malfunction of the memory cell 64 can be prevented.

  Further, in the configuration of the present embodiment, the capacitor insulating film 60 is formed so as to cover the side surface and the upper surface of the lower electrode 59, and the upper electrode 61 is formed so as to cover the capacitor insulating film 60. Therefore, the amount of polarization that can hold data in the capacitive element 62 increases.

  In the first embodiment, the upper electrode 61 is configured to cover the capacitive insulating film 60 and the slit 63. However, the upper electrode 61 is not limited thereto, and the upper electrode 61 includes the lower electrode 59A and the lower electrode 59B. The structure formed so that a space may be filled in the height direction may be used. At this time, the lower electrode 59 may be partially filled in the height direction, or all of the lower electrode 59 may be filled in the height direction.

In the first embodiment, the first insulating film 57 may include silicon nitride (Si ₃ N ₄ ).

  In the first embodiment, an etch back method may be used instead of the CMP method.

  In the first embodiment, the conductive material used for the contact plug 58 may be tungsten (W).

  In the first embodiment, the shape of the lower electrode 59 is a quadrangular shape in the cross-sectional view, but may be a semicircular shape, a triangular shape, or a concave shape. In the case of the concave shape, the surface area of the lower electrode 59 is increased, and a large amount of the capacitive insulating film 60 can be formed. Therefore, the amount of polarization that can hold data in the capacitor 62 increases. The shape of the lower electrode 59 may be circular, elliptical, or quadrangular in the projection view.

In Embodiment 1, a titanium nitride (TiN) film, a titanium nitride (TiSiN) film, or a tantalum aluminum nitride (TaAlN) instead of the titanium aluminum nitride film used as the conductive barrier layer constituting the lower electrode 59 is used. A film or a silicon tantalum nitride (TaSiN) film may be used. Further, instead of a laminated film made of an iridium film and an iridium dioxide film, a laminated film made of a ruthenium (Ru) film and a ruthenium dioxide (RuO ₂ ) film may be used.

  In the first embodiment, the lower electrode 59 may be embedded in the contact plug 58. In this case, since the contact plug also serves as the lower electrode, the manufacturing process can be reduced.

  In the first embodiment, the capacitor insulating film 60 may be formed using a MOD (Metal Organic Decomposition) method or a sputtering method instead of the MOCVD method.

In the first embodiment, the capacitor insulating film 60 is formed of an SBTN film. However, the ferroelectric material having a bismuth layered perovskite structure, lead zirconate titanium (Pb (Zr _x Ti _1-x ) O ₃ ), 5 tantalum oxide (Ta ₂ O _5), barium strontium titanate _{((Ba x Sr 1-x} ) TiO 3), even at high dielectric material, such as bismuth lanthanum titanate _{(Bi x La 1-x)} 4 Ti 3 O 12 Good. The SBTN film is particularly preferable as the capacitor insulating film 60 because the film fatigue characteristics are good and the deterioration of the ferroelectric due to the write / read operation is low. Furthermore, when this material is used, it is possible to operate at a low voltage.

  In the first embodiment, since the thickness of the capacitor insulating film 60 is substantially uniform, the amount of the capacitor insulating film 60 covering each lower electrode 59 is uniform and can be held in each capacitor element 62. There is no variation in the amount of polarization that can occur.

  In the first embodiment, the slit 63 is provided in at least one of the plurality of lower electrodes, and the upper electrode 61 is provided in the slit 63, whereby data destruction of at least one capacitor 62 can be prevented. Furthermore, by providing the slits 63 between all the lower electrodes 59, the electric field generated in the adjacent capacitive elements 62 can be blocked from all the capacitive elements 62.

  Here, as shown in FIG. 10, when the capacitive insulating film 60 between the lower electrode 59A and the lower electrode 59B is connected as in the prior art, the distance between the capacitive element 62A and the capacitive element 62B is 300 nm or less. Then, as shown by the dotted line in FIG. 10, the amount of polarization of the capacitive element 62B is reduced by about 30% due to the influence of the electric field E generated in the capacitive element 62A. Therefore, in the lower electrode 59 arranged in the cell plate line direction, the slit 63 may be formed only in a region where the distance between the lower electrode 59 and the lower electrode 59 is short, that is, a region of 300 nm or less.

  In the first embodiment, the slit 63 is formed by removing the capacitive insulating film 60 until the first insulating film 57 is exposed. However, the slit 63 is removed until the first insulating film 57 is exposed. Instead, a groove may be formed in the capacitor insulating film 60. In this case, the electric field generated in one capacitive element 62 can be weakened by this groove.

  In the first embodiment, the shape of the slit 63 is a rectangle, and the long side of the slit 63 is the same as the width of the lower electrode 59. However, the shape of the slit 63 is not limited to this, and may be a square, an ellipse, or a circle.

  In the first embodiment, the semiconductor memory device in which the capacitive insulating film between the lower electrode and the lower electrode along the cell plate line direction is cut is described. However, the semiconductor memory device is formed on the semiconductor substrate. A first insulating film, a plurality of lower electrodes formed on the first insulating film, and a capacitor insulating film formed to cover the plurality of lower electrodes and the first insulating film A semiconductor memory including an upper electrode formed on the capacitor insulating film and having a gap at least at one location of the capacitor insulating film between the lower electrode and the lower electrode along a cell plate line direction. It may be a device.

  In the first embodiment, the upper electrode 61 is formed of a platinum film, but may be configured such that a titanium film is formed on the platinum film. Further, a titanium nitride film may be used instead of the titanium film. In addition, the present invention is not limited thereto, and an iridium film, a ruthenium film, a rhodium film, or a laminated film thereof may be included instead of the titanium film.

  In the first embodiment, after the capacitor 62 is formed, a film thickness of 5 nm or more and 100 nm is formed on the upper surface of the upper electrode 61 so as to cover the upper electrode 61 and the capacitor insulating film 60 and the upper electrode 61 by CVD or sputtering. An insulating barrier film containing about the following aluminum oxide may be formed. Thereby, hydrogen generated in the manufacturing process after the formation of the capacitive element 62 can be prevented from diffusing into the capacitive element 62.

  The first embodiment can be applied to both 1T / 1C type memory cells and 2T / 2C type memory cells.

  The first embodiment is not limited to the memory cell array as shown in FIG.

(Embodiment 2)
A semiconductor memory device according to the second embodiment of the present invention will be described with reference to the drawings. The difference between the first embodiment and the second embodiment is that a shield 65 that blocks an electric field is formed in the slit 63. Description of points common to the first embodiment is omitted.

  The steps until the upper electrode 61 is formed are the same as those in the first embodiment. FIG. 11 is a fragmentary cross-sectional view of the semiconductor memory device according to the second embodiment. The same components as those in FIG. A photoresist is applied to the entire surface of the upper electrode 61. Then, a resist pattern is formed so as to separate the upper electrode 61 embedded in the slit 63 and the upper electrode 61 formed on the capacitive insulating film 60. Using this resist pattern as a mask, the upper electrode 61 is dry etched. Thereafter, the resist pattern is removed. In this way, as shown in FIG. 11, the upper electrode 61 is separated into an electrode embedded in the slit 63 and an upper electrode 61 formed on the capacitive insulating film 60. Then, by grounding the potential of the electrode embedded in the slit 63, the shield 65 functions as a shield that blocks the electric field.

  The capacitive element 62 formed as described above has a configuration in which a shield 65 made of the same material as that of the upper electrode 61 is formed in the slit 63. Accordingly, since the shield 65 having the ground potential is inserted between the lower electrode 59A having the potential of V (V) and the lower electrode 59B having the potential of 0 (V), the shield 65 causes the lower electrode 59A and the lower electrode 59B to be The electric field generated between the electrode 59B can be effectively cut off. That is, the electric field generated in one capacitive element 62A is blocked, and no electric field is generated between the shield 65 and the lower electrode 59B. Thereby, data destruction of the capacitive element 62B does not occur, and malfunction of the memory cell 64 can be prevented.

  In the present embodiment, the shield 65 is formed of the same material as that of the upper electrode 61. However, the present invention is not limited to this, and it is sufficient if the shield 65 is formed of a conductive material and grounded. The shield 65 may be connected to the semiconductor substrate 50 to fix the potential. In the second embodiment, when a voltage different from the voltage described above is applied to the lower electrode 59 and the upper electrode 60, the potential of the shield 65 is set so that no potential difference is generated between the shield 65 and the lower electrode 59B. Should be set.

  Further, the potential of the shield 65 may be set so that the potential difference between the shield 65 and the lower electrode 59B is smaller than the potential difference between the lower electrode 59A and the lower electrode 59B. In this case, the shield 65 functions as a shield that weakens the electric field.

  As shown in FIG. 5, the second embodiment can also be implemented in a memory cell in the Y-Y ′ line direction orthogonal to the X-X ′ line direction, which is the cell plate line direction. In this case, when the miniaturization progresses in the YY ′ line direction of FIG. 5 and the distance between the capacitive element 62 and the capacitive element 62 becomes short, it occurs in the memory cell array in the adjacent XX ′ line direction. The electric field can be effectively blocked by the shield. Therefore, malfunction of the memory cell can be prevented.

(Embodiment 3)
A semiconductor memory device according to Embodiment 3 of the present invention will be described with reference to the drawings. The difference between the first embodiment and the third embodiment is that after the capacitive insulating film 60 is formed on the lower electrode 59, the upper electrode 61 is formed on the capacitive insulating film 60, and then by dry etching, A slit 63 is formed between the lower electrode 59A and the lower electrode 59B. Description of points common to the first embodiment is omitted. The slit 63 is the same as that in the first embodiment.

  The steps until the capacitor insulating film 60 is formed are the same as those in the first embodiment. FIG. 12 is a fragmentary cross-sectional view of the semiconductor memory device according to the third embodiment. FIG. 13 is a process cross-sectional view of the manufacturing method of FIG. The same components as those in FIG. After the capacitor insulating film 60 is formed, an upper electrode 61 is formed so as to cover the entire surface of the capacitor insulating film 60 as shown in FIG. Since the process of forming the upper electrode 61 is the same as that of the first embodiment, the description thereof is omitted.

  Next, a photoresist is applied to the entire surface of the upper electrode 61. A resist pattern having an opening at a position away from the peripheral edge a of the lower electrode 59 by a distance larger than the film thickness of the capacitive insulating film 60 is formed on the upper surface of the upper electrode 61 between the lower electrode 59A and the lower electrode 59B. Form. Using this resist pattern as a mask, the upper electrode 61 and the capacitor insulating film 60 are removed by dry etching until the upper surface of the first insulating film 57 is exposed. Thereafter, the resist pattern is removed. In this way, as shown in FIG. 13B, the capacitive insulating film 60 and the upper electrode 61 between the lower electrode 59A and the lower electrode 59B are cut. As a result, a slit 63 is formed in the capacitive insulating film 60 between the lower electrode 59A and the lower electrode 59B.

  Further, compared with the first embodiment, the slit 63 is formed after the capacitor insulating film 60 and the upper electrode 61 are formed. Therefore, the capacitor insulating film 60 and the upper portion are formed at a time using one mask pattern. The electrode 61 can be removed, and the slit 63 can be easily formed.

  In the third embodiment, an insulating film made of silicon oxide may be deposited in the slit 63 by a CVD method. Further, an insulating film may be deposited so that the space between the capacitive elements 62 is filled in the height direction of the lower electrode 59. Here, the insulating film made of silicon oxide is an insulating film having a dielectric constant lower than that of the capacitive insulating film 60. Therefore, when a voltage is applied between the lower electrode 59A and the lower electrode 59B, most of the voltage is applied to the insulating film embedded in the slit 63. That is, there is almost no influence on the capacitive element 62B. Therefore, the destruction of data in the other capacitive element 62 due to the electric field generated in one capacitive element 62 is reduced. Here, an insulating film containing silicon nitride may be used instead of silicon oxide.

  As shown in FIG. 5, the third embodiment can also be implemented in a memory cell in the Y-Y ′ line direction orthogonal to the X-X ′ line direction which is the cell plate line direction. In this case, when the miniaturization progresses in the YY ′ line direction of FIG. 5 and the distance between the capacitive element 62 and the capacitive element 62 becomes short, it occurs in the memory cell array in the adjacent XX ′ line direction. The electric field can be blocked.

(Embodiment 4)
A semiconductor memory device according to Embodiment 4 of the present invention will be described without referring to the drawings. The difference between the second embodiment and the fourth embodiment is that the shield formed in the slit is formed of an insulating film having a low dielectric constant, not a conductive material. Further, although the shield potential is fixed in the second embodiment, the shield potential is not fixed in the present embodiment. The slit is the same as that in the first embodiment.

  The steps until the slit is formed are the same as those in the first embodiment, and the subsequent steps will not be described with reference to the drawings. Silicon oxide, which is an insulating film having a dielectric constant lower than that of the capacitor insulating film, is deposited by CVD so as to fill the slit. Thereby, a shield is formed in the slit. The capacitive element formed as described above has a configuration in which a shield made of an insulating film having a dielectric constant lower than that of the capacitive insulating film is formed in the slit. Therefore, since the parasitic capacitance of the shield made of the insulating film having a lower dielectric constant than the capacitive insulating film is smaller than the parasitic capacitance of the capacitive insulating film, the lower electrode of one capacitive element and the lower electrode of the other capacitive element The electric field generated by the potential difference generated between the two is concentrated on the shield. Therefore, the electric field applied to the other capacitive element becomes weak, and the polarization amount of the other capacitive element does not change. Thereby, the destruction of data in the other capacitive element due to the electric field generated in one capacitive element is reduced, and malfunction of the memory cell can be prevented.

  Note that in this embodiment, the upper electrode may be formed so as to cover the capacitor insulating film and the insulating film having a low dielectric constant.

(Embodiment 5)
A semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to the drawings. The difference between the fifth embodiment and the first embodiment is that the disconnection is not caused by forming the upper electrode 61 on the base. The process for this will be described below.

  FIG. 14 is a fragmentary cross-sectional view of the semiconductor memory device according to the fifth embodiment. The same components as those in FIG. As shown in FIG. 14, silicon oxide is deposited over the entire surface of the capacitive insulating film 60 so as to fill the space between the lower electrode 59 </ b> A and the lower electrode 59 </ b> B by CVD. Thereafter, the silicon oxide is removed by CMP until the capacitive insulating film 60 formed on the upper surface of the lower electrode 59 is exposed. As a result, a third insulating film 66 made of silicon oxide is formed between the lower electrode 59A and the lower electrode 59B. The third insulating film 66 is formed so that the upper surface of the capacitive insulating film 60 and the upper surface of the third insulating film 66 are substantially at the same height. Thereby, the shield 65 and the third insulating film 66 are formed between the lower electrode 59A and the lower electrode 59B. Then, the upper electrode 61 is formed on the entire upper surface of the capacitive insulating film 60 and the third insulating film 66.

  In the capacitive element 62 formed as described above, the shield 63 and the third insulating film 66 are made of an insulating film having a dielectric constant lower than that of the capacitive insulating film 60. Therefore, the parasitic characteristics of the shield 63 and the third insulating film 66 are included. The capacity is smaller than the parasitic capacity of the capacity insulating film 60. Therefore, the electric field generated by the potential difference generated between the lower electrode 59A and the lower electrode 59B is concentrated on the shield 63 and the third insulating film 66, and the electric field applied to the capacitive element 62B becomes weak, and the capacitive element 62B The amount of polarization does not change. Therefore, destruction of data in the other capacitive element 62 due to the electric field generated in one capacitive element 62 is reduced, and malfunction of the memory cell 64 can be prevented. If the upper surface of the capacitor insulating film 60 and the upper surface of the third insulating film 66 are formed so as to have substantially the same height, the upper electrode 61 is formed on a flat base, so that no disconnection occurs. In the present embodiment, in order to easily form the upper electrode 61 on the capacitive insulating film 60 and the third insulating film 66, the upper surface of the capacitive insulating film 60 and the upper surface of the third insulating film 66 are separated from each other. Although they are formed so as to have almost the same height, the present invention is not limited to this, and an effect as a shield that weakens the electric field occurs even if the heights are different.

  In the fifth embodiment, the shield 65 and the third insulating film 66 may contain silicon nitride.

  In the fifth embodiment, the shield 65 and the third insulating film 66 may be made of different materials.

  In the fifth embodiment, the upper electrode 61 is formed in the X-ray direction as shown in FIG. 14, but the upper electrode 61 formed on the third insulating film 66 is partially removed, The upper electrode 61 may be formed for each capacitive element 62. In this case, as shown in FIG. 5, the present invention can also be implemented in a memory cell in the Y-Y ′ line direction orthogonal to the X-X ′ line direction, which is the cell plate line direction.

(Embodiment 6)
A semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to the drawings. A difference from the fifth embodiment is that, in a configuration in which the upper electrode 61 is formed on a flat base, a shield 65 made of a conductive material is replaced with a slit 63 instead of an insulating film having a lower dielectric constant than that of the capacitive insulating film 60. Is formed. The shield 65 is the same as that in the second embodiment. Accordingly, the present embodiment is different from the fifth embodiment. This will be specifically described below. Note that a description of points common to the fifth embodiment is omitted.

  FIG. 15 is a process sectional view of the method for manufacturing the semiconductor memory device according to the sixth embodiment. The same components as those in FIG. As shown in FIG. 15A, the process until the upper electrode 61 is formed is the same as that in the first embodiment, and is therefore omitted. A photoresist is applied to the entire surface of the upper electrode 61. Then, a resist pattern that leaves only the upper electrode 61 embedded in the slit 63 is formed. Using this resist pattern as a mask, the other upper electrode 61 is removed by dry etching so as to leave the upper electrode 61 formed in the slit 63. As a result, a shield 65 made of the same conductive material as that of the upper electrode 61 is formed in the slit 63 as shown in FIG. Thereafter, after the third insulating film 66 is formed, a new upper electrode 61 is formed. Since the process of forming the third insulating film 66 and the upper electrode 61 is the same as that of the fourth embodiment, the description thereof is omitted.

(Embodiment 7)
A semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to the drawings. The difference between the first embodiment and the seventh embodiment is that a second insulating film 67, which is a spacer insulating film, is formed between the lower electrode 59A and the lower electrode 59B. Description of points common to the first embodiment is omitted. The slit 63 is the same as that in the first embodiment.

  The steps until the lower electrode 59 is formed are the same as those in the first embodiment. FIG. 16 is a fragmentary cross-sectional view of the semiconductor memory device according to the seventh embodiment. The same components as those in FIG. By the CVD method, silicon oxide is deposited over the entire surface of the lower electrode 59 so as to fill the space between the lower electrode 59A and the lower electrode 59B. Subsequently, silicon oxide is removed by CMP until the upper surface of the lower electrode 59 is exposed. Thereby, the space between the lower electrode 59A and the lower electrode 59B is filled with silicon oxide. As a result, a second insulating film 67 made of silicon oxide is formed between the lower electrode 59 and the lower electrode 59. The lower electrode 59A and the lower electrode 59B are electrically insulated by the second insulating film 67.

  Next, a capacitive insulating film 60 made of SBTN is formed on the upper surface of the lower electrode 59 and the upper surface of the second insulating film 67. Since the process of forming the capacitive insulating film 60 is the same as that of the first embodiment, the description thereof is omitted. Next, a slit 63 is formed in the capacitive insulating film 60 between the lower electrode 59 </ b> A and the lower electrode 59 </ b> B so that the end of the capacitive insulating film 60 protrudes from the surface of the second insulating film 67. Since the process of forming the slit 63 is the same as that of the first embodiment, the description thereof is omitted. Next, the upper electrode 61 is formed over the entire surface of the capacitive insulating film 60 so as to fill the slit 63. Since the process of forming the upper electrode 61 is the same as that of the first embodiment, the description thereof is omitted.

  In the capacitive element 62 formed as described above, as shown in FIG. 16, the second insulating film 67 is formed so as to be embedded between the lower electrode 59A and the lower electrode 59B. The upper surface and the upper surface of the second insulating film 67 are formed to have substantially the same height. Accordingly, since the upper surface of the lower electrode 59 and the upper surface of the second insulating film 67 are substantially the same height, the capacitive insulating film 60 can be formed on the flat base, and as a result, the capacitive insulating film having a uniform film thickness can be formed. The film 60 can be easily formed. The upper electrode 61 is formed so as to cover the slit 63 and the capacitive insulating film 60. Thereby, since the upper electrode 61 is embedded in the slit 63, the electric field generated in the capacitive element 62A is blocked by the upper electrode 61, and no electric field is generated between the upper electrode 61 and the lower electrode 59B. Data destruction of the capacitive element 62B does not occur.

  In the seventh embodiment, before the second insulating film 67 is formed, the side surface of the lower electrode 59 and the surface of the first insulating film 57 may be covered with an insulating barrier layer made of aluminum oxide. Thereby, the insulating barrier layer can prevent hydrogen and oxygen generated in the manufacturing process after the lower electrode 59 is formed from diffusing into the lower electrode 59. Therefore, it is possible to prevent the conductive barrier layer constituting the lower electrode 59 from being reduced by hydrogen and deteriorating the oxygen barrier property of the conductive barrier layer.

  In the seventh embodiment, the upper electrode 61 may be covered with a barrier film. Thereby, the barrier film can prevent the active hydrogen generated by the catalytic reaction of platinum and the hydrogen atoms in the hydrogen atmosphere for annealing the wiring layer from diffusing through the upper electrode 61 and reaching the capacitive insulating film 60. Therefore, the capacitive insulating film 60 is not reduced by hydrogen, and the characteristics of the capacitive element 62 are improved.

(Embodiment 8)
A semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to the drawings. The difference between the seventh embodiment and the present embodiment is that after the upper electrode 61 is formed, the upper electrode 61 filling the slit 63 and the upper electrode 61 on the capacitive insulating film 60 are separated. That is, a shield 65 that blocks an electric field is formed in the slit 63. The shield 65 is the same as that in the second embodiment. Description of points common to the first embodiment and the seventh embodiment is omitted.

  The process until the upper electrode 61 is formed is the same as that of the seventh embodiment. FIG. 17 is a fragmentary cross-sectional view of the semiconductor memory device according to the eighth embodiment. The same components as those in FIG. Since the steps after forming the shield are the same as those in the second embodiment, a description thereof will be omitted.

(Embodiment 9)
A semiconductor memory device according to Embodiment 9 of the present invention will be described with reference to the drawings. The difference between the eighth embodiment and the present embodiment is that a shield 65 made of an insulating film having a dielectric constant lower than that of the capacitor insulating film 60 is formed in the slit 63, and the upper electrode 61 is connected to the upper surface of the shield 65 and the capacitor. That is, the insulating film 60 is formed in contact with the upper surface. The shield 65 is the same as that in the fourth embodiment. Description of points common to the first embodiment is omitted.

  The process until the slit 63 is formed is the same as that of the seventh embodiment. FIG. 18 is a fragmentary cross-sectional view of the semiconductor memory device according to the ninth embodiment. The same components as those in FIG. The step of forming an insulating film having a dielectric constant lower than that of the capacitive insulating film 60 in the slit is the same as that in the fourth embodiment, and thus will be omitted. Further, since the process of forming the upper electrode 61 is the same as that in the first embodiment, the description thereof is omitted.

(Embodiment 10)
A semiconductor memory device according to Embodiment 10 of the present invention will be described with reference to the drawings. The difference between the first embodiment and the present embodiment is that the capacitive element 62 and the capacitive element 62 are completely separated by partially removing the upper electrode 61 formed in the slit 63. . Description of points common to the first embodiment is omitted.

  The steps until the upper electrode 61 is formed are the same as those in the first embodiment. FIG. 19 is a fragmentary cross-sectional view of the semiconductor memory device according to the tenth embodiment. The same components as those in FIG. A photoresist is applied to the entire surface of the upper electrode 61. Then, a resist pattern having an opening is formed in the upper electrode 61 at the center of the slit 63 so that the upper electrode 61 completely covers the capacitive insulating film 60. Using this resist pattern as a mask, the upper electrode 61 is removed by dry etching until the upper surface of the first insulating film 57 is exposed. Thereafter, the resist pattern is removed. Thereby, as shown in FIG. 19, a slit 63 is formed between the capacitive element 62 and the capacitive element 62.

  The semiconductor memory device and the manufacturing method thereof according to the present invention can be applied to a semiconductor memory device or the like that needs to prevent destruction of data of a capacitive element and malfunction of a memory cell.

Sectional view of the main part of a conventional semiconductor memory device The figure which shows the applied electric field at the time of the data writing of a semiconductor memory device (A) Diagram showing polarization state of capacitive element 19A when voltage is applied to capacitive element 19A (b) Diagram showing polarization state of capacitive element 19A when applied voltage of capacitive element 19A is zero (c) Capacitance The figure which shows the polarization state of capacitive element 19B when a voltage is applied to element 19A (d) The figure which shows the polarization state of capacitive element 19B when the applied voltage of capacitive element 19A is set to 0 (A) Schematic diagram of polarization state in which capacitive elements 19A and 19B hold data (b) Schematic diagram of polarization state when data is written to capacitive element 19A Plane principal part figure of the several memory cell which comprises the memory cell array in Embodiment 1 of this invention Sectional drawing of the principal part of the semiconductor memory device in Embodiment 1 of this invention Process sectional drawing of the manufacturing method of the semiconductor memory device in Embodiment 1 of this invention Circuit schematic diagram of cell block shown in FIG. 5 in Embodiment 1 of the present invention Operational diagram of the semiconductor memory device in the first embodiment of the present invention Relationship diagram between the distance between capacitive elements and the amount of polarization in the present invention and the conventional example Sectional drawing of the principal part of the semiconductor memory device in Embodiment 2 of this invention Sectional drawing of the principal part of the semiconductor memory device in Embodiment 3 of this invention Process sectional drawing of the manufacturing method of the semiconductor memory device in Embodiment 3 of this invention Sectional drawing of the principal part of the semiconductor memory device in Embodiment 5 of this invention Process sectional drawing of the manufacturing method of the semiconductor memory device in Embodiment 6 of this invention Sectional drawing of the principal part of the semiconductor memory device in Embodiment 7 of this invention Sectional drawing of the principal part of the semiconductor memory device in Embodiment 8 of this invention Sectional drawing of the principal part of the semiconductor memory device in Embodiment 9 of this invention Sectional drawing of the principal part of the semiconductor memory device in Embodiment 10 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory cell 1A Memory cell 1B Memory cell 10 Semiconductor substrate 11 Source / drain region 11a Source / drain region 11b Source / drain region 12 Gate electrode 13 Element isolation layer 14 Interlayer insulating film 15 Contact plug 16 Lower electrode 16A Lower electrode 16B Lower electrode 17 capacitive insulating film 18 upper electrode 19 capacitive element 19A capacitive element 19B capacitive element E electric field E 'electric field D region

50 Semiconductor substrate 51 Transistor 51A Transistor 51B Transistor 52 Gate electrode 53 Source / drain region 54 Gate insulating film 55 Side wall insulating film 56 Element isolation layer 57 First insulating film 58 Contact plug 59 Lower electrode 59A Lower electrode 59B Lower electrode 60 Capacitance Insulating film 61 Upper electrode 62 Capacitor element 62A Capacitor element 62B Capacitor element 63 Slit 64 Memory cell 65 Shield 66 Third insulating film 67 Second insulating film a Peripheral portion CP Cell plate line WL Word line BL Bit line / BL Bit line

Claims (35)

A semiconductor substrate;
A plurality of lower electrodes formed on a first insulating film formed on the semiconductor substrate;
A capacitive insulating film formed to cover the plurality of lower electrodes and the first insulating film;
In a semiconductor memory device having a plurality of capacitive elements including an upper electrode formed on the capacitive insulating film,
The plurality of capacitive elements are connected to a cell plate line,
A semiconductor memory device, wherein at least one portion of the capacitive insulating film between the lower electrode and the lower electrode along the cell plate line direction is cut. A semiconductor substrate;
A plurality of lower electrodes formed on a first insulating film formed on the semiconductor substrate;
A second insulating film formed between the plurality of lower electrodes;
A capacitive insulating film formed on the second insulating film and the plurality of lower electrodes;
In a semiconductor memory device having a plurality of capacitive elements provided with an upper electrode formed on the capacitive insulating film, the plurality of capacitive elements are connected to a cell plate line,
A semiconductor memory device, wherein at least one portion of the capacitive insulating film between the lower electrode and the lower electrode along the cell plate line direction is cut. 3. The semiconductor memory device according to claim 1, further comprising a shield at a portion where the capacitive insulating film is cut. A semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A plurality of lower electrodes formed on the first insulating film;
A capacitive insulating film formed to cover the plurality of lower electrodes and the first insulating film;
An upper electrode formed on the capacitive insulating film,
At least one portion of the capacitive insulating film between the lower electrode and the lower electrode is cut;
A semiconductor memory device having a shield at a portion where the capacitive insulating film is cut. A semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A plurality of lower electrodes formed on the first insulating film;
A second insulating film formed between the plurality of lower electrodes;
A capacitive insulating film formed on the second insulating film and the plurality of lower electrodes;
An upper electrode formed on the capacitive insulating film,
At least one portion of the capacitive insulating film between the lower electrode and the lower electrode is cut;
A semiconductor memory device having a shield at a portion where the capacitive insulating film is cut. 6. The semiconductor memory device according to claim 3, wherein the shield is made of an insulating film having a dielectric constant lower than that of the capacitive insulating film. The semiconductor memory device according to claim 3, wherein the shield is made of a conductive material. The semiconductor memory device according to claim 7, wherein the shield has a fixed potential. The semiconductor memory device according to claim 7, wherein the shield has a ground potential. The semiconductor memory device according to claim 7, wherein the shield is the upper electrode. The semiconductor memory device according to claim 7, wherein the shield is not in contact with the upper electrode. The semiconductor memory device according to claim 3, wherein the shield blocks or weakens an electric field. A third insulating film formed so as to cover the shield between the lower electrode and the lower electrode;
The third insulating film is an insulating film having a lower dielectric constant than the capacitive insulating film,
The semiconductor memory device according to claim 3, wherein the upper electrode is formed in contact with an upper surface of the third insulating film and an upper surface of the capacitive insulating film. The semiconductor memory device according to claim 1, wherein the portion where the capacitive insulating film is cut is a slit. The semiconductor memory device according to claim 14, wherein a distance from the lower electrode to the slit is larger than a film thickness of the capacitive insulating film. 16. The semiconductor memory device according to claim 14, wherein the slit is not in contact with the lower electrode. The semiconductor memory device according to claim 14, wherein the slit is formed by etching. The semiconductor memory device according to claim 14, wherein a long side of the slit is equal to a width of the lower electrode. The semiconductor memory device according to claim 14, wherein the slit is formed between all the lower electrodes. The semiconductor memory device according to claim 1, wherein a distance between the lower electrode and the lower electrode is greater than 0 nm and equal to or less than 300 nm. 21. The semiconductor memory device according to claim 1, wherein a distance between the lower electrode and the lower electrode is a shortest distance among a plurality of the lower electrode and the lower electrode. 3. The semiconductor memory device according to claim 1, wherein the cell plate line is electrically connected to the upper electrode. 23. The semiconductor memory device according to claim 22, wherein the cell plate line is the upper electrode. A diffusion layer formed on the semiconductor substrate;
24. The semiconductor memory device according to claim 1, further comprising a plug that electrically connects the diffusion layer and the lower electrode. 25. The semiconductor memory device according to claim 1, wherein the capacitive insulating film is made of a ferroelectric material or a high dielectric material. The capacitive insulating films are SrBi ₂ (TaxNb1-x) ₂ O ₉ , Pb (ZrxTi1-x) O ₃ , (BaxSr1-x) TiO ₃ , (BixLa1-x) ₄ Ti ₃ O ₁₂ , Ta ₂ O ₅ (0 26. The semiconductor memory device according to claim 1, comprising any one of ≦ x ≦ 1). Forming a first insulating film on the semiconductor substrate;
Forming a plurality of lower electrodes on the first insulating film (b);
Forming a capacitive insulating film so as to cover the first insulating film and the plurality of lower electrodes;
Forming an upper electrode on the capacitive insulating film (d);
Forming a cell plate line connected to the upper electrode (e),
After the step (c), the method for manufacturing a semiconductor memory device includes a step (f) of cutting at least one portion of the capacitive insulating film between the lower electrode and the lower electrode along the cell plate line direction. . Forming a first insulating film on the semiconductor substrate;
Forming a plurality of lower electrodes on the first insulating film (b);
Forming a second insulating film between the plurality of lower electrodes (g);
Forming a capacitive insulating film on the plurality of lower electrodes and the second insulating film (h);
Forming an upper electrode on the capacitive insulating film (d);
Forming a cell plate line connected to the upper electrode (e),
After the step (h), the method for manufacturing a semiconductor memory device includes a step (f) of cutting at least one portion of the capacitive insulating film between the lower electrode and the lower electrode along the cell plate line direction. . After step (f)
29. The method of manufacturing a semiconductor memory device according to claim 27 or 28, further comprising a step (i) of forming a shield at a portion where the capacitive insulating film is cut. After step (i) and before step (d),
30. The method of manufacturing a semiconductor memory device according to claim 29, further comprising a step of forming a third insulating film so as to cover the shield between the lower electrode and the lower electrode. The step (d)
29. The method of manufacturing a semiconductor memory device according to claim 27, further comprising a step of forming the capacitor insulating film and a portion where the capacitor insulating film is cut. Forming a first insulating film on the semiconductor substrate;
Forming a plurality of lower electrodes on the first insulating film (b);
Forming a capacitive insulating film so as to cover the first insulating film and the plurality of lower electrodes;
Forming an upper electrode so as to cover the capacitive insulating film;
Forming a cell plate line connected to the upper electrode (e),
After step (j), a semiconductor including step (k) of cutting at least one of the capacitor insulating film and the upper electrode between the lower electrode and the lower electrode along the cell plate line direction A method for manufacturing a storage device. The step (f) and the step (k) are:
The method of manufacturing a semiconductor memory device according to any one of claims 27 to 32, which is a step (l) of forming a slit. The step (l)
34. The method of manufacturing a semiconductor memory device according to claim 33, further comprising a step of removing the capacitor insulating film at a position where a distance from the lower electrode to the slit is larger than a thickness of the capacitor insulating film by etching. The step (d) and the step (j) include
The semiconductor memory device according to any one of claims 27 to 34, which is a step of forming the cell plate line.

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