JP2005032982A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a structure capable of avoiding the occurrence of a short circuit between cylindrical storage nodes even when the height of the cylindrical storage node is increased to increase the capacity of a capacitor. <P>SOLUTION: An insulating member 54A composed of a silicon nitride film is provided on the outer peripheral rim of the upper end of the storage node 34A so as to surround the outer peripheral rim. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device including a capacitor element.
[0002]
[Prior art]
In a DRAM (Dynamic Random Access Memory), which has been miniaturized, the use of a cylindrical capacitor structure is increasing in order to increase the capacitance of a capacitor as a capacitive element. Patent Documents 1 to 4 listed below are disclosed as DRAMs that employ such a cylindrical capacitor structure.
[0003]
[Patent Document 1]
JP 11-297960 A
[0004]
[Patent Document 2]
JP-A-11-317504
[0005]
[Patent Document 3]
Japanese Patent Laid-Open No. 11-0117144
[0006]
[Patent Document 4]
JP-A-11-233740
[0007]
[Problems to be solved by the invention]
However, in the DRAM adopting the cylindrical capacitor structure, the mechanical strength decreases as the height of the cylindrical storage node (lower electrode) increases (as the capacitance of the capacitor increases). It is conceivable that the storage node may fall or cause a short circuit between adjacent storage nodes.
[0008]
In a DRAM, when a short circuit occurs between storage nodes, a bit line defect and a pair bit line defect occur. The occurrence of these defects can be remedied by a redundant circuit if the occurrence of defects below a certain level. However, if a defect occurs more than expected, it cannot be remedied by a redundant circuit, resulting in a typical malfunction, resulting in a decrease in yield in the manufacturing process of the semiconductor device.
[0009]
In order to avoid such a collapse of the cylindrical storage node, the lower end of the cylinder is covered with an oxide film on the outside of the storage node, and the lower end region of the storage node is supported by this oxide film. A structure that can be considered. However, in the case of this structure, the portion of the storage node supported by the oxide film is not covered with the dielectric film and the cell plate, and thus becomes a region that does not function as a capacitor. As a result, the capacitance of the capacitor is reduced. In the DRAM, a decrease in the capacitance of the capacitor causes deterioration of device characteristics such as refresh characteristics.
[0010]
Therefore, the present invention has been made to solve the above-described problem, and even if the height of the storage node made of the columnar member is increased in order to increase the capacitance of the capacitor, a short circuit is caused between the storage nodes. An object of the present invention is to provide a semiconductor device having a structure capable of avoiding the occurrence of the above.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor device according to the present invention is a semiconductor device including a capacitive element having a lower electrode, a dielectric film, and an upper electrode, and the lower electrode includes a columnar member extending upward. And an insulating member is provided on the outer periphery of the upper end of the columnar member so as to surround the outer periphery.
[0012]
According to the above configuration, even when the lower electrode made of the columnar member falls down or breaks, the insulating member is provided on the outer peripheral edge of the upper end portion of the columnar member, so This makes it possible to avoid electrical contact. As a result, it is possible to prevent occurrence of a short circuit between adjacent lower electrodes.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device and a manufacturing method thereof according to each embodiment, which is an example based on the present invention, will be described with reference to the drawings.
[0014]
(Embodiment 1)
With reference to FIGS. 1-10, the semiconductor device 100 in Embodiment 1 and its manufacturing method are demonstrated. 1 is a partial plan view of the semiconductor device 100 according to the present embodiment, FIG. 2A is a cross-sectional view taken along the line II (A) -II (A) in FIG. 1, and FIG. It is II (B) -II (B) sectional view taken on the line in 1.
[0015]
3 to 10 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the present embodiment, and (A) corresponds to the cross section taken along the line II (A) -II (A) in FIG. It is process sectional drawing, (B) is process sectional drawing corresponding to the II (B) -II (B) arrow cross section in FIG.
[0016]
The (A)-(A) line direction coincides with the direction in which the word lines extend, and the (B)-(B) line direction coincides with the direction in which the bit lines extend. The same applies to each of the following embodiments.
[0017]
(Configuration of Semiconductor Device 100)
Referring to FIGS. 1 and 2, semiconductor device 100 constitutes a DRAM. An element isolation insulating film 21 is provided on the silicon semiconductor substrate 1 to define an active region. In addition, in a predetermined region on the silicon semiconductor substrate 1 and the element isolation insulating film 21, a doped polysilicon layer 31, a tungsten silicide layer 6, a silicon oxide film 26, a gate oxide film (not shown) are interposed. In addition, a gate electrode having a stacked structure of silicon nitride films 51 and 52 is provided. The side wall of the gate electrode is covered with a sidewall insulating film 5.
[0018]
The plurality of gate electrodes are covered with a first interlayer insulating film 22 made of a silicon oxide film, and a contact plug 32 made of polysilicon doped with impurities (hereinafter referred to as doped polysilicon) is provided in a predetermined region. ing. A second interlayer insulating film 23 and a third interlayer insulating film 24 each made of a silicon oxide film are provided on the first interlayer insulating film 22. A storage node (lower electrode) contact plug 33 connected to the selected contact plug 32 is provided in the second interlayer insulating film 23 and the third interlayer insulating film 24. A bit line 4 is embedded in a predetermined region between the second interlayer insulating film 23 and the third interlayer insulating film 24.
[0019]
On the third interlayer insulating film 24, there are provided a plurality of storage nodes 34A made of hollow cylindrical doped polysilicon as columnar members that are connected to the storage node contact plug 33 and constitute the lower electrode of the capacitor. . Further, an insulating member 54A made of a silicon nitride film is provided on the outer peripheral edge of the upper end of the storage node 34A so as to extend outwardly so as to surround the outer peripheral edge. In addition, on the third interlayer insulating film 24, the bottom of the storage node 34 </ b> A is separated by the silicon nitride film 53.
[0020]
In the present embodiment, as shown in the partial plan view of FIG. 1, the storage nodes 34A are regularly arranged in an oblique lattice shape (houndstooth lattice shape). The array of storage nodes 34A is merely an example, and is not limited to this array.
[0021]
A dielectric film 60 is provided to cover the exposed outer surfaces of the storage node 34A and the insulating member 54A, and a cell plate (upper electrode) 70 is provided to cover the dielectric film 60. The storage node 34A, the dielectric film 60, and the cell plate (upper electrode) 70 constitute a capacitor as a capacitive element.
[0022]
(Method for Manufacturing Semiconductor Device 100)
Next, a method for manufacturing the semiconductor device 100 having the above configuration will be described with reference to FIGS. Note that the manufacturing method until the contact plug 33 is formed in the second interlayer insulating film 23 and the third interlayer insulating film 24 can employ a conventionally known manufacturing method, and thus description thereof is omitted here. (The same is omitted in the manufacturing method in each embodiment shown below).
[0023]
First, referring to FIG. 3, a silicon nitride film 53 is formed on the third interlayer insulating film 24 by the CVD method. Thereafter, a silicon oxide film 25 having a predetermined thickness is formed on the silicon nitride film 53 by a CVD method. Next, referring to FIG. 4, a photoengraving technique and a dry etching process are performed on a predetermined region of silicon oxide film 25 to form contact hole 25h. At this time, the silicon nitride film 53 functions as an etching stopper film when the high aspect silicon oxide film 25 is etched.
[0024]
Next, referring to FIG. 5, doped polysilicon 34 is formed by CVD so as to cover the surface of silicon oxide film 25 and the inside of contact hole 25h. Thereafter, a silicon oxide film 27 is formed by a CVD method so as to cover the surface of the doped polysilicon 34 and fill the inside of the contact hole 25h covered with the doped polysilicon 34. Thereafter, as shown in FIG. 6, the silicon oxide film 25, the silicon oxide film 27, and the doped polysilicon 34 are subjected to CMP (Chemical Mechanical Polishing) treatment, and the doped polysilicon 34 existing on the silicon oxide film 25. Remove.
[0025]
Next, referring to FIG. 7, wet etching is performed on silicon oxide film 25 and silicon oxide film 27. Here, as this etching process, each of the silicon oxide film 25 and the silicon oxide film 27 is set so that the processing speed for the etching treatment agent is sufficiently slower for the wet etching for the silicon oxide film 27 than for the silicon oxide film 25. Material shall be selected. As a result, as shown in FIG. 7, the silicon oxide film 25 is etched more than the silicon oxide film 27, and a recess (h) is formed in the silicon oxide film 25.
[0026]
Next, referring to FIG. 8, a silicon nitride film 54 is formed by a CVD method so as to cover silicon oxide film 25, doped polysilicon 34, and silicon oxide film 27. Thereafter, as shown in FIG. 9, the entire surface of the silicon nitride film 54 is etched back. Thus, a sidewall-shaped insulating member 54A made of the silicon nitride film 54 is formed on the outer periphery of the upper end portion of the doped polysilicon 34 so as to surround the outer periphery.
[0027]
Next, as shown in FIG. 10, the silicon oxide film 25 and the silicon oxide film 27 are simultaneously removed by wet etching. At this time, although the etching processing speeds of the silicon oxide film 25 and the silicon oxide film 27 are different, the silicon nitride film 53 acts as an etching stopper for etching the silicon oxide film 25, and the doping is performed for etching the silicon oxide film 27. The polysilicon 34 acts as an etching stopper. As a result, a hollow cylindrical storage node 34A in which the constituent members are provided only outside is completed. Thereafter, the dielectric film 60 and the cell plate (upper electrode) 70 are formed. Thereby, the semiconductor device 100 shown in FIG. 2 is completed.
[0028]
(Action / Effect)
As described above, according to the semiconductor device 100 and the manufacturing method thereof in the present embodiment, even when the hollow cylindrical storage node 34A is collapsed or folded, the sidewall is formed on the outer periphery of the upper end portion of the storage node 34A. By providing the insulating member 54A having a shape, it is possible to avoid electrical contact with the adjacent storage node 34A. As a result, it is possible to avoid the occurrence of bit line defects and pair bit line defects, and to improve the yield in the manufacturing process of the semiconductor device.
[0029]
In addition, the entire cylindrical portion of the storage node 34A can contribute as a capacitor, and the height of the storage node 34A can be increased, so that the capacitor capacity of the DRAM can be increased. .
[0030]
(Embodiment 2)
Next, with reference to FIGS. 11-15, the semiconductor device 200 in Embodiment 2 and its manufacturing method are demonstrated. 11 is a partial plan view of the semiconductor device 200 in this embodiment, FIG. 12A is a cross-sectional view taken along line XII (A) -XII (A) in FIG. 11, and FIG. 11 is a cross-sectional view taken along line XII (B) -XII (B) in FIG.
[0031]
13 to 15 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the present embodiment, and (A) corresponds to a cross-section taken along line XII (A) -XII (A) in FIG. It is process sectional drawing, (B) is process sectional drawing corresponding to the XII (B) -XII (B) arrow cross section in FIG.
[0032]
In the semiconductor device 200 according to the second embodiment, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals in the drawing, and the repeated description will not be repeated, and only the characteristic parts will be described in detail. Explained.
[0033]
(Configuration of Semiconductor Device 200)
Referring to FIGS. 11 and 12, the characteristic configuration of semiconductor device 200 is that insulating member 54B having the same function as insulating member 54A provided in storage node 34A of semiconductor device 100 has an upper end portion of storage node 34A. As shown in the plan views of FIGS. 11 and 12A, the plurality of storage nodes 34A arranged in an oblique lattice shape are provided on the outer peripheral edge. The insulating member 54B is provided to be connected.
[0034]
(Method for Manufacturing Semiconductor Device 200)
Next, a method for manufacturing the semiconductor device 200 having the above configuration will be described with reference to FIGS. The steps (FIGS. 3 to 7) until the recess (h) is formed in the silicon oxide film 25 are the same as the method for manufacturing the semiconductor device 100.
[0035]
Referring to FIG. 13, a silicon nitride film 54 is formed by CVD so as to cover silicon oxide film 25, doped polysilicon 34, and silicon oxide film 27. In this case, in the cross section viewed along the direction in which the word line shown in FIG. 13A extends, the silicon nitride film 54 between the adjacent doped polysilicons 34 is connected as shown in the cross sectional view. In addition, the silicon nitride film 54 is formed thicker than in the first embodiment. At this time, it is important that the silicon nitride film 54 between the doped polysilicon 34 is not connected in the cross section seen along the direction in which the bit line extends as shown in FIG.
[0036]
Next, as shown in FIG. 14, the entire surface of the silicon nitride film 54 is etched back. Thus, a sidewall-shaped insulating member 54B made of the silicon nitride film 54 is formed on the outer periphery of the upper end portion of the doped polysilicon 34 so as to surround the outer periphery. In the case of this embodiment, as a result of the silicon nitride film 54 being formed thicker than in the case of Embodiment 1, in the cross-sectional portion shown in FIG. It becomes a connected state.
[0037]
Next, as shown in FIG. 15, as in the first embodiment, the silicon oxide film 25 and the silicon oxide film 27 are simultaneously removed by wet etching. As a result, a hollow cylindrical storage node 34A in which the constituent members are provided only outside is completed. Note that the silicon oxide film 25 in the lower region where the sidewall-shaped insulating member 54B in the cross-sectional portion shown in FIG. 15A is connected is sufficiently removed by the wraparound of the etching agent from the surroundings. Thereafter, the dielectric film 60 and the cell plate (upper electrode) 70 are formed. Thereby, the semiconductor device 200 shown in FIG. 12 is completed.
[0038]
(Action / Effect)
As described above, according to the semiconductor device 200 and the manufacturing method thereof in the present embodiment, the same operational effects as in the case of the first embodiment can be obtained. Furthermore, in the semiconductor device 200 in the case of the second embodiment, since the insulating members 54B of the storage nodes 34A adjacent to each other in the oblique direction are provided to be connected, The upper end portions of the node 34A are connected to each other, and the rigidity of the storage node 34A can be improved. As a result, the hollow cylindrical storage node 34 </ b> A can be prevented from falling or breaking with a higher probability.
[0039]
(Embodiment 3)
Next, with reference to FIGS. 16-24, the semiconductor device 300 in Embodiment 3 and its manufacturing method are demonstrated. 16 is a partial plan view of the semiconductor device 300 in this embodiment, FIG. 17A is a cross-sectional view taken along line XVII (A) -XVII (A) in FIG. 16, and FIG. 16 is a cross-sectional view taken along line XVII (B) -XVII (B) in FIG.
[0040]
18 to 24 are cross-sectional views showing a method for manufacturing a semiconductor device in the present embodiment, and FIG. 18A corresponds to a cross section taken along line XVII (A) -XVII (A) in FIG. It is process sectional drawing, (B) is process sectional drawing corresponding to a XVII (B) -XVII (B) arrow cross section in FIG.
[0041]
In the semiconductor device 300 according to the present embodiment, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals in the drawing, and repeated description will not be repeated, and only the characteristic parts will be described in detail. explain.
[0042]
(Configuration of Semiconductor Device 300)
Referring to FIGS. 16 and 17, in the first and second embodiments, the storage node has a hollow cylindrical shape in which the constituent members are provided only on the outside as an example of the columnar member extending upward. As described above, the semiconductor device 300 according to the present embodiment employs a solid cylindrical storage node 34B whose inside is filled with the constituent members as the columnar member. Similar to the configuration, an insulating member 54A is provided on the outer periphery of the upper end of the storage node 34B.
[0043]
(Method for Manufacturing Semiconductor Device 300)
Next, with reference to FIGS. 18-24, the manufacturing method of the semiconductor device 300 which consists of the said structure is demonstrated.
[0044]
Referring to FIG. 18, a silicon nitride film 53 is formed on third interlayer insulating film 24 by the CVD method. Thereafter, a silicon oxide film 25 having a predetermined thickness is formed on the silicon nitride film 53 by a CVD method. A contact hole 25h is formed in a predetermined region of the silicon oxide film 25 by photolithography and dry etching. At this time, the silicon nitride film 53 functions as an etching stopper film when the high aspect silicon oxide film 25 is etched.
[0045]
Next, referring to FIG. 19, doped polysilicon 34 is formed by CVD so as to fill the surface of silicon oxide film 25 and the inside of contact hole 25h. Thereafter, as shown in FIG. 20, the silicon oxide film 25 and the doped polysilicon 34 are subjected to a CMP process to remove the doped polysilicon 34 existing on the silicon oxide film 25, thereby forming a solid cylindrical shape. The storage node 34B is completed.
[0046]
Next, referring to FIG. 21, wet etching is performed on the silicon oxide film 25 to form a recess (h) in the silicon oxide film 25. Next, referring to FIG. 22, a silicon nitride film 54 is formed by a CVD method so as to cover silicon oxide film 25 and storage node 34B. Thereafter, as shown in FIG. 23, the entire surface of the silicon nitride film 54 is etched back. Thus, a sidewall-shaped insulating member 54A made of the silicon nitride film 54 is formed on the outer periphery of the upper end portion of the storage node 34B so as to surround the outer periphery.
[0047]
Next, as shown in FIG. 24, the silicon oxide film 25 is removed by wet etching. At this time, the silicon nitride film 53 acts as an etching stopper for etching the silicon oxide film 25. Thereafter, the dielectric film 60 and the cell plate (upper electrode) 70 are formed. Thereby, the semiconductor device 300 shown in FIG. 17 is completed.
[0048]
(Action / Effect)
As described above, according to semiconductor device 300 and the method for manufacturing the same in the present embodiment, it is possible to obtain the same functions and effects as in the first embodiment. Further, when a solid cylindrical storage node 34B is employed, an insulating member 54A is provided on the outer peripheral edge of the upper end of the storage node 34B even if the short margin decreases due to the effect of miniaturization. Therefore, it is possible to improve the short margin. As a result, the height of the storage node 34B can be increased, and an increase in capacitor capacity can be expected.
[0049]
(Embodiment 4)
Next, with reference to FIGS. 25-29, the semiconductor device 400 and the manufacturing method thereof in the fourth embodiment will be described. 25 is a partial plan view of the semiconductor device 400 in this embodiment, FIG. 26A is a cross-sectional view taken along line XXVI (A) -XXVI (A) in FIG. 25, and FIG. It is XXVI (B) -XXVI (B) arrow directional cross-sectional view in 25.
[0050]
27 to 29 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the present embodiment, and FIG. 27A corresponds to a cross section taken along line XXVI (A) -XXVI (A) in FIG. It is process sectional drawing, (B) is process sectional drawing corresponding to the XXVI (B) -XXVI (B) arrow cross section in FIG.
[0051]
In the semiconductor device 400 according to the fourth embodiment, the same or corresponding parts as those in the third embodiment are denoted by the same reference numerals in the drawing, and repeated description will not be repeated, and only the characteristic parts will be described in detail. Explained.
[0052]
(Configuration of Semiconductor Device 400)
Referring to FIGS. 25 and 26, the characteristic configuration of semiconductor device 400 is that an insulating member 54B having the same function as insulating member 54A provided in storage node 34B of semiconductor device 300 has an upper end portion of storage node 34B. As shown in the plan views of FIG. 25 and FIG. 26A, the plurality of storage nodes 34B arranged in an oblique lattice shape are provided on the outer peripheral edge. The insulating member 54B is provided to be connected.
[0053]
(Method for Manufacturing Semiconductor Device 400)
Next, a method for manufacturing the semiconductor device 400 having the above-described configuration will be described with reference to FIGS. The process until the recess (h) is formed in the silicon oxide film 25 (FIGS. 18 to 21) is the same as the method for manufacturing the semiconductor device 300.
[0054]
Referring to FIG. 27, a silicon nitride film 54 is formed by a CVD method so as to cover silicon oxide film 25 and storage node 34B. In this case, in the cross section viewed along the direction in which the word line shown in FIG. 27A extends, as shown in the cross sectional view, the silicon nitride film 54 between the adjacent storage nodes 34B is connected. The silicon nitride film 54 is formed thicker than in the third embodiment. At this time, it is important that the silicon nitride film 54 between the doped polysilicon 34B is not connected in the cross section seen along the direction in which the bit line extends as shown in FIG.
[0055]
Next, as shown in FIG. 28, the entire surface of the silicon nitride film 54 is etched back. Thus, a sidewall-shaped insulating member 54B made of the silicon nitride film 54 is formed on the outer periphery of the upper end portion of the storage node 34B so as to surround the outer periphery. In the present embodiment, as a result of forming the silicon nitride film 54 thicker than in the case of the third embodiment, the sidewall-shaped insulating member 54B is formed in the cross-sectional portion shown in FIG. It becomes a connected state.
[0056]
Next, as shown in FIG. 29, the silicon oxide film 25 is removed by wet etching as in the case of the third embodiment. Note that the silicon oxide film 25 in the lower region where the sidewall-shaped insulating member 54B in the cross-sectional portion shown in FIG. 29A is connected is sufficiently removed by the wraparound of the etching agent from the periphery. Thereafter, the dielectric film 60 and the cell plate (upper electrode) 70 are formed. Thereby, the semiconductor device 400 shown in FIG. 26 is completed.
[0057]
(Action / Effect)
As described above, according to the semiconductor device 400 and the manufacturing method thereof in the present embodiment, the same operational effects as in the case of the third embodiment can be obtained. Further, in the semiconductor device 400 in the case of the fourth embodiment, the insulating members 54B of the storage nodes 34B adjacent to each other in the oblique direction are provided so as to be connected. The upper end portions of the nodes 34B are connected to each other, and the rigidity of the storage node 34B can be improved. As a result, it is possible to prevent the storage node 34B having a solid cylindrical shape from falling or folding with a higher probability.
[0058]
It should be understood that the above-described embodiments are illustrative in all respects and are not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0059]
【The invention's effect】
According to the semiconductor device based on the present invention, even when the height of the storage node made of the columnar member is increased in order to increase the capacitance of the capacitor, it is possible to avoid the occurrence of a short circuit between the storage nodes. A semiconductor device having a possible structure can be provided.
[Brief description of the drawings]
FIG. 1 is a partial plan view of a semiconductor device according to a first embodiment.
2A is a cross-sectional view taken along line II (A) -II (A) in FIG. 1, and FIG. 2B is a cross-sectional view taken along line II (B) -II (B) in FIG.
FIG. 3 is a first process cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment;
4 is a second process cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment; FIG.
FIG. 5 is a third process cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment.
6 is a fourth process cross-sectional view illustrating the method for manufacturing the semiconductor device in Embodiment 1. FIG.
7 is a fifth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment; FIG.
FIG. 8 is a sixth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment.
FIG. 9 is a seventh process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment;
FIG. 10 is an eighth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment.
FIG. 11 is a partial plan view of the semiconductor device in the second embodiment.
12A is a cross-sectional view taken along line XII (A) -XII (A) in FIG. 11, and FIG. 12B is a cross-sectional view taken along line XII (B) -XII (B) in FIG.
FIG. 13 is a sixth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the second embodiment.
FIG. 14 is a seventh process sectional view showing the method of manufacturing the semiconductor device according to the second embodiment;
15 is an eighth process sectional view showing the method of manufacturing the semiconductor device according to the second embodiment. FIG.
16 is a partial plan view of a semiconductor device in Embodiment 3. FIG.
17A is a cross-sectional view taken along line XVII (A) -XVII (A) in FIG. 16, and FIG. 17B is a cross-sectional view taken along line XVII (B) -XVII (B) in FIG.
FIG. 18 is a first process cross-sectional view illustrating the method for manufacturing the semiconductor device in the third embodiment.
FIG. 19 is a second process cross-sectional view illustrating the method for manufacturing the semiconductor device in the third embodiment.
FIG. 20 is a third process cross-sectional view illustrating the method for manufacturing the semiconductor device in the third embodiment.
FIG. 21 is a fourth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the third embodiment.
FIG. 22 is a fifth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the third embodiment;
FIG. 23 is a sixth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the third embodiment.
24 is a seventh process sectional view showing the method of manufacturing the semiconductor device according to the third embodiment; FIG.
25 is a partial plan view of a semiconductor device in Embodiment 4; FIG.
26A is a cross-sectional view taken along line XXVI (A) -XXVI (A) in FIG. 25, and FIG. 26B is a cross-sectional view taken along line XXVI (B) -XXVI (B) in FIG.
FIG. 27 is a fifth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the fourth embodiment;
FIG. 28 is a sixth process cross-sectional view illustrating the method for manufacturing the semiconductor device in the fourth embodiment;
29 is a seventh process sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate, 4 bit line, 5 sidewall insulating film, 6 tungsten silicide layer, 21 element isolation insulating film, 22 1st interlayer insulating film, 23 2nd interlayer insulating film, 24 3rd interlayer insulating film, 25 silicon oxide Film, 25h contact hole, 26, 27 silicon oxide film, 31 doped polysilicon layer, 32 contact plug, 33 storage node (lower electrode) contact plug, 34 doped polysilicon, 34A, 34B storage node, 51, 52, 53, 54 Silicon nitride film, 54A, 54B Insulating member, 60 Dielectric film, 70 Cell plate (upper electrode), 100, 200, 300, 400 Semiconductor device.

Claims (4)

A semiconductor device comprising a capacitive element having a lower electrode, a dielectric film, and an upper electrode,
The lower electrode has a columnar member extending upward,
A semiconductor device, wherein an insulating member is provided on an outer peripheral edge of an upper end portion of the columnar member so as to surround the outer peripheral edge. A plurality of the capacitive elements are arranged in an oblique lattice shape,
The semiconductor device according to claim 1, wherein the insulating members of the lower electrodes adjacent to each other in an oblique direction are connected to each other. The semiconductor device according to claim 1, wherein the columnar member has a hollow cylindrical shape whose constituent members are provided only outside. The semiconductor device according to claim 1, wherein the columnar member has a solid cylindrical shape whose inside is filled with the constituent members.

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