JP2005026955A - Section filter circuit, transport stream processing apparatus, and digital broadcast reception system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an area for storing a mask pattern. <P>SOLUTION: A comparison circuit 303 operates EOR between a section header stored in a section buffer 301 and a matching pattern stored in a matching pattern RAM 302 (obtains EOR operation data). Next, a run length decoder 305 converts an encoded mask pattern (stored in a mask for matching RAM) indicating a start position of an effective section and a length of the effective section, to a mask pattern having the same bit length as the matching pattern. A mask circuit 306 operates AND between EOR operation data and the mask pattern (obtains AND operation data). Then a coincidence detection circuit 307 discriminates whether bit values of AND operation data are all "0" or not. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for receiving a transport stream, and more particularly to an apparatus including a circuit for obtaining a desired section from a transport stream.
[0002]
[Prior art]
In digital broadcasting, various information such as video, audio, still images, character data, music data, and program guides are transmitted in the transport stream packet format. The digital broadcast receiver is provided with a section filter circuit for extracting necessary section data when the data format in the payload of the received transport stream packet is a section format. A conventional section filter circuit will be described using Patent Document 1 as an example. However, although Patent Document 1 describes a pattern match filter, it may be considered that the same operation as the section filter is performed. Further, the mask for matching in Patent Document 1 corresponds to a mask pattern.
[0003]
<Operation of conventional section filter circuit>
The pattern match filter 24 (FIG. 2 of Patent Document 1) is in DEMUX 5 (FIG. 2 of Patent Document 1), and is necessary for the section of the input transport stream (FIG. 3 (c) of Patent Document 1). It is a block for determining whether the data is unnecessary data or unnecessary data. The operation outline of the pattern matching filter is as follows: the matching pattern 8 bytes set by the CPU 8 (FIG. 3D of Patent Document 1), and the mask for matching 8 bytes in which whether the matching pattern is valid or invalid is specified in bits. (FIG. 3 (e) of Patent Document 1) is used to compare the matching pattern and the section (FIG. 3 (c) of Patent Document 1) for valid bits, and if all match, it is determined that the data is necessary. .
[0004]
[Patent Document 1] Japanese Unexamined Patent Publication No. 2000-32426 (FIGS. 2 and 3)
[0005]
[Problems to be solved by the invention]
In the prior art, since the mask pattern is set with the same bit length as the matching pattern, the area for storing the mask pattern needs the same capacity as the area for storing the matching pattern. Further, when setting a plurality of patterns that differ only in part, it is necessary to set the plurality of patterns individually. For this reason, a large number of areas are necessary to secure an area for storing a necessary number of matching patterns and mask patterns.
[0006]
An object of the present invention is to provide a section filter circuit capable of reducing a capacity required for storing a mask pattern.
[0007]
[Means for Solving the Problems]
Since the bit mask is a continuous bit to a certain extent when viewed in bit units, a mask pattern that has been set as valid or invalid in bit units is set in the form of bit position and bit length. As a result, the mask area can be reduced.
[0008]
However, compared to the bit mask, if the bit position and bit length are set, the number of mask settings is limited. Therefore, the area for setting valid / invalid in conventional bit units and the area for setting the bit position and bit length. Mix. Thereby, an optimal mask pattern region can be determined.
[0009]
In addition, if a part of the multiple patterns is different and different parts are invalid in the other patterns, the multiple patterns are not set individually, but are divided into common pattern parts and different pattern parts. One kind of pattern and mask area are set, and an operation type area that can specify an OR operation for different parts is provided. As a result, the number of setting entries can be reduced (the setting area for the matching pattern and the mask pattern can be reduced).
[0010]
In addition, regarding the setting of the operation type area, not only the OR operation but also the priority of “(“ ”)” operation can be set, thereby reducing the number of setting entries (reducing the setting area of matching pattern and mask pattern) And a comparison that takes into account the priority of the calculation.
[0011]
According to one aspect of the present invention, the section filter circuit includes a matching pattern storage circuit, a mask pattern storage circuit, a mask pattern conversion circuit, and a comparison circuit. The matching pattern storage circuit stores a matching pattern having a predetermined bit arrangement. The mask pattern storage circuit stores an encoded mask pattern encoded in a predetermined bit array. The mask pattern conversion circuit converts the encoded mask pattern stored in the mask pattern storage circuit into a mask pattern. The comparison circuit determines, in bit units, whether or not the section extracted from the transport stream matches the matching pattern stored in the matching pattern storage circuit in the section indicated by the mask data converted by the mask pattern conversion circuit. Do. The mask pattern has the same bit length as the matching pattern. The mask pattern indicates, in bit units, valid sections that should be determined by the comparison circuit and invalid sections that should not be determined by the comparison circuit. The encoded mask pattern indicates a bit position where a valid section exists in the mask pattern.
[0012]
In the section filter circuit described above, the encoded mask pattern indicates a bit position in which an effective interval (interval to be determined by the comparison circuit) exists in the mask pattern. For example, in a 64-bit mask pattern, when it is indicated that a valid section exists in the section 18 to 28 bits from the beginning, the coding mask pattern sets the start position of the valid section to “010010” (= 18) and The bit length of the valid section is “001010” (= 10), and has a 12-bit bit array indicating “010010001010”. The mask pattern creation circuit creates a 64 bit mask pattern from the 12 bit coded mask pattern. Next, the comparison circuit determines whether or not the section (for example, 64 bits) extracted from the transport stream matches the matching pattern (for example, 64 bits) stored in the matching pattern storage circuit in the valid section indicated by the mask pattern. Judge by unit. Thereby, the area for storing (storing) the mask pattern can be reduced.
[0013]
Preferably, the mask pattern storage circuit further stores the mask pattern. In the section indicated by any one of the mask pattern converted by the mask pattern conversion circuit and the mask pattern stored in the matching pattern storage circuit, the section extracted from the transport stream is a matching pattern storage circuit. Whether or not it matches the matching pattern stored in is determined in bit units.
[0014]
In the section filter circuit described above, for example, when the valid section and invalid section of the mask pattern exist alternately, the bit length of the encoded mask pattern is the value after the encoded mask pattern is converted by the mask pattern conversion circuit. It may be longer than the bit length of the mask pattern.
[0015]
In the section filter circuit, the mask pattern storage circuit stores the encoded mask pattern and the unconverted mask pattern. That is, in the above-described case, an unencoded mask pattern is stored in the mask pattern storage circuit. Thereby, the area | region for storing a mask pattern can be reduced rather than the case where only an encoding mask pattern is stored in a mask pattern memory | storage circuit in the above-mentioned case.
[0016]
Preferably, the transport stream processing device includes a packet acquisition circuit, a section data acquisition circuit, the section filter circuit, and a data buffer. The packet acquisition circuit acquires a packet including a desired section from the transport stream. The section acquisition circuit acquires a section from the packet acquired by the packet acquisition circuit. The section filter circuit determines whether or not the section acquired by the section acquisition circuit matches the matching pattern. The data buffer stores sections determined to be matched by the section filter circuit.
[0017]
Preferably, the digital broadcast receiving apparatus includes a flash memory, a CPU, a receiving unit, the transport stream processing apparatus, and a memory. The flash memory stores a specific program. The CPU creates the matching pattern and the mask pattern in accordance with a program stored in the flash memory. The receiving unit receives a transport stream. The transport stream processing apparatus stores sections determined to match the matching pattern. The memory records a section accumulated by the transport stream processing device. The specific program is a program that causes the CPU to create the matching pattern and the coding mask pattern. The matching pattern storage circuit stores a matching pattern created by the CPU. The mask pattern storage circuit stores an encoded mask pattern created by the CPU.
[0018]
According to another aspect of the present invention, the section filter circuit includes a matching pattern storage circuit, a mask pattern storage circuit, and a comparison circuit. The matching pattern storage circuit stores a matching pattern having a predetermined bit arrangement. The mask pattern storage circuit stores a mask pattern having the same bit length as the matching pattern. The comparison circuit compares the section extracted from the transport stream with the matching pattern stored in the matching pattern storage circuit bit by bit in the section indicated by the mask pattern stored in the mask pattern storage circuit, and compares the result. It is determined whether or not the matching pattern matches the section data by performing an operation indicated by the operation type information on an interval indicated by the operation type information in the obtained data (comparison result data). The mask pattern indicates, in bit units, valid sections that should be determined by the comparison circuit and invalid sections that should not be determined by the comparison circuit. The calculation type information indicates the effective interval to be calculated in the comparison result data and the content of the calculation performed on the effective interval.
[0019]
The section filter circuit performs an operation on an effective section indicated by the operation type information in the comparison result data obtained by the comparison circuit. For example, an operation may be considered in which if the section matches the matching pattern in at least one of the three effective sections, the section is determined to match the matching pattern. In this case, the comparison circuit performs comparison using three mask patterns. Accordingly, a plurality of mask patterns can be created from one mask pattern by using the operation type information, and an area necessary for storing the mask pattern can be reduced.
[0020]
Preferably, the transport stream processing device includes a packet acquisition circuit, a section data acquisition circuit, the section filter circuit, and a data buffer. The packet acquisition circuit acquires a packet including a desired section from the transport stream. The section acquisition circuit acquires a section from the packet acquired by the packet acquisition circuit. The section filter circuit determines whether or not the section acquired by the section acquisition circuit matches the matching pattern. The data buffer stores sections determined to be matched by the section filter circuit.
[0021]
Preferably, the digital broadcast receiving apparatus includes a flash memory, a CPU, a receiving unit, the transport stream processing apparatus, and a memory. The flash memory stores a specific program. The CPU creates the matching pattern and the mask pattern in accordance with a program stored in the flash memory. The receiving unit receives a transport stream. The transport stream processing apparatus stores sections determined to match the matching pattern. The memory records a section accumulated by the transport stream processing device. The specific program is a program that causes the CPU to create the matching pattern, the coding mask pattern, and the calculation type information. The matching pattern storage circuit stores a matching pattern created by the CPU. The mask pattern storage circuit stores an encoded mask pattern created by the CPU. The comparison circuit compares the section extracted from the transport stream with the matching pattern stored in the matching pattern storage circuit bit by bit in the section indicated by the mask pattern stored in the mask pattern storage circuit, Whether the matching pattern matches the section data by performing the calculation indicated by the calculation type information on the section indicated by the calculation type information created by the CPU in the data (comparison result data) obtained as a result. Make a decision.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
[0023]
(First embodiment)
FIG. 1 shows the overall configuration of a digital broadcast receiving apparatus according to the first embodiment of the present invention.
[0024]
<Overall configuration of digital broadcast receiver>
The digital broadcast receiving apparatus includes a tuner 101, a demodulation unit 102, a back end unit 103, a flash memory 104, and a main memory 105. The back end unit 103 includes a TS decoder 106, an audio decoder 107, a video decoder 108, a CPU 109, a modem 110, and an interface (I2C, bus I / F). The tuner 101 receives a digital broadcast signal. The demodulator 102 converts the signal received by the tuner 101 into a transport stream format digital signal. The TS decoder 106 extracts audio data, video data, and desired system information (personal information, program guide, etc.) from the transport stream format digital signal obtained by the demodulator 102. The audio decoder 107 decodes the audio data extracted by the TS decoder 106. The video decoder 108 decodes the video data extracted by the TS decoder 106. The flash memory 104 stores a program for operating the CPU 109. The main memory 105 records the system information output from the TS decoder 106. The CPU 109 controls the entire apparatus by a program recorded in the flash memory 104. The modem 110 transmits, for example, billing fee information when a pay broadcast is viewed via a telephone line to a broadcast station or the like. Each device is connected by an interface (I2C, bus I / F) as shown in FIG.
[0025]
<Internal configuration of TS decoder 106>
Next, the internal configuration of the TS decoder 106 is shown in FIG. The TS decoder 106 includes a synchronization detection circuit 201, a PID filter circuit 202, a section detection circuit 203, a section filter circuit 204, and a data buffer 205. The synchronization detection circuit 201 acquires a packet by detecting a synchronization byte included at the head of the packet of the transport stream obtained by the demodulator 102 (see FIG. 1). The PID filter circuit 202 refers to the PID included in the packet header of the packet acquired by the synchronization detection circuit 201 and acquires a desired packet. The section detection circuit 203 detects a section from the payload portion of the packet acquired by the PID filter circuit 202. The section filter circuit 204 determines whether or not the section detected by the section detection circuit 203 is a desired section. The data buffer 205 stores sections determined to be a desired section by the section filter circuit 204. When a certain amount of sections are accumulated in the data buffer 205, the accumulated sections are output to the main memory 105 (see FIG. 1).
[0026]
<Internal Configuration of Section Filter Circuit 204>
Next, the internal configuration of the section filter circuit 204 is shown in FIG. The section filter circuit 204 includes a section buffer 301, a matching pattern RAM 302, a comparison circuit 303, a mask for matching RAM 304, a length decoder 305, a mask circuit 306, a match detection circuit 307, and a control circuit 308. The section buffer 301 stores a section header among the sections detected by the section detection circuit 203 (see FIG. 2). The matching pattern RAM 302 stores matching patterns. The comparison circuit 303 performs an EOR operation (exclusive OR operation) on a bit basis using the section header stored in the section buffer 301 and the matching pattern stored in the matching pattern RAM 302. The mask for matching RAM 304 stores data (encoded mask pattern) that is the basis of the mask pattern. The length decoder 305 converts the encoded mask pattern stored in the mask for matching RAM 304 into a mask pattern. The mask circuit 306 performs an AND operation (logical product operation) in bit units using the data (EOR operation data) obtained by the EOR operation by the comparison circuit 303 and the mask pattern converted by the length decoder 305. The coincidence detection circuit 307 checks whether the bit values of the data (AND operation data) obtained by the AND operation by the mask circuit 306 are all “0”. The data buffer 205 (see FIG. 2) stores section data including a section header for which the coincidence detection circuit 307 determines that all bit values of AND operation data are “0”. The control circuit 308 controls the matching pattern RAM 302, the mask for matching RAM 304, and the coincidence detection circuit 307.
[0027]
Next, the configuration of the transport stream (transport stream including section format data) output from the demodulation unit 102 (see FIG. 2) will be described with reference to FIG.
[0028]
<Description of transport stream>
First, an example of the bit arrangement of the transport stream is shown in FIG. The transport stream is composed of a plurality of transport stream packets (TS packets). A TS packet has a header (4 bytes) and a payload (184 bytes). The header includes a synchronization byte (8 bits), PID (13 bits), and the like. A section is stored in the payload. The section storage format includes a case where a plurality of sections are stored in one payload and a case where the sections are stored across a plurality of payloads.
[0029]
Next, an example of the bit arrangement of sections is shown in FIG. In the section, as typical data types, table id (8 bits), section length (12 bits), transport stream id (16 bits), version number (5 bits), section number (8 bits), last section number (8 bits), Byte etc. exist. In addition, a section (8 bytes = 64 bits) from table id to last section number is a section header.
[0030]
The above is the description of the structure of the transport stream including the section format.
[0031]
Next, the operation of the digital broadcast receiving apparatus according to the first embodiment configured as described above will be described.
[0032]
<Operation of Digital Broadcasting Reception Device in First Embodiment>
The operation of the digital broadcast receiving apparatus in the first embodiment includes processing until the matching pattern is stored in the matching pattern RAM 302 and the mask pattern is stored in the mask for matching RAM 304 (comparison pattern writing processing), and digital broadcasting. There is processing (section storage processing) from reception of the desired system information to the main memory 105 by the TS decoder 106.
[0033]
First, the comparison pattern writing process according to the first embodiment will be described with reference to FIG.
[0034]
<Comparison Pattern Writing Process According to First Embodiment>
[Step ST101]
First, the CPU 109 creates a matching pattern and a mask pattern in accordance with a program stored in the flash memory 104.
[0035]
Here, the matching pattern and the mask pattern will be described with reference to FIG.
[0036]
<Description of matching pattern and mask pattern>
First, an example of the bit arrangement of the matching pattern is shown in FIG. The matching pattern is used when performing EOR operation with the section header. The bit length of the matching pattern is the same as the section header (64 bits in this embodiment). In the figure, in order to facilitate understanding of the bit arrangement, a bit value (binary number) is converted into a hexadecimal value and expressed in a form stored in a block (indicating 8 bits per block). In other words, data in which 64 “0” s or “1” s are originally arranged is represented using 8 blocks each storing one 2-digit value. For example, if the value of the block is “23”, “00100011” is indicated. A mask pattern, an encoded mask pattern, and operation type information, which will be described later, will also be described using a similar notation method. However, 6 bits per block are shown in the description of the encoding mask pattern, and 5 bits per block are shown in the description of the operation type information.
[0037]
Next, FIG. 6B shows an example of the bit arrangement of the mask pattern. The mask pattern is a section (invalid section) that is not required when determining whether or not it is a desired section header among data obtained by EOR calculation using the section header and the matching pattern (EOR calculation data). It is used to extract a section (effective section) necessary for determining whether or not the section header is deleted. That is, in the mask pattern, a section having a bit value “1” indicates a valid section, and a section having a bit value “0” indicates an invalid section. The bit length of the mask pattern is the same as the matching pattern (64 bits in this embodiment).
[0038]
Further, the matching pattern and the mask pattern usually correspond one to one. One matching pattern and one mask pattern are treated as one comparison pattern.
[0039]
The above is the description of the matching pattern and the mask pattern.
[0040]
[Step ST102]
Next, the CPU 109 analyzes the bit arrangement of the created mask pattern according to the program stored in the flash memory 104. That is, the arrangement of the bit having the bit value “0” and the bit having the bit value “1” is checked.
[0041]
[Step ST103]
Next, according to the program stored in the flash memory 104, the CPU 109, in the analyzed mask pattern, the bit position (start position) where the valid section whose bit value indicates “1” starts and the bits from the start position to the end of the section Find the length (length).
[0042]
[Step ST104]
Next, the CPU 109 creates an encoding mask pattern using the start position and length of the effective section obtained in step ST103 according to the program stored in the flash memory 104.
[0043]
Here, the encoding mask pattern will be described with reference to FIG.
[0044]
<Description of coding mask pattern>
An example of the bit arrangement of the mask pattern is shown in FIG. The encoded mask pattern includes a bit position (start position) where a valid section having a bit value of “1” in the mask pattern shown in FIG. 6B starts and a bit length (from the start position to the end of the valid section) Length) in units of 6 bits. For example, when the bit value of the 0th to 7th bit sections is “1”, the start position of the valid section is “00”, and the length from the start position to the end of the valid section is “08”. The encoding mask pattern is divided in units of 6 bits, and is arranged in the order of “start position (6 bits)” and “length (6 bits)”. That is, an effective section in which the bit value indicates “1” is described by one set of one start position and one length (total 12 bits). When the 0th to 7th bits are the valid section, the actual bit arrangement of the coding mask pattern is “000000001000”.
[0045]
The above is the description of the encoding mask pattern.
[0046]
That is, the CPU 109 creates an encoding mask pattern in which one effective section is expressed in units of 12 bits (start position is 6 bits, length is 6 bits) using the start position and length of the effective section obtained in step ST103. .
[0047]
[Step ST105]
Next, the CPU 109 writes the matching pattern in the matching pattern RAM 302. Further, the CPU 109 writes the encoded mask pattern in the mask for matching RAM 304.
[0048]
As described above, the matching pattern is stored in the matching pattern RAM 302, and the encoded mask data is stored in the mask for matching RAM 304.
[0049]
Next, the section storing process according to the first embodiment will be described. In particular, processing in the section filter circuit will be described with reference to FIG.
[0050]
<Section Storage Processing According to First Embodiment>
First, a broadcast signal received via the tuner 101 (FIG. 1) is input to the demodulation unit 102.
[0051]
Next, the demodulator 102 (FIG. 1) converts the input broadcast signal into a digital signal in the transport stream format, and outputs the digital signal to the synchronization detection circuit 201 (FIG. 2) included in the TS decoder 106.
[0052]
Next, the synchronization detection circuit 201 (FIG. 2) acquires a TS packet by detecting a synchronization byte included at the beginning of the packet of the transport stream obtained by the demodulation unit 102. (See Fig. 4 (1))
Next, the PID filter circuit 202 (FIG. 2) identifies the PID (see FIG. 4 (1)) included in the header of the packet detected by the synchronization detection circuit 201 (FIG. 2). If the packet is a desired packet as a result of identification, the payload of the packet is output to the section detection circuit 203 (FIG. 2). When the PID filter circuit 202 identifies a packet storing audio data, the PID filter circuit 202 outputs the payload of the packet to the audio decoder 107 (FIG. 1), and identifies the packet storing video data. The payload of the packet is output to the video decoder 108 (FIG. 1).
[0053]
Next, the section detection circuit 203 (FIG. 2) acquires a section (see FIG. 4 (2)) from the payload output from the PID filter circuit 202, and the acquired section is used as the data buffer 205 (FIG. 2) and the section filter. The data is output to the section buffer 301 (FIG. 3) included in the circuit 204.
[0054]
Next, the section buffer 301 (FIG. 3) stores a section header (see FIG. 4 (2)) among the sections input from the section detection circuit 203.
[0055]
Next, the comparison circuit 303 (FIG. 3) performs an EOR operation (exclusive OR operation) using the section header stored in the section buffer 301 and the matching pattern stored in the matching pattern RAM 302 (FIG. 3). Performed in units (see FIG. 7). That is, in each bit, “0” is set when the bit value of the section header matches the bit value of the matching pattern, and “1” is set when they do not match.
[0056]
Next, the length recorder 305 (FIG. 3) converts the encoded mask pattern stored in the mask for matching RAM 304 (FIG. 3) into a mask pattern (see FIG. 7). That is, as shown in FIG. 7, an encoded mask pattern (36 bits) indicating the start position and length of the effective section is converted into a mask pattern (64 bits).
[0057]
Next, the mask circuit 306 (FIG. 3) performs an AND operation (logical product operation) using the data (EOR operation data) obtained by the EOR operation by the comparison circuit 303 and the mask pattern converted by the length recorder 305. This is performed in bit units (see FIG. 7). That is, for each bit, the bit value of the EOR operation data is “1” and the bit value of the mask pattern is “1”, otherwise “0”.
[0058]
Next, the coincidence detection circuit 307 (FIG. 3) checks whether or not all the bit values of the data (AND operation data) obtained by the AND operation by the mask circuit 306 are “0”. When all the bit values are “0”, this section header is determined to be a desired section header.
[0059]
Next, the data buffer 205 (see FIG. 2) is obtained by the section detection circuit 203 (see FIG. 2) when all the bit values of the AND operation data are “0” by the coincidence detection circuit 307 (FIG. 3). Saved sections. That is, the coincidence detection circuit 307 stores a section including a section header in which all bit values indicate “0”. Next, the data buffer 205 (see FIG. 2) stores a certain amount of sections and then outputs them to the main memory 105 (FIG. 1).
[0060]
Next, the main memory 105 (FIG. 1) records the section input from the data buffer 205.
[0061]
As described above, desired system information is recorded in the main memory 105.
[0062]
The control circuit 308 (FIG. 3) controls the matching pattern RAM 302, the mask for matching RAM 304, and the coincidence detection circuit 307, and a section header is compared with all the comparison patterns. That is, after processing (comparison processing) from the comparison circuit 303 to the coincidence detection circuit 307 is performed on one section header using one comparison pattern (a set of one matching pattern and one mask pattern), The comparison process is performed again using one comparison pattern. In this way, it is performed for one section header and all comparison patterns.
[0063]
<Effects of First Embodiment>
As described above, the mask for matching RAM 304 stores an encoded mask pattern (36 bits) having a bit length shorter than that of the mask pattern (64 bits). Thus, for example, as shown in FIG. 7, a 64-bit storage area is required to store the mask pattern. However, if an encoded mask pattern is used, the mask pattern can be stored in a 36-bit storage area. Can be reduced.
[0064]
Note that the matching pattern stored in the matching pattern RAM 302 and the encoded mask pattern stored in the mask for matching RAM 304 can be newly written by the CPU 109. That is, the CPU 109 can rewrite the matching pattern and the mask pattern in the middle of the process according to an instruction from the user or the like.
[0065]
The modem 110 may be installed outside the back end unit 103.
[0066]
(Second Embodiment)
As described above, the method in which the mask pattern is expressed by the start position and the length of the effective section by the encoded mask pattern is effective when the sections having the bit value “1” are continuous, but the bit value When “0” and “1” are mixed at short intervals (for example, when “0” and “1” are alternately present for each bit), there is a possibility of exceeding 64 bits.
[0067]
The digital broadcast receiving apparatus according to the second embodiment of the present invention has the same overall configuration, the internal configuration of the TS decoder 106, and the internal configuration of the section filter circuit 204 as those of the first embodiment. In the second embodiment, the mask for matching RAM 304 included in the section filter circuit 204 further stores an unencoded mask pattern in addition to the encoded mask pattern.
[0068]
Normally, the matching pattern RAM 302 stores a plurality of matching patterns, and the mask for pattern RAM 304 stores a plurality of mask patterns. That is, when determining a desired section, a plurality of comparison patterns (a set of matching patterns and mask patterns) are used. In addition, about 32 sets of comparison patterns can be set for each transport.
[0069]
The operation of the digital broadcast receiving apparatus according to the second embodiment will be described below.
[0070]
<Operation of Digital Broadcasting Reception Device According to Second Embodiment>
The operation of the digital broadcast receiving apparatus according to the second embodiment differs from the process according to the first embodiment in the process of the mask circuit 306 in the comparison pattern writing process and the section storing process. Therefore, these two processes will be described below.
[0071]
First, the comparison pattern writing process in the digital broadcast receiving apparatus according to the second embodiment will be described with reference to FIG.
[0072]
<Comparison Pattern Writing Process According to Second Embodiment>
[Steps ST101 to 104]
First, as in the first embodiment, the CPU 109 creates a matching pattern and a mask pattern.
[0073]
[Step ST201]
Next, the CPU 109 checks the bit length of the encoding mask pattern according to the program stored in the flash memory 104. If the bit length of the encoded mask pattern is shorter than the bit length of the mask pattern before conversion, the process proceeds to step ST105, and if not, the process proceeds to step ST203.
[0074]
[Step ST105]
Next, as in the first embodiment, the CPU 109 writes the matching pattern in the matching pattern RAM 302 according to the program stored in the flash memory 104. Further, the CPU 109 writes the encoding mask pattern in the mask for matching RAM 304 according to the program stored in the flash memory 104.
[0075]
[Step ST202]
On the other hand, when the bit length of the encoded mask pattern is longer than the bit length of the mask pattern before conversion in step ST201, the CPU 109 writes the matching pattern in the matching pattern RAM 302 according to the program stored in the flash memory 104. Further, the CPU 109 writes an unconverted mask pattern in the mask for matching RAM 304 in accordance with a program stored in the flash memory 104.
[0076]
An example of the mask pattern thus stored in the mask for matching RAM 304 is shown in FIG. In this example, the mask for matching RAM 304 stores 16 entries of an encoded mask pattern and 16 entries of an unencoded mask pattern. That is, in this case, 16 entries out of 32 entries stored in the mask for matching RAM 304 are mask patterns in which the reduction of the storage area by encoding cannot be expected.
[0077]
The above is the description of the comparison pattern writing process in the second embodiment.
[0078]
Next, processing in the mask circuit 306 according to the second embodiment will be described.
[0079]
<Processing in Mask Circuit 306 According to Second Embodiment>
The mask circuit 306 performs an AND operation (logical product operation) on a bit basis using the data (EOR operation data) obtained by the EOR operation by the comparison circuit 303 and the mask pattern converted by the length recorder 305. Alternatively, the mask circuit 306 performs an AND operation (logical product operation) in bit units using data (EOR operation data) obtained by the EOR operation by the comparison circuit 303 and a mask pattern stored in the mask for matching RAM 304. Do. That is, the comparison circuit 303 uses the mask pattern converted by the length decoder 305 and the mask pattern stored in the mask for matching RAM 304. Next, the data obtained by the AND operation is output to the coincidence detection circuit 307.
[0080]
<Effects of Second Embodiment>
As described above, if it is not possible to reduce the recording area even after conversion to the coded mask pattern, the mask pattern is not coded. In this way, by mixing the encoded mask pattern and the non-encoded mask pattern, it is possible to effectively use the storage area of the mask for matching RAM 304 as compared with the case where only the encoded mask pattern is used. it can.
[0081]
Note that the ratio between the number of entries in the encoded mask mask pattern and the number of entries in the mask pattern that has not been converted can be optimized according to the broadcaster and the target model.
[0082]
(Third embodiment)
Some comparison patterns constitute similar patterns. For example, there are cases such as matching patterns a301 and a302 and mask patterns b301 and b302 shown in FIG. Conventionally, even those having such a similar pattern are set one by one (one set of comparison patterns) in the matching pattern RAM 302 and the mask for matching RAM 304 one by one.
[0083]
The digital broadcast receiving apparatus according to the third embodiment of the present invention has the same overall configuration (see FIG. 1) and TS decoder 106 (see FIG. 2) as compared with the first embodiment. The internal configuration (see FIG. 3) of the section filter circuit 204 is different. The third embodiment includes a section filter circuit 214 shown in FIG. 10 instead of FIG. The section filter circuit 214 circuit shown in FIG. 10 includes an operation type decoder 401 instead of the length decoder 305. The mask for matching RAM 304 further stores operation type information in addition to the encoded mask pattern. The operation type decoder 401 creates another mask pattern using the operation type information stored in the mask for matching RAM 304 based on the mask pattern stored in the mask for matching RAM 304. The operation type information indicates a position where the OR operation is performed (the operation type information will be described later).
[0084]
The operation of the digital broadcast receiving apparatus according to the third embodiment will be described below.
[0085]
<Operation of Digital Broadcasting Receiver according to Third Embodiment>
The operation of the digital broadcast receiving apparatus according to the third embodiment differs from that according to the first embodiment in the processing in the section filter circuit 214 (see FIG. 10) in the comparison pattern writing process and the section storing process. Therefore, these two processes will be described below. In the first and second embodiments, the bit length of the section header stored in the data buffer is 64 bits, but in the third embodiment, it is 96 bits. Similarly, the matching pattern and the mask pattern are 96 bits.
[0086]
First, a comparison pattern writing process according to the third embodiment will be described with reference to FIGS. 11 and 12.
[0087]
<Comparison Pattern Writing Process According to Third Embodiment>
In the comparison pattern writing process according to the third embodiment, calculation type information is further written in addition to the matching pattern and the mask pattern.
[0088]
[Step ST301]
First, the CPU 109 creates a matching pattern and a mask pattern in accordance with a program stored in the flash memory 104. At this time, at least two patterns are created. For example, matching patterns a301 and a302 and mask patterns b301 and b302 as shown in FIG. 12 are created.
[0089]
[Step ST302]
Next, the CPU 109 analyzes the bit pattern of the matching pattern and the bit pattern of the mask pattern according to the program stored in the flash memory 104. That is, the arrangement of the bit having the bit value “0” and the bit having the bit value “1” is checked.
[0090]
[Step ST303]
Next, according to the program stored in the flash memory 104, the CPU 109 pays attention to the bit arrangement of each pattern and determines a section showing a common pattern and a section showing a different pattern in byte units. In the case of FIG. 12, the matching pattern a301 and the mask pattern b301 have effective sections A, B, C, and G, while the matching pattern a302 and the mask pattern b302 have effective sections A, B, C, and H. In this case, effective sections A, B, and C exist in both, but effective sections G and H exist in only one. Therefore, as shown in FIG. 12, a section showing a common pattern is a section in which both effective sections exist and an invalid section, and a section showing a different pattern is a section in which only one effective section exists. That is, the section showing the common pattern is the section of the 1st to 9th bytes and the section of the 11th to 12th bytes, and the section showing the different pattern is the section of the 9th to 10th and 10th to 11th bytes.
[0091]
[Step ST304]
Next, according to the program stored in the flash memory 104, the CPU 109 analyzes the position of the effective section indicated by each pattern in the section indicating a different pattern (the section where the position of the effective section is different). In the case of FIG. 12, the 9th to 10th byte sections in the mask pattern b301 are valid sections G, and the 10th to 11th byte sections are invalid sections, but the 9th to 10th byte sections in the mask pattern b302. The valid section H is the invalid section and the 10th to 11th bytes.
[0092]
[Step ST305]
Next, in accordance with the program stored in the flash memory 104, the CPU 109 creates a comprehensive matching pattern and a comprehensive mask pattern that include all valid sections in a section showing a different pattern. That is, with respect to the comprehensive matching pattern and the comprehensive mask pattern, a bit value indicated by any one of all patterns is set in a section indicating a common pattern, and at least one of all patterns is set in a section indicating a different pattern. A bit value indicated by an effective section included in one pattern is set. In the case of FIG. 12, the comprehensive matching pattern a3001 and the comprehensive mask pattern b3001 include valid sections A, B, C, G, and H.
[0093]
[Step ST306]
Next, the CPU 109 creates calculation type information using the result of determination in step ST303 according to the program stored in the flash memory 104.
[0094]
Here, the calculation type information will be described.
[0095]
<Explanation of calculation type information>
The operation type information indicates the byte position where the OR operation is performed. The OR operation is a 1-byte section before and after the 1-byte section before and after the byte position indicated in the operation type information (2-byte section centered on the byte position indicated by the operation type information). It refers to the process of selecting one of them. In the case of FIG. 12, the calculation type information c3001 indicates a process of selecting one of the valid section G and the valid section H. In the case of FIG. 12, one value indicating the byte position where the OR operation is performed is stored for one block (5 bits per block).
[0096]
[Step ST307]
Next, the CPU 109 writes the matching pattern in the matching pattern RAM 302 according to the program stored in the flash memory 104. In addition, the CPU 109 writes the encoding mask pattern and calculation type information in the mask for matching RAM 304.
[0097]
The above is the description of the comparison pattern writing process in the third embodiment.
[0098]
Next, processing in the section filter circuit 214 according to the third embodiment will be described.
[0099]
<Processing in Section Filter Circuit 214 According to Third Embodiment>
The processing in the section filter circuit 214 according to the third embodiment is different from that according to the first embodiment in the processing by the mask circuit 306. The mask circuit 306 performs an AND operation as described above using the mask pattern output from the operation type decoder 401. Therefore, the processing in the operation type decoder 401 will be described below with reference to FIGS. 13 and 14.
[0100]
<Processing in Operation Type Decoder 401>
[Step ST311]
First, the comprehensive mask pattern stored in the mask for matching RAM 304 is input to the operation type decoder 401. For example, a comprehensive mask pattern b3001 as shown in FIG. 14 is input.
[0101]
[Step ST312]
Next, the operation type decoder 401 acquires the operation type information stored in the mask for matching RAM 304. For example, calculation type information c3001 as shown in FIG. 14 is acquired.
[0102]
[Step ST313]
Next, the calculation type decoder 401 analyzes the acquired calculation type information. That is, the OR operation stored in the operation type information and the byte position where the operation is performed are examined. In the case of FIG. 14, the calculation type information c3001 indicates that the calculation is performed at the 10th byte, and therefore the section in which the calculation is performed is indicated as the 9th to 11th bytes. The operation type information c3001 indicates that an OR operation is performed on 1 byte before and after the 10th byte.
[0103]
[Step ST314]
Next, the operation type decoder 401 selects an effective section from the comprehensive mask pattern according to the operation obtained by analyzing the operation type information. In the case of FIG. 14, using the result of analyzing the calculation type information c3001, there are a case where the 9th to 10th byte effective section G is selected and a case where the 10th to 11th byte effective section H is selected.
[0104]
[Step ST315]
Next, the operation type decoder 401 creates a mask pattern in which all bit values are set to “0” for the operation interval other than the effective interval selected in step ST314 in the comprehensive mask pattern. Thus, the original mask pattern is restored based on the comprehensive mask pattern according to the calculation. The restored mask pattern corresponds to the comprehensive matching pattern. In the case of FIG. 14, two selection methods are obtained in the process in step ST <b> 314, that is, when the effective section G is selected and when the effective section H is selected. Accordingly, the mask value b301 in which the bit value of the 10th to 11th bytes of the comprehensive mask pattern b3001 is set to “0”, and the bit value of the 9th to 10th bytes of the comprehensive mask pattern b3001 are “ A mask pattern b302 set to “0” is created. The created mask patterns b301 and b302 correspond to the comprehensive matching pattern a3001, and the comprehensive matching pattern a3001 and the mask pattern b301 constitute one comparison pattern, and the comprehensive matching pattern a3001 and the mask pattern b302 are 1 Configure one comparison pattern.
[0105]
[Step ST316]
Next, the operation type decoder 401 outputs the restored mask pattern to the mask circuit 306. In the case of FIG. 14, the mask patterns b301 and b302 are output to the mask circuit 306.
In this way, the mask patterns b301 and b302 are restored based on the comprehensive mask pattern b3001.
[0106]
The above is the description of the processing in the section filter circuit 214 according to the third embodiment.
[0107]
<Effects of Third Embodiment>
As described above, the operation type decoder 401 restores the original mask pattern using the operation type information stored in the mask for matching RAM 304. Thereby, compared with the case where a matching pattern and a mask pattern are created and stored in the matching pattern RAM 302 and the mask for matching RAM 304 as they are, the area required for storing the matching pattern and the mask pattern can be reduced.
[0108]
(Fourth embodiment)
The overall configuration of the digital broadcast receiver according to the fourth embodiment of the present invention is the same as that of the digital broadcast receiver according to the third embodiment (see FIGS. 1, 2 and 10), but the operation type information is different. Therefore, the calculation type information in the fourth embodiment will be described below.
[0109]
<Description of Calculation Type Information in Fourth Embodiment>
The operation type information in the fourth embodiment indicates an OR operation position, an AND operation position, and a section (calculation section) in which the operation is performed.
[0110]
The OR operation indicates a process of selecting one of a section existing ahead and a section existing rearward before and after the byte position indicated in the operation type information.
[0111]
The AND operation refers to a process of simultaneously selecting two sections existing ahead and behind the byte positions indicated in the operation type information. The AND operation is performed with priority over the OR operation.
[0112]
The calculation interval is indicated by “(” and “)”. That is, it refers to a section from the byte position indicated by “(” to the byte position indicated by “)” by the calculation type information. Calculations within the calculation interval are performed with priority over calculations outside the calculation interval.
[0113]
Further, the calculation type information stores one calculation value in one block (one block of 5 bits). In order to distinguish the type of operation, the value indicating the byte position where the OR operation is performed is indicated by the high-order bit “0”, and the start position “(” or the end of the operation section ”)” of the operation section is indicated. The value indicating the byte position to be set is indicated by “1” in the upper bits. Furthermore, the byte position that is not indicated by the value stored in the calculation type information in the interval in which the calculation is performed is the position where the AND calculation is performed. In addition, when an AND operation is performed between calculation intervals, a value indicating the calculation interval is stored in duplicate in two blocks (see calculation type information c4011 shown in FIG. 17).
[0114]
In a section in which no calculation section is set, the calculation section is one byte after the byte position one byte before the first byte position indicated by the calculation type information and the last byte position indicated by the calculation type information. This is the interval up to the bit position. For example, in the case of FIG. 15, since the first byte position indicated by the calculation type information c4001 is “09”, that is, the ninth byte, the start position of the section in which the calculation is performed is the eighth byte. Further, since the rearmost byte position indicated by the operation type information c4001 is “0B”, that is, the 11th byte, the end position of the section in which the operation is performed is the 12th byte.
[0115]
The above is the description of the calculation type information in the fourth embodiment.
[0116]
Next, the operation of the digital broadcast receiver according to the fourth embodiment will be described.
[0117]
<Description of Operation of Digital Broadcasting Reception Device according to Fourth Embodiment>
The operation of the digital broadcast receiving apparatus according to the fourth embodiment is the same as that according to the third embodiment, but the created operation type information is different. Therefore, processing related to the operation type information (comparison pattern writing processing and operation in the operation type decoder 401) will be described below.
[0118]
First, a comparison pattern writing process according to the fourth embodiment will be described with reference to FIGS. 11 and 15.
[0119]
<Comparison Pattern Writing Process According to Fourth Embodiment>
[Steps ST301 and 302]
First, processing similar to that of the third embodiment is performed, and matching patterns a401, a402, and a403 and mask patterns b401, b402, and b403 as shown in FIG. 15 are created and the bit arrangement is analyzed.
[0120]
[Step ST303]
Next, processing similar to that of the third embodiment is performed, and a section showing a common pattern and a section showing a different pattern are determined. In the case of FIG. 15, the section showing the common pattern is the 1st to 8th byte section, and the section showing the different pattern is the 8th to 12th byte section.
[0121]
[Step ST304]
Next, the same processing as in the third embodiment is performed, and the position of the effective section indicated by each pattern is analyzed in the section indicating a different pattern (the section where the position of the effective section existing in each pattern is different). In the case of FIG. 15, the 8th to 9th byte sections in the mask pattern b401 are valid sections G and the 9th to 12th byte sections are invalid sections, and the 9th to 11th byte sections in the mask pattern b402 are valid sections. The 8th to 9th and 11th to 12th byte sections are invalid sections, the 11th to 12th byte sections in the mask pattern b403 are valid sections, and the 8th to 11th byte sections are invalid sections.
[0122]
[Step ST305]
Next, processing similar to that of the third embodiment is performed, and a comprehensive matching pattern a4001 and a comprehensive mask pattern b4001 as shown in FIG. 15 are created.
[0123]
[Step ST306]
Next, processing similar to that of the third embodiment is performed to create calculation type information. In the case of FIG. 15, there are a case where only the effective section G exists in a section showing a different pattern, a case where only the effective sections H and I exist, and a case where only the effective range J exists. Therefore, the operation indicated as (effective section G) or (effective section H, I) or (effective section J) must be stored in the operation type information c4001. In other words, the byte position where the AND operation is performed is indicated as the 10th byte, and the byte position where the OR operation is performed is indicated as the 9th byte (between the valid intervals G and H) and the 11th byte (between the valid intervals I and J). Information is needed. Therefore, as shown in FIG. 15, “09” and “0B” are stored in each block of the operation type information c4001.
[0124]
[Step ST307]
Next, the same processing as in the third embodiment is performed, and the created comprehensive matching pattern is written in the matching pattern RAM 302, and the comprehensive mask pattern and operation type information are written in the mask for matching RAM 304. In the case of FIG. 15, the comprehensive matching pattern a4001 is written in the matching pattern RAM 302, and the comprehensive mask pattern b4001 and the operation type information c4001 are written in the mask for matching RAM304.
[0125]
The above is the description of the comparison pattern writing process.
[0126]
Next, processing in the operation type decoder 401 according to the fourth embodiment will be described with reference to FIGS. 13 and 16.
[0127]
<Operation of Operation Type Decoder 401>
[Steps ST311, 312]
First, as in the third embodiment, a comprehensive mask pattern b4001 and calculation type information c4001 as shown in FIG. 16 are input.
[0128]
[Step ST313]
Next, the calculation type information is analyzed as in the third embodiment. Here, the calculation interval and the content of the calculation are examined. In the case of FIG. 16, the operation type information c4001 indicates that the operation is performed on the ninth byte and the eleventh byte. Therefore, the calculation interval is the 8th to 12th byte interval. The operation type information c4001 indicates that an OR operation is performed at the 9th and 11th bytes and an AND operation is performed at the 10th byte.
[0129]
[Step ST314]
Next, as in the third embodiment, an effective section existing in the calculation section is selected from the comprehensive mask pattern. In the case of FIG. 16, using the result of analyzing the calculation type information c4001, when selecting the valid section G of the 8th to 9th bytes, when selecting the valid sections H and I of the 9th to 11th bytes, In some cases, the valid section J of the ˜12th byte is selected.
[0130]
[Step ST315]
Next, as in the third embodiment, a mask pattern in which all bit positions are set to “0” is created for the calculation section other than the valid section selected in step ST314 in the comprehensive mask pattern. In the case of FIG. 16, in the process in step ST314, three selection methods are obtained, that is, the case where the valid section G is selected, the case where the valid sections H and I are selected, and the case where the valid section J is selected. Accordingly, the mask pattern in which the bit value indicated by the valid section G is set for the 8th to 9th bytes in the calculation section of the comprehensive mask pattern b4001, and the bit value in the 10th to 11th bytes is set to “0”. b401 and the bit values indicated by the valid sections H and I are set for the 9th to 11th byte sections in the calculation section of the comprehensive mask pattern b3001, and the bit values of the 8th to 9th and 11th to 12th byte sections are set. The bit value indicated by the effective section J is set for the 11th to 12th bytes in the calculation section of the set mask pattern b402 set to “0” and the comprehensive mask pattern b4001, and the bits in the 8th to 11th bytes A mask pattern b403 having a value set to “0” is created.
[0131]
[Step ST316]
Next, the restored mask pattern is output to the mask circuit 306 as in the third embodiment. In the case of FIG. 16, mask patterns b 401, b 402, and b 403 are output to the mask circuit 306.
[0132]
The above is the processing in the section filter circuit 214 according to the fourth embodiment.
[0133]
Further, another example of the above-described processing will be described with reference to FIGS. 17 and 18. Here, only the data change will be described, and the description of the operation by the digital broadcast receiving apparatus will be omitted.
[0134]
First, data change associated with the comparison pattern writing process according to the fourth embodiment will be described with reference to FIG.
[0135]
<Comparison Pattern Writing Process According to Fourth Embodiment>
First, matching patterns a411, a412, a413, a414 and mask patterns b411, b412, b413, b414 are created.
[0136]
Next, a section showing a different pattern is a section of the 8th to 12th bytes. In the mask pattern b411, the 8th to 9th and 10th to 11th bytes are the valid sections G and I, the 8th to 9th and 11th to 12th bytes in the mask pattern b412 are the valid sections G and J, and the 9th to 9th in the mask pattern b413. The 11th byte is the valid sections H and I, and the 9th to 10th and 11th to 12th bytes are the valid sections H and J in the mask pattern b414.
[0137]
Next, a comprehensive pattern a 4011 and a comprehensive mask pattern b 4011 including all the valid sections G, H, I, and J are created.
[0138]
When attention is paid to the effective sections G and H, either mask pattern (effective section G or H) is included in any mask pattern. If attention is paid to the valid sections I and J, either one (the valid section I or J) is similarly included. In other words, the calculation type information c4011 is calculated such that any one of the valid sections G or H is included in the section of the 8th to 10th bytes, and any one of the effective sections I or J is included in the section of the 10th to 12th bytes. Must be stored in Therefore, “88” is set in the operation type information c4011, in order to indicate that the eighth byte is the start point of the operation section, and “09” in order to indicate that the ninth byte is the byte position where the OR operation is performed. And “8A” is set to indicate that the 10th byte is the end of the computation interval. Furthermore, “8A” is set to indicate that the 10th byte is the start point of another calculation section, and “0B” is set to indicate that the 11th byte is a byte position where an OR operation is performed. , “8C” is set to indicate that the 12th byte is the end of the computation interval.
[0139]
Next, the created comprehensive matching pattern a 4011 is stored in the matching pattern RAM 302, and the created comprehensive mask pattern b 4011 and the operation type information c 4011 are stored in the mask for matching RAM 304.
[0140]
The above is the description of the data change accompanying the comparison pattern writing process.
[0141]
Next, changes in data accompanying processing in the operation type decoder 401 will be described with reference to FIG.
[0142]
<Processing in Operation Type Decoder 401 According to Fourth Embodiment>
First, the comprehensive mask pattern b 4011 and the operation type information c 4011 are input to the operation type decoder 401.
[0143]
Next, the calculation type information c4011 is analyzed, and the calculation interval and the content of the calculation are examined. Since the operation type information c4011 stores “88”, “8A”, “8A”, and “8C”, the operation sections are the 8th to 10th byte sections and the 10th to 12th byte sections. . Since the operation type information c4011 stores “09” and “0B”, an OR operation is performed on the 9th byte and an OR operation is performed on the 11th byte.
[0144]
Next, an effective section existing in the calculation section is selected from the comprehensive mask pattern b4011. According to the result of analyzing the calculation type information c4011, when the valid sections G and I are selected, the valid sections G and J are selected, the valid sections H and I are selected, and the valid sections H and J are selected. May be selected.
[0145]
Next, in accordance with the selection method described above, the mask pattern b411 in which all bit values of the calculation sections (sections 8 to 12 bytes) other than the sections G and I are included in the comprehensive mask pattern b4011, and the comprehensive mask The mask pattern b412 in which all the bit values of the calculation sections other than the sections G and J in the pattern are set to “0”, and the bit values of the calculation sections other than the sections H and I in the comprehensive mask pattern are all set to “0”. The mask pattern b413 and the mask pattern b414 in which all the bit values of the calculation sections other than the sections H and J in the comprehensive mask pattern are set to “0” are created.
[0146]
Next, the created mask patterns b411, b412, b413, b414 are output to the mask circuit 306.
[0147]
This completes the description of the data change accompanying the processing in the operation type decoder 401.
[0148]
Next, another example of the above-described processing will be described with reference to FIG. Here, only the data change associated with the comparison pattern writing process will be described with reference to FIG. 19, and the description of the operation by the digital broadcast receiving apparatus will be omitted.
[0149]
<Comparison pattern writing process>
First, matching patterns a421, a422, a423, a424 and mask patterns b421, b422, b423, b424 are created.
[0150]
Next, a section showing a different pattern is a section of the 8th to 12th bytes. In the mask pattern b421, the 8th to 9th bytes are the valid section G, in the mask pattern b422, the 9th to 10th bytes are the valid section H, and in the mask pattern b423, the 10th to 11th bytes are the valid section I. In b424, the 11th to 12th bytes are the valid section J.
[0151]
Next, a comprehensive matching pattern a 4021 and a comprehensive mask pattern b 4021 including all the valid sections G, H, I, and J are created as shown in FIG.
[0152]
Next, calculation type information is created. In sections showing different patterns, there are cases where only the valid section G exists, only the valid section H exists, only the valid section I exists, and only the valid section J exists. Therefore, an operation indicated as (effective section G) or (effective section H) or (effective section I) or (effective section J) must be stored in the operation type information. In other words, information indicating the byte position for performing the OR operation as the ninth, tenth, and eleventh bytes (between the valid intervals G, H, I, and J) is required. Therefore, as shown in FIG. 19, “09”, “0A”, and “0B” are stored in each block of the operation type information c4021.
[0153]
Next, the created comprehensive matching pattern a 4021 is stored in the matching RAM 302, and the created comprehensive mask pattern b 4021 and operation type information c 4021 are stored in the mask for matching RAM 304.
[0154]
The above is the description about the data change accompanying the comparison pattern writing process.
[0155]
<Effects of Fourth Embodiment>
As described above, the operation type information indicates the OR operation, the AND operation, and the priority order of the operations. The operation type decoder 401 can indicate more operations than the third embodiment by using these operations and the priority order. Therefore, a variety of mask patterns can be restored in the operational decoder than in the third embodiment. As a result, the capacity for storing the mask pattern can be reduced as compared with the case where all the required number of mask patterns are stored, and more types of mask patterns than when only the OR operation is stored in the operation type information. Can be restored.
[0156]
【The invention's effect】
In the section filter circuit according to the present invention, the encoded mask pattern indicates a bit position where an effective section (section to be judged by the comparison circuit) exists in the mask pattern. For example, in a 64-bit mask pattern, when it is indicated that a valid section exists in the section 18 to 28 bits from the beginning, the coding mask pattern sets the start position of the valid section to “010010” (= 18) and The bit length of the valid section is “001010” (= 10), and has a 12-bit bit array indicating “010010001010”. The mask pattern creation circuit creates a 64 bit mask pattern from the 12 bit coded mask pattern. Next, the comparison circuit determines whether or not the section (for example, 64 bits) extracted from the transport stream matches the matching pattern (for example, 64 bits) stored in the matching pattern storage circuit in the valid section indicated by the mask pattern. Judge by unit. Thereby, the area for storing (storing) the mask pattern can be reduced.
[0157]
In another section filter circuit according to the present invention, an operation is performed on the valid section indicated by the operation type information in the comparison result data obtained by the comparison circuit. For example, an operation may be considered in which if a section matches the matching pattern in at least one of the three effective sections, the section is determined to match the matching pattern. In this case, the comparison circuit performs comparison using three mask patterns. Accordingly, a plurality of mask patterns can be created from one mask pattern by using the operation type information, and an area necessary for storing the mask pattern can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a digital broadcast receiving apparatus according to a first embodiment of the present invention.
2 is a block diagram showing an internal configuration of the TS decoder shown in FIG. 1. FIG.
3 is a block diagram showing an internal configuration of a section filter circuit shown in FIG. 2. FIG.
FIG. 4 is a diagram illustrating an example of a transport stream including section format data.
FIG. 5 is a flowchart showing comparison pattern writing processing by the digital broadcast receiving apparatus shown in FIG. 1;
FIG. 6 is a diagram illustrating an example of a matching pattern, a mask pattern, and an encoded mask pattern.
7 is a diagram illustrating an example of data change associated with section storage processing by the digital broadcast receiving apparatus illustrated in FIG. 1;
FIG. 8 is a flowchart showing a comparison pattern writing process in the digital broadcast receiving apparatus according to the second embodiment of the present invention.
FIG. 9 is a diagram illustrating an example of a mask pattern and an encoded mask pattern stored in a mask for matching RAM according to the second embodiment.
FIG. 10 is a block diagram showing an internal configuration of a section filter circuit according to a third embodiment of the present invention.
FIG. 11 is a flowchart showing a comparison pattern writing process in the digital broadcast receiving apparatus according to the third embodiment of the present invention.
12 is a diagram showing an example of data change associated with the comparison pattern writing process shown in FIG.
FIG. 13 is a flowchart showing a process in an operation type decoder according to a third embodiment of the present invention.
14 is a diagram showing an example of a change in data accompanying processing in the operation type decoder shown in FIG.
FIG. 15 is a diagram showing an example of data change associated with a comparison pattern writing process in the digital broadcast receiving apparatus according to the fourth embodiment of the present invention;
FIG. 16 is a diagram showing an example of a change in data accompanying a process in an operation type decoder according to the fourth embodiment of the present invention.
FIG. 17 is a diagram showing an example of data change associated with a comparison pattern writing process in the digital broadcast receiving apparatus according to the fourth embodiment of the present invention;
FIG. 18 is a diagram showing another example of data change accompanying processing in the arithmetic type decoder according to the fourth embodiment of the present invention;
FIG. 19 is a diagram showing still another example of a change in data associated with a comparison pattern writing process in the digital broadcast receiving apparatus according to the fourth embodiment of the present invention.
[Explanation of symbols]
101 tuner
102 Demodulator
103 Backend section
104 flash memory
105 Main memory
106 TS decoder
107 audio decoder
108 Video decoder
109 CPU
110 Modem
201 Synchronization detection circuit
202 PID filter
203 section detection circuit
204, 214 Section filter circuit
205 Data buffer
301 Section buffer
302 Matching pattern RAM
303 Comparison circuit
304 Mask for matching RAM
305 length decoder
306 Mask circuit
307 Match detection circuit
308 Control circuit
401 Operation type decoder

Claims (7)

A matching pattern storage circuit for storing a matching pattern having a predetermined bit arrangement;
A mask pattern storage circuit for storing an encoded mask pattern encoded in a predetermined bit array;
A mask pattern conversion circuit for converting an encoded mask pattern stored in the mask pattern storage circuit into a mask pattern;
In a valid section indicated by the mask pattern converted by the mask pattern conversion circuit, a determination is made on a bit basis as to whether or not the section extracted from the transport stream matches the matching pattern stored in the matching pattern storage circuit. A comparison circuit,
The mask pattern is
Having the same bit length as the matching pattern;
The valid section in which the comparison circuit should make a judgment and the invalid section in which the comparison circuit should not make a judgment are shown in bit units,
The encoding mask pattern is
A section filter circuit characterized by indicating a bit position where the valid section exists in the mask pattern. In claim 1,
The mask pattern storage circuit further stores the mask pattern,
The comparison circuit is
A section extracted from the transport stream is stored in the matching pattern storage circuit in an effective section indicated by one of the mask pattern converted by the mask pattern conversion circuit and the mask pattern stored in the mask pattern storage circuit. A section filter circuit characterized in that a determination is made on a bit-by-bit basis as to whether or not the matching pattern matches. A transport stream processing apparatus comprising the section filter circuit according to claim 1,
A packet acquisition circuit for acquiring a packet including a desired section from the transport stream;
A section acquisition circuit for acquiring the section from the packet acquired by the packet acquisition circuit and outputting the section to the section filter circuit; and a data buffer for storing the section determined to match a matching pattern by the section filter circuit. A transport stream processing apparatus. A digital broadcast receiving device comprising the transport stream processing device according to claim 3,
A first memory for storing a specific program;
A CPU for creating the matching pattern and the coding mask pattern according to a program stored in the first memory,
The specific program is:
A program for causing the CPU to create the matching pattern and the coding mask pattern;
The matching pattern storage circuit includes:
Storing the matching pattern created by the CPU;
The mask pattern storage circuit includes:
Storing an encoding mask pattern created by the CPU;
The digital broadcast receiving device further receives a transport stream and outputs the transport stream to the transport stream processing device;
A digital broadcast receiving apparatus, comprising: a second memory for recording section data stored in the transport stream processing apparatus. A matching pattern storage circuit for storing a matching pattern having a predetermined bit arrangement;
A mask pattern storage circuit for storing a mask pattern having the same bit length as the mask pattern;
In the effective section indicated by the mask pattern stored in the mask pattern storage circuit, the section extracted from the transport stream and the matching pattern stored in the matching pattern storage circuit are compared bit by bit, and the result of the comparison A comparison circuit that determines whether or not the section matches the matching pattern by performing the calculation indicated by the calculation type information on the section indicated by the calculation type information in the obtained data (comparison result data). With
The mask pattern is
The valid section in which the comparison circuit should make a judgment and the invalid section in which the comparison circuit should not make a judgment are shown in bit units,
The calculation type information is
A section filter circuit characterized by showing an effective section to be calculated in the comparison result data and a content of calculation performed on the effective section. A transport stream processing apparatus comprising the section filter circuit according to claim 5,
A packet acquisition circuit for acquiring a packet including desired section data from the transport stream;
A section acquisition circuit that acquires the section data from the packet acquired by the packet acquisition circuit and outputs the section data to the section filter circuit;
A transport stream processing apparatus comprising: a data buffer for storing sections determined to be matched by the section filter circuit. A digital broadcast receiver comprising the transport stream processing device according to claim 6,
A first memory for storing a specific program;
A CPU for creating the matching pattern, the coding mask pattern, and the calculation type information according to a program stored in the first memory;
The specific program is:
A program for causing the CPU to create the matching pattern, the coding mask pattern, and the operation type information;
The matching pattern storage circuit includes:
Storing the matching pattern created by the CPU;
The mask pattern storage circuit includes:
Storing an encoding mask pattern created by the CPU;
The comparison circuit is
In a section indicated by the mask pattern stored in the mask pattern storage circuit, the section extracted from the transport stream and the matching pattern stored in the matching pattern storage circuit are compared bit by bit, and the result of the comparison is obtained. Whether or not the matching pattern and the section data match by performing the calculation indicated by the calculation type information on the section indicated by the calculation type information created by the CPU in the obtained data (comparison result data) Judgment
The digital broadcast receiving device further receives a transport stream and outputs the transport stream to the transport stream processing device;
A digital broadcast receiving apparatus, comprising: a second memory for recording section data stored in the transport stream processing apparatus.

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