JP2005025733A5 - - Google Patents

Claims (9)

  A memory controller that controls access to a flash memory in which stored data is erased in units of physical blocks,
  A buffer for holding data to be written to the flash memory or data read from the flash memory;
  A host interface for controlling the buffer so that it can be randomly accessed in a unit of access in the memory address space of the host system,
  The correspondence between the logical address managed on the host system side and the physical address in the flash memory is managed in units of 512 bytes to transfer data from the buffer to the flash memory or from the flash memory to the buffer. With a flash memory interface that controls the data transfer of
  A flash memory controller, wherein a memory address of an area having the same capacity as the buffer in the memory address space of the host system is assigned to the buffer.   The flash memory controller according to claim 1, wherein the buffer has a capacity of 512 bytes.   2. The flash memory controller according to claim 1, wherein a capacity of the buffer is equal to a capacity of one page constituting the physical block.   An address register to which an address included in a memory address space or an I / O address space of the host system is assigned;
  The physical address in the flash memory serving as a transfer destination or transfer source of data transfer controlled by the flash memory interface is specified based on address information set in the address register by the host system. The flash memory controller according to any one of claims 1 to 3.   5. A flash memory system comprising: the memory controller according to claim 1; and a flash memory in which stored data is erased in units of physical blocks.   A flash memory control method for controlling access to a flash memory in which stored data is erased in units of physical blocks,
  The correspondence between the logical address managed on the host system side and the physical address in the flash memory is managed in units of 512 bytes, and data to be written to the flash memory or data read from the flash memory is held. A transfer step for controlling data transfer from the buffer to the flash memory or data transfer from the flash memory to the buffer; and
  A random access step for controlling the buffer so that the buffer can be randomly accessed in an access unit in the memory address space of the host system
  A flash memory control method, wherein a memory address of an area having the same capacity as the buffer in the memory address space of the host system is assigned to the buffer.   7. The flash memory control method according to claim 6, wherein the capacity of the buffer is 512 bytes.   7. The flash memory control method according to claim 6, wherein a capacity of the buffer is equal to a capacity of one page constituting the physical block.   An address information reading step of reading address information set by the host system from an address register to which an address included in the memory address space or I / O address space of the host system is assigned;
  The physical address in the flash memory serving as a transfer destination or transfer source of data transfer controlled in the transfer step is specified based on address information set in the address register by the host system. The method for controlling a flash memory according to claim 6.