JP2005018942A - Integrated circuit with associative memory function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit having an associative memory function in which load imposed on a control section is reduced. <P>SOLUTION: A retrieval payload data shift section 9 is provided with n latches LT1 to LTn (where n≥2). Each of the latches stores one byte latch data. The retrieval payload data shift section 9 obtains n byte length retrieval payload data DP while shifting payload data inputted from an input terminal P1 in one byte unit. Data related to the retrieval payload data DP are given to a CAM array 11 as retrieval objective data DS. When entry data DE of the CAM array 11 and the retrieval objective data DS are agreed with each other, a hit signal hit instructing an agreement is outputted from the CAM array 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit with an associative memory function, which incorporates an associative memory such as a CAM (Content-Addressable Memory).
[0002]
[Prior art]
In a router in a network, an associative memory called a CAM is generally used as a routing table that describes a MAC (Media Access Control) address. CAM is disclosed in Patent Document 1, for example. A high-speed search is enabled by a search operation unique to CAM.
[0003]
[Patent Document 1]
US Pat. No. 6,542,391
[0004]
[Problems to be solved by the invention]
However, since the CAM is merely a memory having a function of detecting whether or not there is an object to be searched at high speed, most processing in the router is NPU (Network Processor Unit: Network Processor), ASIC (Application Specific Integrated Circuit). ) Etc., and the control occupancy rate is extremely large and the control unit is overloaded, so queuing processing considering the priority level, packet logging and creation of statistics, etc. There is a problem that the performance of processing executed by a control unit such as accounting processing that is processing is adversely affected.
[0005]
The present invention has been made to solve the above problems, and an object thereof is to obtain an integrated circuit with an associative memory function capable of reducing a load applied to a control unit such as an NPU or an ASIC.
[0006]
[Means for Solving the Problems]
An integrated circuit with an associative memory function according to claim 1 of the present invention receives input data including payload data, captures the payload data in predetermined bit units, and shifts the predetermined bits × predetermined bits A payload data shift unit that obtains search payload data consisting of a length, stores at least one entry data, and compares search target data that is data related to the search payload data with the at least one entry data And an associative memory unit that outputs a comparison result signal indicating whether or not there is a match.
[0007]
An integrated circuit with an associative memory function according to a fourth aspect of the present invention is an associative memory unit capable of storing input data as entry data having a predetermined length, and the entry data is divided into a plurality of divided data, and the plurality of divided data A checksum calculation unit for obtaining a checksum calculation result of the data; and a selector capable of selectively outputting one of the entry data and the checksum calculation result.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
<Embodiment 1>
(principle)
The payload data corresponding to the information storage portion in the packet data corresponds to data in the application layer whose network layer is the fourth layer or higher, and this payload data may include a character string to be detected by a firewall or the like. It is important to find this character string as soon as possible and prohibit the passage of packets. However, conventionally, IDS (Intrusion Detection System) functions such as firewalls have been handled by control units such as NPUs and ASICs, and signature matching search that searches for character strings to be detected from all payload data It was a great load for the control unit. In the first embodiment, the IDS function is provided in an integrated circuit with an associative memory function.
[0009]
FIG. 1 is a block diagram schematically showing the concept of an integrated circuit with an associative memory function according to the first embodiment of the present invention.
[0010]
As shown in the figure, characters A, B, C, D,... Each represented by 1 byte (8 bits) are serially input to the input terminal P1 in units of 1 byte, and 1 character is input to the latch unit 21. It is latched every time.
[0011]
The search payload data shift unit 19 has four latch units 19a to 19d each capable of storing 1-byte latch data. The latch units 19a to 19d perform a shift operation in which the latch unit 19a takes in the latch data of the latch unit 21 and the latch units 19b to 19d take in the latch data of the latch units 19a to 19c in synchronization with a clock (not shown). . The 4-byte data (1 byte (= 8 bits) (predetermined bit) × 4 (predetermined length)) latched in the latch units 19a to 19d in the search payload data shift unit 19 becomes the search payload data DP. .
[0012]
On the other hand, the CAM array 11 can store a plurality of entry data DE of at least 4 bytes. In this example, it is assumed that the entry data DEx, which is one of the entry data DE, is a character string “EFGH”.
[0013]
As shown in FIG. 1, when payload data is input in the order of A, B, C, D, E, F, G, H... To the input terminal P1, the time when the character “A” is latched by the latch unit 19d. At t0, the search payload data DP becomes the character string “ABCD”. Thereafter, when the time t1 to t6 elapses in synchronization with the clock, the search payload data DP becomes “EFGH” at the time t4 and coincides with the entry data DEx (HIT). In the first embodiment, the matching information is included in the comparison result signal result and output to the outside so that the integrated circuit with an associative memory function itself has a signature matching search function.
[0014]
(Constitution)
FIG. 2 is a block diagram showing a configuration of an integrated circuit with built-in CAM which is an integrated circuit with an associative memory function according to the first embodiment. As shown in the figure, all or a part of header data D11 corresponding to the header portion in the packet data is transmitted through the input terminal P1 that can be input in units of 1 byte, respectively, for the first header portion 17 and the second header portion 18 respectively. Stored in For example, the first header portion 17 stores the second to fourth layer header data of the network layer, and the second header portion 18 stores the second layer header data.
[0015]
Further, via the input terminal P1, payload data D12 corresponding to the payload portion (user information portion) in the packet data is sent to the latch unit 21, and offset data D13 indicating the shift status of the payload data D12 is sent to the offset information output unit 20, respectively. Given. Further, setting data D14 from the input terminal P1 to the mask register 14 is given as necessary.
[0016]
FIG. 3 is an explanatory diagram showing the relationship between the CAM built-in integrated circuit 10 and the ASIC 1. As shown in the figure, the ASIC 1 receives the packet data D1, classifies the header data D11 and the payload data D12 from the packet data D1, and all or part of the header data D11 is classified into the first header portion 17 and the second header portion 18. The payload data D12 is given to the latch unit 21 in the preceding stage of the search payload data shift unit 9.
[0017]
Further, the ASIC 1 outputs a control signal SC (including the operation code OP.code) for controlling the operation of the CAM built-in integrated circuit 10 and is incremented by 1 from the initial value “0” in synchronization with the input of one character of the payload data D12. Then, the offset data D13 is output to the offset information output unit 20. Further, setting data D14 for data setting of the mask register 14 is given as necessary.
[0018]
On the other hand, the CAM built-in integrated circuit 10 outputs to the ASIC 1 a comparison result signal result including a hit signal hit indicating information on matching / mismatching with entry data in the CAM array 11 and an offset signal offset indicating a shift state at that time. . Although ASIC1 is shown in FIG. 3, the above-described operation of ASIC1 may be performed by an NPU that is another control unit.
[0019]
In FIG. 2, the first header data DH11 and the second header data DH12 output from the first header portion 17 and the second header portion 18 are taken into the selector 16, and the selector 16 selects one of the header data DH11 and DH12. Is output as header data DH. The selection content of the selector 16 is the operation code OP. Included in the control signal SC from the ASIC 1. controlled by code.
[0020]
The search payload data shift unit 9 has n latch units LT1 to LTn (n ≧ 2) each capable of storing 1-byte latch data.
[0021]
The latch units LT1 to LTn receive the latch data stored in the latch unit 21 in synchronization with a clock CLK obtained from the outside, and the latch data of the latch units LT1 to LT (n−1) is latched by the latch unit LT1. The shift operation that LT2 to LTn respectively capture is executed. Data of n bytes (8 bits (predetermined bit) × n (predetermined length)) latched in the latch units LT1 to LTn in the search payload data shift unit 9 becomes the search payload data DP.
[0022]
The header part 15a of the search data combination part 15 takes in the header data DH, and the payload part 15b takes in the search payload data DP, combines both data, and outputs them as combination search data D15 (DH + DP).
[0023]
In the AND gate group 13 including a plurality of AND gates G1, combination search data D15 is given to one input of the plurality of AND gates G1. On the other hand, the mask data stored in the mask register 14 is given to the other input of each of the plurality of AND gates G1 of the AND gate group 13. The data output from each AND gate G1 of the AND gate group 13 becomes the search target data DS.
[0024]
The CAM array 11 is. A plurality of entry data DE that can be compared with the search target data DS is stored. That is, each entry data DE is composed of more than the number of bytes corresponding to the search target data DS.
[0025]
Then, when any of the plurality of entry data DE matches the search target data DS, the CAM array 11 receives a hit signal hit including information indicating the match and information indicating the matched entry data DE by an address or the like. When it does not match any entry data DE, it outputs a hit signal hit including information indicating that all do not match. The hit signal hit also includes information indicating whether or not there are two or more matching entry data DE.
[0026]
For example, if the memory size of the CAM array 11 is 1 Mbit and the lookup length is 144b (bits) × 8K entries and 288b × 4K entries and two types of programs are possible, 144 bits × 8K entries and 13 bits Output information (information indicating one of 8K entries), a flag indicating whether the search result is a hit (match) or a miss (mismatch), and a flag indicating that there are two or more search results Is output as a hit signal hit.
[0027]
It is to be noted that which of the operations of reading and writing the entry data DE and the search processing of the search target data DS and the entry data DE is performed on the CAM array 11 is the operation code OP. It can be controlled by an instruction by code.
[0028]
The priority encoder 12 selects one entry data DE in accordance with a predetermined priority when the hit signal hit indicates that the entry data DE is equal to or greater than 2, and matches only the one entry data DE. An instructed hit signal hit is output to the output bus 22. FIG. 2 schematically shows a case where the hit signal hit indicates matching with one entry data DE, and the hit signal hit in the CAM array 11 is output to the output bus 22 as it is.
[0029]
The offset information output unit 20 synchronizes with the timing at which the comparison result of the search payload data DP stored in the search payload data shift unit 9 appears as the comparison result signal result. The data D13 is output on the output bus 22 as the offset signal offset.
[0030]
As a result, the hit signal hit and the offset signal offset output on the output bus 22 are output to the external ASIC 1 via the output terminal P12 as the comparison result signal result.
[0031]
Note that the connection relationship between the clock CLK and the reset signal RST to each component (CAM array 11 or the like) of the CAM built-in integrated circuit 10 is not shown, but is given to each component, and each component is synchronized with the clock CLK. It is initialized when an active reset signal RST is input.
[0032]
(Operation)
FIG. 4 is an explanatory diagram schematically showing a signature matching search operation of the CAM built-in integrated circuit 10 according to the first embodiment. In the example of FIG. 4, a case where the latch number n of the latch unit LT of the search payload data shift unit 9 is “8” is shown as an example.
[0033]
As shown in the figure, the header data D11 in the packet data D1 is searched for data via the first header part 17 or the second header part 18, the selector 16, the header part 15a, the mask register 14, and the AND gate group 13. Set as DS header data DH (DH0 to DH9). As shown in FIG. 4, the header data changes from header data DH0 to DH9 over time in synchronization with the clock CLK, but is actually fixed to either the first header data DH11 or the second header data DH12.
[0034]
On the other hand, the payload data D12 (“ABcdEfGH...”) Is shifted by 1 character (1 byte) from the first 8 characters “ABcdEfGH”, while the search payload data DP is synchronized with the clock CLK with the passage of time. It changes as data DP0 to DP9. That is, search payload data DP0 = “ABcdEfGH” (no shift (offset)) (offset0), DP1 = “BcdEfGHW” (shift once (offset1)), DP2 = “cdEfGHWA” (shift two times (offset2)). And change.
[0035]
Here, when “Warning!” Is registered in the portion corresponding to the search payload data DP as the entry data DE of the CAM array 11, the search payload data DP8 = “Warning!” (8 shifts (offset8)) At this time, the hit signal hit becomes an active state (indicated by a capital letter “HIT” in FIG. 4).
[0036]
As a result, a signature matching search for searching for the fact that the character string “Warning!” Is included in the payload data D12 as the comparison result signal result can be performed.
[0037]
FIG. 5 is a timing chart showing details of the operation of the CAM built-in integrated circuit 10 according to the first embodiment. The example of FIG. 5 also shows a case where the number of latches n of the latch unit LT of the search payload data shift unit 9 is “8”, as in FIG. In the example of FIG. 5, the case where the payload data D12 is “ABCDEFGHIJKLMNOPQ...” Is shown.
[0038]
As shown in the figure, each operation is executed in synchronization with the “H” rising or “L” falling of the clock CLK. The opcode OP. Included in the control signal SC. The code is used to control the selector 16, and in the example of FIG. 5, the first header data DH11 is selected when the first to fourth and seventh to ninth searches (Search) are executed, and the fifth and sixth searches are executed. An example in which 2 header data DH12 is selected is shown. Here, the search operation for the search payload data DP after the i (i ≧ 1) shift operation is performed is the i-th search operation.
[0039]
The offset data D13 is incremented by “1” in synchronization with the number of searches i and is output to the offset information output unit 20. That is, when the least significant byte LSB of the search payload data DP is “I”, it is set to “1” (00000001), and thereafter, offset data D13 incremented by “1” in synchronization with the clock CLK is output as offset information. Given to part 20.
[0040]
The data is taken into the search payload data shift unit 9 in synchronization with the “L” falling of the clock CLK, and input to the payload unit 15 b in synchronization with the “H” rising of the next clock CLK.
[0041]
After that, after the time (latency) is delayed by the pipeline processing of the search data combination unit 15, mask register 14, AND gate group 13, CAM array 11 and priority encoder 12, the hit signal hit is output from the priority encoder 12. . FIG. 5 shows a case where the latency is 4 clocks. That is, the result of the i-th search process (Search-i) is output as a hit signal (hit-i) delayed by 4 clocks.
[0042]
The offset information output unit 20 delays the offset data D13 by 4 clocks and outputs it as an offset signal offset. As a result, an offset signal offset indicating the shift status i is output in synchronization with the i-th hit signal (hit-i), so that the offset signal offset indicates the shift status during the search processing corresponding to the hit signal hit. It can be recognized accurately.
[0043]
As described above, since the CAM built-in integrated circuit 10 according to the first embodiment has a signature matching search function for the header data D11 and the payload data D12, the control unit such as the ASIC 1 or the NPU does not need to perform the signature matching search process. The burden on the control unit can be reduced.
[0044]
In the first embodiment, since the search payload data shift unit 9 is input in units of 1 byte, the band ratio consumed on the data pin during one search is 1 byte / 1 search. On the other hand, conventionally, since all data strings to be searched are generally input from the data pin input, the search is n bytes / 1. Therefore, the CAM built-in integrated circuit 10 of the first embodiment also has an effect of saving the band to 1 / n.
[0045]
In addition, the search target data DS can be determined by arbitrarily masking the combination search data D15 by the AND gate group 13 and the mask register 14. The writing to the mask register 14 can be set by setting data D14 input from the input terminal P1.
[0046]
For example, if all of the search payload data DP is masked by the AND gate group 13 and the mask register 14, it can be used for address search, which is a normal router function based on the header data DH. If both the header data DH and the search payload data DP are validated, they can be used as IDS by the signature matching function in addition to the normal router function. Accordingly, mass production is realized as the application is widened by the amount applicable to IDS in addition to the router function. As a result, the production cost can be reduced by the quantity.
[0047]
The search data combination unit 15, the mask register 14, and the AND gate group 13 variably set the bit length (header length) of the header data portion and the bit length (payload length) of the payload data portion in the search target data DS. can do. For example, when the bit length of the search target data DS is 288 bits, the first combination in which the header length is 32 bits, the payload length is 256 bits, the header length is 128 bits, and the payload length is 160 bits. It is possible to change to the third combination in which the header length is 0 bit and the payload length is 288 bits. However, in order to realize the first to third combinations, the number of bits stored in at least one of the first header portion 17 and the second header portion 18 and the header portion 15a is 128 bits or more, search payload data It is necessary to set the number of bits stored in the shift unit 9 and the payload unit 15b to 288 bits or more.
[0048]
As described above, the header length and payload length are variable when the network layer to be searched is the third layer L3. A header length of 32 bits is sufficient, but in the fourth layer L4 and the like, a longer header length is set. This is to cope with the case where the required header length differs depending on the network layer to be searched.
[0049]
<Embodiment 2>
(principle)
FIG. 6 is an explanatory diagram showing a packet data structure. As shown in the figure, the packet data includes preamble (Pre-amble) information 61, SFD (Start Frame Delimiter) information 62, transmission source (destination) information 63, transmission destination (Source) information 64, type and length ( Type / Length) information 65, a transmission message 66, PAD (Padding) data 67, and FCS (Frame Check Sequence) information 68. Note that octet in FIG. 6 means a data length with 8 bits (1 byte) as one unit.
[0050]
The data of the second layer L2 of the network layer corresponds to the transmission source information 63 and the transmission destination information 64, and a classification process (processing such as packet flow identification and class identification) is performed based on these information.
[0051]
The third layer data 66a of the transmitting message 66 is subjected to classification processing, checksum filtering processing, etc., and the fourth layer data 66b is subjected to classification processing, checksum filtering processing, etc. Signature matching processing, checksum filtering processing, and the like executed by the CAM built-in integrated circuit 10 of the first embodiment are performed on the fifth to seventh layer data 66c.
[0052]
Since a 4-byte error detection code is set in the FCS information 68, it is possible to detect whether or not the packet is normally received based on the FCS information 68.
[0053]
Further, a portion corresponding to each network layer of the transmitting message 66 has a checksum function for detecting whether or not the message is normally received. That is, in each network layer of the transmission message 66, it is divided into a plurality of chunks (chunks) every 16 bits, addition is performed for each chunk, and the lower 16 bits or less of the addition result is information of the transmission message 66. Has a function of storing as a part of the checksum information. Therefore, if the transmission message 66 is generated by adding the checksum information on the transmission side for each layer of the network layer, the checksum calculation for each layer is performed on the reception side, and the checksum result is compared with the checksum information. As a result, it is possible to detect in which hierarchy an error has occurred on the receiving side.
[0054]
FIG. 7 is an explanatory diagram showing a specific configuration for realizing the conventional checksum operation. As shown in the figure, the integrated circuit 25 with a built-in CAM has a CAM array 4, and reads the entry data DE of the CAM array 4 from the output terminal P30 via the dedicated bus 6, the common bus 7, etc. . Then, the read data RD is input to the input unit P11 of the ASIC 26 via the 144-bit signal line L11.
[0055]
The ASIC 26 reads the data of the k-th layer (any of k = 3 to 7) as read data RD by an internal checksum addition function 1a (which can be realized by hardware or software), and is 16-bit unit ([15: 0] , [31:16], [47:32], [63:48],..., [127: 112], [143: 128]) to obtain the final checksum. The result sum [15: 0] can be obtained, and the check sum information of the kth layer stored in the SRAM 2 is fetched through the 16-bit signal line L12 and the input / output terminal P12, and the final check of the kth layer is performed. Based on the comparison result between the sum result sum [15: 0] and the checksum information of the kth layer, it is possible to detect whether or not the reception of the kth layer has been performed normally.
[0056]
However, as described above, causing the ASIC 26 to perform the checksum calculation process entirely as described above places a load on the ASIC 26.
[0057]
Therefore, in a CAM built-in integrated circuit capable of taking the payload portion into the CAM array, such as the CAM built-in integrated circuit 10 of the first embodiment in which the header portion and the payload portion of the packet data are input to the CAM array, the transmission message 66, the third layer data 66a to the fifth to seventh layer data 66c are taken into the CAM array, and the checksum calculation result of each of these data 66a to 66c is further calculated in the CAM built-in integrated circuit. In the second embodiment, the above-described checksum filtering function can be realized.
[0058]
(Constitution)
8 and 9 are explanatory views showing the read data output function of the CAM built-in integrated circuit 3 according to the second embodiment.
[0059]
As shown in the figure, CAM arrays 40 to 43 corresponding to partial associative memory sections classified into four banks (Bank = 0 to 3) are provided, and sense amplifiers 40a to 43a to 72 of the CAM arrays 40 to 43 are provided. Bit read data RD0 to RD3 are read to dedicated buses 44 to 47.
[0060]
For example, as shown in FIG. 9, when the CAM array 40 has an entry data length of 288 bits, the selector 5 for narrowing the output 288 bits of the sense amplifier 40a to 72 bits is used as the output section of the sense amplifier 40a. The selector 5 outputs 72-bit read data RD0. The selector 5 is controlled by a selection signal S5 that is a part of the control signal SC output from the ASIC1. The illustration of the selector 5 is omitted in FIG. Further, when the CAM arrays 41 to 43 have an entry data length of 288 bits, the configuration is the same as that shown in FIG.
[0061]
The dedicated buses 44 to 47 are connected to a 288-bit common bus 48, and read data RD 0 to RD 3 are input to the selector 49. The selector 49 outputs any one of the read data RD0 to RD3 as the read data RD72 from the output terminal P30 based on the selection signal S49 which is a part of the control signal SC such as ASIC1.
[0062]
FIG. 10 is an explanatory diagram showing a checksum calculation result output function in the CAM built-in integrated circuit 3 according to the second embodiment.
[0063]
As shown in the figure, checksum operation units 50 to 53 corresponding to four partial checksum operation units are provided at the output units of the sense amplifiers 40a to 43a of the CAM arrays 40 to 43. The checksum calculation units 50 to 53 classify the output data of the sense amplifiers 40a to 43a into a plurality of chunks every 16 bits, and checksum calculation results DCS0 to DCS3 are the lower 16 bits of the sum of the 16 bit data of the plurality of checks. And output to dedicated buses 54-57. The checksum calculation results DCS0 to DCS3 described above correspond to a plurality of partial checksum calculation results.
[0064]
It should be noted that the data input of each network layer that is the target of the checksum calculation result can be handled by performing the same as normal writing under the control of the ASIC 1, for example. Data output of each network layer can be handled by, for example, reading written checksum calculation target data from the sense amplifier as in normal reading.
[0065]
The dedicated buses 54 to 57 are combined into a 64-bit common bus 58 and output from the output terminal P30 as a 64-bit checksum operation result DCS64. That is, the checksum calculation result DCS64 is set in the order of checksum calculation results DCS0 to DCS3 from the lower order. That is, the checksum calculation result DCS6 is an aggregate of checksum calculation results DCS0 to DCS3. Since 72 bits can be output from the output terminal P30, the upper 8 bits are reserved data fixed at an appropriate value.
[0066]
FIG. 11 is an explanatory diagram showing the periphery of the CAM array 40 in the CAM built-in integrated circuit 3 according to the second embodiment. The integrated circuit 3 with built-in CAM of the second embodiment has the normal data read function shown in FIGS. 8 and 9 and the checksum operation result output function shown in FIG. 10, and this configuration is specifically shown. It is FIG.
[0067]
As shown in the figure, 288-bit data is read from the sense amplifier 40 a of the CAM array 40 to the checksum calculation unit 50. The checksum calculation unit 50 is classified into 18 chunks CS0 to CS17 every 16 bits, and receives 16-bit data output from the corresponding sense amplifier 40a. For example, chunk CS0 reads 0-15 bit information of sense amplifier 40a, chunk CS16 reads 256-271 bit information of sense amplifier 40a, and chunk CS17 reads 272-287 bit information of sense amplifier 40a.
[0068]
The checksum operation unit 50 outputs the lower 16 bits of the sum of the 16-bit data stored in the chunks CS0 to CS17 to the dedicated bus 54 as the checksum operation result DCS0 of the CAM array 40. The checksum calculation results DCS1 to DCS3 of the CAM arrays 41 to 43 are similarly output to the dedicated buses 55 to 47, and the 64-bit checksum calculation result DCS64 is input to the selector 35 from the common bus 58.
[0069]
On the other hand, the 288-bit output of the sense amplifier 40a is input to the selector 5 in addition to the checksum operation unit 50, and is output to the common bus 48 as 72-bit read data RD0 from the selector 5, as shown in FIG. Similarly, the read data RD1 to RD3 of the CAM arrays 41 to 43 are also output to the dedicated buses 45 to 47, synthesized into 288 bits by the common bus 48, and any one of the read data RD0 to RD3 is selected by the selector 49. The data is output to the selector 35 as 72-bit read data RD72.
[0070]
The selector 35 receives an operation code OP. Based on the code, read data RD72 is output during normal read, and checksum operation result DCS64 is output during checksum operation.
[0071]
As described above, since the CAM built-in integrated circuit 3 according to the second embodiment has a checksum calculation function, the control unit such as the ASIC 1 or the NPU performs checksum calculation processing for detecting normal reception of data in each network layer. You don't have to do most of it. As a result, the burden on the control unit can be greatly reduced.
[0072]
In the second embodiment, the checksum calculation results DCS0 to DCS3 of each of the four CAM arrays 40 to 43 are configured to be output in a lump. Therefore, the checksums of the CAM arrays 40 to 43 are independently generated. Compared to the required case, the execution performance can be four times higher.
[0073]
Of course, by combining the first and second embodiments, a CAM built-in integrated circuit capable of executing both the signature matching function and the checksum calculation function can be obtained.
[0074]
【The invention's effect】
As described above, the integrated circuit with an associative memory function according to claim 1 according to the present invention outputs a comparison result signal that indicates whether or not there is a match by comparing the search object data with at least one entry data. Thus, a signature matching process of detecting a predetermined character string included in the payload data can be executed.
[0075]
As a result, the control unit that controls the integrated circuit with an associative memory function according to the first aspect does not need to perform the signature matching process, so that the load on the control unit can be reduced.
[0076]
Since the integrated circuit with an associative memory function according to the fourth aspect of the present invention can execute the checksum calculation process, the control unit for controlling the integrated circuit with the associative memory function according to the fourth aspect is Has the effect of reducing.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a concept of an integrated circuit with an associative memory function according to a first embodiment of the present invention;
FIG. 2 is a block diagram showing a configuration of a CAM built-in integrated circuit according to the first embodiment;
FIG. 3 is an explanatory diagram showing the relationship between a CAM built-in integrated circuit and an ASIC;
FIG. 4 is an explanatory diagram schematically showing a signature matching search operation of the CAM built-in integrated circuit according to the first embodiment.
FIG. 5 is a timing chart showing details of the operation of the CAM built-in integrated circuit according to the first embodiment;
FIG. 6 is an explanatory diagram showing a packet data structure.
FIG. 7 is an explanatory diagram showing a specific configuration for realizing a conventional checksum operation.
FIG. 8 is an explanatory diagram illustrating a read data output function of the CAM built-in integrated circuit according to the second embodiment;
FIG. 9 is an explanatory diagram showing a read data output function of the CAM built-in integrated circuit according to the second embodiment;
FIG. 10 is an explanatory diagram illustrating a checksum operation result output function in the CAM built-in integrated circuit according to the second embodiment;
FIG. 11 is an explanatory diagram showing the periphery of a CAM array in a CAM built-in integrated circuit according to the second embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ASIC (NPU), 2 SRAM, 3,10 CAM built-in integrated circuit, 9, 19 Search payload data shift part, 11, 40-43 CAM array, 12 Priority encoder, 13 AND gate group, 14 Mask register, 15 Data combination unit for search, 15a header unit, 15b piload unit, 5, 16, 35, 49 selector, 17 first header unit, 18 second header unit, 20 offset information output unit, 50-53 checksum calculation unit.

Claims (5)

A payload data shift unit that receives input data including payload data, captures the payload data in predetermined bit units, and obtains search payload data consisting of the predetermined bits × predetermined length while shifting the predetermined bit units;
An associative memory unit that stores at least one entry data and outputs a comparison result signal that indicates whether there is a match by comparing search target data that is data related to the search payload data and the at least one entry data When,
An integrated circuit with an associative memory function. An integrated circuit with an associative memory function according to claim 1,
The input data further includes header data;
A search data combination unit for obtaining combination search data by combining the header data and the search payload data;
A search data mask part for selectively obtaining the combination search data and obtaining the search target data;
An integrated circuit with an associative memory function further provided. An integrated circuit with an associative memory function according to claim 1 or 2,
The comparison result signal includes offset information indicating a shift status of the search payload data.
Integrated circuit with associative memory function. An associative memory unit capable of storing input data as entry data of a predetermined length;
A checksum calculation unit that divides the entry data into a plurality of divided data and obtains a checksum calculation result of the plurality of divided data;
A selector capable of selectively outputting one of the entry data and the checksum operation result;
An integrated circuit with an associative memory function. An integrated circuit with an associative memory function according to claim 4,
The associative memory unit includes a plurality of partial associative memory units,
The checksum operation unit includes a plurality of partial checksum operation units corresponding to the plurality of partial associative memory units, and the plurality of partial checksum operation units output a plurality of partial checksum operation results,
The checksum operation result includes an aggregate of the plurality of partial checksum operation results.
Integrated circuit with associative memory function.

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