JP2005012716A - Analog/digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the influence of mismatching of the end side of an amplifier sequence constituting an analog/digital (A/D) converter to a practically negligible level. <P>SOLUTION: In the A/D converter provided with an impedance circuit network of a resistor R2 between the outputs of amplifier sequence amp1-amp(n), a square circuit is provided which outputs an output signal obtained by squaring the input signal to both ends of the amplifier line. A signal obtained by adding an analog signal VIN and reference signals VRT+(1/2)V<SB>LSB</SB>, VRT-(1/2)V<SB>LSB</SB>is inputted to the square circuit, and a squared output is applied to the outputs of amplifiers at both ends. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

ここでパラメータａ、ｂは、
【００２１】
【数２】

で与えられる値に設計される。ここで、Ｉ_ｔａｉｌは差動対のテール電流、β＝μ（Ｃ_ｏｘ／２）（Ｗ／Ｌ）は差動対トランジスタのトランスコンダクタンスパラメータである。
【００２２】
２乗回路の入力は、アナログ入力信号として電圧ＶＩＮと、レファレンス信号として電圧ＶＲＴ＋Ｖ_ＬＳＢ ／２とが与えられる。ここで、Ｖ_ＬＳＢはアナログ信号に対する１量子化ステップに相当する電圧である。このため、端部のレファレンス抵抗は他の抵抗値の半分の値に設定されている。
【００２３】
２乗回路の出力は、前記条件での出力電流Ｉを電流Ｉ_２０とすると次式▲１▼で与えられる。
【００２４】
【数３】

【００２５】
第１の実施の形態を説明するために回路解析用の補助回路を使用する。
図３は、本実施の形態の補助回路を示す図であり、図４は、本実施の形態を構成する差動対回路の構成を示す図である。図３に示す補助回路の構成は、図２に示す回路の終端回路部（点線で囲ってある部分）を無限個並列に接続された増幅器列に置き換えたものである。
【００２６】
以下、第１の実施の形態の動作を図１〜図４を参照して詳細に説明する。
回路解析の為にＭＯＳ型トランジスタの飽和領域でのドレイン電流を考えると、ドレイン電流Ｉ_Ｄは、Ｉ_Ｄ＝β（Ｖ_ＧＳ−Ｖ_ＴＨ）^２で与えられる。ここで、β＝μ（Ｃ_ｏｘ／２）（Ｗ／Ｌ）はトランジスタのトランスコンダクタンスパラメータ、Ｖ_ＧＳはゲートソース間電圧、Ｖ_ＴＨはスレッショルド電圧である。図４に示すようにテール電流Ｉ_ｔａｉｌが供給されＭＯＳ差動対回路の差動入力を入力電圧Ｖ_ｉとすると、ＭＯＳ差動対回路の差動出力電流ΔＩ_Ｄは、
【００２８】
【数４】

で与えられる（例えば、トリケップス企画部編集「携帯無線端末のＣＭＯＳ化のためのアナログ回路設計技術」、１９９９年１２月１６日、株式会社トリケップス発行、Ｐ１０８〜１０９参照）。
【００２９】
よって、ｎ番目の差動対回路の入力電圧は、ＶＩＮとＶＲＴ−（ｎ−１）Ｖ_ＬＳＢであり、差動電圧はＶＩＮ−ＶＲＴ＋（ｎ−１）Ｖ_ＬＳＢであるので、テール電流をＩ_ｔａｉｌとすると、差動対回路の出力電流Ｉ_Ｄｎは次のように求められる。
【００３０】
【数５】

ここで増幅器は無限に並んでいるので、増幅器の出力電圧は、Ｒ_２が非常に大きく実質的にＲ_２→∞の極限での出力電圧と等しいと考えることができる。
すると、
【００３２】
【数６】

Ｒ_２に流れる電流Ｉ_２ｎは、
【００３３】
【数７】

であるので、Ｉ_２ｎは、
【００３４】
【数８】

となる。上式をｎに関して２次で近似し、
【００３５】
【数９】

を用いて、
【００３６】
【数１０】

となる。ここで、次の公式、
【００３７】
【数１１】

をもちいて、
【００３８】
【数１２】

と表せる。ここで、
【００３９】
【数１３】

であるので、
【００４０】
【数１４】

よって、Ｒ_２に流れる電流は、以下で与えられる。
【００４１】
【数１５】

端部の抵抗Ｒ_２、つまりｎ＝０の場合の電流Ｉ_２０は、以下で与えられる。
【００４２】
【数１６】

ここで式▲１▼と式▲２▼を比較すると、等しい電流値になっている。すなわち、図２に示す回路と図３に示す回路で、電流Ｉ_２０が等しく、終端部以外の回路は等価であるため、増幅器の出力は等しくなることが分かる。
【００４３】
図２に示す回路の出力は、図３に示す回路の出力と等しいため、無限に増幅器が並んでいる場合と同じ出力電圧が得られ、理想的な出力電圧を得ることができる。
次に、本発明の実施の形態に適用可能な２乗回路の具体例について説明する。
図５は、本実施の形態に適用可能な２乗回路の例を示す図である。第１、第２のＭＯＳ型トランジスタＱ１とＱ２と、第３及び第４のＭＯＳ型トランジスタＱ３とＱ４で構成された差動対トランジスタと、第１ないし第４の定電流源Ｉ_０で構成されている。この２乗回路は、それぞれテール電流源Ｉ_０を備える２対のＭＯＳ不平衡差動対回路の構成でなり、各差動対回路は、それぞれ２つのＭＯＳ型トランジスタＱ１とＱ２及びＱ３とＱ４で構成され、各差動対回路を構成するＭＯＳ型トランジスタＱ１とＱ２及びＱ３とＱ４はソース電極が共通接続され、ゲート電極間に入力Ｖ_ｉが印加され、ドレイン電極は互いに他の差動対回路の逆相関係にあるＭＯＳ型トランジスタのドレイン電極と交叉接続されている。更に交叉接続されたドレイン電極同士は、テール電流源と同一の電流値を有する電流源Ｉ_０が接続され、各ドレイン電極から合成電流が出力される。つまり、各差動対回路を構成するＭＯＳ型トランジスタの出力電流が加算され、差動的な出力である２つの出力電流Ｉ_{ｏｕｔ ＋}、Ｉ_{ｏｕｔ −}を出力する２乗回路が実現される。
【００４４】
この回路の出力電流Ｉ_{ｏｕｔ ＋}、Ｉ_{ｏｕｔ −}は、
【００４５】
【数１７】

の時、以下で与えられる（例えば、トリケップス企画部編集「携帯無線端末のＣＭＯＳ化のためのアナログ回路設計技術」、１９９９年１２月１６日、株式会社トリケップス発行、Ｐ１０６〜１０７参照）。
【００４６】
【数１８】

Ｖ_ｉ＝ＶＩＮ−ＶＲＴ−Ｖ_ＬＳＢ／２を代入し、
【００４７】
【数１９】

ここでＫ、Ｉ_０はパラメータであるが、
電流Ｉ_２０（式▲１▼）とＩ_ｏｕｔ＋を等しいと置くと、
【００４８】
【数２０】

上式より、Ｋ、Ｉ_０は一意に決定されるため、式▲１▼に等しい電流源が実現される。
【００４９】
図６は、本発明の実施の形態に適用可能な他の２乗回路の例を示す図である。第１及び第２のＭＯＳ型トランジスタＱ１とＱ２で構成された差動対トランジスタと、ドレイン−ソース間が並列接続された第３及び第４のＭＯＳ型トランジスタＱ３とＱ４でなる回路と、第１及び第２の定電流源Ｉ_０で構成されている。
【００５０】
この２乗回路は、テール電流源Ｉ_０を備える２つのＭＯＳ型トランジスタＱ１とＱ２で構成したＭＯＳ平衡差動対回路と、該差動対回路のテール電流を共用するソース電極とそのドレイン電極とを互いに並列接続したＭＯＳ型トランジスタＱ３とＱ４とで構成される。２つのＭＯＳ型トランジスタＱ１とＱ２とで構成された差動対回路は、ソース電極が共通接続され、ゲート電極には互いに逆相関係の入力Ｖ_ｃｏｍ＋Ｖ_ｉ／２とＶ_ｃｏｍ−Ｖ_ｉ／２が印加され、ドレイン電極が共通接続され、該共通接続されたドレイン電極に、テール電流源と同一の電流値を有する電流源Ｉ_０が接続され、その接続点が一方の電流出力となる。更に互いに並列接続したＭＯＳ型トランジスタＱ３とＱ４には、固定信号Ｖ_ｃｏｍが共通接続され、ドレイン電極から合成電流が出力される。つまり、差動対回路には基準電位に対し互いに逆相関係の信号Ｖ_ｃｏｍ＋Ｖ_ｉ／２とＶ_ｃｏｍ−Ｖ_ｉ／２が印加され、ドレイン及びソースの共通接続回路のゲート電極にはその固定信号Ｖ_ｃｏｍ印加され、それぞれのドレイン電極から逆相関係の２つの出力電流Ｉ_{ｏｕｔ ＋}、Ｉ_{ｏｕｔ −}が出力され２乗回路が実現される。
この回路の出力電流Ｉ_{ｏｕｔ ＋}、Ｉ_{ｏｕｔ −}は、
【００５１】
【数２１】

の時、以下で与えられる（例えば、トリケップス企画部編集「携帯無線端末のＣＭＯＳ化のためのアナログ回路設計技術」、１９９９年１２月１６日、株式会社トリケップス発行、Ｐ１１８〜１１９参照）。
【００５２】
【数２２】

Ｖ_ｉ＝ＶＩＮ−ＶＲＴ−Ｖ_ＬＳＢ／２を代入し、
【００５３】
【数２３】

ここで、β_２、Ｉ_０はパラメータであるが、Ｉ_２０とＩ_ｏｕｔ＋が等しいと置くと、
【００５４】
【数２４】

上式より、β_２、Ｉ_０は一意に決定されるため、式▲１▼に等しい電流源を実現できる。
【００５５】
図５及び図６に示す２乗回路の出力電流Ｉ_{ｏｕｔ ＋}、Ｉ_{ｏｕｔ −}は、複数の差動増幅器でなる増幅器列の端部の増幅器の差動出力の各出力端子に、例えば図１に示すようにそれぞれ印加される。つまり、レファレンス電圧ＶＲＴが入力される増幅器ａｍｐ１の出力に印加される出力電流Ｉｏｕｔ＋、Ｉｏｕｔ−は、ドレイン電流の変化が同相となる側のＭＯＳ型トランジスタのドレイン電極側に出力電流Ｉｏｕｔ＋を印加され、ドレイン電流の変化が逆相となる側のＭＯＳ型トランジスタのドレイン電極側に出力電流Ｉｏｕｔ−を印加される。また、レファレンス電圧ＶＲＢが入力される増幅器ａｍｐ（ｎ）の出力に印加される出力電流Ｉｏｕｔ＋、Ｉｏｕｔ−は、ドレイン電流の変化が同相となる側のＭＯＳ型トランジスタのドレイン電極側に出力電流Ｉｏｕｔ−を印加され、ドレイン電流の変化が逆相となる側のＭＯＳ型トランジスタのドレイン電極側に出力電流Ｉｏｕｔ＋を印加される。
【００５６】
以上、第１の実施の形態により、端部の増幅器の出力側に２乗回路からＩ＝−ａＶ_ｉ ^２＋ｂの電流を供給することにより、無限に増幅器が並んでいる場合と同じ出力電圧が得られ、理想的な出力電圧が得るように構成した例を示したが、本発明は、かかる構成に加えて従来の端部への付加回路を併用したり、精度誤差を勘案して前記電流の近似的な電流を使用する等、以下のような実施の形態を構成することが可能である。
（第２の実施の形態）
図７は、本発明の第２の実施の形態を示す図である。本実施の形態はアナログ／デジタル変換における比較用の増幅器としては不要である、ダミーの差動対トランジスタ構成の増幅器（ダミー増幅器）ａｍｐ０及びａｍｐ（ｎ＋１）を増幅器列の端部に設け、更にダミー増幅器に対して２乗回路を有し、アナログ入力信号とレファレンス信号の合成（加算）信号を２乗回路に入力し、その出力をダミー増幅器の出力端子に供給する構成としたものである。ダミー増幅器を追加することにより、レファレンス信号としてＶＲＴ＋（３／２）Ｖ_ＬＳＢとＶＲＴ−（３／２）Ｖ_ＬＳＢに設定している。増幅器列の終端回路として不整合の影響を抑制する２つの回路手段を設けた構成となり、回路電流と配置（面積）等が問題とならないかぎり特性上は一層の改善を図ることができる。
【００５７】
（第３の実施の形態）
図８は、本発明の第２の実施の形態を示す図である。第１の実施の形態における基準電圧を発生する直列接続構成の抵抗回路のうち、端部の抵抗Ｒ_２／２は、必ずしも他の抵抗値の半分の値になっている必要はない。つまり、端部の抵抗を他の抵抗と同じ値にしレファレンス信号をＶＲＴ＋１Ｖ_ＬＳＢとＶＲＴ−１Ｖ_ＬＳＢに設定したものである。第３の実施の形態は、精度誤差が比較的大きくても問題ない場合や第２の実施の形態にようにダミー増幅器等の従来の付加回路を併用する場合には、レファレンス信号が供給される端部の抵抗の抵抗値は変更してよく、Ｒｒ／２〜Ｒｒの範囲で適宜設定することが可能である。
【００５８】
（第４の実施の形態）
図９は、本発明の第４の実施の形態を示す図である。終端回路として、増幅器の負荷抵抗に比例し、増幅器のトランスコンダクタンスに比例し、平均化抵抗に反比例する定電流回路を接続する構成としたものである。
例えば、第４の実施の形態の終端回路の定電流回路として、
【００５９】
【数２５】

で与えられる電流値を出力するように設計する。ここで、ｇ_ｍは増幅器のトランスコンダクタンス、Ｒ_１は増幅器の負荷抵抗である。ここで、Ｉ_ｔａｉｌを差動対のテール電流、β＝μ（Ｃ_ｏｘ／２）（Ｗ／Ｌ）を差動対トランジスタのトランスコンダクタンスパラメータとする。
第１〜第３の実施の形態は増幅器のトランスコンダクタンスｇ_ｍが入力信号により変化する前提で計算したが、一定であると近似してもアナログ／デジタル変換装置としての精度に問題ない場合は、
【００６０】
【数２６】

としてよいので、上記定電流回路の電流値は、
【００６１】
【数２７】

に近似することが可能である。
【００６２】
図３に示す補助回路の電流式▲２▼と比較すると、式▲３▼は式▲２▼の近似になっている。
本実施の形態では、２つの定電流回路を使用し、各定電流回路の出力電流Ｉは複数の差動増幅器でなる増幅器列の端部の増幅器の差動出力の各出力端子に図９に示す方向にそれぞれ印加される。つまり、レファレンス電圧ＶＲＴが入力される増幅器ａｍｐ１の出力に印加される各出力電流Ｉは、入力Ｖｉの変化に対し、ドレイン電流の変化が同相となる側のＭＯＳ型トランジスタのドレイン電極側に出力電流Ｉを吐出する方向に印加され、ドレイン電流の変化が逆相となる側のＭＯＳ型トランジスタのドレイン電極側に出力電流Ｉを吸い込む方向に印加される。また、レファレンス電圧ＶＲＢが入力される増幅器ａｍｐ（ｎ）の出力に印加される各出力電流Ｉは、入力Ｖｉの変化に対し、ドレイン電流の変化が同相となる側のＭＯＳ型トランジスタのドレイン電極側に出力電流Ｉを吸い込む方向に印加され、ドレイン電流の変化が逆相となる側のＭＯＳ型トランジスタのドレイン電極側に出力電流Ｉを吐出する方向に印加される。
【００６３】
本実施の形態によれば、端部の増幅器に無限に増幅器が並んでいる場合と近似的に等しい電流が供給されるため、無限に増幅器が並んでいる場合と近似的に等しい出力電圧が得られ、精度誤差が比較的大きくても問題ない場合には、ほぼ理想的な出力電圧を得ることができる。
【００６４】
（第５の実施の形態）
図１０は、本発明の第５の実施の形態を示す図である。第２〜第４の実施の形態の組合せ構成でなるものである。終端回路として定電流源を用いるとともにダミー増幅器をも用いた構成としている。ダミー増幅器との併用により増幅器ａｍｐ１、ａｍｐ（ｎ）での不整合の影響はより改善され定電流回路等の使用による精度誤差の問題は解消される。
【００６５】
以上の実施の形態の外に、ダミー増幅器との併用構成と基準電圧を発生する直列接続の抵抗回路の構成の組合せとして、増幅器列の端部の増幅器をダミー増幅器とし、２乗回路をダミー増幅器に設け、かつレファレンス信号は、前記増幅器列の端部の増幅器の基準電圧に対し量子化ステップだけ異なるようにする構成とすることも可能である。つまり、ダミー増幅器と抵抗回路の各抵抗を抵抗値Ｒｒとする等の構成とすることが可能である。
また、以上の実施の形態では、増幅器列を構成する増幅器は差動対トランジスタ構成を例に説明したが、本発明は他の増幅器構成を有するアナログ／デジタル変換装置にも適用可能であり、増幅器の差動出力構成を必須とするものではなく、この場合は図５、６に示す２乗回路もその出力の差動信号の一方のみを使用することができる。
更に、図５、図６により式▲１▼に等しい電流源を実現できる２乗回路の回路例を示したが、同図の２乗回路はあくまでも例であり、本発明はかかる回路だけに限定されるものではないことは明らかである。
【００６６】
【発明の効果】
本発明によれば、増幅器列の出力は、２乗回路でなる電流源回路又は定電流回路の使用により、増幅器が無限に並んでいる場合と同じ出力電圧が得られるので、理想的な出力電圧を得ることが可能であり、ダミー増幅器を使用せず若しくは最小限の使用により、アナログ／デジタル変換装置を構成する増幅器列の終端側の不整合の影響を実用上問題とならないレベルまで低減することが可能である。
【００６７】
また、ダミー増幅器を併用した場合には一層のアナログ／デジタル変換の精度の向上を図ることが可能であり、また、電流源回路を簡略化することが可能であり、繰り返し性の増幅器を有するモノリシック集積回路に適用して好適である。更に終端回路として２乗回路又は定電流回路のみを使用する構成とする場合には低消費電力・低面積の面で優れた集積回路が実現される。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態を示す図である。
【図２】第１の実施の形態のより具体的構成を示す図である。
【図３】第１の実施の形態の動作説明のための補助回路を示す図である。
【図４】増幅器をＭＯＳ型トランジスタで構成した差動対トランジスタを示す図である。
【図５】２乗回路の構成例を示す図である。
【図６】２乗回路の他の構成例を示す図である。
【図７】本発明の第２の実施の形態を示す図である。
【図８】本発明の第３の実施の形態を示す図である。
【図９】本発明の第４の実施の形態を示す図である。
【図１０】本発明の第５の実施の形態を示す図である。
【図１１】従来技術を示す図である。
【図１２】他の従来技術を示す図である。
【符号の説明】
ａｍｐ０〜ａｍｐ（ｎ＋１） 増幅器（差動増幅器）
Ｑ１〜Ｑ４ ＭＯＳ型電界効果トランジスタ（ＭＯＳ型トランジスタ）
Ｒ_１ 負荷抵抗
Ｒｒ、Ｒｒ／２、 抵抗
Ｒ_２ インピーダンス網（抵抗）
ＶＩＮ アナログ入力信号
Ｉ_０ 定電流源
Ｉ_ｔａｉｌ テール電流
Ｉ_Ｄ０〜Ｉ_Ｄ４ ドレイン電流
Ｉ_１１〜Ｉ_１４ 負荷電流
Ｖ_ｉ 入力信号（電圧）
Ｉ_２０〜Ｉ_２４、Ｉ_２ｎ 増幅器の出力端子間の電流[0001]
[Technical field to which the invention belongs]
The present invention relates to an analog / digital conversion device, and more particularly to an analog / digital conversion device including means for reducing the influence of mismatch at the end of an amplifier array of a flash type analog / digital converter.
[0002]
[Prior art]
A flash type analog / digital converter (A / D converter) mainly includes a transconductance amplifier (amplifier), a comparator, and a decoding circuit. Here, the amplifier is composed of a current source, a differential pair transistor having a common source configuration such as a field effect transistor, and a load resistor, and these circuit elements all cause an input offset of the A / D converter.
[0003]
FIG. 11 is a diagram showing a configuration of a first conventional example of a flash A / D converter. Normal flash A / D converter is 2^N−1 (N: number of bits of digital output) amplifier. Reference voltages Vref (1) to Vref (n) generated by dividing the reference signals (voltages) VRT and VRB by a series connection circuit of a resistor Rr are input to one input terminal and an analog input VIN, respectively. 2^N−1 differential amplifiers amp1 to amp (n) and a resistor network connected between the output terminals (see Patent Document 1).
[0004]
As a method of mitigating the input offset, the output is averaged by an averaging resistor network composed of a resistor network between the outputs of a plurality of adjacent amplifiers. In this way of connecting the averaging resistor network, the amplifiers are not infinitely arranged, so that the transition point of the A / D converter is shifted in the amplifier at the end as compared with the case where the output voltage is infinitely arranged. To do. In other words, since the number of amplifiers is finite, there is an effect that the input offset of the amplifier on the end side increases. As a result, the differential linearity and integral linearity of the digital output are adversely affected and the conversion characteristics are deteriorated.
[0005]
Therefore, in such a configuration, even if the A / D converter is configured as a monolithic chip, the number of devices that can satisfy a high-accuracy standard may be much smaller than expected, so the yield as a monolithic chip is increased. May be extremely low. Further, in order to avoid the above-described influence of the flash type A / D converter shown in FIG.^NSome attempts have been made with respect to the circuit at the end of the average resistance network, such as an arrangement with more than -1.
[0006]
FIG. 12 is a diagram showing a configuration of a second conventional example of a flash A / D converter. 2 of the flash type A / D converter of the first conventional example^N-Extra dummy amplifiers amp0 and amp (n + 1) are mounted on both end sides of one differential amplifier amp1 to amp (n), and the resistance Rx having a different value from the averaging resistor R2 is connected to the end amplifier. The above-described influence is mitigated by using a termination circuit configured to connect the two (see Non-Patent Document 1).
[0007]
[Patent Document 1]
US Pat. No. 5,175,550
[Non-Patent Document 1]
IEEE Journal of Solid-State Circuits, Vol. 37, no. 12, Dec 2002 p1599-1609
[0008]
[Problems to be solved by the invention]
However, the results of previous attempts on flash A / D converters have not been satisfactory. In such a configuration, on the termination side of the averaging resistor network, the impedance at the termination and its vicinity is still different from the other parts, and a different current value is given to the amplifier on the termination side, which is infinite. This is because it is not possible to obtain the same output voltage as when the amplifiers are arranged side by side. Further, even with the configuration of the second conventional example, a sufficiently good characteristic may not be realized with only a single dummy amplifier, and mounting one or more dummy amplifiers is disadvantageous in terms of circuit current and area. There was also a problem.
[0009]
(the purpose)
The main object of the present invention has been made in view of the above-mentioned problems, and by using the improved technique, the effect of mismatch on the termination side of the averaged impedance network of the amplifier array is regarded as a practical problem. It is to be possible to reduce to a level that does not become.
Another object of the present invention is to provide an analog / digital conversion apparatus that obtains an ideal output voltage by adding a current source at the end, reduces the number of dummy amplifiers or the like, or does not use it at all.
[0010]
[Means for Solving the Problems]
The analog / digital conversion device of the present invention has an impedance network (for example, R in FIG. 1) that averages the output between output terminals.₂) And an analog input signal (for example, VIN in FIG. 1) and a reference signal (for example, VRT + 1 / 2V in FIG. 1)._LSBVRB-1 / 2V_LSB) In an analog / digital converter having an amplifier array (for example, amp1 to amp (n) in FIG. 1), a square circuit whose input / output characteristics have a square characteristic (for example, FIGS. 1, 5, and 6). ), And a combined signal of the analog signal and the reference signal is input to the squaring circuit, and the output of the squaring circuit is input to the amplifier at the end of the amplifier row (for example, amp1, amp (n) in FIG. 1). The square circuit is proportional to the load resistance of the amplifier, proportional to the transconductance of the amplifier, and between the output terminals of the amplifier when the input of the amplifier is no signal. It has a characteristic of outputting a current inversely proportional to the resistance (for example, equation (3) in FIG. 9).
[0011]
An analog / digital conversion apparatus according to the present invention includes an impedance circuit network that averages outputs between output terminals, and includes an amplifier string for inputting an analog input signal and a reference signal. A constant current circuit (for example, FIG. 9) that outputs a constant current proportional to the load resistance of the amplifier, proportional to the transconductance of the amplifier, and inversely proportional to the resistance between the output terminals of the amplifier to the output terminal of the amplifier at the end. ) Is applied.
[0012]
The amplifier at the end of the amplifier row is a dummy amplifier (for example, FIG. 7 and FIG. 10), and each amplifier in the amplifier row inputs an analog input signal to one input terminal, and the other It is a differential amplifier having a differential pair transistor that sequentially inputs different reference voltages for the quantization step to the input terminal.
[0013]
Further, the reference signal is a voltage that is different from the reference voltage of the amplifier at the end of the amplifier array by approximately ½ of the quantization step, and the reference voltage has a resistance value of a resistance at both ends. It is generated by dividing a positive and negative reference signal by a resistor circuit composed of a plurality of resistors connected in series, which is approximately ½ of the resistance value of another resistor.
[0014]
Each of the differential pair transistors is a MOS transistor (for example, a source electrode connected in common, a tail current source connected, a gate electrode connected to each input terminal, and a drain electrode connected to the output terminal) 4).
[0015]
In the squaring circuit, a first tail current source is commonly connected to each source electrode, and a combined signal of an analog input signal and a reference signal (for example, V in FIG. 5) is connected between the gate electrodes._i) Are input to the first and second MOS transistors (for example, Q1 and Q2 in FIG. 5), and a second tail current source is commonly connected to each source electrode, and an analog input signal and a reference are connected between the gate electrodes. The drain electrodes of the third and fourth MOS transistors (for example, Q3 and Q4 in FIG. 5) and the first and fourth MOS transistors (for example, Q1 and Q4 in FIG. 5) to which the combined signal of the signals is input. Third and fourth constant current sources respectively connected to a common connection point and a common connection point of drain electrodes of second and third MOS transistors (for example, Q2 and Q3 in FIG. 5); 4 constant current sources and output terminals respectively provided at connection points of the drain electrodes, or a first tail current source is commonly connected to each source electrode, First and second MOS transistors (for example, Q1 and Q2 in FIG. 6) in which a composite signal of an analog input signal and a reference signal is differentially input to the gate electrode, and a first tail to each source electrode A current source is commonly connected, and a fixed signal (for example, V in FIG. 6) is connected to the gate electrode._com) To which the drain electrodes of the third and fourth MOS transistors (eg, Q3 and Q4 in FIG. 6) and the first and second MOS transistors (eg, Q1 and Q2 in FIG. 6) are connected. A second constant current source connected to the output terminal, an output terminal provided at a connection point between the second constant current source and the drain electrode, and third and fourth MOS transistors (for example, Q3 and Q4 in FIG. 6). And an output terminal provided at a common connection point of the drain electrode.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a first embodiment of an analog / digital conversion apparatus according to the present invention. In an analog / digital converter having an impedance network between the outputs in order to average the output of the amplifier train, the output signal obtained by squaring the input signal is output to both ends (both ends) of the amplifier train. The signal obtained by adding the analog signal and the reference signal is input to the square circuit, and the squared output is applied to the outputs of the amplifiers at both ends.
[0017]
In the first embodiment, an analog input VIN is connected to one input terminal, a resistor Rr / 2 at both ends is connected to the other input terminal, and a plurality of resistors Rr (reference resistors) between them are connected in series to provide a reference signal VRT + V._LSB/ 2, VRT-V_LSBReference voltages Vref (1) to Vref (n) generated by dividing / 2 are input n (= 2)^N-1) an amplifier composed of a differential amplifier amp1 to amp (n) and a circuit network of a resistor R2 connected between its output terminals, and two squaring circuits at the end, and an input VIN Reference signal VRT + V_LSB/ 2, input VIN and reference signal VRT-V_LSBA squaring circuit for inputting / 2 is provided, and the output current I of each squaring circuit is applied to the terminal amplifiers amp1 and amp (n).
[0018]
FIG. 2 is a diagram showing a circuit in which the amplifier of the circuit shown in FIG. 1 is expressed at the transistor level. As an example, an amplifier is a circuit that receives a current supply, inputs a differential signal, and outputs a signal corresponding thereto. For example, two enhanced insulated field effect transistors (MOS type transistors) are used, and their source electrodes are connected in common, and the current value I_tailAre connected to the first reference potential (ground) via the tail current source of the respective terminals, each gate electrode is used as an input terminal, and each drain electrode is connected to a load resistor R.₁This is a transconductance amplifier (amplifier) composed of a differential pair transistor connected to the second reference potential (power supply) via
[0019]
Furthermore, in the present embodiment, as the input / output characteristics of the above-described square circuit, the input voltage V_iThe output current I is a square circuit having the following equation.
[0020]
[Expression 1]

Where parameters a and b are
[0021]
[Expression 2]

Designed to the value given by Where I_tailIs the tail current of the differential pair, β = μ (C_ox/ 2) (W / L) is a transconductance parameter of the differential transistor.
[0022]
The input of the squaring circuit is the voltage VIN as an analog input signal and the voltage VRT + V as a reference signal._LSB / 2 is given. Where V_LSBIs a voltage corresponding to one quantization step for an analog signal. For this reason, the reference resistance at the end is set to a half value of the other resistance values.
[0023]
The output of the square circuit is obtained by converting the output current I under the above conditions to the current I₂₀Then, it is given by the following formula (1).
[0024]
[Equation 3]

[0025]
In order to explain the first embodiment, an auxiliary circuit for circuit analysis is used.
FIG. 3 is a diagram illustrating an auxiliary circuit according to the present embodiment, and FIG. 4 is a diagram illustrating a configuration of a differential pair circuit configuring the present embodiment. The configuration of the auxiliary circuit shown in FIG. 3 is obtained by replacing the termination circuit portion (portion surrounded by a dotted line) of the circuit shown in FIG. 2 with an infinite number of amplifier rows connected in parallel.
[0026]
Hereinafter, the operation of the first embodiment will be described in detail with reference to FIGS.
Considering the drain current in the saturation region of a MOS transistor for circuit analysis, the drain current I_DI_D= Β (V_GS-V_TH)²Given in. Where β = μ (C_ox/ 2) (W / L) is the transconductance parameter of the transistor, V_GSIs the gate-source voltage, V_THIs the threshold voltage. As shown in FIG._tailIs supplied to the differential input of the MOS differential pair circuit as the input voltage V_iThen, the differential output current ΔI of the MOS differential pair circuit_DIs
[0028]
[Expression 4]

(For example, edited by Trikeps Planning Department, “Analog Circuit Design Technology for CMOSization of Portable Wireless Terminals”, December 16, 1999, published by Trikeps, Inc., P108-109).
[0029]
Therefore, the input voltage of the nth differential pair circuit is VIN and VRT− (n−1) V._LSBThe differential voltage is VIN−VRT + (n−1) V_LSBSince the tail current is I_tailThen, the output current I of the differential pair circuit_DnIs obtained as follows.
[0030]
[Equation 5]

Here, since the amplifiers are infinitely arranged, the output voltage of the amplifier is R₂Is very large and substantially R₂→ It can be considered to be equal to the output voltage at the limit of ∞.
Then
[0032]
[Formula 6]

R₂Current I flowing through_2nIs
[0033]
[Expression 7]

So I_2nIs
[0034]
[Equation 8]

It becomes. Approximate the above equation in terms of n with respect to n,
[0035]
[Equation 9]

Using,
[0036]
[Expression 10]

It becomes. Where the following formula:
[0037]
## EQU11 ##

Use
[0038]
[Expression 12]

It can be expressed. here,
[0039]
[Formula 13]

So
[0040]
[Expression 14]

Therefore, R₂The current flowing through is given by:
[0041]
[Expression 15]

End resistance R₂That is, the current I when n = 0₂₀Is given below.
[0042]
[Expression 16]

Here, when the formulas (1) and (2) are compared, the current values are equal. That is, in the circuit shown in FIG. 2 and the circuit shown in FIG.₂₀Since the circuits other than the termination are equivalent, it can be seen that the outputs of the amplifiers are equal.
[0043]
Since the output of the circuit shown in FIG. 2 is equal to the output of the circuit shown in FIG. 3, the same output voltage as when the amplifiers are arranged infinitely is obtained, and an ideal output voltage can be obtained.
Next, a specific example of a squaring circuit applicable to the embodiment of the present invention will be described.
FIG. 5 is a diagram illustrating an example of a squaring circuit applicable to the present embodiment. A differential pair transistor composed of first and second MOS transistors Q1 and Q2, third and fourth MOS transistors Q3 and Q4, and first to fourth constant current sources I;₀It consists of Each of the square circuits has a tail current source I₀Each of the differential pair circuits is composed of two MOS transistors Q1 and Q2 and Q3 and Q4, and the MOSs constituting each differential pair circuit. The source electrodes of the type transistors Q1 and Q2 and Q3 and Q4 are connected in common, and the input V is connected between the gate electrodes._iIs applied, and the drain electrode is cross-connected to the drain electrode of the MOS transistor which is in the opposite phase relationship of the other differential pair circuit. Furthermore, the cross-connected drain electrodes are connected to a current source I having the same current value as that of the tail current source.₀Are connected, and a combined current is output from each drain electrode. That is, the output currents of the MOS transistors constituting each differential pair circuit are added, and two output currents I which are differential outputs are added._{out +}, I_{out −}Is realized.
[0044]
Output current I of this circuit_{out +}, I_{out −}Is
[0045]
[Expression 17]

(Refer to, for example, edited by Triqueps Planning Department “Analog Circuit Design Technology for CMOSization of Portable Wireless Terminals”, December 16, 1999, published by Trikepes, P106-107).
[0046]
[Formula 18]

V_i= VIN-VRT-V_LSBSubstitute / 2,
[0047]
[Equation 19]

Where K, I₀Is a parameter,
Current I₂₀(Formula (1)) and I_{out +}Are equal,
[0048]
[Expression 20]

From the above formula, K, I₀Is uniquely determined, so that a current source equal to equation (1) is realized.
[0049]
FIG. 6 is a diagram showing an example of another squaring circuit applicable to the embodiment of the present invention. A differential pair transistor composed of first and second MOS transistors Q1 and Q2, a circuit composed of third and fourth MOS transistors Q3 and Q4 connected in parallel between the drain and the source; And the second constant current source I₀It consists of
[0050]
This squaring circuit includes a tail current source I₀MOS-type transistors Q3 and Q4 in which a MOS balanced differential pair circuit composed of two MOS-type transistors Q1 and Q2 including a source electrode sharing the tail current of the differential pair circuit and its drain electrode are connected in parallel with each other. It consists of. A differential pair circuit composed of two MOS transistors Q1 and Q2 has a source electrode connected in common, and a gate electrode with an input V having an opposite phase relationship to each other._com+ V_i/ 2 and V_com-V_i/ 2 is applied, the drain electrodes are commonly connected, and a current source I having the same current value as the tail current source is connected to the commonly connected drain electrodes.₀Are connected, and the connection point becomes one current output. Further, the MOS transistors Q3 and Q4 connected in parallel to each other have a fixed signal V_comAre commonly connected, and a combined current is output from the drain electrode. In other words, the differential pair circuit has signals V that are opposite in phase to the reference potential._com+ V_i/ 2 and V_com-V_i/ 2 is applied, and the fixed signal V is applied to the gate electrode of the drain and source common connection circuit._comTwo output currents I of opposite phase from each drain electrode_{out +}, I_{out −}Is output to realize a square circuit.
Output current I of this circuit_{out +}, I_{out −}Is
[0051]
[Expression 21]

(See, for example, edited by Trikeps Planning Department, “Analog Circuit Design Technology for CMOSization of Portable Wireless Terminals,” December 16, 1999, published by Trikeps, Inc., P118-119).
[0052]
[Expression 22]

V_i= VIN-VRT-V_LSBSubstitute / 2,
[0053]
[Expression 23]

Where β₂, I₀Is a parameter, but I₂₀And I_{out +}Are equal,
[0054]
[Expression 24]

From the above equation, β₂, I₀Is uniquely determined, so that a current source equal to equation (1) can be realized.
[0055]
The output current I of the square circuit shown in FIGS._{out +}, I_{out −}Is applied to each output terminal of the differential output of the amplifier at the end of the amplifier row composed of a plurality of differential amplifiers, for example, as shown in FIG. In other words, the output currents Iout + and Iout− applied to the output of the amplifier amp1 to which the reference voltage VRT is input are applied to the drain electrode side of the MOS transistor on the side where the drain current changes in phase, The output current Iout− is applied to the drain electrode side of the MOS transistor on the side where the drain current changes in the opposite phase. Further, the output currents Iout + and Iout− applied to the output of the amplifier amp (n) to which the reference voltage VRB is input are the output current Iout− on the drain electrode side of the MOS transistor on the side where the change of the drain current is in phase. , And the output current Iout + is applied to the drain electrode side of the MOS transistor on the side where the drain current changes in the opposite phase.
[0056]
As described above, according to the first embodiment, I = −aV from the squaring circuit on the output side of the amplifier at the end._i ²Although an example in which an output voltage that is the same as an infinite array of amplifiers is obtained by supplying a current of + b and an ideal output voltage is obtained has been shown, the present invention is not limited to this configuration. Thus, it is possible to configure the following embodiments, such as using a conventional additional circuit at the end or using an approximate current of the current in consideration of an accuracy error.
(Second Embodiment)
FIG. 7 is a diagram showing a second embodiment of the present invention. In this embodiment, dummy differential pair transistor amplifiers (dummy amplifiers) amp0 and amp (n + 1), which are not necessary as a comparison amplifier in analog / digital conversion, are provided at the end of the amplifier row, and further dummy The amplifier has a squaring circuit, a combined (added) signal of an analog input signal and a reference signal is input to the squaring circuit, and its output is supplied to the output terminal of the dummy amplifier. By adding a dummy amplifier, VRT + (3/2) V as a reference signal_LSBAnd VRT- (3/2) V_LSBIs set. As a termination circuit of the amplifier array, two circuit means for suppressing the influence of mismatching are provided, and the characteristics can be further improved as long as the circuit current and the arrangement (area) are not problematic.
[0057]
(Third embodiment)
FIG. 8 is a diagram showing a second embodiment of the present invention. The resistance R at the end of the series connection resistance circuit for generating the reference voltage in the first embodiment₂/ 2 does not necessarily have to be half of the other resistance values. That is, the resistance at the end is set to the same value as other resistors, and the reference signal is VRT + 1V._LSBAnd VRT-1V_LSBIs set. In the third embodiment, a reference signal is supplied when there is no problem even if the accuracy error is relatively large, or when a conventional additional circuit such as a dummy amplifier is used together as in the second embodiment. The resistance value of the resistance at the end may be changed and can be set as appropriate within the range of Rr / 2 to Rr.
[0058]
(Fourth embodiment)
FIG. 9 is a diagram showing a fourth embodiment of the present invention. As the termination circuit, a constant current circuit proportional to the load resistance of the amplifier, proportional to the transconductance of the amplifier, and inversely proportional to the averaging resistance is connected.
For example, as a constant current circuit of the termination circuit of the fourth embodiment,
[0059]
[Expression 25]

It is designed to output the current value given by. Where g_mIs the transconductance of the amplifier, R₁Is the load resistance of the amplifier. Where I_tailIs the tail current of the differential pair, β = μ (C_ox/ 2) Let (W / L) be the transconductance parameter of the differential pair transistor.
The first to third embodiments are the transconductance g of the amplifier._mIs calculated based on the premise that it changes depending on the input signal, but if there is no problem with the accuracy as an analog / digital converter even if it is approximated to be constant,
[0060]
[Equation 26]

Therefore, the current value of the constant current circuit is
[0061]
[Expression 27]

It is possible to approximate
[0062]
Compared with the current formula (2) of the auxiliary circuit shown in FIG. 3, the formula (3) is an approximation of the formula (2).
In this embodiment, two constant current circuits are used, and the output current I of each constant current circuit is shown in FIG. 9 at each output terminal of the differential output of the amplifier at the end of the amplifier row composed of a plurality of differential amplifiers. Each is applied in the direction shown. That is, each output current I applied to the output of the amplifier amp1 to which the reference voltage VRT is input is an output current on the drain electrode side of the MOS transistor on the side where the change of the drain current is in phase with the change of the input Vi. I is applied in the direction in which I is discharged, and is applied in the direction in which the output current I is sucked into the drain electrode side of the MOS transistor on the side where the drain current changes in the opposite phase. Further, each output current I applied to the output of the amplifier amp (n) to which the reference voltage VRB is input is the drain electrode side of the MOS transistor on the side where the change of the drain current is in phase with the change of the input Vi. Is applied in the direction in which the output current I is absorbed, and in the direction in which the output current I is discharged to the drain electrode side of the MOS transistor on the side where the change in the drain current is in the opposite phase.
[0063]
According to the present embodiment, a current that is approximately equal to the case where the amplifiers are lined infinitely is supplied to the amplifier at the end, and thus an output voltage that is approximately equal to the case where the amplifiers are lined infinitely is obtained. If there is no problem even if the accuracy error is relatively large, an almost ideal output voltage can be obtained.
[0064]
(Fifth embodiment)
FIG. 10 is a diagram showing a fifth embodiment of the present invention. This is a combination of the second to fourth embodiments. A constant current source is used as a termination circuit and a dummy amplifier is also used. By using together with the dummy amplifier, the influence of mismatch in the amplifiers amp1 and amp (n) is further improved, and the problem of accuracy error due to the use of a constant current circuit or the like is solved.
[0065]
In addition to the above embodiment, as a combination of the combined configuration with the dummy amplifier and the configuration of the series-connected resistor circuit for generating the reference voltage, the amplifier at the end of the amplifier row is the dummy amplifier, and the square circuit is the dummy amplifier. The reference signal may be different from the reference voltage of the amplifier at the end of the amplifier row by a quantization step. That is, the resistance of the dummy amplifier and the resistance circuit can be set to the resistance value Rr.
In the above embodiment, the amplifier constituting the amplifier row has been described by taking a differential pair transistor configuration as an example. However, the present invention can also be applied to an analog / digital conversion device having another amplifier configuration. In this case, the squaring circuit shown in FIGS. 5 and 6 can also use only one of the output differential signals.
Further, FIG. 5 and FIG. 6 show a circuit example of a squaring circuit that can realize a current source equal to the equation (1). However, the squaring circuit in the figure is only an example, and the present invention is limited to such a circuit. Obviously not.
[0066]
【The invention's effect】
According to the present invention, since the output of the amplifier array can be obtained by using a current source circuit or a constant current circuit formed of a square circuit, the same output voltage as when the amplifiers are infinitely arranged can be obtained. The effect of mismatch at the termination side of the amplifier array constituting the analog / digital converter can be reduced to a level that does not cause a problem in practice by not using a dummy amplifier or by using the dummy amplifier at a minimum. Is possible.
[0067]
In addition, when a dummy amplifier is used in combination, it is possible to further improve the accuracy of analog / digital conversion, to simplify the current source circuit, and to provide a monolithic having a repeatable amplifier. It is suitable for application to an integrated circuit. Further, when only a square circuit or a constant current circuit is used as a termination circuit, an integrated circuit excellent in terms of low power consumption and a small area is realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of the present invention.
FIG. 2 is a diagram showing a more specific configuration of the first embodiment.
FIG. 3 is a diagram showing an auxiliary circuit for explaining the operation of the first embodiment;
FIG. 4 is a diagram illustrating a differential pair transistor in which an amplifier is configured by a MOS transistor.
FIG. 5 is a diagram illustrating a configuration example of a square circuit.
FIG. 6 is a diagram illustrating another configuration example of the square circuit.
FIG. 7 is a diagram showing a second embodiment of the present invention.
FIG. 8 is a diagram showing a third embodiment of the present invention.
FIG. 9 is a diagram showing a fourth embodiment of the present invention.
FIG. 10 is a diagram showing a fifth embodiment of the present invention.
FIG. 11 is a diagram showing a conventional technique.
FIG. 12 is a diagram showing another conventional technique.
[Explanation of symbols]
amp0 to amp (n + 1) amplifier (differential amplifier)
Q1-Q4 MOS field effect transistors (MOS type transistors)
R₁  Load resistance
Rr, Rr / 2, resistance
R₂  Impedance network (resistance)
VIN Analog input signal
I₀  Constant current source
I_tail  Tail current
I_D0~ I_D4  Drain current
I₁₁~ I₁₄  Load current
V_i  Input signal (voltage)
I₂₀~ I₂₄, I_2n  Current between amplifier output terminals

Claims (10)

An analog / digital conversion apparatus having an amplifier circuit for inputting an analog input signal and a reference signal, having an impedance circuit network that averages outputs between output terminals, and having a square circuit whose input / output characteristics have a square characteristic. An analog / digital conversion apparatus characterized in that a combined signal of an analog signal and a reference signal is input to the square circuit, and an output of the square circuit is applied to an output terminal of an amplifier at an end of the amplifier row. . The square circuit has a characteristic of outputting a current that is proportional to the load resistance of the amplifier, proportional to the transconductance of the amplifier, and inversely proportional to the resistance between the output terminals of the amplifier when the amplifier input is no signal. The analog / digital conversion apparatus according to claim 1, further comprising: In an analog / digital converter having an amplifier circuit for inputting an analog input signal and a reference signal, an impedance circuit that averages outputs between output terminals, and an amplifier output terminal at an end of the amplifier array, An analog / digital conversion characterized by applying an output of a constant current circuit that outputs a constant current proportional to the load resistance of the amplifier, proportional to the transconductance of the amplifier, and inversely proportional to the resistance between the output terminals of the amplifier. apparatus. 4. The analog / digital conversion apparatus according to claim 1, wherein the amplifier at the end of the amplifier row is a dummy amplifier. Each amplifier of the amplifier array is a differential amplifier having a differential pair transistor that inputs an analog input signal to one input terminal and sequentially inputs different reference voltages to the other input terminal by a quantization step. The analog / digital conversion device according to claim 1, 2, 3, or 4. 6. The analog / digital conversion apparatus according to claim 5, wherein the reference signal is a voltage that is different from a reference voltage of an amplifier at an end of the amplifier array by approximately ½ of a quantization step. The reference voltage is generated by dividing a positive and negative reference signal by a resistor circuit formed by connecting a plurality of resistors whose resistance values at both ends are approximately ½ of the resistance values of other resistors. The analog / digital conversion apparatus according to claim 6. Each of the differential pair transistors includes a MOS transistor in which a source electrode is commonly connected, a tail current source is connected, a gate electrode is connected to each input terminal, and a drain electrode is connected to the output terminal. 8. The analog / digital conversion device according to claim 5, 6 or 7. In the squaring circuit, a first tail current source is commonly connected to each source electrode, and a first and second MOS transistors in which a composite signal of an analog input signal and a reference signal is input between gate electrodes, Third and fourth MOS transistors each having a second tail current source connected in common to each source electrode and a combined signal of an analog input signal and a reference signal input between the gate electrodes, and first and fourth transistors A third constant current source connected to a common connection point of the drain electrode of the MOS transistor and a common connection point of the drain electrode of the second and third MOS transistors; 9. The analog / digital device according to claim 1, further comprising an output terminal provided at a connection point between the constant current source and the drain electrode. Conversion apparatus. In the square circuit, a first tail current source is commonly connected to each source electrode, and a combined signal of an analog input signal and a reference signal is differentially input to each gate electrode. MOS type transistors, third and fourth MOS type transistors in which a first tail current source is commonly connected to each source electrode, and a fixed signal is input to the gate electrode, and first and second MOS type transistors A second constant current source connected to a common connection point of the drain electrodes, an output terminal provided at a connection point of the second constant current source and the drain electrode, and third and fourth MOS transistors 9. The analog / digital conversion apparatus according to claim 1, further comprising an output terminal provided at a common connection point of the drain electrodes.

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