JP2005012090A - Method of manufacturing semiconductor wafer, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor wafer having high uniformity of in-plane resistance rate, and to provide a method of manufacturing a semiconductor device having small irregularity of breakdown voltage. <P>SOLUTION: The method of manufacturing semiconductor wafer includes a first injection process for forming a silicon crystal by a floating zone method and injecting N type impurity of prescribed concentration, and a second injection process for performing neutron irradiation and injecting phosphorus in a prescribed concentration onto the silicon crystal after the first injection process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor wafer used for a medium breakdown voltage semiconductor device or the like.
[0002]
[Prior art]
In general, a semiconductor device having a withstand voltage of about 300 to 500 V class, which is called a medium withstand voltage, uses a silicon wafer having a resistivity of about 10 to 20 Ωcm.
[0003]
In forming such a silicon wafer, a floating zone method (hereinafter referred to as FZ method) is generally used. The FZ method is a manufacturing method in which a part of rod-shaped polycrystalline silicon is melted by a high-frequency heating coil and a single crystal is grown downward, and since a crucible is not used, there is little impurity mixing into the silicon melt, and high purity. This method is suitable for forming a silicon single crystal.
[0004]
In such an FZ crystal, a predetermined amount of impurities can be doped into the FZ crystal by mixing a predetermined amount of impurities into polycrystalline silicon as a raw material (see, for example, Non-Patent Document 1).
[0005]
By such a method, for example, a single crystal doped with phosphorus of about 3.33 × 10 ¹⁴ / cm ³ is formed. Next, this is finished into a wafer having a resistivity of about 15 Ωcm by slice lap processing. Furthermore, after forming a diffusion layer on the obtained wafer, a diffusion wafer is formed by performing single-sided mirror finishing.
[0006]
Then, a medium voltage semiconductor device such as a power MOS transistor is formed using the wafer thus formed.
[0007]
[Non-Patent Document 1] "Science of Silicon" Published by Realize Inc.
Published: 1996/06/28, p. 50-59
[0008]
[Problems to be solved by the invention]
However, according to the dope at the time of forming the FZ crystal, the in-plane resistance variation when processed into a wafer is about ± 10 to 15%, and it is difficult to uniformly control the impurity distribution. When a semiconductor device is formed using such a wafer, there is a problem that a breakdown voltage variation defect occurs. For this reason, various growth conditions for single crystals have been studied in order to improve the variation in resistivity, but it has not been sufficient.
[0009]
On the other hand, in a non-doped FZ crystal with high resistance and low impurities, ³⁰ Si contained in silicon by about 3% becomes ³¹ P by neutron irradiation, so that the desired impurity can be controlled by controlling the irradiation amount. (Phosphorus) doping can be performed. This dope by neutron irradiation (NTD: Neutron Transmutation Doping) is particularly high in uniformity, so that it can be expected that variations in breakdown voltage can be suppressed. However, in order to obtain a 10 to 20 Ωcm wafer used for a medium voltage semiconductor device, it is necessary to irradiate for a long time. Accordingly, there is a problem that the irradiation request destination cannot cope with the processing capacity because the cost is increased and the occupation time of the irradiation furnace becomes long. Moreover, there was a concern that phosphorus may be further sulfurized by prolonged irradiation.
[0010]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor wafer with high uniformity of in-plane resistivity and a method for manufacturing a semiconductor device with small variations in breakdown voltage.
[0011]
[Means for Solving the Problems]
According to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor wafer comprising: a first injection step of forming a silicon crystal by a floating zone method and injecting an N-type impurity at a predetermined concentration; And a second injection step for injecting a predetermined concentration of phosphorus.
[0012]
Further, according to one embodiment of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a first implantation step of forming a silicon crystal by a floating zone method and implanting a predetermined concentration of N-type impurities; A second implantation step of irradiating the silicon crystal with neutrons and implanting a predetermined concentration of phosphorus; a step of processing the silicon crystal into a semiconductor wafer; a step of forming an impurity diffusion region at a predetermined position of the semiconductor wafer; The method includes a step of forming an electrode on a wafer.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0014]
1 to 4 show a semiconductor wafer manufacturing process in this embodiment. First, as shown in FIG. 1, a 5-inch, (100) single crystal 1 having a resistivity of 250 Ωcm is pre-doped with 2.0 × 10 ¹³ / cm ³ of phosphorus by the FZ method. At this time, as a doping method of phosphorus, when pulling up the single crystal, PH ₃ may be flowed into Ar gas so as to have a predetermined concentration, and may be dissolved in the melted portion 3 by the high-frequency heating coil 2. The crystalline silicon rod 4 may be doped in advance. Furthermore, the dopant distribution in the molten portion may be controlled by applying a magnetic field.
[0015]
Next, as shown in FIG. 2, the formed ingot of the FZ crystal is divided into blocks 5 and doped with 2.8 × 10 ¹⁴ / cm ³ of phosphorus by neutron irradiation, so that the resistivity is 16.5 Ωcm. Then, as shown in FIG. 3, this is finished into a wafer 6 by slice lap processing. Furthermore, as shown in FIG. 4, the wafer 6 is heated in a furnace at about 1200 ° C., and vapor of phosphorus oxychloride (POCl ₃ , liquid) is supplied to the wafer 6 together with a gas of 0 ₂ / N _2. A phosphorous silicate glass (not shown) and a high-concentration shallow phosphorus diffusion layer (not shown) are formed on the surface. Then, after removing the phosphosilicate glass, heat treatment is performed for several tens to several hundreds of hours in a furnace at about 1280 ° C. (drive-in process), and after forming the deep diffusion layer 7, the diffusion wafer 8 is formed by performing single-side mirror processing To do.
[0016]
An oxide film 9 is formed on the entire surface of the obtained diffusion wafer 8 as shown in FIG. 5, and a high concentration boron, for example, is implanted and diffused in a predetermined region as shown in FIG. After that, a gate oxide film 11 is formed. Then, as shown in FIG. 7, the gate electrode 12 made of polysilicon and the base region 13 are formed by implanting boron, for example, and the source region is implanted by implanting arsenic or phosphorus, for example, as shown in FIG. After forming the region 14 and forming the interlayer insulating film 15, as shown in FIG. 9, each electrode 16 is formed to form a power MOS transistor.
[0017]
FIG. 10 shows the in-plane resistivity variation in the slice-wrapped wafer shown in FIG. In addition, as a comparative example, the dispersion | variation in the resistivity in the wafer phosphorus-doped to 16.5 ohm-cm at the time of the conventional FZ crystal formation is shown simultaneously. As shown in the figure, in the wafer according to the present embodiment, it can be seen that the variation is reduced to about 1/10 compared with the conventional one. Further, in the power MOS transistor as shown in FIG. 9, the breakdown voltage distribution corresponding to the position in the wafer plane is shown in FIG. As a comparative example, the breakdown voltage distribution in a power MOS transistor formed using a wafer doped with phosphorus up to 16.5 Ωcm without using the conventional NTD method is shown simultaneously. As shown in the figure, in the power MOS transistor according to the present embodiment, the in-plane breakdown voltage is substantially constant.
[0018]
In this embodiment, 2.8 × 10 ¹⁴ / cm ³ is doped with phosphorus by NTD, but 1.5 to 6.4 × 10 ¹⁴ / cm ³ is appropriate as the doping amount of phosphorus by NTD. . That is, 1.5 to 6.4 × 10 ¹⁴ / cm ^{3 of 30} Si existing in the wafer may be converted to ³¹ P. More preferably, it is 2.0-4.5 * 10 < ¹⁴ > / cm < ³ >. If it is less than 1.5 × 10 ¹⁴ / cm ³ , the resistivity cannot be lowered sufficiently, or the pre-dope dependency becomes high, and the variation in the in-wafer resistivity cannot be sufficiently reduced. On the other hand, if it exceeds 6.4 × 10 ¹⁴ / cm ³ , the doping time by NTD becomes long, and the irradiation request destination cannot cope with the processing capability.
[0019]
Further, although it varies depending on the required resistivity of the semiconductor wafer (7.5 to 25 Ωcm for a medium withstand voltage), 75 to 95% of the total dope is appropriate for doping by NTD. More preferably, it is 80 to 90% of the total dope amount. If the doping amount by NTD is less than 75%, the amount of pre-doping at the time of forming the FZ crystal is increased and the variation in the in-wafer resistivity is sufficiently reduced, although it is improved as compared with the doping at the time of forming the conventional FZ crystal. I can't. On the other hand, if it exceeds 95%, the doping time by NTD becomes long, and it becomes difficult to sufficiently obtain the effect of shortening the doping time by performing pre-doping before NTD.
[0020]
In this embodiment, phosphorus is doped by pre-doping, but other N-type impurities such as As and Sb may be used.
[0021]
In the present embodiment, the power MOS transistor is formed from the obtained semiconductor wafer, but it can be used for other medium-voltage semiconductor devices such as an NPN bipolar transistor.
[0022]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of a semiconductor wafer with high uniformity of in-plane resistivity, and the manufacturing method of a semiconductor device with a small withstand pressure | voltage fluctuation can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing a manufacturing process of a semiconductor wafer in one embodiment of the present invention.
FIG. 2 is a diagram showing a manufacturing process of a semiconductor wafer in one embodiment of the present invention.
FIG. 3 is a diagram showing a manufacturing process of a semiconductor wafer in one embodiment of the present invention.
FIG. 4 is a view showing a manufacturing process of a semiconductor wafer in one embodiment of the present invention.
FIG. 5 is a diagram showing a manufacturing process of a power MOS transistor in one embodiment of the present invention.
FIG. 6 is a diagram showing a manufacturing process of a power MOS transistor in one embodiment of the present invention.
FIG. 7 is a diagram showing a manufacturing process of the power MOS transistor in one embodiment of the present invention.
FIG. 8 is a diagram showing a manufacturing process of the power MOS transistor in one embodiment of the present invention.
FIG. 9 is a diagram showing a manufacturing process of the power MOS transistor in one embodiment of the present invention.
FIG. 10 is a diagram showing variation in resistivity within a surface.
FIG. 11 is a diagram showing a breakdown voltage distribution of a power MOS transistor corresponding to a position in the wafer plane.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 FZ single crystal 2 High frequency heating coil 3 Molten part 4 Polycrystalline silicon rod 5 Block 6 Wafer 7 Diffusion layer
8 Diffusion wafer 9 Oxide film 10 Guard ring 11 Gate oxide film 12 Gate electrode 13 Base region 14 Source region 15 Interlayer insulating film 16 Electrode

Claims (5)

Forming a silicon crystal by a floating zone method and injecting an N-type impurity at a predetermined concentration;
A method of manufacturing a semiconductor wafer, comprising a second implantation step of irradiating the silicon crystal with neutrons after the first implantation step and implanting a predetermined concentration of phosphorus. 2. The method of manufacturing a semiconductor wafer according to claim 1, wherein 80 to 90% of the impurity amount is implanted in the second implantation step. 3. The method of manufacturing a semiconductor wafer according to claim 1, wherein the N-type impurity implanted in the first implantation step is phosphorus. 4. The method of manufacturing a semiconductor wafer according to claim ³ , wherein the phosphorus concentration implanted in the second implantation step is 1.5 to 6.4 × 10 ¹⁴ / cm ³ . Forming a silicon crystal by a floating zone method and injecting an N-type impurity at a predetermined concentration;
After the first implantation step, a second implantation step of irradiating the silicon crystal with neutrons and injecting a predetermined concentration of phosphorus;
Forming a semiconductor wafer from the silicon crystal;
Forming an impurity diffusion region at a predetermined position of the semiconductor wafer;
A method of manufacturing a semiconductor device, comprising: forming an electrode on the semiconductor wafer.

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