JP2005012074A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a fine contact hole using a KrF lithography technique. <P>SOLUTION: A TEOS film as an interlayer insulating film 2 is formed on a silicon substrate 1 to have a thickness larger than a desired film thickness, e.g., to have a thickness of 2,000 nm. A resist pattern 3 is formed on a TEOS (tetraethylorthosilicate) film 2 using the KrF lithography technique. The substrate is etched with use of the resist pattern 3 as a mask to form a contact hole 4 in the TEOS film 2. The diameter of the contact hole 4 is reduced by etching back the upper layer of the TEOS film 2, for example, by about 1,000 nm. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a fine contact hole.
[0002]
[Prior art]
As semiconductor devices have been highly integrated and miniaturized in recent years, gate electrodes have been made thinner and gate insulating films have been made thinner. As a result, the fine processing limit is being reached also in the contact formation process for connecting the substrate and the wiring layer.
The next-generation technology currently being developed is called a 90 nm node, and the hole diameter of the contact hole is about 120 nm. To achieve this hole diameter, it is necessary to use an exposure apparatus whose light source an ArF excimer laser and F ₂ excimer laser. That is, a contact hole diameter of 120 nm or less could not be achieved using an exposure apparatus that uses a KrF excimer laser currently applied in mass production as a light source.
[0003]
[Problems to be solved by the invention]
However, for example, in order to introduce an exposure apparatus using a new light source such as an ArF excimer laser or an F ₂ excimer laser, there is a problem that a large capital investment is required for a semiconductor manufacturing factory. Further, when an exposure apparatus using a new light source is introduced, there is a problem that the process development period is prolonged, such as development of a resist for the light source.
[0004]
The present invention has been made to solve the above-described conventional problems, and an object thereof is to form a fine contact hole by using a KrF lithography technique.
[0005]
[Means for solving the problems]
A method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film on a substrate,
Forming a connection hole in the interlayer insulating film;
Removing the upper layer portion of the interlayer insulating film after forming the connection hole;
It is characterized by including.
[0006]
In the manufacturing method according to the present invention, it is preferable to remove the upper layer portion of the interlayer insulating film so that a desired connection hole diameter is obtained.
[0007]
In the manufacturing method according to the present invention, it is preferable that an upper layer portion of the interlayer insulating film is removed by etch back.
[0008]
In the manufacturing method according to the present invention, it is preferable that the step of forming the connection hole and the step of removing the upper layer portion of the interlayer insulating film are performed with the same etching apparatus.
[0009]
In the manufacturing method according to the present invention, a first interlayer insulating film is formed as the interlayer insulating film, and a second interlayer insulating film is formed on the first interlayer insulating film,
Forming the connection hole in the second interlayer insulating film;
It is preferable that the upper layer portion of the second interlayer insulating film is removed and the connection hole formed in the second interlayer insulating film is extended into the first interlayer insulating film.
[0010]
A method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film having a thickness of 1000 nm to 2500 nm on a substrate,
Forming a resist film on the interlayer insulating film;
Transferring a pattern to the resist film using a KrF laser and forming a resist pattern;
Forming a connection hole in the interlayer insulating film by dry etching the interlayer insulating film using the resist pattern as a mask;
Removing the resist pattern;
Removing the upper layer portion of the interlayer insulating film by etch back;
It is characterized by including.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.
[0012]
Embodiment 1 FIG.
FIG. 1 is a process sectional view for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
First, as shown in FIG. 1A, a TEOS film as an interlayer insulating film 2 is formed with a film thickness of 2000 nm on a silicon substrate as a substrate 1 by using a plasma CVD method. Here, the film thickness of the interlayer insulating film 2 is preferably, for example, 1000 nm to 2500 nm. This is because the effect of the present invention cannot be obtained when the film thickness of the interlayer insulating film 2 is less than 1000 nm, or the obtained effect is insufficient. When the film thickness exceeds 2500 nm, the aspect ratio of the contact hole This is because it exceeds 15 and etching processing becomes difficult. The deposition temperature of the interlayer insulating film 2 is, for example, 600 ° C.
Next, a resist pattern 3 having an opening with a diameter of, for example, 170 nm is formed on the TEOS film 2 using a known lithography technique such as a KrF lithography technique. Specifically, after a resist film is formed on the TEOS film 2, a resist pattern 3 is formed by transferring the pattern onto the resist film using a KrF excimer laser as a light source.
[0013]
Next, as shown in FIG. 1B, a contact hole reaching the silicon substrate 1 from the surface of the TEOS film 2 is formed as the connection hole 4 by dry etching using the resist pattern 3 as a mask. An ICP etching apparatus can be used for etching the TEOS film 2. Etching conditions are, for example, C ₄ F ₆ : O ₂ : Ar flow rate = 50: 20: 200 sccm; pressure: 50 mTorr; RF power (Top / Bias) = 2000/2800 W; cathode electrode temperature: −10 ° C. . The hole diameter of the contact hole 4 formed by such etching is, for example, about 160 nm on the surface of the TEOS film 2. The taper angle of the contact hole 4 may be 89.8 degrees or less. In addition, since the aspect ratio of the contact hole 4 formed by this etching process is 15 or less, a well-known etching technique can be used.
Subsequently, the resist pattern 3 is removed by ashing using oxygen plasma. The ICP etching apparatus can be used to remove the resist pattern 3.
[0014]
Next, as shown in FIG. 1C, the upper layer portion of the TEOS film 2 is etched back by about 1000 nm, for example. For this etch-back, the ICP etching apparatus or the parallel plate etching apparatus can be used. Etch back conditions are, for example, C ₄ F ₆ : O ₂ : Ar flow rate = 50: 50: 200 sccm; pressure: 50 mTorr; RF power (Top / Bias) = 2000/2800 W; cathode electrode temperature: −10 ° C. It is. The hole diameter after such etch back is smaller than the hole diameter after etching (after contact hole formation), for example, about 120 nm. During the etch back, the inner wall of the contact hole 4 is covered with a deposit (byproduct), so that the hole diameter of the contact hole 4 does not increase.
Here, the film thickness of the TEOS film 2 to be etched back (hereinafter also referred to as “etch back amount”) may be determined according to the hole diameter of the target. Hereinafter, the relationship between the etch back amount and the hole diameter will be described. This relationship is also applied to Embodiments 2 to 4 described later.
[0015]
FIG. 2 is a diagram showing the relationship between the etch back amount and the contact hole diameter after the etch back in the first embodiment of the present invention.
As shown in FIG. 2, assuming that the hole diameter after etching (after contact hole formation) is ra, the etch back amount is Δt, and the taper angle after etching (after contact hole formation) is θ, the hole diameter rb after etch back. Is represented by the following formula (1).
rb = ra−2Δt / tan θ (1)
That is, from the above equation (1), the etch back amount Δt may be determined so that a desired hole diameter rb is obtained.
For example, when the interlayer insulating film 2 is formed with a thickness of 2500 nm, and the contact hole 4 having a hole diameter ra of 160 nm and a taper angle θ of 89.8 degrees is formed in the interlayer insulating film 2, it is an approximation. When the etch back amount Δt is 1250 nm, the hole diameter rb is 140 nm, when the etch back amount Δt is 1600 nm, the hole diameter rb is 130 nm, and when the etch back amount Δt is 1700 nm, the hole diameter rb is 120 nm. It becomes.
[0016]
As described above, in the first embodiment, the TEOS film 2 is formed on the silicon substrate 1 to be thicker than the desired thickness, the contact hole 4 is formed in the TEOS film 2, and then the upper layer of the TEOS film 2 is formed. The part was removed by etch back. By controlling the etch back amount of the TEOS film 2, the hole diameter of the contact hole 4 can be reduced to a desired value.
Therefore, a known lithography technique such as the KrF lithography technique can be used to form the resist pattern 3 for forming the contact hole 4 (for etching the TEOS film 2). That is, a fine contact hole can be formed using KrF lithography technology. For this reason, it is not necessary to introduce an exposure apparatus using a new light source such as an ArF excimer laser or an F ₂ excimer laser, the capital investment cost can be greatly reduced, and the process development man-hour can be greatly reduced. Can do.
In the first embodiment, the etching for forming the contact hole 4, the plasma ashing of the resist pattern 3, and the etching back of the TEOS film 2 are performed using the same ICP type etching apparatus. Thereby, throughput can be improved.
[0017]
In the first embodiment, the case where the connection hole 4 is a contact hole reaching the surface of the silicon substrate 1 has been described. However, the present invention is not limited to this, and the connection hole 4 is a via hole connected to the wiring on the silicon substrate. The present invention can also be applied (the same applies to other embodiments described later).
[0018]
In the first embodiment, the upper layer portion of the TEOS film 2 is removed by etch back. However, planarization may be performed using a CMP (Chemical Mechanical Polishing) method. However, when the CMP method is used, it is necessary to appropriately remove the slurry accumulated in the contact hole (the same applies to other embodiments described later).
[0019]
In the first embodiment, the case where the TEOS film is used as the interlayer insulating film 2 has been described. However, the same effect can be obtained when BPSG, PSG, SiOF, or an organic silicon film is used (others described later). The same applies to the embodiment).
[0020]
Embodiment 2. FIG.
FIG. 3 is a process sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
The second embodiment is characterized in that semiconductor elements such as the gate insulating film 11, the gate electrode 12, and the sidewalls 13 for forming the LDD are formed before the interlayer insulating film 2 is formed.
[0021]
First, although not shown, element isolation is formed in the element isolation region of the silicon substrate 1 using an STI method or the like, and a well region is formed in the active region of the silicon substrate 1 isolated by the element isolation. Next, as shown in FIG. 3A, a gate oxide film, for example, is formed on the silicon substrate 1 as a gate insulating film 11 by a thermal oxidation method, and a fine gate electrode 12 is formed on the gate insulating film 11. To do. The structure of the gate electrode 12 is arbitrary, and examples thereof include a polysilicon gate, a tungsten gate, a silicide gate, and a salicide gate. Then, a side wall 13 for forming LDD made of, for example, a nitride film is formed on the side wall of the gate electrode 12. Although not shown, source / drain regions are formed in the upper layer of the silicon substrate 1 by ion implantation and annealing, and silicide regions such as cobalt silicide are formed as necessary.
[0022]
Next, a TEOS film as an interlayer insulating film 2 is formed to a thickness of 2000 nm using the same method as in the first embodiment (see FIG. 1A) so as to cover the gate electrode 12 on the silicon substrate 1. To do. Then, in order to reduce the level difference of the TEOS film 2, the TEOS film 2 is planarized by using a CMP method. Further, similarly to the first embodiment, a resist pattern 3 having an opening with a diameter of, for example, 170 nm is formed on the TEOS film 2 using the KrF lithography technique.
[0023]
Next, as shown in FIG. 3B, a contact hole 4 reaching the surface of the silicon substrate 1 is formed between the gate electrodes 12 by the same method as in the first embodiment (see FIG. 1B). The hole diameter of the formed contact hole 4 is, for example, about 160 nm on the surface of the TEOS film 2 as in the first embodiment. Thereafter, the resist pattern 3 is removed by ashing.
[0024]
Next, as shown in FIG. 3C, the upper layer portion of the TEOS film 2 is etched back by, for example, about 1000 nm by the same method as in the first embodiment (see FIG. 1C). The hole diameter after such etch back is smaller than the hole diameter after etching (after contact hole formation), for example, about 120 nm.
[0025]
As described above, in the second embodiment, after the semiconductor element such as the gate electrode 12 is formed, the TEOS film 2 is formed thicker than a desired film thickness, and the contact hole 4 is formed in the TEOS film 2. Thereafter, the upper layer portion of the TEOS film 2 was removed by etch back. By controlling the etch back amount of the TEOS film 2, the hole diameter of the contact hole 4 can be reduced to a desired value.
Therefore, according to the second embodiment, the same effect as in the first embodiment can be obtained.
Furthermore, according to the second embodiment, the fine contact hole 4 can be formed between the fine gate electrodes 12 using the KrF lithography technique. Thereby, an alignment margin between the gate electrode 12 and the contact hole 4 can be secured. Therefore, the alignment margin can be gained by reducing the size of the contact hole 4.
[0026]
Embodiment 3 FIG.
FIG. 4 is a process sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
The third embodiment is characterized in that the interlayer insulating film formed of a single layer in the first embodiment has a laminated structure of a first interlayer insulating film 5 and a second interlayer insulating film 6.
[0027]
First, as shown in FIG. 4A, a nitride film as a first interlayer insulating film 5 is formed with a film thickness of 50 nm on a silicon substrate 1 by LPCVD using dichlorosilane and ammonia gas. Next, a TEOS film as the second interlayer insulating film 6 is formed with a film thickness of 2000 nm on the nitride film 5 by the same method as in the first embodiment (see FIG. 1A). The deposition temperature of the nitride film 5 is, for example, 760 ° C., and the deposition temperature of the TEOS film 6 is, for example, 600 ° C.
Next, a resist pattern 3 having an opening with a diameter of, for example, 170 nm is formed on the TEOS film 6 using a known lithography technique such as a KrF lithography technique.
[0028]
Next, as shown in FIG. 4B, a contact hole 4 is formed in the TEOS film 6 by the same method as in the first embodiment (see FIG. 1B). The etching for forming the contact hole 4 stops at the surface of the nitride film 5. Then, the resist pattern 3 is removed by ashing using oxygen plasma.
[0029]
Subsequently, as shown in FIG. 4C, the upper layer portion of the TEOS film 6 is etched back by about 1000 nm, for example, and the contact hole 4 formed in the TEOS film 6 is extended into the lower nitride film 5. An ICP type etching apparatus or a parallel plate type etching apparatus can be used for this etch back. Etch back conditions are, for example, C ₄ F ₆ : O ₂ : Ar flow rate = 50: 50: 200 sccm; pressure: 50 mTorr; RF power (Top / Bias) = 2000/2800 W; cathode electrode temperature: −10 ° C. It is. The hole diameter after such etch back is smaller than the hole diameter after etching (after contact hole formation), for example, about 120 nm.
[0030]
As described above, in the third embodiment, the interlayer insulating film has a laminated structure of the nitride film 5 and the TEOS film 6. This interlayer insulating film is formed to be thicker than desired, and after forming the contact hole 4 in the TEOS film 6, the upper layer portion of the TEOS film 6 is removed by etch back and the contact hole 4 is formed in the nitride film 5. Extended. By controlling the etch back amount of the TEOS film 6, the hole diameter of the contact hole 4 can be reduced to a desired value.
Therefore, according to the third embodiment, the same effect as in the first embodiment can be obtained.
Although not shown, when the element isolation film is formed on the silicon substrate 1 and the contact hole 4 is formed on the element isolation film, the nitride film 5 can be used as an etching stopper film.
[0031]
Embodiment 4 FIG.
FIG. 5 is a process sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
The fourth embodiment is a combination of the second embodiment and the third embodiment.
[0032]
First, element isolation and well regions are formed in the silicon substrate 1 by a method similar to that of the second embodiment (see FIG. 2A). Thereafter, as shown in FIG. 5A, semiconductor elements such as a gate insulating film 11, fine gate electrodes 12, sidewalls 13, and source / drain regions are sequentially formed on the silicon substrate 1.
[0033]
Next, a nitride film 5 is formed to a thickness of 50 nm so as to cover the gate electrode 12 on the silicon substrate 1 by the same method as in the third embodiment (see FIG. 4A). The TEOS film 6 is formed with a film thickness of 2000 nm. Then, in order to reduce the level difference of the TEOS film 6, the TEOS film 6 is planarized by using a CMP method. Further, a resist pattern 3 having an opening with a diameter of, for example, 170 nm is formed on the TEOS film 6 using the KrF lithography technique.
[0034]
Next, as shown in FIG. 5B, a contact hole 4 is formed in the TEOS film 6 by the same method as in the third embodiment (see FIG. 4B). The etching for forming the contact hole 4 stops at the surface of the nitride film 5. Then, the resist pattern 3 is removed by ashing using oxygen plasma.
[0035]
Subsequently, as shown in FIG. 5C, the upper layer portion of the TEOS film 6 is etched back by, for example, about 1000 nm by the same method as in the third embodiment (see FIG. 4C), and the TEOS film 6 The contact hole 4 formed in 1 is extended into the underlying nitride film 5. The hole diameter after such etch back is smaller than the hole diameter after etching (after contact hole formation), for example, about 120 nm.
[0036]
As described above, in the fourth embodiment, after the semiconductor elements such as the gate electrode 12 are formed, the nitride film 5 and the TEOS film 6 as interlayer insulating films are formed thicker than desired. Then, after forming the contact hole 4 in the TEOS film 6, the upper layer portion of the TEOS film 6 was removed by etching back and the contact hole 4 was extended into the nitride film 5. By controlling the etch back amount of the TEOS film 6, the hole diameter of the contact hole 4 can be reduced to a desired value.
Therefore, according to the fourth embodiment, the same effect as in the second and third embodiments can be obtained. In the fourth embodiment, since the nitride film 5 is formed on the gate electrode 12, the contact hole 4 can be formed in a self-aligning manner.
[0037]
【The invention's effect】
According to the present invention, the fine contact hole can be formed using the KrF lithography technique.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view for illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a relationship between an etch back amount and a contact hole diameter after etch back in Embodiment 1 of the present invention.
FIG. 3 is a process sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 4 is a process sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention;
FIG. 5 is a process sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention;
[Explanation of symbols]
1 Substrate (silicon substrate)
2 Interlayer insulation film (TEOS film)
3 resist pattern 4 connection hole (contact hole)
5 First interlayer insulating film (nitride film)
6 Second interlayer insulating film (TEOS film)
11 Gate insulating film 12 Gate electrode 13 Side wall

Claims (6)

Forming an interlayer insulating film on the substrate;
Forming a connection hole in the interlayer insulating film;
Removing the upper layer portion of the interlayer insulating film after forming the connection hole;
A method for manufacturing a semiconductor device, comprising: The manufacturing method according to claim 1,
A method of manufacturing a semiconductor device, comprising: removing an upper layer portion of the interlayer insulating film so that a desired connection hole diameter is obtained. In the manufacturing method of Claim 1 or 2,
A method of manufacturing a semiconductor device, wherein an upper layer portion of the interlayer insulating film is removed by etch back. In the manufacturing method in any one of Claim 1 to 3,
A method of manufacturing a semiconductor device, wherein the step of forming the connection hole and the step of removing the upper layer portion of the interlayer insulating film are performed by the same etching apparatus. In the manufacturing method in any one of Claim 1 to 4,
Forming a first interlayer insulating film as the interlayer insulating film, and a second interlayer insulating film on the first interlayer insulating film;
Forming the connection hole in the second interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: removing an upper layer portion of the second interlayer insulating film; and extending the connection hole formed in the second interlayer insulating film into the first interlayer insulating film. Forming an interlayer insulating film having a thickness of 1000 nm to 2500 nm on a substrate;
Forming a resist film on the interlayer insulating film;
Transferring a pattern to the resist film using a KrF laser and forming a resist pattern;
Forming a connection hole in the interlayer insulating film by dry etching the interlayer insulating film using the resist pattern as a mask;
Removing the resist pattern;
Removing the upper layer portion of the interlayer insulating film by etch back;
A method for manufacturing a semiconductor device, comprising:

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