JP2005006145A - Terminal equipment for data communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable operation even in the environment of a limited memory resource (RAM) when performing BCH encoding/decoding processing by saving the memory resource (RAM) for BCH coded data in terminal equipment for data communication. <P>SOLUTION: The terminal equipment for data communication performs data communication between a calling station and a called station, and includes a RAM (random access memory) for temporarily storing communication data and a microcomputer for data communication control. The data communication is performed using the BCH code. The terminal equipment further includes an error correction processor which performs distributed encoding and/or decoding processing in real time on a transmission/reception bit-by-bit basis. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a BCH error correction process for correcting a data error included in transmission / reception data in a data communication terminal device incorporating a RAM (random access memory) and a microcomputer (microcomputer).
[0002]
[Prior art]
As an error correction process of a data communication terminal device, an error correction method disclosed in JP-A-5-74066 has been conventionally known. In this error correction method, BCH code data is collectively encoded / decoded before transmission and after reception. For this reason, by holding the memory data in the RAM storing all the raw data and the BCH code data until transmission / reception is completed, about twice as much memory resources (RAM) as the raw data are required.
[0003]
In the case of a system that transmits and receives 256 bytes, a memory resource (RAM) of 256 × 2 512 bytes at the time of transmission and 256 × 2 512 bytes at the time of reception and a total of 1024 bytes is required.
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 5-74066
[Problems to be solved by the invention]
However, this error correction method has the following problems. That is, in this error correction method, since BCH code data is encoded / decoded before transmission and after reception, memory resources (RAM) storing all raw data and BCH code data are completely transmitted / received. , There is a problem that requires about twice as much memory resources (RAM) as raw data.
[0006]
The present invention has been made to solve such problems, and an object of the present invention is to provide a data communication terminal device that can operate even in an environment where memory resources (RAM) required for BCH code data are restricted. .
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a data communication terminal device according to claim 1 includes a RAM (random access memory) for temporarily storing communication data and a microcomputer (microcomputer) for controlling data communication. In a data communication terminal device that performs data communication between a calling station and a called station, data communication is performed using a BCH code, and encoding and / or decoding is distributed in real time for each bit transmission / reception. An error correction processing unit is provided.
[0008]
According to a second aspect of the present invention, there is provided a data communication terminal device comprising a one-chip microcomputer integrally including the RAM and the microcomputer.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a data communication terminal device according to the invention will be described with reference to the accompanying drawings.
[0010]
First, an error correction process using BCH (31, 16) that assigns a 15-bit error control code to 16-bit unit data and an error-coded data transmission process method will be described with reference to FIG.
[0011]
In the case of a system in which the transmission data has a maximum of 256 bytes, a 256-byte transmission raw data area and a 2-byte BCH code data area are prepared during transmission processing. A total of 258 byte memory resources (RAM) of 256 + 2 are required as the fixed area amount.
[0012]
In error correction using BCH (31, 16), since the code part is 15 bits, 2 bytes are prepared as a BCH code data area. The 16th bit of the BCH code data area is an even parity boundary.
[0013]
Code data transmission using BCH (31, 16) repeats 16-bit data transmission → 16-bit BCH code data transmission → 16-bit data transmission →.
[0014]
[Step 1] The raw data to be transmitted is stored in the transmission raw data area. As the next transmission bit data, the first bit of the transmission raw data area is designated and a transmission start request is made.
[0015]
[Step 2] In the transmission processing for each bit, it is determined whether the bit data to be transmitted next is a raw data portion or a BCH code data portion.
[0016]
[Step 3] If the bit data to be transmitted next is a raw data portion, an operation for creating a BCH code data portion is performed based on the bit data value. Performs computation by the generator polynomial ^{G (X) = X 15 +} X 11 + X 10 + X 9 + X 8 + X 7 + X 5 + X 3 + X 2 + X + 1 of the BCH (31,16) for every 1 bit, sequential data into BCH code data area accumulate. The BCH code data is determined at the time of transmission of the last bit (16th bit in 16-bit units) of the raw data portion. After the calculation is completed, the bit data value of the raw data that is the basis of the calculation is designated as the next transmission bit data.
[0017]
[Step 4] When the bit data to be transmitted next is BCH code data, the next transmission bit data value in the data stored in the BCH code data area is designated as the next transmission bit data. The BCH code data area is released after transmission of 16 bits of BCH code data is completed, and functions as a BCH code data area of 16-bit raw data. The BCH code data area is always fixed regardless of the amount of the raw data area.
[0018]
[Step 5] The bit data designated as the next transmission bit data is transmitted.
[0019]
[Step 6] If transmission of all transmission data has been completed, the error encoded data transmission processing is terminated. If transmission data still remains, repeat from [Step 3].
[0020]
Next, the error decoding reception processing method will be described. In the case of a system in which the received data is a maximum of 256 bytes, a 256-byte received raw data area and a BCH (31, 16) generator polynomial G (X) = X ¹⁵ + X ¹¹ + X ¹⁰ + X ⁹ + X ⁸ + X at the time of reception processing ⁷ + X ⁵ + X ³ + X ² + X + 1 3 primitive polynomials g1 (X) = X ⁵ + X ² +1, g2 (X) = X ⁵ + X ⁴ + X ³ + X ² +1, g3 (X) = X ⁵ + X ⁴ For + X ² + X + 1, an area of BCH primitive polynomial divider circuit calculation results for 1 byte is prepared. A total of 259 byte memory resources (RAM) of 256 + 3 are required as the fixed area amount.
[0021]
Code data reception using BCH (31, 16) repeats 16-bit data reception → 16-bit BCH code data reception → 16-bit data reception →.
[0022]
[Step 21] One bit of data is received.
[0023]
[Step 22] Divide circuit information calculation of each primitive polynomial necessary for error correction (BCH decoding) is performed from the received bit data. The calculation is performed every time from the first bit of the data part to the last bit of the continuous BCH part, and the result is stored in each BCH primitive polynomial divider circuit calculation result each time.
[0024]
[Step 23] Each time the last bit of the BCH part is received (32-bit reception), the error bit is confirmed from the calculation result of each BCH primitive polynomial divider circuit, and the error of the received data area is corrected. If there are no errors, do not correct.
[0025]
[Step 24] When the specified data amount is received, the reception process is completed.
[0026]
【The invention's effect】
As described above, according to the data communication terminal device of the first aspect, the RAM (random access memory) having a limited storage capacity for temporarily storing the communication data and the microcomputer (microcomputer) for performing the data communication control, In a data communication terminal device that performs data communication between a calling station and a called station, performs data communication using a BCH code, and performs encoding and / or decoding for each bit transmission / reception By including an error correction processing unit that performs distributed processing in real time, it is possible to reliably perform operation even in an environment where memory resources (RAM) are restricted.
[0027]
Further, according to the data communication terminal device according to claim 2, in the data communication terminal device according to claim 1, the component is constituted by a one-chip microcomputer integrally including the RAM and the microcomputer. As the number of points is reduced, low cost, space saving, and high reliability can be achieved.
[Brief description of the drawings]
FIG. 1 is a flowchart of transmission processing of error correction encoded data of a data communication terminal device according to the present invention.
FIG. 2 is a flowchart of reception processing of error correction encoded data in the data communication terminal device according to the present invention.

Claims (2)

A data communication terminal device that incorporates a RAM (random access memory) that temporarily stores communication data and a microcomputer (microcomputer) that performs data communication control and performs data communication between a calling station and a called station In
What is claimed is: 1. A data communication terminal device comprising an error correction processing unit that performs data communication using a BCH code and performs distributed processing in real time for each bit transmission and reception for encoding and / or decoding. 2. The data communication terminal device according to claim 1, wherein the data communication terminal device comprises a one-chip microcomputer integrally including the RAM and the microcomputer.

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