JP2005005687A - Plasma etching method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma etching method for an interlayer insulation film which prevents crown fence formation. <P>SOLUTION: (a) A via resist 306 is formed on a via BARC 305. (b) The via BARC 305 is etched by using the via resist 306 as a mask. (c) A capping film 304 and an interlayer insulation film 303 are etched to an etching stopper film 302 to form a via hole (VH) 307a. (d) The via resist 306 and the via BARC 305 are removed. (e) A trench BARC 308 is formed on the capping film 304 and in the VH 307a, and then a trench resist 309 having a trench pattern 310 is formed on the trench BARC 308. (f) The trench BARC 308 formed on the interlayer insulation film 303 and in the VH 307a is etched so that the height of the trench BARC is always lower than the trench bottom. (g) The capping film 304 and the interlayer insulation film 303 are etched to form a trench 310a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a plasma processing method in a plasma processing apparatus, and more particularly to a plasma etching processing method suitable for processing a low dielectric constant interlayer insulating film material.

  Semiconductor LSIs are not only miniaturized as the speed increases, but also the wiring material has shifted to Cu for lower resistance. However, since Cu dry etching is technically difficult, after the interlayer insulating film disposed around the Cu wiring is first etched, Cu is embedded by plating or the like, and planarization CMP (Chemical Mechanical Polishing) is performed on the upper part of the wiring. Damascene technology is employed in which excess Cu in the wiring is scraped and used as wiring.

  Among the damascene technologies, a dual damascene process is used in which a connection hole with a lower layer wiring is etched at the same time as the wiring groove. As an application, the connection hole connecting the lower layer wiring is formed before the upper layer wiring. A via first (Dia First) dual damascene process is being adopted (see, for example, Patent Document 1).

  The via first dual damascene process makes it possible to simplify the manufacturing process and shorten TAT (Turn and Around Time) in an etching process for forming a connection hole for connecting an upper layer wiring and a lower layer wiring. There exists an advantage that manufacturing cost can be reduced significantly (for example, refer to patent documents 1).

The steps of a conventional via first dual damascene process will be described with reference to the cross-sectional views of FIGS. First, as shown in FIG. 1A, a lower layer wiring 101 made of Cu is formed, and an etching stopper film 102 made of SiC is formed thereon. Next, an interlayer insulating film 103 made of SiOC is formed, and a cap film 104 made of, for example, SiO ₂ is formed thereon. Next, an antireflection film 105 made of BARC (Bottom Anti Reflective Coating) is formed, and a via resist 106 is formed thereon. A via hole pattern 107 for fine holes is formed in the via resist 106.

  Using the via resist 106 as a mask, the antireflection film 105 is etched as shown in FIG. 1B, and then the interlayer insulating film 103 is etched following the cap film 104 as shown in FIG. 1C. Etching is performed up to the stopper film 102 to form a via hole 107a.

  Next, after removing the via resist 106 and the via antireflection film 105 as shown in FIG. 1D, a trench antireflection film 108 is formed as shown in FIG. A trench resist 109 is formed thereon. At this time, the trench antireflection film 108 is buried in the via hole 107a, and a trench pattern 110 for a fine wiring groove is formed in the trench resist (trench mask) 109. .

  After the trench antireflection film 108 is etched using the trench mask 109 as shown in FIG. 1 (f), the interlayer insulating film 103 is continued from the cap film 104 as shown in FIG. 1 (g). Is etched to a desired film thickness to form a trench 110a.

At this time, the trench antireflection film 108 and the interlayer insulating film 103 embedded in the via are etched at the same time. However, when the selection ratio of the interlayer insulating film 103 to the antireflection film 108 in the via is high (interlayer insulating film etching rate). / Antireflection film etching rate> 1) Since the antireflection film 108 in the via is etched with a delay, an etching residue occurs. Etching residue of the antireflection film is generated at the facet portions of the via hole and the trench, and reaction products during trench etching are deposited starting from this, and as shown in FIG. 1G, a ring-shaped crown fence 111 is formed. Is formed.
JP 2001-102449 A

  In the via first dual damascene process, a trench groove and a via hole are formed, and then a metal material such as Cu is embedded therein. At this time, a metal film must be coated on the trench groove and the inner wall of the via hole in advance. However, the formation of the crown fence as described above causes a problem in covering with the metal film, and the subsequent process of embedding of a metal material such as Cu cannot be sufficiently formed, and the characteristics of the device are greatly deteriorated. Become.

  An object of the present invention is to provide an etching method that prevents a crown fence formed during etching of an interlayer insulating film in a via first dual damascene process, obtains a desired processing shape, and does not impair the characteristics of the interlayer insulating film Is to provide.

  The present invention provides a plasma etching method having a dual damascene structure in which a hole is formed in an insulating film on a substrate, an antireflection film is embedded in the formed hole, and a trench is formed in the embedded portion. The above problem is solved by having a step of preferentially etching the antireflection film embedded in the hole with an oxygen gas of 0.3 Pa to 3.0 Pa as a pre-process for forming the film.

  The present invention relates to a plasma etching processing method using a via first dual damascene process for forming a dual damascene structure on an insulating film on a substrate, the step of forming holes in the insulating film on the substrate, and the formation A step of embedding an antireflection film in the formed hole, a step of etching the embedded antireflection film with an oxygen gas of 0.3 Pa to 3.0 Pa, and a step of forming a trench after the etching To achieve the above-mentioned problems.

In the processing method, the present invention provides that the oxygen gas flow rate is in the range of 5 to 300 ml / min, the bias power density applied to the substrate is 1 W / cm ² or less, and the substrate temperature is The said subject is achieved by being between 20 degreeC-80 degreeC.

  According to the present invention, it is possible to suppress the formation of the crown fence without deteriorating the characteristics and processed shape of the interlayer insulating film. As a result, a highly reliable semiconductor LSI can be manufactured.

An embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a sectional view showing a schematic configuration of a UHF wave ECR plasma etching apparatus to which the etching method according to the present invention is applied. In this etching apparatus, oxygen, CF-based gas (for example, CF ₄ ), Ar gas, etc. are provided on the surface of the upper antenna 201 from a cylinder through a gas pipe and a mass flow controller (not shown) in an evacuated etching processing chamber 200. The fine holes are supplied to the processing chamber 200 as a shower. Moreover, it adjusts to a desired pressure with a variable valve (not shown).

  Next, a high frequency generated from the UHF power source 202 having a frequency of 450 MHz is introduced into the processing chamber via the matching filter circuit 203 and the upper antenna 201. The interaction between the magnetic field formed by the coil 204 arranged around the processing chamber and the power source of the UHF wave generates ECR discharge, dissociates the etching gas, and forms the plasma 205. Further, a high frequency generated from an RF bias power supply 211 having a frequency of 13.56 MHz is applied to the upper antenna 201 via the matching filter circuit 212, F is consumed on the antenna surface, and the composition of active species in the plasma is changed. It is a device configuration that can. A substrate 207 is placed on a substrate placement electrode 206 provided below the processing chamber. In this example, a substrate having a diameter of 200 mm was used. An 800 KHz RF bias power source 208 is connected to the substrate mounting electrode 206 via a matching filter circuit 209. As a result, ions in the plasma are drawn onto the substrate, and anisotropic etching proceeds by an ion-assisted reaction by interaction with radicals adsorbed on the surface. The reaction product generated during the etching is exhausted by the turbo pump 210.

  A processing step of a via first dual damascene process for preventing the formation of a crown fence using the plasma etching apparatus will be described with reference to cross-sectional views of FIGS. The processing steps shown in FIGS. 3 (a) to 3 (e) are the same as those in FIGS. 1 (a) to 1 (e), which are the steps of the conventional via first dual damascene described above, and thus description thereof is omitted. To do. The reference number 100 in FIG. 1 shows the same contents as the reference number 300 in FIG.

  As shown in FIG. 3F, following the etching of the trench antireflection film 308 formed on the interlayer insulating film 303, a certain amount of the trench antireflection film 308 embedded in the via hole 307a is etched. As shown in FIG. 3G, the amount of etching is appropriately determined so that the height of the antireflection film is always lower than the bottom of the trench when the interlayer insulating film 303 is etched.

  The details of the etching process processed by such a method will be described below. Table 1 shows the trench antireflection film etching conditions. That is, the etching conditions of the antireflection film for trench are as follows: plasma source power: 400 W, oxygen flow rate: 20 ml / min, processing pressure: 0.3 pa, substrate temperature: 80 ° C., substrate applied power: 200 W (8 inch wafer) Carried out.

  Moreover, in the said Example, although board | substrate application electric power was demonstrated with 200W, this invention is not limited to this figure. That is, it was confirmed that the power applied to the substrate was effective up to a range of 300 W in consideration of damage-lessness to the substrate.

  Next, the processing pressure dependence of the etching rate of the resist film under the conditions shown in Table 1 will be described with reference to FIG. As shown in the figure, the etching rate of the resist film depends on the processing pressure. When the interlayer insulating film is a low dielectric constant insulating film, there is a concern that the relative dielectric constant increases due to etching, but according to the process conditions of the present invention, the relative dielectric constant of the interlayer insulating film 303 is 3.0. The increase was not observed.

  Further, as shown in FIG. 3F, no change was observed in the width dimension of the resist pattern.

  The processing conditions in Table 1 can be appropriately changed according to the type of the via hole buried film and the interlayer insulating film, and the buried film is etched within the range shown in Table 2 without impairing the characteristics. I was able to.

  Next, FIG. 5 shows changes in the relative dielectric constant in the range shown in Table 2. That is, the conditions for etching the antireflection film for trench are as follows: oxygen flow rate: 5 to 300 ml / min, processing pressure: 0.3 to 1.0 Pa, substrate temperature: 20 to 80 ° C., substrate applied power: 0 to 300 W (8 inches) Various types can be changed within the range of (wafer).

  Thereafter, as in the conventional case, as shown in FIG. 3G, the interlayer insulating film 303 is etched to a desired film thickness after the cap film 304 to form a trench 310a. At this time, the trench antireflection film 308 and the interlayer insulating film 303 embedded in the via are etched simultaneously, but the antireflection film in the via hole is sufficiently etched by the etching method described above. The generation of the crown fence could be suppressed.

  Next, application examples according to the present invention will be described with specific numerical values with reference to cross-sectional views of FIGS. 3 (e) to 3 (g). 3E, the thickness of the trench resist 309 is 600 nm, the thickness of the trench antireflection film 308 is 100 nm, the thickness of the cap film 304 is 50 nm, and the thickness of the interlayer insulating film 303 is 600 nm. The film thickness of the antireflection film embedded in 308 is 750 nm (film thickness of antireflection film 308 for trench + film thickness of cap film 304 + film thickness of interlayer insulating film 303 = film thickness of antireflection film 308 embedded in hole 307a). is there.

  As shown in FIG. 3F, the antireflection film 308 is etched under the etching conditions shown in Table 1. At this time, the antireflection film 308 buried in the hole 307a is also etched at the same time. The etching rate of the antireflection film 308 for trenches and the antireflection film 308 embedded in the holes 307a is about 350 nm / min, as shown in FIG.

  Further, the etching rate of the cap film 304 is 0 nm / min because it is etching with oxygen gas. The etching time at this time was 1 minute. Therefore, the film thickness of the antireflection film 308 embedded in the hole 307a shown in FIG. 3F is 400 nm.

Next, as shown in FIG. 3G, the cap film 304 and the interlayer insulating film 303 are etched at 300 nm / min, the antireflection film 308 embedded in the hole 307a is etched at 150 nm / min, and the selection ratio = 2 ( When the etching is performed in 1 minute to the depth of the trench 310a of 300 nm with an etching gas such as Ar / CF ₄ / CHF ₃ by the etching speed of the interlayer insulating film 303 / the etching speed of the antireflection film 308 embedded in the hole 307a) The film thickness of the antireflection film 308 embedded in 307a is 250 nm, and the crown fence can be prevented by keeping the height of the antireflection film 308 always lower than the bottom of the trench 310a.

Sectional drawing which shows the process of the conventional via first dual damascene process. Sectional drawing which shows schematic structure of the UHF wave ECR plasma etching processing apparatus used in order to show one Example of the plasma processing method of this invention. Sectional drawing which shows the process process of the via first dual damascene process for preventing the crown fence formation which is an Example of this invention. The pressure dependence of the etching rate of a resist film in the case of using an etching process condition for suppressing the formation of a crown fence according to an embodiment of the present invention. The pressure and oxygen gas flow rate dependence of a dielectric constant when the etching process conditions for suppressing the crown fence formation which is an Example of this invention are used.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Lower layer wiring, 102 ... Etching stopper film, 103 ... Interlayer insulating film, 104 ... Cap film, 105 ... Antireflection film for via, 106 ... Via resist, 107 ... Via hole pattern, 107a ... Via hole, 108 ... Reflection for trench Preventive film 109 ... Resist for trench, 110 ... Pattern for trench, 110 a ... Trench, 111 ... Crown fence, 200 ... Processing chamber, 201 ... Antenna, 202 ... UHF power supply, 203 ... Matching filter circuit, 204 ... Coil, 205 ... Plasma, 206 ... Substrate mounting electrode, 207 ... Substrate, 208 ... Matching filter circuit, 209 ... RF bias power supply, 210 ... Turbo pump, 211 ... RF bias power supply, 212 ... Matching filter circuit, 301 ... Lower layer Wiring 302 ... Etching stopper film 303 ... Interlayer insulating film 304 ... Cap film 305 Anti-reflection film for via 306 Via resist 307 Via hole pattern 307a Via hole 308 Anti-reflection film for trench 309 ... Resist for trench, 310 ... Pattern for trench, 310a ... Trench

Claims (6)

In a dual damascene plasma etching method, a hole is formed in an insulating film on a substrate, an antireflection film is embedded in the formed hole, and a trench is formed in the embedded portion.
A plasma etching processing method comprising a step of preferentially etching an antireflection film embedded in the hole with an oxygen gas of 0.3 Pa to 3.0 Pa as a pre-process for forming the trench. In a plasma etching method using a via first dual damascene process for forming a dual damascene structure on an insulating film on a substrate,
Forming a hole in the insulating film on the substrate; embedding an antireflection film in the formed hole; and preferentially filling the embedded antireflection film with an oxygen gas of 0.3 Pa to 3.0 Pa. And a step of forming a trench after etching. A plasma etching method comprising: In the plasma etching processing method according to claim 1 or 2,
A plasma etching method, wherein an oxygen gas flow rate is in a range of 5 to 300 ml / min. In the plasma etching processing method according to claim 1 or 2,
A plasma etching method, wherein a bias power density applied to a substrate is 1 W / cm ² or less. In the plasma etching processing method according to claim 3,
A plasma etching method, wherein a bias power density applied to a substrate is 1 W / cm ² or less. In the plasma etching processing method of Claim 5,
A plasma etching method, wherein the substrate temperature is between 20 ° C. and 80 ° C.

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