JP2004529378A - Alternating phase shift masking for multi-level masking resolution - Google Patents

Abstract

The method and system of the present invention produces an alternating phase shift mask for multiple phase shift mask resolution levels for multiple build classes. The method includes processing a pattern defining a first and second build class of features in the layer for a photolithographic mask defining the layer; and a phase shift window pair for a first build resolution level. Defining a first layout dimension for the phase shift window pair for a second build resolution level; and a first layout dimension for the phase shift window pair for the first build class. Laying out a plurality of phase shift window pairs, comprising: using a second layout dimension for the phase shift window pair for the second build class; Assigning the first and second phase shift values to the phase shift windows within the shift window pair. This process results in the creation of a set of masks for defining layers of material in the integrated circuit or other workpiece. The set of masks comprises a first mask having a plurality of phase shift window pairs in an opaque field for defining a structure in a layer defined by each phase shift window. The first mask has a plurality of phase shift windows in an opaque field for defining a structure in the layer defined by each phase shift window. A phase shift window in the plurality of phase shift windows includes respective first and second class windows, wherein the first class has a width dimension based on a first layout width; The second class has a width dimension based on a second layout width, and the first layout width is larger than the second layout width.
[Selection diagram] Fig. 1

Description

【Technical field】
[0001]
The present invention relates to manufacturing small-sized features of objects, such as integrated circuits, using photolithographic masks. More precisely, the invention relates to the use of phase shift masking for complex layouts for integrated circuits and similar objects.
[Background Art]
[0002]
Phase shift masking has been used to create small size features in integrated circuits, as described in US Pat. No. 5,858,580. Typically, these features have been limited to selected elements of the design, having small and crisp dimensions. While manufacturing small size features in integrated circuits has resulted in improved speed and performance, it is desirable to apply phase shift masking more widely in the manufacture of such devices. However, expanding phase shift masking to more complex designs has greatly increased the complexity of the mask layout problem. For example, when laying out phase shift zones in a high density design, phase conflicts will occur. One type of phase conflict is that two phase shifted regions having the same phase are exposed by a mask, for example, overlapping the phase shifted regions to draw adjacent lines in the exposure pattern. This is a position selection in the layout that is laid out near the modeling. If the phase shifting regions have the same phase, they will not cause the necessary optical interference to produce the desired effect. Therefore, it is necessary to prevent inadvertent layout of the phase shift region that competes with the phase. See Wu et al., "Alternate PSM Design and the Flow from Design to Manufacturing," SAME, Oct. 26, 2000.
[0003]
Another problem with the layout of complex designs that rely on small size features arises because of the isolated exposed space having narrow dimensions between unexposed areas or lines.
[0004]
One factor that adds difficulty to the process of laying out complex patterns using phase shift masking is that the width of the phase shift region results in a direction orthogonal to the sides between the opposite phase regions. Occurs because it has a significant effect on the image. If the width is too narrow, the resulting image may have a wider line width. If the width is too wide, the size of the phase shifter for one feature will begin to interfere with adjacent features in the layout. Furthermore, if adjacent features also use the phase shift region, undesirable phase conflicts may occur along the sides of the phase shift region.
[0005]
Because of these and other complications, applying phase shift masking techniques to complex designs requires an improved approach to phase shift mask design and the establishment of new phase shift layout techniques.
[0006]
[Patent Document 1]
U.S. Pat. No. 5,858,580
[Non-patent document 1]
"Alternate PSM Design and Flow from Design to Manufacturing" Wu et al., SAME, October 26, 2000.
DISCLOSURE OF THE INVENTION
[Means for Solving the Problems]
[0007]
The present invention provides a method and system for manufacturing an alternating phase shift mask that uses multiple phase shift mask resolution levels for multiple build classes. In some embodiments, the method includes:
Processing a pattern defining a first and second build class of features in the layer for a photolithographic mask defining the layer;
Defining a first layout dimension for the phase shift window pair for the first build resolution level and a second layout dimension for the phase shift window pair for the second build resolution level;
Using a first layout dimension for a phase shift window pair for the first build class and using a second layout dimension for a phase shift window pair for the second build class; Laying out a plurality of phase shift window pairs;
Assigning first and second phase shift values to the phase shift windows in the plurality of phase shift window pairs.
[0008]
In one embodiment, the processing includes reading a layout file identifying dimensions of the features in the pattern, and processing the layout file to identify features in first and second modeling classes. , Including. The features in the first modeling class have line segments with a first line width, for example, corresponding to transistor gates, and the features in the second modeling class have line segments with a second line width. However, for example, it corresponds to a narrow interconnection line for connecting to a small transistor gate, and the first line width is smaller than the second line width. Another example is both transistor gates to form two classes of transistors characterized by slightly different channel widths.
[0009]
In one embodiment of the present invention, there is provided an apparatus comprising means for performing the above process.
[0010]
The process of some embodiments results in the fabrication of a set of masks for defining layers of material in an integrated circuit or other workpiece. The set of masks comprises a first mask having a plurality of phase shift window pairs in an opaque field for defining a structure in a layer defined by each phase shift window. The first mask has a plurality of phase shift windows in an opaque field for defining a structure in the layer defined by each phase shift window. A phase shift window in the plurality of phase shift windows includes respective first and second class windows, wherein the first class has a width dimension based on a first layout width; The second class has a width dimension based on a second layout width, and the first layout width is larger than the second layout width.
[0011]
The phase shift window has a width dimension based on the layout width when the phase shift window is laid out using another feature after the overlay, and the phase shift area overlaps with another phase shift area. In that case, the width of at least one segment of the phase shift zone has a width equal to the layout width.
[0012]
The set of masks includes a second mask having a second opaque area and a transparent area, the second opaque area defining an interconnect structure in the layer and a plurality of phase shifts. This is for interconnecting the structures defined by the shift windows and preventing erasure of the structures defined by the phase shift windows.
[0013]
In this way, the images exposed by the first class of phase shift window pairs have smaller dimensions than the images exposed by the second class of phase shift window pairs. The present invention is extendable to any number of classes of phase shift windows characterized by different widths, or other characteristics, resulting in multiple classes having different resolutions as a result of the different classes of characteristics. Provide images of modeling classes.
[0014]
In one embodiment, the invention is a method comprising processing a pattern defining exposed and unexposed regions for a lithographic mask defining a layer. The exposed areas in the pattern having dimensions smaller than the size of the first feature are identified as a first class feature. An exposed area in the pattern having a dimension smaller than the size of the second feature and greater than the size of the first feature is identified as a second class feature. A plurality of phase shift window pairs are laid out as described above for the first mask. A phase shift value is assigned to each of the first and second phase shift windows of the plurality of phase shift window pairs.
[0015]
According to another embodiment, the present invention comprises, as described above, instructions for performing a process of laying out a phase shift mask with multiple phase shift mask resolution levels involving a plurality of modeling classes, and It has a data processing system that includes other resources. In yet another embodiment, the present invention stores instructions for performing a process of laying out a phase shift mask with multiple phase shift mask resolution levels involving multiple modeling classes, as described above. An article of manufacture including a machine-readable storage medium is provided. In yet another embodiment, the present invention is directed to a machine, comprising, as described above, instructions for performing a process of laying out a phase shift mask with multiple phase shift mask resolution levels involving a plurality of feature classes. Has readable communication.
[0016]
The present invention is characterized by the use of phase shift masking with multiple phase shift resolution levels to produce integrated circuits or other workpieces with very fine features. Methods and tools are provided that increase flexibility. Other aspects and advantages of the present invention can be understood with reference to the accompanying drawings, detailed description, and claims.
BEST MODE FOR CARRYING OUT THE INVENTION
[0017]
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 illustrates the use of an alternating phase shift mask with multiple phase shift resolution levels involving multiple modeling classes to lay out a phase shift mask, fabricate a complementary mask, and implement such a mask. 1 illustrates a process performed by a computer system and a manufacturing system for printing and manufacturing an integrated circuit.
[0018]
The process, in this example, begins by reading a layout file that defines the complex layers of the integrated circuit (step 10). For example, one such complex layer may include a polysilicon interconnect layer that includes a transistor gate structure. Next, the process identifies a first set of features that are members of the first feature class. For example, features having dimensions smaller than a first specified value are identified as members of a first modeling class, such as transistor gates (step 11). Then, a second set of features to be exposed in a second feature class is identified. For example, a feature having a dimension smaller than a second specific value that is greater than the first specific value that characterized the first modeling class is identified (step 12). First and second sets of shift window pairs comprising phase shift windows having first and second layout dimensions are laid out for the first and second sets of features (step 13). The first and second sets of shift window dimensions are characterized by varying the layout width in a dimension orthogonal to the side of the phase transition. Other phase shift window layout dimensions provide multiple resolution levels for different build classes, for example, the width of an opaque area along the phase transition between paired phase shift windows. Can be changed. Next, the phase shift values for the phase shift window pairs are assigned or "colored" (step 14), the first window of each pair having a phase shift of θ degrees and the second of each pair being second. The window will have a phase shift of (180 + θ) degrees, where θ is nominally zero degrees in some embodiments. Other optical proximity modification techniques, or other mask layout processes, are performed to complete the phase shift mask layout process, as is known in the art (step 15). At this point, a machine readable layout file is created that includes the phase shift structure for the multiple modeling class. A complementary binary mask is laid out, whereby the features exposed using the opaque field-shifting mask are interconnected in layers (step 16). In a subsequent step, a mask is printed or otherwise manufactured for use in exposing a layer of material during the manufacture of a workpiece, such as a large circuit (step 17). Finally, in a preferred system, the integrated circuit is manufactured using a phase shift mask (step 18).
[0019]
2A to 2D show the layout of a phase shift mask for a first class of builds, in this example, a width, such as a width defining a channel length for transistors of 0.12 microns or less. For transistor gates having dimensions smaller than one specific value. FIG. 2A is an external view of a layout file that defines a model. Thus, the layers on the integrated circuit are defined within box 100. The transistor gate is defined by a polysilicon line 101. Implant region 102 provides the source and drain of the transistor, creating an active region of the transistor below the transistor gate defined by line 101. According to the present invention, the phase shift window will be laid out to expose an area that will define line 101 within the active area. Thus, in FIG. 2B, a region 105 defining a transistor gate is identified on the active region of the transistor. FIG. 2C shows phase shift windows 106 and 107 laid out adjacent to region 105. The phase shift windows 106 and 107 have a length L parallel to the feature 105 to be defined. In this class of fabrication, the phase shift windows 106 and 107 have a layout width W1, which is the width of the edges of the phase shift windows 106 and 107 where phase conflicts may cause exposure of the region 105. Is orthogonal to FIG. 2D shows the phase shift windows 106 and 107 after they have been "colored", i.e., assigned 0 and 180 degree phase shift characters, respectively. Phase shift windows 106 and 107 are laid out in an opaque area 108 to define a phase shift mask. Although not shown, a complementary binary mask is created to provide interconnects and other necessary structures in the layers of the device.
[0020]
3A to 3D show the layout of a phase shift mask for a second class of shaping, in this example a first specific value characterizing the width of the transistor gate described with reference to FIGS. 2A to 2D. A narrow interconnect having a dimension smaller than a larger second specified value. For example, if the first specified value is 0.12 microns or less, the second specified value is 0.16 microns or less. Thus, FIG. 3A illustrates layer 120 of an integrated circuit having interconnect features 121. The interconnect feature 121 is defined to have a width less than a second specified value. Therefore, this is a critical feature for the layout of the phase shift mask for this second class of features. Thus, the marginal feature 122 is defined in FIG. 3B. FIG. 3C shows the layout of phase shift windows 123 and 124 on opposite sides of feature 122. In this example, the phase shift windows 123 and 124 have a layout width W2 that is smaller than the layout width used in the sequence shown in FIG. 2C. FIG. 3D shows the phase shift regions 123 and 124 after the relative phase shift values 0 ° and 180 ° have been assigned to the phase shift regions 123 and 124, respectively. The phase shift regions 123 and 124 are laid out in the opaque field 125. Complementary binary masks (not shown) are used for interconnects and other features in the layer that are independent of phase shift.
[0021]
In this way, multiple classes of phase shift modeling are defined, as can be seen in FIGS. 2A to 2D and FIGS. 3A to 3D. The width of the resulting exposed pattern is based on the phase shift window layout widths W1 and W2. According to the present invention, a single phase shift mask containing a plurality of modeling classes is realized using phase shift window pairs having different layout widths. In this manner, a wide dimensioned feature that can be achieved using a narrow phase shift window, and a simple feature with a feature that must be implemented using a narrow dimension and wide phase shift window. Can be combined on one mask. Furthermore, the coloring of the combined shift region is simplified on systems that rely on a single wide or single class of phase shift shaping.
[0022]
4A to 4D show a layout of a pattern having a plurality of modeling classes on a single mask. FIG. 4A illustrates a layer 150 of an integrated circuit having a polysilicon gate feature 140 and a polysilicon interconnect feature including segments 141 and 142. Implant 151 is shown with features representing the source and drain regions of the transistor having an active channel region below gate feature 140. In the first step of the process shown in FIG. 4B, the gate cells of the layout are identified and the phase shift cells 153 and 154 are laid out in a manner that defines the gate region 152 using the layout width defined for the first build class. Is done. In the next step, shown in FIG. 4C, critical build cells defined as interconnect structures having a width less than a specified value but greater than a gate width are identified. The phase shift cells 156 and 157 overlay the phase shift cells 153 and 154 using the layout width defined for the second modeling class and are laid out along the sides of the modeling 155. In this example, the layout width for the first modeling class is larger than the layout width for the second modeling class. The resulting phase shift window has segments in the final window shape having a width based on the layout width for both build classes.
[0023]
In FIG. 4D, phase shift windows 160 and 162 are colored with phase shift angles of 0 and 180 degrees, respectively, as shown. The phase shift window thus colored is realized in the opaque area 161. The phase shift windows implement the phase transition with an opaque material such as chrome that is adjacent to each other and defines a spacing along the phase transition between the windows. Typically, the transition from the 0 degree phase window to the 180 degree phase window is in the center of the opaque band between the windows. However, opaque bands between windows allow other layouts.
[0024]
A complementary binary mask (not shown) is added for use in implementing the layers of the workpiece, as discussed above. In this way, the phase shift cells 156 and 157 are implemented in a manner that does not prevent the region 142 from taking the required width for the layout. Similarly, the use of narrow phase shift windows 156-157 simplifies the overall integrated circuit layout by reducing the chance of phase contention with adjacent phase shift cells.
[0025]
5A to 5D show a layout of a pattern having multiple build classes on a single mask according to an alternative process flow. FIG. 5A illustrates a layer 150 as in FIG. 4A of an integrated circuit having a polysilicon gate feature 140 and a polysilicon interconnect feature including segments 141 and 142. Implant 151 is shown with features representing the source and drain regions of the transistor having an active channel region below gate feature 140. In the first step of the alternative process shown in FIG. 5B, gate cells 152 of the layout and critical interconnect cells 155 of the layout are identified. In the next step, shown in FIG. 5C, the combined phase shift cells 158 and 159 are laid out for both the first class build (gate) and the second class build (critical width interconnect). As a result, the layout is basically the same as that of the combination cell shown in FIG. 4C. In the final step shown in FIG. 5D, as shown, the phase shift windows 160 and 162 are colored with respective phase shift angles of 0 and 180 degrees. The phase shift cell thus colored is implemented in the opaque field 161. A complementary binary mask (not shown) is added for use in implementing the layers of the workpiece, as discussed above.
[0026]
In the opaque field 161 shown in FIGS. 4D and 5D, opaque features are laid out between the phase shift regions. The width of the opaque feature between the phase shift regions can be adjusted in addition to adjusting the width of the phase shift window itself. Thus, the width of the phase shift window and the width of the opaque feature between the phase shift windows can be manipulated to define a plurality of feature classes for the layout of the shift mask.
[0027]
Laying out phase shift regions on complex masks involves overlapping phase shift areas and layers such as lines cut at an angle to overlay the layout dimensions of the phase shift areas. And resolution of other modeling shapes. The resulting mask will have a phase shift window with a complex polygonal shape, rather than a simple rectangle. However, in some embodiments of the present invention, the phase shift windows for the first and second build classes have width dimensions based on different layout widths. The phase shift window has a width dimension based on the layout width when the phase shift window is laid out using another feature after the overlay, and the phase shift area overlaps with another phase shift area. In that case, the width of at least one segment of the phase shift zone has a width equal to the layout width.
[0028]
Generating a phase shift mask for a complex structure is not a trivial matter of processing. FIG. 6 shows a data processing system for such a task. The machine 250 of FIG. 6 includes a processor 252 connected to receive data representing a user signal from the user input circuit 254 and provide the display 256 with data defining an image. Processor 252 is further coupled to access mask and layer layout data 258 that defines the mask layout being created and the layout for the layer of material to be exposed using the mask. The processor 252 is further connected to receive command data 260 indicative of the command through the command input circuit 262, the command input circuit 262 being a memory 264, a storage medium access device 266 or a network 268 as shown. The instructions received from the connection to can be provided.
[0029]
In executing the command represented by the instruction data 260, the processor 252 uses the layout data 258 to provide the display 256 with data defining a layout for the mask and, optionally, an image of the mask layout. , Display a sample layout.
[0030]
As noted above, FIG. 6 shows three possible sources from which the instruction input circuit 262 can receive data indicative of an instruction: a memory 264, a storage medium access device 266, and a network 268.
[0031]
The memory 264 may be any conventional memory in the machine 250, including random access memory (RAM) or read only memory (ROM), or any type of peripheral or remote memory device.
[0032]
The storage medium access device 266 may be a drive or other suitable device or circuit for accessing the storage medium 270, such as, for example, one or more tapes, diskettes or sets of flexible disks. Such a magnetic medium, an optical medium such as a set of one or more CD-ROMs, or any suitable medium for storing data. Storage medium 270 may be part of machine 250, may be part of a server or other peripheral or remote memory device, or may be a software product. In each case, storage medium 270 is an article of manufacture that can be used with machine 250. The data units can be located on the storage medium 270 such that the storage medium access device 266 can access the data units and supply them to the processor 252 in sequence through the instruction input circuit 262. As supplied in sequence, the data units form instruction data 260 and display the instructions as shown.
[0033]
Network 268 can provide command data 260 received as communication from machine 280. The processor 282 of the machine 280 can establish a connection with the processor 252 over the network 268 via the network connection circuit 284 and the instruction input circuit 262. Either processor can initiate the connection, and the connection may be established with any suitable protocol. Then, the processor 282 can access the instruction data stored in the memory 286 and transmit the instruction data to the processor 252 via the network 268, so that the processor 252 receives the instruction data 260 from the network 268. be able to. Next, the processor 252 can store and execute the instruction data 260 in the memory 264 or somewhere.
[0034]
The resulting layout data is stored in machine readable form or displayed in communication with a remote system.
[0035]
In this example, the automatic assignment of the phase shift region and the addition of the optical proximity correction shaping as described above are provided to facilitate the processing. For example, in a data processing system as shown in FIG. 6, a phase shift mask layout is generated by the present process, which is executed using a design rule check programming language (for example, a Vampier design rule checker provided by Cadence Design System Co., Ltd.). The three stages include defining the input layer, generating the output layer, and coloring the phase shift region.
[0036]
Utilizing a design rule checker, all exposed features (i.e., lines) of the input layout having a size smaller than the minimum feature size or having features of a feature class implemented in accordance with the present invention using multiple phase shift resolution levels. ) Can be identified. In some embodiments, different minimum build dimensions apply to multiple build classes. In this way, the minimum feature can be identified by subtracting slightly more than one-half of the minimum feature size for the line from the input feature of the original size. As a result, all structures having dimensions smaller than the minimum dimension are removed. The remaining structure can then be reconstructed by adding back more than half the smallest dimension. The smallest dimension structure can then be identified by taking the original input structure and subtracting out all the structures obtained in the reconstruction step. This process can be characterized as performing a size down operation to remove small size features, and then performing a size up operation on the remaining edges to produce the calculated layout. Next, small sized features are identified by performing an "AND NOT" operation between the AND NOT of the original layout and the calculated layout.
[0037]
The phase shift region, in a simple case, copies the input structure of each build class, adjusts the width of the resulting polygon to the desired layout width for each build class, and corresponds to the phase shift window pair. It is formed by arranging a polygon at a modeling position. Phase "coloring" can be applied automatically or manually to the resulting phase shift window pair, so that the 0 degree and 180 degree regions are laid out correctly.
[0038]
The above simple example provides an alternative process flow for laying out phase shift windows for multiple resolution levels based on the phase shift window layout width. This process can be easily extended to complex layouts with three or more resolution levels, depending on the needs of a particular layout problem. Very fine grading in resolution can be achieved by fine tuning the width of the phase shift window and the spacing between them.
[0039]
In summary, using the multi-resolution class of the present invention to define alternating phase shift masks used to fabricate integrated circuits and other finely shaped workpieces, the shape of the laid out feature can be extended. And excellent control, and almost no problems due to phase competition occur.
[0040]
The foregoing description of various embodiments of the invention has been presented for purposes of illustration and description. The description is not intended to limit the invention to the precise form disclosed. Many modifications can be made to derive equivalent structures, as will be apparent to those skilled in the art.
[Brief description of the drawings]
[0041]
FIG. 1 is a flowchart of a layout process related to a multiple phase shift mask resolution level according to the present invention.
2A to 2D show a conventional process for laying out a phase shift window pair for a transistor gate or other building class.
3A to 3D show a process for laying out phase shift window pairs for builds of build classes other than those shown in FIG. 2;
4A to 4D illustrate steps taken in laying out a plurality of build classes in a pattern, according to an embodiment of the present invention.
FIGS. 5A to 5D show steps taken in laying out a plurality of modeling classes in one pattern according to another embodiment of the present invention.
FIG. 6 is a data processing system for performing a process of laying out a plurality of build classes in one pattern, such as a pattern for a photolithographic mask used in one layer in an integrated circuit or other workpiece. Is shown.

Claims (50)

Processing a pattern defining a first and second build class of features in the layer for a photolithographic mask defining the layer;
Defining a first layout dimension for the phase shift window pair for the first build resolution level and a second layout dimension for the phase shift window pair for the second build resolution level;
Using a first layout dimension for the phase shift window pair for the first build class and using a second layout dimension for the phase shift window pair for the second build class. Laying out a plurality of phase shift window pairs, including:
Assigning first and second phase shift values to the phase shift windows within the plurality of phase shift window pairs. The processing includes reading a layout file identifying dimensions of a build in the pattern, and processing the layout file to identify builds in the first and second build classes. The method of claim 1, wherein The build in the first build class has a line segment with a first line width, the build in the second build class has a line segment with a second line width, and the first line The method of claim 1, wherein a width is less than the second line width. The features in the first modeling class are line segments corresponding to transistor gates having a first width, and the features in the second modeling class are line segments corresponding to interconnect lines having a second width. The method of claim 1, wherein the first width is less than the second width. The method of claim 1, wherein the layer comprises polysilicon. The method of claim 1, wherein the first and second phase shift values include a [theta] phase shift and a (180+ [theta]) degree phase shift. The method of claim 1, wherein the phase shifting window pair further comprises an opaque area located between the paired first and second windows. The opaque area between the first and second windows has a first width within the first class of phase shift window pair and a second width within the second class of phase shift window pair. The method of claim 7, wherein: The method of claim 1, comprising laying out a complementary mask with opaque and transparent regions defining additional features in the layer. The method of claim 9, wherein the complementary mask comprises a binary mask. The method of claim 9, comprising creating a machine readable layout file defining a layout of the phase shift mask and the complementary mask. The method of claim 9, including fabricating the phase shift mask and the complementary mask. 13. The method of claim 12, including fabricating an integrated circuit using the phase shift mask and the complementary mask. The method of claim 1, wherein the first layout dimension includes a first layout width, the second layout dimension includes a second layout width, and the first layout width is larger than the second layout width. The described method. In a set of masks for defining a layer of material in an integrated circuit,
A first mask having a plurality of phase shift window pairs in an opaque field for defining a structure in a layer defined by each phase shift window, the first mask having a plurality of phase shift windows in the plurality of phase shift windows. The transfer window includes windows of a first class and a second class, respectively, wherein the first class has a width dimension based on a first layout width, and the second class has a second layout width. A first mask having a width dimension based on the first layout width, the first layout width being larger than the second layout width;
A second mask having a second opaque area and a transparent area for interconnecting structures defined by the plurality of phase shift windows and preventing erasure of the structures defined by the phase shift windows. A second mask defining an interconnect structure in said layer. The set of masks of claim 15, wherein said layer comprises polysilicon. Assigning a phase shift value to a pair of windows in the first and second class windows, wherein one of the pair of windows has a phase shift of θ degrees, 16. The set of masks according to claim 15, wherein the other of the windows has a phase shift of (180+ [theta]) degrees. The set of masks of claim 17, wherein the pair of windows further includes an opaque area located between the one window and the other window. The opaque area has a first width between a pair of windows of the first class of windows and a second width between a pair of windows of the second class of windows. The set of masks according to claim 18. An apparatus comprising a data processing system that includes a memory for storing instructions, the instructions comprising:
A first layout dimension for a phase shift window pair for processing a pattern and defining a feature in first and second feature classes in the layer for a lithographic mask defining the layer; Defining a second layout dimension for the phase shift window pair for the second build resolution level;
Using a first layout dimension for the phase shift window pair for the first build class and using a second layout dimension for the phase shift window pair for the second build class, Lay out a shift window pair,
An apparatus comprising: assigning first and second phase shift values to phase shift windows of the plurality of phase shift window pairs. The instructions include a command for reading a layout file identifying dimensions of a build in the pattern and processing the layout file to identify builds in the first and second build classes. The device according to claim 20. The build in the first build class has a line segment with a first line width, the build in the second build class has a line segment with a second line width, and the first line The apparatus of claim 20, wherein the width is less than the second line width. The features in the first modeling class are line segments corresponding to transistor gates having a first width, and the features in the second modeling class are line segments corresponding to interconnect lines having a second width. The apparatus of claim 20, wherein the first width is less than the second width. The device of claim 20, wherein the layer comprises polysilicon. 21. The apparatus of claim 20, wherein the first and second phase shift values include a [theta] degree phase shift and a (180+ [theta]) degree phase shift. 21. The apparatus of claim 20, wherein the phase shifting window pair further comprises an opaque area located between the paired first and second windows. The opaque area between the first and second windows has a first width within the first class of phase shift window pair and a second width within the second class of phase shift window pair. 21. The apparatus of claim 20, wherein: 21. The apparatus of claim 20, wherein the instructions include a command to lay out a complementary mask with opaque and transparent regions defining additional features in the layer. The apparatus of claim 20, wherein the complementary mask comprises a binary mask. 30. The apparatus of claim 29, wherein the instructions include commands for creating a machine readable layout file defining a layout of the phase shift mask and the complementary mask. 21. The method according to claim 20, wherein the first layout size includes a first layout width, the second layout size includes a second layout width, and the first layout width is larger than the second layout width. The described device. An article of manufacture comprising a machine-readable storage medium for storing instructions, the instructions comprising:
A first layout dimension for a phase shift window pair for processing a pattern and defining a feature in first and second feature classes in the layer for a lithographic mask defining the layer; Defining a second layout dimension for the phase shift window pair for the second build resolution level;
Using a first layout dimension for the phase shift window pair for the first build class and using a second layout dimension for the phase shift window pair for the second build class, Lay out a shift window pair,
An article comprising a command for assigning first and second phase shift values to phase shift windows of the plurality of phase shift window pairs. The instructions include a command for reading a layout file identifying dimensions of a build in the pattern and processing the layout file to identify builds in the first and second build classes. An article according to claim 32. The build in the first build class has a line segment with a first line width, the build in the second build class has a line segment with a second line width, and the first line The article of claim 32, wherein the width is less than the second line width. The features in the first modeling class are line segments corresponding to transistor gates having a first width, and the features in the second modeling class are line segments corresponding to interconnect lines having a second width. 33. The article of claim 32, wherein the first width is smaller than the second width. In a machine-readable communication comprising a signal including instructions, the instructions being transmitted over a communication medium, wherein the instructions comprise:
A first layout dimension for a phase shift window pair for processing a pattern and defining a feature in first and second feature classes in the layer for a lithographic mask defining the layer; Defining a second layout dimension for the phase shift window pair for the second build resolution level;
Using a first layout dimension for the phase shift window pair for the first build class and using a second layout dimension for the phase shift window pair for the second build class, Lay out a shift window pair,
Communication comprising a command to assign first and second phase shift values to phase shift windows of the plurality of phase shift window pairs. The instructions include a command for reading a layout file identifying dimensions of a build in the pattern and processing the layout file to identify builds in the first and second build classes. 37. The communication of claim 36. The build in the first build class has a line segment with a first line width, the build in the second build class has a line segment with a second line width, and the first line The communication of claim 36, wherein a width is smaller than the second line width. The features in the first modeling class are line segments corresponding to transistor gates having a first width, and the features in the second modeling class are line segments corresponding to interconnect lines having a second width. The communication of claim 36, wherein the first width is smaller than the second width. Means for processing a pattern, defining features in first and second features classes in the layer, for a lithographic mask defining the layer;
Means for defining a first layout dimension for the phase shift window pair for the first build resolution level and a second layout dimension for the phase shift window pair for the second build resolution level;
Using a first layout dimension for the phase shift window pair for the first build class and using a second layout dimension for the phase shift window pair for the second build class. Means for laying out a phase shift window pair of
Means for assigning first and second phase shift values to the phase shift windows of the plurality of phase shift window pairs. The means for processing includes means for reading a layout file identifying dimensions of features in the pattern, and means for processing the layout file to identify features in the first and second modeling classes. 41. The apparatus of claim 40, comprising: means. The build in the first build class has a line segment with a first line width, the build in the second build class has a line segment with a second line width, and the first line 41. The apparatus of claim 40, wherein a width is less than the second line width. The features in the first modeling class are line segments corresponding to transistor gates having a first width, and the features in the second modeling class are line segments corresponding to interconnect lines having a second width. The apparatus of claim 40, wherein the first width is less than the second width. The device of claim 40, wherein the layer comprises polysilicon. 41. The apparatus of claim 40, wherein the first and second phase shift values include a [theta] degree phase shift and a (180+ [theta]) degree phase shift. 41. The apparatus of claim 40, wherein the phase shifting window pair further comprises an opaque area located between the paired first and second windows. The opaque area between the first and second windows has a first width within the first class of phase shift window pair and a second width within the second class of phase shift window pair. 47. The apparatus of claim 46, wherein: 41. The apparatus of claim 40, comprising means for laying out a complementary mask with opaque and transparent regions defining additional features in the layer. 49. The apparatus of claim 48, wherein said complementary mask comprises a binary mask. 49. The apparatus of claim 48, including means for producing a machine readable layout file defining a layout of the phase shift mask and the complementary mask.

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