JP2004519188A - Switchable FET circuit - Google Patents

Abstract

For example, a switching circuit for switching an input DC voltage having a predetermined polarity used in a synchronous DC / DC converter is provided. The switching circuit is divided between the high-potential-side package 52 and the low-potential-side package 56, and each package includes switches 6, 8 connected between a logic input terminal 90 and switching output terminals 84, 86. The switching output terminals 84, 86 of the high and low potential packages are connected in series between the input voltage terminals 4, 2. The pulse width modulator 18 is connected to the logic input terminal 90 of each package, and supplies an AC control signal to alternately switch the high potential and low potential switches 6 and 8. Each of the high-potential and low-potential packages controls each switch based only on the voltage of each logic input terminal and each switching output terminal so that the high-potential and low-potential side packages are not simultaneously turned on. The logic circuit 150 can use a predetermined delay or integrate a sense circuit configuration that switches based on the voltage of the output terminal. In this way, the need to control the interconnection between the high and low potential packages is avoided.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to switched FET (field effect transistor) circuits and, more particularly, to methods of operating such circuits as used in, for example, synchronous DC / DC voltage converters.
[0002]
[Prior art]
Circuits with switchable FETs are well known. Examples include DC / DC converters that are commonly used to convert voltage from one voltage level to another, such as providing a 1.5V voltage line from a 12V power supply. .
[0003]
FIG. 1 schematically shows a synchronous DC / DC converter which is one form of the converter. The input voltage Vin is applied between the input terminals 2 and 4. A pair of transistors--in this example, field effect transistors--6 and 8 are connected between input terminals 2 and 4. The transistor 6 connected to the input terminal 2 is called a control FET or a high-potential transistor, and the transistor 8 connected to the ground is called a synchronous FET or a low-potential transistor. The high potential side is relatively more positive than the low potential side, although it is not necessary that the high or low potential side be specifically grounded.
[0004]
The node between transistors 6 and 8 is called switching node 10. The switching node feeds output terminal 16 across capacitor 14 via inductor 12.
[0005]
Controlled and synchronous FETs are driven by corresponding drivers 30 and 32, respectively.
[0006]
The control circuit 18 has an input terminal reaching the input control terminal 20 and another input terminal supplied with power from the output terminal 16 via the feedback path 22. The control circuit 18 supplies a control signal to control the FETs 6 and 8, and keeps the voltage at the output terminal by repeatedly turning on and off the switching transistors 6 and 8. The control signal is an AC signal that alternately conducts the control type and the synchronous type FET. The mark space ratio is variable, i.e., the ratio of the time that the controlled FET is conducting to the time that the synchronous FET is conducting is adjusted to achieve the target voltage at the output terminal 16.
[0007]
Examples of such DC / DC converters include WO98 / 49607 assigned to Intel Corporation and US Pat. No. 5,479,089 assigned to Lee.
[0008]
A feature of the synchronous DC / DC converter is that it is not always desirable to turn on the high potential side transistor 6 and the low potential side transistor 8 simultaneously. When both transistors are turned on, the input voltage is short-circuited by current flowing directly between the two input terminals 2 and 4 via the controllable FET and the synchronous FET. This phenomenon is called "shoot-through". Therefore, the control circuit 18 is normally configured to ensure that only one of the two transistors 6 and 8 is turned on.
[0009]
This is conventionally done by monitoring two voltages. The voltage at the switching node 10 is monitored so that the low-side transistor 8 does not switch on until the high-side transistor 6 turns off. The voltage at the gate 24 of the low-side transistor 8 is monitored so that the high-side transistor does not switch on until the low-side transistor 8 turns off. For example, Patent Document 1 describes a circuit of this type. Also, for example, a similar circuit is described in Patent Document 2.
[0010]
The dead time during which both FETs are non-conductive is determined by the threshold voltage of the transistor and the capacity of the synchronous FET. These threshold voltages and FET capacities will vary roughly depending on the manufacturing spread of the parameters of the selected FET, as well as on the individual selected FET. This means that these parameters must be conservatively estimated to produce dead time that avoids shoot-through. This typically results in a longer dead time than would be possible if the control circuit were optimized for the particular FET used.
[0011]
[Patent Document 1]
WO98 / 49607
[Patent Document 2]
U.S. Pat. No. 5,479,089
[0012]
[Problems to be solved by the invention]
Currently, it is aimed at increasing switching and clock speeds. This means that the importance of the dead time in which neither the high-potential-side transistor 6 nor the low-potential-side transistor 8 is turned on increases. It is beneficial to shorten this dead time.
[0013]
Another drawback occurs when multiple FETs connected in parallel are used instead of a single high-side and low-side transistor. Depending on variations in gate resistance and other parameters that are again caused by manufacturing variations in the circuits in which the FETs are provided, the parallel-connected FETs will never switch at exactly the same time. Therefore, it is difficult to accurately determine when all of the high-potential-side or low-potential-side FETs are turned off, that is, when other FETs are turned on. Usually, a solution is to provide a gate resistor in the circuit. However, this slows down the switching of the FETs and increases the losses associated with switching, especially at high frequencies. Therefore, it would be beneficial to provide a circuit configuration that would make the use of parallel connected FETs easier.
[0014]
[Means for Solving the Problems]
According to the present invention, there is provided a switching circuit for switching an input DC voltage of a predetermined electrode pressurized to an input voltage, wherein the switching circuit includes a logic input terminal and a switch connected between the switching output terminals. A high-potential-side package and a low-potential-side package provided, switching output terminals of the high-potential-side and low-potential-side packages are connected in series between input voltage terminals, and further, a logic input terminal of the package. And a pulse width modulator for supplying an AC control signal to a logic input terminal so as to alternately switch between a high potential side switch and a low potential side switch. Each switch based on only the voltage on each logic input terminal and switching output terminal so that the switches on the potential side package do not conduct simultaneously. Control to contain logic circuitry.
[0015]
Therefore, shoot-through can be prevented without providing a complicated circuit configuration for passing a control signal between the high potential side circuit and the low potential side circuit. The only control signal required is an AC Pulse Width Modulated (PWM) control signal that is at a logic level. Since the driver circuits in the high-potential side and low-potential side components do not depend on signals from the other of the components, the switching speed is increased, and the dead time when both switches are non-conductive is reduced. Be shorter.
[0016]
The switch may be an FET.
[0017]
A node connecting the high potential side package and the low potential side package is called a switching node. The logic circuit configuration in each package may include a sense circuit that controls switching of a corresponding switch based on a voltage at a switching node and a voltage input terminal.
[0018]
In a preferred embodiment, the sense circuit includes an edge detector that detects the voltage edge of the pole opposite the predetermined electrode and turns on the corresponding FET only after the voltage edge is detected.
[0019]
Instead, the logic circuit causes a delay before the corresponding FET switches on and after the control signal switches.
[0020]
The driver circuit can be separated from the control circuit, and the low voltage side of the driver circuit can be directly connected to the source of the corresponding FET. In this manner, the area of the circuit for driving the gate can be reduced. This reduces the gate-source loop inductance and makes the gate-source voltage rise and fall more quickly. Furthermore, the parasitic inductance at the source connection prevents the gate-source voltage from lowering and consequently slowing down the FET switching.
[0021]
The driver can be directly connected to the gate of the corresponding FET without providing a resistor between the driver and the gate. Such a resistor was necessary in conventional designs where the controlled FET was turned on by monitoring the gate voltage of the synchronous FET.
[0022]
The high-potential-side and low-potential-side components can be easily configured in parallel. This is because each component has a circuit configuration for avoiding shoot-through.
[0023]
By integrating each FET and driver in the corresponding package, a large space is available and the design can be simplified over a wide range. Each FET can now be viewed as a device that takes a digital input to ensure conduction for an appropriate time and automatically controls its gate drive to prevent shoot-through and reduce dead time.
[0024]
The high potential side component has a bootstrap diode inside and can be separated from the control circuit. This causes the voltage used in the FET to be inconsistent with the voltage used to drive the control and driver circuits.
[0025]
The internal regulator secures a stable operating voltage for driving the gate and is configured to supply power to the provided level shifter.
[0026]
Even without external monitoring, thermal protection is provided so that if a fault occurs, the FET is directly shut off.
[0027]
The power can easily be increased. For example, on a multilayer FR4 PCB laid in a surface mount package, the loss of each device is limited to about 3W. More phases are needed to increase the power. That is, it is necessary to drive additional FETs at various phases using the phase shifted PWM signal. This is because it is dangerous to add a package by paralleling devices because of the possibility of shoot-through and mutual conduction. The sensing operation at the switching node of each component enables parallelization, and the solution of the present invention can be easily solved.
[0028]
The invention also relates to the high and low potential components themselves. Therefore, in another aspect, the invention relates to a high-potential component that can be used in a switching circuit for switching an input DC voltage of a predetermined polarity, wherein the high-potential component comprises a package, wherein the package comprises a source, FET including a drain and a gate, a driver for controlling the gate, a voltage input terminal connected to the drain for inputting the high voltage side of the input DC voltage, an output terminal connected to the source, and logic for receiving an alternating control signal An input terminal; and a logic circuit for controlling a driver to switch the high-side FET based on the logic input, wherein the logic circuit includes a low-level terminal connected between an output terminal of the input DC voltage and the ground side. By detecting the voltage of the source of the FET and controlling the switching of the FET based on the logical input so that the FET does not conduct simultaneously as the potential side FET. Nsu circuit is provided.
[0029]
In yet another aspect, the invention relates to a low potential component used in a switching circuit for switching an input DC voltage of a predetermined polarity, wherein the low potential component comprises a package, wherein the package comprises a source, FET having a drain and a gate, a driver for controlling the gate, a voltage input terminal connected to a source for inputting a low voltage side of the input DC voltage, an output terminal connected to the drain, and a logic for receiving an AC control signal An input terminal, and a logic circuit controlling the driver to switch the FET based on the switching on the logic input terminal, wherein the logic circuit is connected between the high voltage side of the input DC voltage and the output terminal. The high-potential side FET detects the voltage at the drain of the FET and controls switching of the FET based on the logical input so that the FET does not conduct at the same time. Scan circuit mounted, the driver is separated from the logic circuit and is compliant directly to the source.
[0030]
The present invention provides a high-potential-side component having a controlled FET connected between an input DC terminal and a switching node, and a low-potential-side component having a synchronous FET connected to a switching node and a ground terminal. For driving a synchronous DC / DC converter circuit including a step of alternately driving a high-potential-side package and a low-potential-side package by an AC control signal, and preventing synchronous and control-type FETs from being simultaneously turned on. And In the above method, the controllable FET is turned off in response to a change in the polarity of the AC control signal from the first polarity to the second polarity in the high-potential side package, and the AC signal is switched from the second polarity to the first polarity. The control type FET is turned on after a delay time according to the polarity change, and the synchronous type FET is turned off according to the polarity change of the AC signal from the second polarity to the first polarity in the low potential side package. This is achieved by switching the synchronous FET on after a delay time according to the change in the polarity of the AC signal from the first polarity to the second polarity.
[0031]
The delay step includes a delay of a predetermined time.
[0032]
Instead, the delaying step includes waiting for the negative edge of the voltage at the switching node and triggering each FET to switch on.
[0033]
BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention, certain embodiments are described below, by way of example only, with reference to the accompanying drawings.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
Referring to FIG. 2, a particular embodiment of the present invention relates to the low side component 56. The low potential side component includes a synchronous FET 8 including a drain 106, a source 108, and a gate 110. The drain 106 and the source 108 are connected to a drain terminal 84 and a source terminal 86, respectively. The driver 32 is connected to the gate 110 and drives the gate 110. The logic circuit 150 drives the driver 32 according to the signal received at the logic level input terminal 90.
[0035]
The logic circuit includes a sense circuit 153 that triggers the driver 32 when a predetermined voltage state occurs at the drain 106 of the synchronous FET 8. The sense circuit 153 is configured to trigger when the voltage drops to a predetermined level, for example, -0.5 V or less. Alternatively, the sense circuit could trigger on the negative edge of the synchronous FET drain 106. The logic circuit configuration 150 is configured to turn off the driver 32 when the signal at the logic level input terminal 90 changes from the first polarity to the second polarity. When the AC signal reverses from the second polarity to the first polarity, the driver 32 switches on only after the sense circuit 153 triggers. In this way, external logic connection parts other than the logic signal supplied to the logic level input terminal 90 become unnecessary.
[0036]
Logic circuit 150 is powered by a connection line to power input terminals 80 and 82 which are connected to Vcc and ground, respectively. The ground feedback to the driver circuit goes not directly to the ground terminal 82 but directly to the FET source 108 along the driver feedback line 138. Accordingly, the logic circuit 150 includes a sense input terminal 152 connected to the drain 106 that senses the voltage at the drain and triggers the driver 32.
[0037]
The direct connection 138 between the driver 32 and the source 108 in the low side component is a low inductance feedback path for the current used to drive the gate 110. That is, the areas of the driver 32, the gate 110, and the feedback path 138 are reduced. This reduces transient effects caused by switching currents passing through the parasitic inductance. However, a direct connection is not required.
[0038]
The level shift circuit 136 is shown between the logic circuit and the driver 32. Again, this is not essential, but isolating the synchronous FET driver 32 ensures that the direct connection 138 does not have the adverse effect of significantly swinging the voltage on the body of the semiconductor die, and thus on the logic circuit 150. .
[0039]
The corresponding high-side component 52 is shown in FIG. The controllable FET 6 has a drain 100, a source 102 and a gate 104. Drain 100 and source 102 are connected to drain terminal 84 and source terminal 86, respectively. The driver 30 is connected to the gate 110 and drives the gate 110. The logic circuit 150 drives the driver 30 via the level shift circuit 136 according to the signal received at the logic level input terminal 90.
[0040]
The logic circuit 150 includes a sense circuit 153 that triggers the driver 32, as in the case of the low-potential-side configuration unit 56. However, in this case, the voltage is detected at the source 102 of the controlled FET 6. The sense circuit 153 can be configured to trigger when the voltage drops below a predetermined level, for example, -0.5V. Instead, the sense circuit can be triggered on the negative going edge. The logic circuit 150 turns off the driver 32 when the signal at the logic level input terminal 90 switches from the second polarity to the first polarity (the same polarity is intended as used above in the low potential side component 56). Has been). When the AC signal reverses from the first polarity to the second polarity, the driver 32 turns on only after the sense circuit 153 has triggered. In this way, an external logic connection separate from the logic signal sent to logic level input terminal 90 is not necessary to control the controlled FET.
[0041]
It is desirable that the control FET 6 and the synchronous FET 8 are alternately turned on. In the above description of the high potential side component 52 and the low potential side component 56, the signal applied to one logic input terminal 90 of the high potential side component 52 and the low potential side component 56 is used for the other logic. Since it is assumed that the signal applied to the input terminal is the same, when the AC signal has one polarity, one of the control type FET 6 and the synchronous FET 8 turns on, and when the AC signal has the other polarity, the control type FET 6 The other of the FET 6 and the synchronous FET 8 is turned on.
[0042]
Of course, it is also possible to configure the logic circuit 150 in the controllable FET 6 and the synchronous FET 8 so that the invention is implemented externally, for example using an inverter connected to one of the input terminals 90. In this case, the control-type FET 6 is switched on because the polarity of the signal that turns on the synchronous FET 8 when applied to the logic input terminal 90 of the low potential side package 56 and the logic input terminal of the high potential side package 52 90 due to the signal of the same polarity applied to 90.
[0043]
Logic circuit 150 is powered by connection lines to power input terminals 80 and 82 which are connected to Vcc and ground, respectively. The ground feedback of the driver circuit reaches the FET source 102 directly via the driver feedback 138 instead of the ground terminal 82.
[0044]
The bootstrap diode 160 is connected between the high voltage input terminal 80 and the boost terminal 94 and supplies power to the driver 30. A bootstrap diode is not required. For example, it can be omitted when sufficient input DC voltage is available. Alternatively, the driver can be powered directly from the Vcc input terminal 80.
[0045]
As illustrated, the use of n-channel FETs is not essential, as switches and alternatives can use p-channel FETs and even bipolar transistors. It is particularly advantageous to use a p-channel FET in the high-side component with an n-channel FET in the low-side component. In such a case, the bootstrap diode 160 can be omitted.
[0046]
The high-potential-side component 52 and the low-potential-side component 56 are connected to form a circuit as shown in FIG. Each of the high-potential-side component 52 and the low-potential-side component 56 in the illustrated embodiment has an FET 6, 8 implemented as one die, a corresponding logic circuit configuration 150, drivers 30, 32, Included are level shifters 132, 136 implemented as separate dies 50, 54.
[0047]
The high-potential-side control FET 6 and the low-potential-side synchronous FET 8 are connected in series between the supply input terminal 4 and the ground 2. A DC input voltage of a predetermined polarity is connected between these input terminals.
[0048]
The drain 100 of the controlled FET 6 is connected to the power input terminal 4 and the source 102 to switch the node 10. The drain 106 of the synchronous FET 8 is connected to the switching node 10 and the source 108 and reaches the ground 2.
[0049]
The switching node 10 is grounded via an inductor 12 and a capacitor 14. An output terminal 16 of the circuit is taken between the inductor 12 and the capacitor 14.
[0050]
The control circuit 18 supplies a logic level AC pulse width modulation (PWM) switching signal via a logic input terminal 90. The control circuit drives the logic circuit 150. Feedback path 22 provides feedback from output terminal 16 to control circuit 18. The mark space ratio of the AC PWM switching signal, that is, the ratio of the time the switching signal is high to the time low, changes to control the output voltage at output terminal 16. Various suitable circuits are known for the control circuit 18 and will not be described further. It is a feature of the present invention that it can be used with a wide variety of control circuits that provide a suitable PWM output signal.
[0051]
The individual voltage input terminal 36 supplies power to the drivers 30 and 32, the logic circuit 150, and the control circuit 18.
[0052]
Control circuit 18 provides a series of control signal switching pulses that are controlled using feedback path 22 to maintain the voltage at output terminal 16 at the required value.
[0053]
When the control signal drops, the controlled FET 6 switches off. Because of this, the current continues to be drawn by the inductor 12, so that the voltage at the switching node 10 begins to drop more than through the controlled FET 6, and the current passes through the body diode 164 of the synchronous FET 8. This process ends with the voltage at the switching node 10 determined by the voltage drop on the body diode 164 of the synchronous FET 8. This voltage is about -0.8V.
[0054]
When the voltage of the switching node falls below a predetermined reference value, for example, -0.5 V, the logic circuit 150 of the low-potential-side component is triggered to turn on the low-potential-side driver 32 and, consequently, the synchronous FET 8. . Since the voltage at the switching node 10 does not go negative until the controlled FET 6 is switched off, the risk of shoot-through is avoided.
[0055]
When the synchronous FET 8 switches on and becomes saturated, the voltage at the switching node 10 rises to about -0.1V.
[0056]
When the control signal rises, first the synchronous FET 8 switches off. Again, current is sent to the body diode 164 of the synchronous FET, and the voltage at the switching node 10 goes negative. When the voltage drops below a predetermined voltage, the logic circuit 150 of the high-side component is triggered, in which case the driver 30 is turned on and the control FET 6 is turned on.
[0057]
This cycle is then repeated.
[0058]
Therefore, the control FET 8 is turned on only when it detects, via the switching node 10, that the body diode 164 of the synchronous FET 8 is conducting. This scheme is believed to switch the synchronous FET 8 off in a more accurate manner than the conventional scheme using the voltage at the gate 110 of the synchronous FET 8. As a result of this increased accuracy, the dead time when both FETs are non-conducting, which is an essential problem in switching devices quickly, is reduced.
[0059]
By combining the simple driver 30 or the driver 32 inside each of the high potential side component 52 and the low potential side component 56 with the sense circuit 150 responsive to one of the source gate and drain voltages of the corresponding FET, Even if there is no control signal flowing between the high potential side circuit and the low potential side circuit, synchronous DC / DC operation can be ensured. The only control signal required is an AC pulse width modulation (PWM) control signal, which is at a logic level. Since the driver circuits 30, 32 of the high-potential component 52 and the low-potential component 56 do not depend on the signal from the other of the components 52, 56, the switching is quicker and neither of the FETs is switched off. The dead time in the conductive state can be reduced.
[0060]
The drivers 30 and 32 are directly connected to the gates 104 and 110 of the corresponding FETs 6 and 8, without the need to place resistors between the drivers 30 and 32 and the gates 104 and 110. Such a resistor may be needed in conventional designs where the controlled FET 6 switches on, triggered by monitoring the voltage at the gate 110 of the synchronous FET 8.
[0061]
The high-potential-side constituent section 52 and the low-potential-side constituent section 56 including the FETs 6 and 8 and the driver 30 and the driver 32 each have their own circuit configuration for avoiding shoot-through, so that they can be easily configured in parallel.
[0062]
By providing the driver 30 or the driver 32 together with the FET 6 or the FET 8, the area on the board can be reduced and the design of the board can be simplified. Each component 52 or 56 is considered to be a device that takes a digital input and automatically controls its gate drive to ensure that it is conducting at the appropriate time, preventing shoot-through and reducing dead time. .
[0063]
An optional bootstrap capacitor 162 holds the voltage on the driver 30 of the high side component. The capacitor charge is charged to the diode 160 at each point in the cycle when the voltage at the switching node is low, ie, at the end of the period when the synchronous FET is on. Capacitor 162 can be omitted if a suitable alternative voltage source is available.
[0064]
Thermal protection is provided so that the FET can be cut off directly in the event of a failure without external monitoring.
[0065]
It is easier to increase the power. On a motherboard on which a surface equipment package is laid, the maximum power loss of each device is limited to a certain level. To increase power, more phases are needed, that is, additional FETs need to be driven at different phases using phase shifted PWM signals. This is because parallelization of devices is dangerous because there is a risk of shoot-through or mutual conduction. The sensing at the switching node of each component enables parallelization, and the solution of the present invention can be easily solved.
[0066]
INDUSTRIAL APPLICABILITY The present invention can be applied to a power converter, an automatic system, a logic converter of a power interface, a power supply, and a motor drive.
[0067]
The present invention is not limited to the illustrated configuration. For example, it is also possible to provide an internal regulator so as to secure a reliable operating voltage of the gate drive and supply power to an arbitrary level shifter.
[0068]
The high and low potential components 52 and 56 are each integrated into a single package in the illustrated embodiment. However, it is also possible to integrate the entire circuit in a single package.
[Brief description of the drawings]
FIG.
It is a schematic block diagram of the conventional synchronous DC / DC converter.
FIG. 2
It is a schematic structure figure of a 1st embodiment of the present invention.
FIG. 3
It is a schematic structure figure of a 2nd embodiment of the present invention.
FIG. 4
FIG. 4 is a diagram showing a configuration of an embodiment of a synchronous DC / DC voltage converter using the configuration shown in FIGS. 2 and 3.
[Explanation of symbols]
56 Low potential side component
8 Synchronous FET
106 drain
108 sauce
110 gate
150 logic circuit
153 Sense circuit
136 level phase shift circuit

Claims (16)

A switching circuit for switching an input DC voltage having a predetermined polarity applied to an input voltage terminal,
A high-potential-side package and a low-potential-side package each including a logic input terminal and a switch connected between a switching output terminal, wherein a switching output terminal of the high-potential-side package and a low-potential-side package is connected to the input terminal. A high-potential side package and a low-potential side package directly connected between the voltage terminals,
A pulse width modulator connected to the logic input terminals of the both packages, supplying an AC control signal to the logic input terminal, and alternately switching the high-potential side and the low-potential side switch;
The high-potential and low-potential side packages respectively control corresponding switches based only on the voltages of the corresponding logic input terminals and switching output terminals so that the switches of the high-potential and low-potential side packages are not simultaneously turned on. A switching circuit, comprising: 2. The switching circuit according to claim 1, wherein the switches of the high-potential and low-potential side packages are FETs. The output terminals of the high-potential and low-potential packages are connected by a switching node, and the logic circuits of the high-potential and low-potential-side packages switch corresponding switches based on the voltage of the switching node and the logic input terminal, respectively. 3. The switching circuit according to claim 1, further comprising a sense circuit for controlling. Each sense circuit detects a voltage edge having a polarity opposite to a predetermined polarity of an output terminal connected to the switching node, and triggers switching of the FET to ON only after the voltage edge is detected. The switching circuit according to claim 3, wherein The logic circuit switches off each of the FETs when the AC control signal switches to a predetermined polarity, and switches each of the FETs after a predetermined delay has elapsed since the alternating control signal switched to the opposite polarity. 3. The switching circuit according to claim 1, wherein the switching circuit is turned on. 6. The switching circuit according to claim 1, wherein the plurality of high-potential-side components and the plurality of low-potential-side components are arranged in parallel. 7. The low potential side component, wherein the switch is driven by a driver which is separated from the logic circuit by a level shifter, wherein the driver is directly compliant with the low voltage side of the switch. 3. The switching circuit according to claim 1. Used in a switching circuit that switches an input DC voltage of a predetermined polarity,
An FET including a source, a drain, and a gate;
A driver for controlling the gate,
A voltage input terminal connected to the drain for inputting a high voltage side of the input DC voltage;
An input terminal connected to the source,
A logic input terminal for receiving an AC control signal,
A sense circuit that detects the voltage of the source of the FET and controls switching of the FET so that the FET is not simultaneously turned on is connected to a low-voltage circuit connected between the output terminal and the ground side of the input DC voltage. A high-potential-side component, comprising: a package including a potential-side FET and controlling the driver to switch the FET based on the logic input terminal. 9. The high potential according to claim 8, wherein the sense circuit detects a voltage edge having a polarity opposite to the predetermined polarity at the output terminal, and triggers switching of the FET to ON only after a voltage edge is detected. Side components. 10. The high-side component according to claim 8, wherein the driver and the FET are provided on separate semiconductor dies of the package, and the bonding wire connects a low voltage connection line on the driver directly to a source of the FET. . Used in a switching circuit that switches an input DC voltage of a predetermined polarity,
An FET including a source, a drain, and a gate;
A driver for controlling the gate,
A voltage input terminal connected to the source for inputting a low voltage side of the input DC voltage;
An output terminal connected to the drain,
A logic input terminal for receiving an AC control signal,
A sense circuit is connected between the high voltage side of the input DC voltage and the output terminal to detect the voltage of the drain of the FET and control the switching of the FET so that the FET is not simultaneously turned on. A logic circuit that controls the driver to switch the FET based on a switch of the logic input terminal.
The low-potential-side component, wherein the driver includes a package separated from the logic circuit and directly compliant with the source. The low side component of claim 11, wherein the driver and FET are provided on separate semiconductor dies of the package, and wherein an adhesive wire connects a low voltage connection on the driver directly to a source of the FET. 13. The sense circuit according to claim 11, wherein a voltage edge having a polarity opposite to a predetermined polarity of the output terminal is detected, and the switching of the FET is turned on only after the voltage edge is detected. Of the low-potential side. A synchronous type including a high-potential side package including a controllable FET connected between an input DC terminal and a switching node, and a low-potential side package including a synchronous FET connected between the switching node and a ground terminal. A method of operating a DC / DC converter circuit, comprising:
Driving the high-potential side and low-potential side packages alternately with a pulse width modulated AC signal;
Preventing the synchronous and controllable FETs from being simultaneously turned on;
In the high-potential-side package, the control-type FET is turned off according to a change in the polarity of the AC signal from the first polarity to the second polarity, a delay time is set, and the second polarity is switched from the second polarity to the first polarity. Switching the synchronous FET on in response to a change in polarity of the AC signal. The method of claim 14, wherein the delaying step includes a delay of a predetermined time. 15. The method of claim 14, wherein the delaying step includes waiting for a negative edge of the voltage at the switching node and triggering each of the FETs to switch on.