JP2004364114A - Image processor and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce memory capacity to be used to inversely quantize compressed image data in an image processor that decompresses the compressed image data which are subjected to progressive coding and divided into a plurality steps for transferring. <P>SOLUTION: A a first scan component detection result memory 111 and a code bit memory 112 are provided as memories used by a digital signal processing circuit that can perform high-speed processing for each element unit. An inverse quantization circuit 102 converts compressed image data of this stage into inversely quantized data of the step on the basis of the first scan component detection result and code bits. An inverse DCT conversion circuit 104 applies inverse DCT conversion to the inversely quantized data of the step, and a superposition circuit 113 subsequently superimposes the inversely quantized data of the step on inversely DCT converted image data up to the previous step stored in an image data memory 114. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing device for expanding compressed image data.
[0002]
[Prior art]
In general, a compression method using a DCT (Discrete Cosine Transform) method is widely used as a compression technique for image data. In this compression method, three primary color signals of color component information R, G, and B of each pixel in an image block unit (8 or 16 pixels in the horizontal direction and 8 or 16 pixels in the vertical direction) are converted into Y, U, After the conversion into the three components of V, the image data is converted into a frequency space by DCT conversion, and the image data is compressed by performing Huffman coding for each frequency component.
[0003]
There are two methods of compressing the above-described image data: sequential coding and progressive coding. In the sequential coding, image data of one screen is sequentially compressed in units of image blocks. On the other hand, progressive coding is a method of compressing image data of an entire screen in a plurality of stages.
[0004]
In order to decompress the sequentially encoded compressed image data, decompression processing is performed on the compressed image data block by block to generate one image. On the other hand, in order to expand the progressively encoded compressed image data, one image data is expanded in a plurality of stages. That is, in the expansion processing of the progressive compressed image data, one rough whole image having a low resolution and gradation is expanded, and then the image is sequentially expanded stepwise so that the resolution and the gradation become higher. Perform processing.
[0005]
With the rapid spread of the Internet in recent years, when processing image data, the above-described image data compression method has been widely used. In this case, similarly to the above-described sequential-encoded compressed image data, progressive-encoded compressed image data is widely used, for example, as described in Patent Documents 1, 2, or 3.
[0006]
On the other hand, terminal devices that handle such compressed image data include not only ordinary PCs (Personal Computers) but also terminal devices such as mobile phones and personal digital assistants. The feature of these portable terminals is that they are small and lightweight, and their image display circuits are provided with circuits having a low resolution and capable of displaying only a small amount of color information, unlike image display circuits such as PCs. Often. Further, in such a portable terminal, it is required that the capacity of the memory be realized with a smaller capacity.
[0007]
Hereinafter, an example of a conventional image processing apparatus using these portable terminals will be described with reference to the drawings.
[0008]
FIG. 8 is a block diagram showing a conventional image processing apparatus for expanding compressed image data.
[0009]
In the figure, 301 is a Huffman decoding circuit, 302 is an inverse quantization circuit, 303 is a quantization table creation circuit, 304 is an inverse DCT transformation circuit, 305 is a color space transformation circuit, and 306 is a color number reduction circuit. Reference numeral 307 denotes a compressed image data memory; 308, an image data memory after inverse quantization; and 309, a final image data memory.
[0010]
Further, in FIG. 8, 331 is a signal line of compressed image data, 332 is a Huffman-decoded image data signal line, 333 is a quantization table information related data signal line, 334 is a quantization table data signal line, and 335 is inverse quantization. The coded image data signal line 336 is an inversely quantized image data signal line up to the previous stage of the progressively encoded image data. Reference numeral 337 denotes a YUV image data signal line subjected to inverse DCT conversion, 338 denotes an RGB image data signal line subjected to color space conversion, and 339 denotes an RGB image data signal line after the number of colors has been reduced.
[0011]
Next, a description will be given of a process of decompressing progressively encoded compressed image data in the conventional image processing apparatus shown in FIG.
[0012]
When performing the expansion processing of the progressively coded compressed image data at each stage, the compressed image data coded by the frequency division type progressive coding is transferred for each element unit of the image at the time of transfer. There is a divided bit system in which a plurality of bits representing an element are divided into a plurality of bits and sequentially transferred for each divided bit. The expansion processing of compressed image data transferred by the divided bit system will be described below.
[0013]
"Process 1"
The Huffman decoding circuit 301 analyzes header information from the compressed image data in the compressed image data memory 307, extracts quantization table data, and performs Huffman decoding of the compressed image data.
[0014]
Here, the compressed image data stored in the compressed image data memory 307 is made up of 64 elements as shown in FIG. 3, and each element unit has a plurality of bits (for example, 8 bits). The plurality of bits of each element are divided into a plurality of parts and sequentially transferred. More specifically, for example, when each element unit is composed of 8 bits, it is divided into, for example, four bit groups, and the divided bit group of each element unit illustrated in FIG. The divided bit sets for each element illustrated in FIGS. 9B, 9C, and 9D are sequentially transferred thereafter. The number of division bits for each element unit shown in FIG. 4A is larger for lower frequency components, and the number of division bits for each element unit shown in FIG. 4D is larger for higher frequency components. For example, in the first element which is a low-frequency component, there are 3 bits in FIG. 4A, 3 bits in FIG. 4B, 2 bits in FIG. 4C, and 0 bits in FIG. 4D. On the other hand, in the 64th element, which is a high frequency component, 0 bit in FIG. 4A, 1 bit in FIG. 4B, 4 bits in FIG. 4C, and 3 bits in FIG. 4D. Therefore, the scan component transmitted first in each element unit, that is, the first scan component of each element is transmitted for the first time in the first to 58th element units, as can be seen from FIG. In the 59th to 64th element units, the data is transferred for the second time as shown in FIG.
[0015]
"Process 2"
The inverse quantization circuit 302 performs an inverse quantization process on the compressed image data at this stage, which has been Huffman-decoded by the Huffman decoding circuit 301, based on the quantization table created by the quantization table creation circuit 303. At this time, the dequantized compressed image data of this stage and the compressed image data of the previous stage stored in the image data memory 308 after dequantization are superimposed to obtain the inverse quantized image data of this stage. Create compressed image data. The new compressed image data is updated in the dequantized image data memory 308.
[0016]
"Process 3"
In the inverse DCT transform circuit 304, the image data up to this stage, which has been inversely quantized by the inverse quantization circuit 302, is inversely DCT-transformed and expanded to generate pixel data (YUV data) such as luminance information.
[0017]
"Process 4"
The color space conversion circuit 305 performs color space conversion of the YUV data subjected to the inverse DCT conversion by the inverse DCT conversion circuit 304 to generate color information data (RGB image data), and outputs the color information data to the color number reduction circuit 306. .
[0018]
"Process 5"
The number-of-colors reduction circuit 306 reduces the number of colors to a gradation that matches the gradation performance of the image display circuit that has the gradations of R (red), G (green), and B (blue). At this time, processing is performed using a technique such as an error diffusion method so that the appearance of the image is as different as possible before and after the color number reduction is performed. When these series of processes are completed, the decompressed image data is stored in the final image data memory 309.
[0019]
[Patent Document 1]
JP-A-6-113301
[Patent Document 2]
JP-A-6-268873
[Patent Document 3]
WO 99/07155 pamphlet
[0020]
[Problems to be solved by the invention]
However, the conventional image processing apparatus has a problem in that a large-capacity compressed image data memory 308 that stores all of the dequantized image data for one screen is required. More specifically, in the conventional image processing apparatus, in the stage of input data to the inverse DCT transform circuit 304, that is, in the stage of inverse quantization by the inverse quantization circuit 302, the compressed image data at this stage is It is superimposed on the compressed image data up to the previous stage. For this reason, the amount of the inversely quantized compressed image data is required for all the pixels of one screen by the number of bits of the required resolution of the YUV data such as the luminance information. Had a large capacity.
[0021]
In particular, in a small and lightweight terminal device such as a mobile phone or a portable information terminal, it is required that the memory has a smaller capacity. In addition, in order to realize low power and low cost in these mobile phones and portable information terminals, a central processing unit (CPU) having a lower processing capability than a PC (Personal Computer) and a voice, audio, image, etc. In many cases, a digital signal processor (DSP) for implementing the media processing efficiently and at high speed is mounted. In a system equipped with both a central processing circuit having this low processing capability and a processor for digital signal processing for high-speed processing, when the progressive image data is expanded, the digital signal processing processor uses the Huffman decoding circuit 301, It has a quantization circuit 302, a quantization table creation circuit 303, an image data memory 308 after inverse quantization, and an inverse DCT conversion circuit 304, and a central processing circuit is a compressed image data memory 307, a color space conversion circuit 305, a color A number reduction circuit 306 and a final image data memory 309 are provided. Therefore, the central processing circuit controls the final image data memory 309 and the compressed image data memory 307, and the digital signal processing processor controls the image data memory 308 after the inverse quantization.
[0022]
However, the memory controlled by the digital signal processing processor is a memory that requires a high-speed operation, and the cost per storage unit is high. On the other hand, the memory controlled by the central processing circuit can operate at a low speed, the cost per storage unit is low, and even if the memory is large, it is lower than the small memory controlled by the digital signal processing processor. Price.
[0023]
Therefore, it is important to reduce the capacity of the image data memory 308 after the inverse quantization controlled by the digital signal processing processor in order to reduce the system cost.
[0024]
An object of the present invention is to provide an image processing apparatus for decompressing compressed image data, in which the compressed image data is encoded by frequency-division progressive coding, and sequentially transferred in a divided bit system for each element unit. Even in some cases, measures are taken to reduce the capacity of the expensive and high-speed data memory controlled by the digital signal processing circuit.
[0025]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, when decompressing compressed image data encoded by the progressive encoding of the frequency division type and divided bit system, the compressed image data of each stage divided into bits Each of the expensive and high-speed data memories controlled by the digital signal processing circuit stores only a minimum amount of information so that the dequantized data at that stage can be satisfactorily generated. The superimposition of the compressed image data is performed after the inverse DCT transform controlled by the central processing circuit.
[0026]
According to the present invention, as another solution, when the capacity of an expensive and high-speed data memory is limited to a small amount, the expensive and high-speed operation can be performed so that a desired resolution can be obtained for the entire reproduced image. The appropriate capacity of the data memory is appropriately distributed among the elements of the compressed image data.
[0027]
Specifically, the image processing apparatus according to the first aspect of the present invention provides compressed image data encoded by frequency division progressive coding, divided into a plurality of bits for each element unit, and sequentially transferred for each divided bit. An image processing apparatus for decompressing, wherein a scan component detection circuit that detects a first scan component for each element unit of the compressed image data, and wherein the first scan component is detected for each element unit by the scan component detection circuit. A scan component detection result memory, a code bit memory for storing a code bit for each element unit of the compressed image data based on a detection result of the scan component detection circuit, the scan component detection result memory and the code An inverse quantization circuit that inversely quantizes the compressed image data for each element based on the output of the bit memory; A decompression processing circuit for decompressing the compressed image data at the stage corresponding to each divided bit obtained by the inverse quantization circuit, a superimposition circuit, and an image data memory, wherein the superimposition circuit is provided in the image data memory. The stored data and the current stage image data expanded by the expansion processing circuit are superimposed, and the image data memory stores the image data superimposed by the superimposition circuit.
[0028]
According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the image processing apparatus further includes a first processor and a second processor, wherein the first processor includes the scan component detection circuit, the scan component detection result memory, It has a sign bit memory, the inverse quantization circuit and the decompression circuit, and the second processor has the superposition circuit and the image data memory.
[0029]
According to a third aspect of the present invention, in the image processing apparatus according to the first aspect, a color space conversion circuit that performs color space conversion on the compressed image data expanded by the expansion processing circuit to obtain color information data; A color number reduction circuit for reducing the number of colors by lowering the gradation of the color information data obtained by the space conversion circuit, wherein the superimposing circuit and the image data memory include the color space conversion circuit and the color number reduction circuit; It is characterized by being arranged between.
[0030]
According to a fourth aspect of the present invention, in the image processing apparatus of the third aspect, the image processing apparatus is provided in a mobile terminal including a mobile phone and a mobile information terminal.
[0031]
An image processing apparatus according to a fifth aspect of the present invention is an image processing apparatus for expanding compressed image data encoded by frequency division progressive coding, divided into a plurality of bits for each element unit, and sequentially transferred for each divided bit. A screen size detection circuit that analyzes header information of the compressed image data to detect a screen size of the compressed image data; an image data memory having a predetermined storage capacity; A bit number calculation circuit for calculating the number of bits allocated to each element unit of the compressed image data based on the screen size and the storage capacity of the image data memory; and a first scan for each element unit of the compressed image data. A scan component detection circuit for detecting a component, and the first scan for each element unit by the scan component detection circuit. Based on the outputs of the scan component detection result memory and the image data memory, and dequantizes the compressed image data for each element unit. An inverse quantization circuit for storing in the image data memory compressed image data within the number of bits assigned to each element by the bit number calculation circuit in the compressed image data, and an inverse quantization circuit. A decompression processing circuit for decompressing the compressed image data.
[0032]
According to a sixth aspect of the present invention, in the image processing apparatus according to the fifth aspect, the image processing apparatus further includes a first processor and a second processor, wherein the first processor includes the screen size detection circuit, the image data memory, and the number of bits. It has a calculation circuit, the scan component detection circuit, the scan component detection result memory, the inverse quantization circuit, and the decompression processing circuit.
[0033]
The image processing method according to the present invention is an image processing method for decompressing compressed image data encoded by frequency division progressive coding, divided into a plurality of bits for each element unit, and sequentially transferred for each divided bit. A method for detecting a first scan component for each element unit of the compressed image data, and storing that a first scan component is detected for each element unit based on a detection result of the scan component, A code bit is stored for each element unit, and then, based on the stored detection result of the first scan component for each element unit and a code bit for each element unit, the compressed image data is stored for each element unit. In addition to the inverse quantization, the compressed image data at this stage obtained by the inverse quantization is expanded, and then the expanded image data at this stage And repeating the combining image data and superimposed up.
[0034]
The image processing method according to the present invention is an image processing method for expanding compressed image data encoded by frequency division progressive coding, divided into a plurality of bits for each element unit, and sequentially transferred for each divided bit. Analyzing the header information of the compressed image data to detect the screen size of the compressed image data, and based on the screen size and the storage capacity of the provided image data memory, Calculate the number of bits allocated to each element unit, then detect the first scan component for each element unit of the compressed image data, and, based on the detection result of the scan component, determine the first scan component for each element unit. Is detected, and thereafter, the stored scan component detection result and the compression stored in the image data memory are stored. Based on the image data, the compressed image data is dequantized for each element unit, and the compressed image data within the number of bits allocated to each element unit among the dequantized compressed image data is converted to the image data. The method is characterized in that the compressed image data that has been dequantized is repeatedly expanded and stored in the memory.
[0035]
As described above, according to the first to fourth and seventh aspects of the present invention, since the scan component detection circuit, the scan component detection result memory, and the sign bit memory are provided, the scan component detection result and the sign bit for each element unit are stored. Based on this, the compressed image data at this stage is correctly dequantized. The inverse-quantized compressed image data of the current order is subjected to inverse DCT transform, and then superimposed on the compressed image data after inverse DCT transform up to the previous stage stored in the image data memory by the superimposing circuit, The compressed image data after the inverse DCT conversion up to this stage is obtained.
[0036]
Here, in the arithmetic processing up to the inverse DCT transformation, that is, the arithmetic processing performed by the digital signal processing device capable of high-speed processing, a scan component detection result memory and a sign bit memory are used, and each of these memories has a 1-bit capacity. As a result, the capacity of the memory used by the digital signal processing circuit can be significantly reduced as compared with the related art.
[0037]
According to the inventions of claims 5, 6 and 8, the screen size is detected in advance from the compressed image data, and the number of bits allocated to each element of the image data memory is calculated according to the screen size. After that, when the compressed image data is inversely quantized, the calculated number of allocated bits in each element unit of the inversely quantized compressed image data is equal to the dequantized compressed image data memory. Is stored in Accordingly, the capacity distribution of each element of the compressed image data memory after inverse quantization becomes appropriate, and even if the compressed image data memory after inverse quantization has a small capacity, the screen size of the compressed image data is reduced. Regardless, the entire screen can be displayed well with a uniform resolution.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an image processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.
[0039]
(First Embodiment)
FIG. 1 shows an overall configuration of an image processing apparatus according to a first embodiment of the present invention. The image processing apparatus shown in the figure is built in a portable terminal such as a portable telephone or a portable information terminal, and expands a JPEG (Joint Photographic Coding Experts Group) color-compressed still image.
[0040]
In FIG. 1, 101 is a Huffman decoding circuit, 102 is an inverse quantization circuit, 103 is a quantization table creation circuit, 104 is an inverse DCT conversion circuit (decompression processing circuit), 105 is a color space conversion circuit, and 106 is a color number reduction circuit. , 107 is a compressed image data memory, and 109 is a final image data memory. The compressed image data memory 107 stores compressed image data encoded by frequency division progressive coding.
[0041]
110 is a first scan component detection circuit for detecting the first scan component for each element unit of the compressed image data, 111 is a scan component detection result memory for storing that the first scan component is detected for each element unit, and 112 is a scan component detection result memory. A sign bit memory for each element unit for storing "positive" or "negative" sign bits of the data for each element unit, 113 is a superimposition circuit, 114 is a superimposed image data expanded up to the previous stage. An image data memory 115 is a selector.
[0042]
Reference numeral 131 denotes a compressed image data signal line, 132 denotes a Huffman-decoded image data signal line, 133 denotes a quantization table information-related data signal line, 134 denotes a quantization table data signal line, and 135 denotes inverse quantization for each stage. A data signal line 136 is a YUV image data signal line subjected to inverse DCT conversion in each stage, and 137 is a YUV image data obtained by superimposing the YUV image data expanded up to the previous stage and the current stage YUV image data. Reference numeral 138 denotes an RGB image data signal line subjected to color space conversion, and 139 denotes an RGB image data signal line after the number of colors has been reduced.
[0043]
Further, 140 is a YUV image data signal line after the selector 115, 141 is a signal line of the first scan detection result for each element unit, 142 is a code bit signal line for each element unit, and 143 is the first scan detection result memory 111 Reference numeral 144 denotes a signal line from the sign bit memory 112, and 145 denotes a signal line of image data obtained by superimposing image data expanded to the previous stage.
[0044]
FIG. 2 shows the data structure of the compressed image data stored in the compressed image data memory 107. In the figure, each of the 64 pixels has 8 bits of data, and the first first sign bit (11... 18 to 81... 88) and 7 bits of data (11x. 18x to 81x to 88x).
[0045]
Next, a description will be given of a process of decompressing progressively encoded compressed image data. Here, FIGS. 4A to 4D illustrate an example of a process of decompressing progressively encoded compressed image data in the case of bit division in four stages.
[0046]
FIG. 3 shows 8 × 8 pixel data, and the numbers 1 to 64 represent the transfer order of the compressed image data. FIGS. 4A to 4D show the number of division bits of the 8 × 8 pixel data. 4A shows the number of divided bits at the first stage, FIG. 4B shows the number of divided bits at the second stage, FIG. 4C shows the number of divided bits at the third stage, and FIG. Indicates the number of division bits in each stage.
[0047]
"Process 1"
The Huffman decoding circuit 101 transfers the first-stage compressed image data having a predetermined number of division bits for each element unit shown in FIG. 4A from the compressed image data memory 107, and obtains a profile of the compressed image data. Parses some header information.
[0048]
"Process 2"
The Huffman decoding circuit 101 performs a Huffman decoding process on the first-stage compressed image data, outputs the Huffman-decoded compressed image data to an inverse quantization circuit 102, and outputs a quantization table from the compressed image data. Is output to the quantization table creation circuit 103.
[0049]
"Process 3"
The first scan component detection circuit 110 uses the compressed image data after Huffman decoding from the Huffman decoding circuit 101 to detect whether or not there is pixel data in which the first scan component exists for each element unit, and determines the detection result. The first scan detection result memory 111 for each element unit is stored.
[0050]
For example, referring to FIG. 4, in the first stage shown in FIG. 4A, the first to 28th pixel data of FIG. 3 correspond to 3 bits, and the 29th to 58th pixel data of FIG. Pixel data up to 1 bit. That is, in the first stage, the first to the 58th scan components in FIG. 3 include the first scan component for each element unit. Therefore, in the first stage, the result information "1" of detecting the first scan component for the pixels corresponding to the 1st to 58th pixels is stored in the first scan component detection result memory 111.
[0051]
In the second stage shown in FIG. 4B, the first scan component exists in the 59th to 64th pixel data in FIG. Therefore, in the second stage, the first scan component detection result memory 111 overwrites and stores the result information “1” of the result of detecting the first scan component for the pixels corresponding to the 59th to 64th pixels.
[0052]
In the third and fourth stages shown in FIG. 4C and FIG. 4D, the first scan component of each element unit has already been detected for all the elements, and the first scan component has been first detected for all the elements. Since there is no scan component, the storage content of the first scan component detection memory 111 is not updated.
[0053]
Further, at the same time, when the first scan component detection circuit 110 determines that the pixel data includes the first scan for each element unit, the code bit of the image data of each element unit for which it is determined that the first scan component exists exists. Is detected, and the code bit in each element unit is stored in the code bit memory 112.
[0054]
For example, referring to FIG. 4, in the first stage shown in FIG. 4A, three bits of code bits for the first to 28th elements in which the first scan component exists, and the 29th element The code bits for one bit for the elements up to the 58th element are stored in the code bit memory 112. In the second stage shown in FIG. 4B, one code bit for the 59th to 64th elements in which the first scan component exists is stored in the code bit memory 112. In the third and fourth stages shown in FIGS. 4 (c) and 4 (d), since the first scan component has already been detected in all the elements and the first scan component does not exist, the code bit The content stored in the memory 112 is not updated.
[0055]
"Process 3"
In the inverse quantization circuit 102, the quantization table information from the quantization table creation circuit 103, the compressed image data Huffman-decoded by the Huffman decoding circuit 101, and the detection of the first scan component detection result memory 111 for each element unit Using the result and the code bit information of the code bit memory 112 for each element unit, the Huffman-decoded compressed image data at this stage is inversely quantized and output to the inverse DCT transform circuit 104.
[0056]
Here, the data of each element unit that has been determined to be the first scan component in each element unit is inversely quantized. On the other hand, if the first scan component has been detected by the previous stage, the inverse quantization circuit 102 outputs the data of each element unit that is determined not to be the first scan component from the sign bit memory 112. After the sign bit information is obtained, the current data of each element unit is inversely quantized according to the “positive” or “negative” sign indicated by the sign bit, and then output to the inverse DCT transform circuit 104.
[0057]
For example, in the first stage shown in FIG. 4A, three bits of the first to 28th elements and one bit of the 29th to 58th elements where the first scan component exists are used. , And outputs the result to the inverse DCT transform circuit 104. In the second stage shown in FIG. 4B, inverse quantization is performed for one bit of the 59th to 64th elements in which the first scan component exists, and the first scan component that has already detected the first scan component is used. Regarding the three bits at this stage of the first to twenty-eighth elements and the one bit at this stage of the twenty-ninth to fifty-eighth elements, the own element stored in the sign bit memory 112 After performing a predetermined process on the basis of the sign bit information, the inverse quantization process is performed and output to the inverse DCT transform circuit 104. In the third and fourth stages shown in FIGS. 4 (c) and 4 (d), since the first scan component has already been detected in all the elements, the bits of the current stage of all the elements are as follows. After performing the corresponding processing based on the sign bit information of the sign bit memory 112, an inverse quantization process is performed and output to the inverse DCT transform circuit 104.
[0058]
"Process 4"
The inverse DCT transform circuit 104 performs an inverse DCT transform on the compressed image data of the current stage that has been inversely quantized by the inverse quantization circuit 102 to expand the image data, thereby generating pixel data (YUV data) such as luminance information.
[0059]
Thereafter, the superimposition circuit 113 superimposes the image data of the current stage from the inverse DCT transform circuit 104 and the image data of the previous stage stored in the image data memory 114 to obtain the luminance information up to this stage. And the like is generated. At the same time, the generated pixel data is stored in the image data memory 114.
[0060]
"Process 5"
The color space conversion circuit 105 performs color space conversion on the YUV data generated by the inverse DCT conversion circuit 104, generates color information data (RGB image data), and outputs the color information data to the color number reduction circuit 106.
[0061]
"Process 6"
The color number reduction circuit 106 reduces the number of colors to R (red), G (green), and B (blue) to a gradation suitable for the performance related to the gradation of the image display circuit of the image processing circuit. . At this time, processing is performed using a technique such as an error diffusion method so that the appearance of the image is as different as possible before and after the color number reduction is performed. When a series of these processes is completed, the decompressed image data is stored in the final image data memory 109.
[0062]
In the present embodiment, for the digital signal processing from the Huffman decoding circuit 101 to the inverse DCT transform circuit 104, a 1-bit first detection result memory 111 for each element unit and a 1-bit code bit for each element unit Only the memory 112 is provided, and the compressed image data after the Huffman decoding at this stage can be converted into the inversely quantized data at this stage by using a 2-bit memory for each element unit. Unlike the compressed image data memory 308 after inverse quantization shown in FIG. 8, it is not necessary to have 8-bit data for each element unit, and the memory used for digital signal processing can be configured with a small capacity.
[0063]
On the other hand, the image data memory 114 after the inverse DCT transformation needs a large capacity, but is arranged at the position after the inverse DCT transformation, and a central processing circuit (CPU) having a lower processing capacity than the PC is required. Since it is used and a low-speed operation is sufficient, even a large capacity can be obtained at a low price.
[0064]
Note that the image processing apparatus shown in FIG. 1 is also capable of decompressing sequentially encoded compressed image data. Hereinafter, this decompression processing will be described.
[0065]
"Process 1"
The sequentially encoded compressed image data in the compressed image data memory 107 is directly input to the Huffman decoding circuit 101.
[0066]
"Process 2"
After analyzing the header information of the input compressed image data, the Huffman decoding circuit 101 performs a Huffman decoding process on the compressed image data, outputs the result to the inverse quantization circuit 102, and outputs a quantized image from the compressed image data. The data related to the quantization table is output to the quantization table creation circuit 103.
[0067]
"Process 3"
The inverse quantization circuit 102 performs an inverse quantization process on the quantization table information from the quantization table creation circuit 103 and the quantized image data Huffman-decoded by the Huffman decoding circuit 101, and outputs the result to the inverse DCT transform circuit 104. .
[0068]
"Process 4"
The inverse DCT transformation circuit 104 expands the compressed image data by inverse DCT transforming the image data of each block dequantized by the inverse quantization circuit 102 to obtain pixel data (YUV data) such as luminance information. Is generated and output to the color space conversion circuit 105.
[0069]
"Process 5"
The color space conversion circuit 105 performs color space conversion on the YUV data generated by the inverse DCT conversion circuit 104, generates color information data (RGB image data), and outputs the color information data to the color number reduction circuit 106.
[0070]
"Process 6"
The number-of-colors reduction circuit 106 reduces the number of colors by reducing the gradation of each color of R (red), G (green), and B (blue) to a gradation that matches the performance related to the gradation of the display circuit of its own. I do. At this time, processing is performed using a technique such as an error diffusion method so that the appearance of the image is as different as possible before and after the color number reduction is performed. When these series of processes are completed, the decompressed image data is stored in the final image data memory 109.
[0071]
In this embodiment, the superposition circuit 113 and the image data memory 114 are arranged between the inverse DCT conversion circuit 104 and the color space conversion circuit 105. May be arranged between the color space conversion circuit 105 and the color number reduction circuit 106.
[0072]
Further, in the present embodiment, the portable terminal provided with the color number reduction circuit 106 is exemplified. However, when the image processing device of the present invention is provided in an image display device not provided with the color number reduction circuit 106, the final image The memory 109 may be shared by the image data memory 114.
[0073]
(Second embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.
[0074]
The image processing apparatus shown in FIG. 5 further includes a header analysis circuit 116 relating to an image size, a storage capacity allocating circuit 117, and an inverse-quantized And an image data memory 108. The image data memory 108 after the inverse quantization has a built-in sign bit memory 112.
[0075]
In the figure, 151 is a signal line of header information relating to the image size, 152 is a signal line of an analysis result relating to the image size of the header analysis circuit 116, 153 is an output of the storage capacity allocating circuit 117, and is an image after inverse quantization. This is bit allocation information of the data memory 108. The compressed image data up to this stage, which has been inversely quantized by the inverse quantization circuit 102, is output to the image data memory 108 after inverse quantization via the signal line 135 and stored.
[0076]
Further, the image processing apparatus shown in FIG. 5 does not include the superposition circuit 113, the image data memory 114 after the inverse DCT transform, and the selector 140 in the image processing apparatus shown in FIG.
[0077]
Next, expansion processing of compressed image data encoded by the frequency division progressive coding will be described. Similar to the first embodiment, description will be made using an example in which bits are divided into four stages in FIGS. 3 and 4A to 4D.
[0078]
"Process 1"
The Huffman decoding circuit 101 analyzes header information which is a profile of the compressed image data stored in the compressed image data memory 107.
[0079]
Subsequently, a header analysis circuit (screen size detection circuit) 116 relating to the image analyzes the image size of the compressed image data stored in the compressed image data memory 107 and detects the screen size of the compressed image data. The storage capacity allocating circuit (bit number calculating circuit) 117 determines bit allocation (number of allocated bits) for each element unit in the compressed image data memory 108 after inverse quantization based on the detected screen size. .
[0080]
For example, assuming that the capacity of the image data memory 108 after inverse quantization is 6 Kbytes (49152 bits = 6 × 1024 × 8 bits), the compressed image size is 96 × 96, and YUV = 4: 2: 0, the necessary pixel data is Y pixels = 96 × 96 = 9216, U and V pixels = 48 × 48 × 2 = 4608. Therefore, the number of allocated bits per element unit in the image data memory 108 is 49152 bits / (9216 + 4608) pixels = 3.56 bits / pixel. Therefore, in this case, the bit allocation per element unit except for the sign bit is two bits (the sign bit is stored in the sign bit memory 112).
[0081]
"Process 2"
The Huffman decoding circuit 101 analyzes the header information of the compressed image data, performs a Huffman decoding process on the compressed image data, outputs the result to the inverse quantization circuit 102, and outputs data relating to the quantization table from the compressed image data. And outputs it to the quantization table creation circuit 103.
[0082]
Thereafter, the first scan component detection circuit 110 uses the compressed image data after the Huffman decoding process, which is the output of the Huffman decoding circuit 101, to detect whether or not the first scan component exists for each element unit. The detection result is stored in the first scan component detection result memory 111 for each element unit.
[0083]
For example, in the case of FIG. 4, as shown in FIG. 4A, in the first stage, the first to 28th pixel data of FIG. 3 correspond to 3 bits, and the 29th to 58th pixel data of FIG. Exist for one bit. That is, in the first stage, the first scan component exists for each element unit in the 1st to 58th pixels in FIG. Therefore, in the first stage, the result information “1” of detecting the first scan component for each element unit is stored in the scan component detection result memory 111 for each element unit for the pixels corresponding to the 1st to 58th pixels. I do. In the second stage shown in FIG. 3B, the first scan component exists in the 59th to 64th pixel data in FIG. 3, so in the second stage, the pixels corresponding to the 59th to 64th pixels are On the other hand, the result information "1" of detecting the first scan component for each element unit is overwritten and stored in the first scan component detection result memory 111. In the third and fourth stages shown in FIGS. 3C and 3D, the first scan component is already detected in all element units, and the first scan component is in all element units. Therefore, the storage content of the first scan component detection result memory 111 is not updated.
[0084]
At the same time, in the element for which it is determined that the first scan component is present in the first scan component detection circuit 110 in each element unit, the code bit of the image data of the element is detected, and the code bit is detected in each element unit. Separately, it is stored in the sign bit memory 112.
[0085]
"Process 3"
In the inverse quantization circuit 102, the quantization table information from the quantization table creation circuit 103, the quantized image data Huffman-decoded by the Huffman decoding circuit 101, the detection result of the first scan component detection result memory 111, and the code Using the code bit information for each element unit of the bit memory 112 and the image data 108 after the inverse quantization, inverse quantization processing of the quantized image data up to this stage is performed, and the inverse DCT transform circuit 104 Output. At this time, of the inversely quantized data, bits other than the sign bit are stored in the inversely quantized image data memory 108 within the number of allocated bits per element unit controlled by the storage capacity allocating circuit 117. I do. At the same time, based on the scan component detection result information for each element in the first scan component detection result memory 111, each element for which the first scan component has been detected by the previous stage is detected by the inverse quantum The dequantized image 135 is stored in the dequantized image data memory 108 within the number of bits per element unit allocated by the storage capacity allocating circuit 117.
[0086]
For example, in the case of FIG. 4, in the first stage shown in FIG. 4A, three bits of code bits of data of each element unit from 1 to 28 in FIG. The sign bit of one bit of the data of each element from the 29th to 58th in FIG. 3 is stored in the sign bit memory 112. In the second stage shown in FIG. 6B, one sign bit of data of each element unit from 59th to 64th in FIG. 3 where the first scan component exists is stored in the sign bit memory 112. In the third stage and the fourth stage shown in FIGS. 9C and 9D, since the scan components have already been detected in all the element units, the storage contents of the sign bit memory 112 are updated. Absent.
[0087]
Further, in the present embodiment, the assignment other than the code bit for each element unit is 2 bits. Therefore, in the first stage shown in FIG. Of the bits, two bits other than the sign bit are stored in the image data memory 108 after the inverse quantization. Since there are no bits other than the sign bit in the 29th to 58th element units in FIG. 3, the bits are not stored in the image data memory 108 after the inverse quantization. In the second stage shown in FIG. 4B, the previously stored bits correspond to two bits up to the 1st to 28th positions in FIG. 3, and the 29th to 58th positions in FIG. One bit is stored in the image data memory 108 after inverse quantization for each element unit. In the third stage shown in FIG. 4C, the previously stored bits correspond to two bits for the 1st to 28th positions in FIG. 3, and the pixel data in the second stage for the 29th to 58th positions in FIG. In addition to the 1 bit, the upper 1 bit of the 4 bits of the pixel data of each element in the third stage is the 59th to 64th of FIG. The upper two bits of the four bits of the pixel data are stored in the image data memory 108 after inverse quantization for each element unit.
[0088]
"Process 4"
In the inverse DCT transform circuit 104, the compressed image data is expanded by performing inverse DCT transform of the image data at this stage, which has been inversely quantized by the inverse quantization circuit 102, to obtain pixel data such as luminance information (YUV data). ).
[0089]
"Process 5"
The color space conversion circuit 105 performs color space conversion on the YUV data generated by the inverse DCT conversion circuit 104, generates color information data (RGB image data), and outputs the color information data to the color number reduction circuit 106.
[0090]
"Process 6"
The number-of-colors reduction circuit 106 reduces the number of colors to a gradation that matches the performance of the display circuit having the R (red), G (green), and B (blue) colors. At this time, processing is performed using a technique such as an error diffusion method so that the appearance of the image is as different as possible before and after the color number reduction is performed. When these series of processes are completed, the decompressed image data is stored in the final image data memory 109.
[0091]
Therefore, in the present embodiment, the screen size of the compressed image data in the compressed image data memory 107 is detected in advance by the header analysis circuit 116, and the storage capacity allocating circuit 117 determines the screen size and the inverse quantum The number of allocated bits of pixel data for each element unit is determined according to the storage capacity of the image data memory 108 after the quantization, and then the compressed image for each element unit is inversely quantized by the inverse quantization circuit 102. The data is stored in the image data memory 108 after the inverse quantization within the number of allocated bits. Accordingly, the capacity distribution of each element unit of the image data memory 108 after the inverse quantization becomes appropriate, and even if the image data memory 108 has a small capacity, regardless of the screen size of the compressed image data, The entire screen can be displayed well with a uniform resolution.
[0092]
(Third embodiment)
Next, an image processing apparatus according to a third embodiment of the present invention will be described.
[0093]
FIG. 6 shows an image processing apparatus according to the present embodiment, which has two processors 201 and 202. The overall configuration of this image processing apparatus is the same as the configuration shown in FIG.
[0094]
The first processor 201 includes a Huffman decoding circuit 101, an inverse quantization circuit 102, a quantization table creation circuit 103, an inverse DCT transformation circuit 104, a first scan component detection circuit 110 for each element unit, and a first And a DSP for performing digital signal processing at high speed, having a scan component detection result memory 111 and a code bit memory 112 for each element unit.
[0095]
On the other hand, the second processor 202 converts the decompressed image data after superimposition up to the previous stage into a color space conversion circuit 105, a color number reduction circuit 106, a compressed image data memory 107, a final image data memory 109, a superimposition circuit 113. It is realized by a CPU having an image data memory 114 for storing and a selector 115 and performing general-purpose processing.
[0096]
In the present embodiment, specifically, the scan component detection result memory 111 and the code bit memory 112 need to be controlled by the first processor 201 that processes digital signal processing at high speed and operate at high speed. Since each of the memories 111 and 112 is constituted by a 1-bit memory for each element unit, it is extremely small as compared with a conventional image data memory constituted by a plurality of bits (for example, 8 bits) for each element unit. Can be capacity. In addition, since the image data memory 114 after the inverse DCT conversion is controlled by the CPU 202 that performs general-purpose processing and does not need to operate at a high speed, it can be obtained at a low price even with a large capacity.
[0097]
(Fourth embodiment)
Next, an image processing apparatus according to a fourth embodiment of the present invention will be described.
[0098]
FIG. 7 illustrates an image processing apparatus according to the present embodiment, which includes two processors 201 and 202. The overall configuration of this image processing apparatus is the same as the configuration shown in FIG.
[0099]
The first processor 201 includes a Huffman decoding circuit 101, an inverse quantization circuit 102, a quantization table creation circuit 103, an inverse DCT conversion circuit 104, a first scan component detection circuit 110 for each element unit, and a first , A scan component detection result memory 111, a code bit memory 112 for each element unit, an image data memory 108 after inverse quantization, a header analysis circuit 116, and a storage capacity allocating circuit 117. This is realized by the DSP performed in the above.
[0100]
On the other hand, the second processor 202 includes a color space conversion circuit 105, a color number reduction circuit 106, a compressed image data memory 107, and a final image data memory 107, and is realized by a CPU that performs general-purpose processing.
[0101]
Therefore, in the present embodiment, the inversely quantized image data memory 108 including the sign bit memory 112 is controlled by the first processor 201 that performs digital signal processing at high speed, and needs to operate at high speed. Since the image data memory 308 including the bit memory 112 is composed of small bits (3 bits) for each element unit, the conventional image data memory 308 shown in FIG. 8 is composed of multiple bits (8 bits) for each element unit. Memory capacity used by a processor that performs digital signal processing at high speed can be reduced as compared to the case where
[0102]
【The invention's effect】
As described above, according to the image processing apparatus and the image processing method according to the first to fourth and seventh aspects of the present invention, only a scan component detection result memory and a sign bit memory are provided as memories, Since the compressed image data of the current stage is correctly converted into the dequantized data of the current stage, and after the inverse DCT conversion, the compressed image data of the current stage is superimposed on the compressed image data of the previous stage. By eliminating the need for a large-capacity memory for storing all of the dequantized image data for one screen, the capacity of the memory used by the digital signal processing circuit can be significantly reduced.
[0103]
Further, according to the image processing apparatus and the image processing method of the invention according to claims 5, 6 and 8, the screen size is detected in advance from the compressed image data, and each element unit of the image data memory is detected in accordance with the screen size. Since the number of bits allocated to the compressed image data memory after inverse quantization is appropriately determined, the compressed image data memory after inverse quantization is limited to a small capacity by appropriately allocating the capacity of each element unit. Regardless of the screen size of the data, the entire screen can be favorably displayed with a uniform resolution suitable for a small image display circuit of a mobile phone or a portable information terminal.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an image processing apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a data configuration of each element constituting compressed image data.
FIG. 3 is a diagram showing a compression order of compressed image data.
4A is a diagram showing the number of divided bits in pixel units in the first stage of compressed image data, FIG. 4B is a diagram showing the number of divided bits in the second stage, and FIG. 4C is a diagram showing the third stage FIG. 7D is a diagram showing the number of divided bits in the fourth stage.
FIG. 5 is a block diagram illustrating an image processing apparatus according to a second embodiment of the present invention.
FIG. 6 is a block diagram illustrating an image processing apparatus according to a third embodiment of the present invention.
FIG. 7 is a block diagram illustrating an image processing apparatus according to a fourth embodiment of the present invention.
FIG. 8 is a block diagram illustrating a conventional image processing apparatus.
[Explanation of symbols]
101 Huffman decoding circuit
102 Inverse quantization circuit
103 Quantization table creation circuit
104 inverse DCT transformation circuit (decompression processing circuit)
105 Color space conversion circuit
106 color number reduction circuit
107 Compressed image data memory
108 Image data memory after inverse quantization
109 Final image data memory
110 scan component detection circuit
111 Scan component detection result memory
112 Sign bit memory
113 Superposition circuit
114 Image Data Memory
115 selector
116 Header Analysis Circuit (Screen Size Detection Circuit)
117 Storage capacity allocation circuit (bit number calculation circuit)
201 DSP (first processor)
202 CPU (second processor)

Claims (8)

An image processing apparatus that expands compressed image data that is encoded by frequency division type progressive encoding and divided into a plurality of bits for each element unit and sequentially transferred for each divided bit,
A scan component detection circuit that detects a first scan component for each element unit of the compressed image data,
A scan component detection result memory that stores that a first scan component is detected for each element unit by the scan component detection circuit;
A code bit memory that stores a code bit for each element unit of the compressed image data based on a detection result of the scan component detection circuit;
An inverse quantization circuit that inversely quantizes the compressed image data for each element based on the output of the scan component detection result memory and the sign bit memory;
A decompression processing circuit for decompressing the compressed image data at the stage corresponding to each divided bit obtained by the inverse quantization circuit,
A superposition circuit;
With an image data memory,
The superimposing circuit superimposes the data stored in the image data memory and the current stage image data expanded by the expansion processing circuit,
The image processing apparatus according to claim 1, wherein the image data memory stores the image data superimposed by the superimposing circuit. The image processing apparatus according to claim 1,
Comprising first and second processors,
The first processor includes the scan component detection circuit, the scan component detection result memory, the sign bit memory, the inverse quantization circuit, and the decompression processing circuit,
The image processor according to claim 2, wherein the second processor includes the superimposing circuit and the image data memory. The image processing apparatus according to claim 1,
A color space conversion circuit that performs color space conversion on the compressed image data expanded by the expansion processing circuit to obtain color information data,
A color number reduction circuit that reduces the number of colors by lowering the gradation of the color information data obtained by the color space conversion circuit,
The image processing apparatus according to claim 1, wherein the superposition circuit and the image data memory are arranged between the color space conversion circuit and the color number reduction circuit. The image processing apparatus according to claim 3, wherein
The image processing apparatus is provided in a mobile terminal including a mobile phone and a mobile information terminal. An image processing apparatus that expands compressed image data that is encoded by frequency division type progressive encoding and divided into a plurality of bits for each element unit and sequentially transferred for each divided bit,
A screen size detection circuit that analyzes header information of the compressed image data and detects a screen size of the compressed image data;
An image data memory having a predetermined storage capacity;
A bit number calculation circuit that calculates the number of bits allocated to each element of the compressed image data based on the screen size detected by the screen size detection circuit and the storage capacity of the image data memory;
A scan component detection circuit that detects a first scan component for each element unit of the compressed image data,
A scan component detection result memory that stores that a first scan component is detected for each element unit by the scan component detection circuit;
Based on the outputs of the scan component detection result memory and the image data memory, the compressed image data is dequantized for each element unit, and the bit number calculation circuit converts the dequantized compressed image data to each element unit. An inverse quantization circuit for storing compressed image data within the allocated number of bits in the image data memory;
A decompression circuit for decompressing the compressed image data obtained by the inverse quantization circuit. The image processing apparatus according to claim 5, wherein
Comprising first and second processors,
The first processor includes the screen size detection circuit, the image data memory, the bit number calculation circuit, the scan component detection circuit, the scan component detection result memory, the inverse quantization circuit, and the decompression processing circuit. An image processing apparatus characterized by the above-mentioned. An image processing method for decompressing compressed image data encoded by frequency division progressive encoding and divided into a plurality of bits for each element unit and sequentially transferred for each divided bit,
Detecting the first scan component for each element unit of the compressed image data,
Based on the detection result of the scan component, storing that the first scan component was detected for each element unit, and storing a sign bit for each element unit,
Subsequently, based on the stored detection result of the first scan component for each element unit and the code bit for each element unit, the compressed image data is dequantized for each element unit,
Decompress the compressed image data at this stage obtained by the inverse quantization,
Thereafter, superimposing the decompressed image data of the current stage with the image data of the previous stage is repeated. An image processing method for decompressing compressed image data encoded by frequency division progressive encoding and divided into a plurality of bits for each element unit and sequentially transferred for each divided bit,
Analyzing the header information of the compressed image data to detect the screen size of the compressed image data,
Based on this screen size and the storage capacity of the provided image data memory, calculate the number of bits allocated to each element unit of the compressed image data,
Subsequently, the first scan component is detected for each element unit of the compressed image data,
Based on the detection result of the scan component, storing that the first scan component was detected for each element unit,
Thereafter, based on the stored scan component detection result and the compressed image data stored in the image data memory, the compressed image data is inversely quantized for each element unit,
Of the dequantized compressed image data, the compressed image data within the number of bits allocated to each element unit is stored in the image data memory,
An image processing method characterized by repeating expanding the dequantized compressed image data.

Images