JP2004363640A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit operated under the reception of a plurality of power supply voltages wherein no through-current is made to flow to a next stage circuit when no power supply voltage is applied to an input buffer. <P>SOLUTION: The semiconductor integrated circuit is provided with: the input buffer 10 for outputting a signal on the basis of a signal inputted to an input terminal when receiving a first power supply voltage; a detection circuit 30 for detecting whether or not the first power supply voltage is applied to the input buffer; and the next stage circuit 40 that is operated upon reception of a second power supply voltage, outputs a signal on the basis of a signal outputted from the input buffer when the detection circuit detects that the first power supply voltage is supplied to the input buffer, and fixes its output level when the detection circuit detects that no first power supply voltage is supplied to the input buffer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to semiconductor integrated circuits such as ICs and LSIs, and more particularly to a semiconductor integrated circuit that operates by being supplied with a plurality of power supply voltages.
[0002]
[Prior art]
In recent years, in order to realize high-speed operation and low power consumption of various electronic devices, high integration and low voltage of semiconductor integrated circuits such as ICs and LSIs used in these electronic devices have been advanced. However, it is extremely difficult to uniformly reduce the operating voltages of all the semiconductor integrated circuits in consideration of the characteristics unique to the device. Therefore, a plurality of semiconductor integrated circuits operating at different power supply voltages may be connected to each other.
[0003]
In order to cope with such a case, a semiconductor integrated circuit having an input circuit including an input buffer operated by supplying a high power supply voltage and a next-stage circuit operated by supplying a low power supply voltage has been developed. FIG. 6 shows an example of an input circuit in a conventional semiconductor integrated circuit. In this example, an inverter is used as the input buffer and the next stage circuit.
[0004]
The input circuit shown in FIG. 6 includes an input buffer 10 to which a high power supply voltage HV _DD (for example, 3.3 V) is supplied and a next-stage circuit 20 to which a low power supply voltage LV _DD (for example, 1.8 V) is supplied. Contains. When an input signal is supplied from an external circuit to the input buffer 10 via an external input terminal (pad) PD, the input buffer 10 performs current amplification based on the input signal and supplies an output signal to the next-stage circuit 20. I do.
[0005]
In such a semiconductor integrated circuit, when the access to the external circuit is not performed, the supply of the power supply voltage HV _DD may be stopped while the power supply voltage LV _DD is supplied for reasons such as a reduction in power consumption. In such a case, since the output of the input buffer 10 is in a high impedance state, the input potential of the next stage circuit 20 is in an indefinite state. By its potential, both P-channel MOS transistors and N-channel MOS transistor are serially connected together on to the next-stage circuit 20, there is a problem that the penetration current I ₀ will flow.
[0006]
Japanese Patent Application Laid-Open No. H11-163,087 discloses a control voltage detection circuit configured with an output power supply system and stabilizing the output of the semiconductor integrated circuit having a multiple power supply system in order to stabilize the output of the IC when the power supply voltage is turned off. There is disclosed a semiconductor integrated circuit adapted to input to an output fixing circuit connected to an output of the circuit. However, Patent Document 1 does not disclose stabilizing the operation of the input circuit.
[0007]
[Patent Document 1]
JP-A-6-19412 (page 1, FIG. 1)
[0008]
[Problems to be solved by the invention]
In view of the above, an object of the present invention is to provide a semiconductor integrated circuit that operates with a plurality of power supply voltages supplied thereto, and when a power supply voltage is not supplied to an input buffer, a through current flows to a next-stage circuit. It is not to be.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit that operates by being supplied with a plurality of power supply voltages, and is configured to input to an input terminal when a first power supply voltage is supplied. An input buffer that outputs a signal based on a signal to be supplied, a detection circuit that detects whether or not the first power supply voltage is supplied, and a next-stage circuit that operates with the second power supply voltage supplied. When the detection circuit detects that the first power supply voltage is supplied, outputs a signal based on the signal output from the input buffer, and detects that the first power supply voltage is not supplied. And a next-stage circuit for fixing the output level when is detected.
[0010]
Here, the detection circuit includes an impedance element having one end connected to the second power supply voltage, a transistor having a drain connected to the other end of the impedance element, and having the first power supply voltage supplied to the gate to perform a switching operation. May be included.
Further, the input buffer may include an inverter configured by a P-channel transistor and an N-channel transistor connected in series.
[0011]
Further, the next-stage circuit may include a NAND circuit that inverts and outputs a logical product of a control signal that is at a high level when the first power supply voltage is supplied and a signal output from the input buffer. . Alternatively, the next-stage circuit may include a NOR circuit that inverts and outputs a logical sum of a control signal that becomes low level when the first power supply voltage is supplied and a signal output from the input buffer. .
In the above, the first power supply voltage may be higher than the second power supply voltage.
[0012]
According to the present invention configured as described above, when the detection circuit detects that the first power supply voltage is not supplied, the output level of the next-stage circuit is fixed. When the power supply voltage of 1 is not supplied, a through current can be prevented from flowing to the next stage circuit.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the same elements are denoted by the same reference numerals and description thereof will be omitted.
FIG. 1 is a diagram illustrating a configuration of an input circuit included in a semiconductor integrated circuit according to a first embodiment of the present invention. The semiconductor integrated circuit includes a plurality of power supply voltages, a first power supply voltage HV _DD (3.3 V in the present embodiment) and a second power supply voltage LV _DD (1. 8 V).
[0014]
As shown in FIG. 1, an input circuit included in the semiconductor integrated circuit receives a signal based on a signal input from an external circuit to an external input terminal (pad) PD when a power supply voltage HV _DD is supplied. , An input buffer 10 that detects whether or not the power supply voltage HV _DD is supplied, and a next-stage circuit 40 that operates when the power supply voltage LV _DD is supplied.
[0015]
Power supply voltage detecting circuit 30, as shown in FIG. 2, a power supply voltage LV _DD to the resistance as an impedance element having one end connected R1, the drain is connected to the other end of the resistor R1, the power source voltage HV _DD is the gate is supplied with the N-channel MOS transistors QN21 to perform a switching operation, is connected to the drain of the transistor QN21, the power supply voltage _{LV DD} contains an inverter 31 which operates when supplied with.
[0016]
Here, when the power supply voltage HV _DD is supplied, the transistor QN21 is turned on, the inverted control signal CN output from the drain of the transistor QN21 becomes low level, and the control signal CN output from the inverter 31 becomes high. Level. On the other hand, when the power supply voltage HV _DD is not supplied, the transistor QN21 is turned off, the inverted control signal CN output from the drain of the transistor QN21 goes high, and the control signal CN output from the inverter 31 goes low. It becomes.
[0017]
As the input buffer 10, as shown in FIG. 3, an inverter including a P-channel MOS transistor QP31 and an N-channel MOS transistor QN31 connected in series is used. When the power supply voltage HV _DD is supplied, the inverter inverts the signal A input to the input terminal and outputs the inverted signal A as the output signal X.
[0018]
As the next-stage circuit 40, as shown in FIG. 4, a NAND circuit composed of P-channel MOS transistors QP41 and QP41 and N-channel MOS transistors QN41 and QN41 is used. The NAND circuit inverts the logical product of the signals B1 and B2 input to the two input terminals when the power supply voltage LV _DD is supplied, and outputs the inverted signal as an output signal Y.
[0019]
Referring to FIG. 1 again, a signal output from the input buffer 10 is supplied to one input terminal of the next stage circuit 40, and an output from the power supply voltage detection circuit 30 is supplied to the other input terminal of the next stage circuit 40. Control signal CN is supplied.
[0020]
When the supply of the power supply voltage HV _DD is detected and the control signal CN is at a high level, the next-stage circuit 40 inverts the signal input from the input buffer 10 and supplies the inverted signal to the internal circuit. On the other hand, when it is detected that the power supply voltage HV _DD is not supplied and the control signal CN is at a low level, the next-stage circuit 40 fixes the output to a high level.
[0021]
According to such an input circuit, even when the supply of the power supply voltage HV _DD is stopped while the power supply voltage LV _DD is being supplied, there is no possibility that the through current I ₀ flows in the next-stage circuit.
[0022]
Next, a second embodiment of the present invention will be described.
FIG. 5 is a diagram illustrating a configuration of an input circuit included in a semiconductor integrated circuit according to the second embodiment of the present invention. In the present embodiment, a NOR circuit is used as the next stage circuit in place of the NAND circuit in the first embodiment.
[0023]
As shown in FIG. 5, the input circuit includes an input buffer 10 which operates when the power supply voltage HV _DD is supplied, the power supply voltage detecting circuit 30 to the power supply voltage HV _DD detects whether it is supplied, supply voltage LV _DD has a next-stage circuit 50 which operates when supplied with.
[0024]
The next-stage circuit 50, when the power supply voltage LV _DD is supplied, NOR circuit which inverts and outputs a logical sum of the signals input to the two input terminals is used. A signal output from the input buffer 10 is supplied to one input terminal of the next stage circuit 50, and an inverted control signal CN output from the power supply voltage detection circuit 30 is supplied to the other input terminal of the next stage circuit 50. Is supplied.
[0025]
When it is detected that the power supply voltage HV _DD is supplied and the inversion control signal CN is at a low level, the next-stage circuit 50 inverts the signal input from the input buffer 10 and supplies the inverted signal to the internal circuit. . On the other hand, when it is detected that the power supply voltage HV _DD is not supplied and the inversion control signal CN is at a high level, the next-stage circuit 40 fixes the output to a low level.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an input circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a specific circuit example of a power supply voltage detection circuit.
FIG. 3 is a diagram showing a specific circuit example of an input buffer.
FIG. 4 is a diagram showing a specific circuit example of a next-stage circuit.
FIG. 5 is a diagram illustrating a configuration of an input circuit according to a second embodiment of the present invention.
FIG. 6 is a diagram showing an example of an input circuit in a conventional semiconductor integrated circuit.
[Explanation of symbols]
Reference Signs List 10 input buffer, 30 power supply voltage detection circuit, 31 inverter, 40, 50 next stage circuit, PD external input terminal (pad), R1 resistor, QP31 to QP42 P-channel MOS transistor, QN21 to QN42 N-channel MOS transistor

Claims (6)

A semiconductor integrated circuit that operates by being supplied with a plurality of power supply voltages,
An input buffer that outputs a signal based on a signal input to an input terminal when the first power supply voltage is supplied;
A detection circuit for detecting whether or not the first power supply voltage is supplied;
A second-stage circuit that operates by being supplied with a second power supply voltage, based on a signal output from the input buffer when the detection circuit detects that the first power supply voltage is being supplied; A next-stage circuit that outputs a signal and fixes an output level when the detection circuit detects that the first power supply voltage is not supplied;
A semiconductor integrated circuit comprising: The detection circuit,
An impedance element having one end connected to the second power supply voltage;
A transistor having a drain connected to the other end of the impedance element, a first power supply voltage being supplied to a gate, and performing a switching operation;
The semiconductor integrated circuit according to claim 1, comprising: The semiconductor integrated circuit according to claim 1, wherein the input buffer includes an inverter including a P-channel transistor and an N-channel transistor connected in series. 2. The next-stage circuit includes a NAND circuit that inverts and outputs a logical product of a control signal that goes high when a first power supply voltage is supplied and a signal output from the input buffer. The semiconductor integrated circuit according to any one of claims 1 to 3. The circuit of the next stage includes a NOR circuit that inverts and outputs a logical sum of a control signal that goes low when a first power supply voltage is supplied and a signal output from the input buffer. The semiconductor integrated circuit according to any one of claims 1 to 3. The semiconductor integrated circuit according to claim 1, wherein the first power supply voltage is higher than the second power supply voltage.

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