JP2004363548A - 集積回路ダイ製作方法 - Google Patents
集積回路ダイ製作方法 Download PDFInfo
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- JP2004363548A JP2004363548A JP2003402763A JP2003402763A JP2004363548A JP 2004363548 A JP2004363548 A JP 2004363548A JP 2003402763 A JP2003402763 A JP 2003402763A JP 2003402763 A JP2003402763 A JP 2003402763A JP 2004363548 A JP2004363548 A JP 2004363548A
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Abstract
【解決手段】従来必要であったワイヤボンドを排除し、回路(62)がまだウエファーフォーマット内にある間に集積回路パッケージを提供する方法である。その上に集積回路(62)を製作したウエファー基板がパターン化され、エッチングされて、基板を通る信号及び接地バイア(74、72)を形成する。裏側接地面(82)は接地バイア(72)と接触するように付着される。保護層(90)が基板の頂表面(76)上に形成され、保護層(98)は基板の底表面上に形成され、底部保護層(98)は集積回路(62)間で除去された基板材料の区域を満たす。バイア(106)が底部保護層(98)を通して形成され、ウエファー基板は集積回路(62)間でダイ処理される。
【選択図】 図6
Description
64 ウエファー基板
66 集積回路ダイ
72、74 バイア
78、80 パッド
82 接地面
90、98 保護層
106、108 バイア
112 パッケージ化ダイ
120 ウエファー構造体
122 バイア
130 パッケージ組立体
132、134 パッケージ化ダイ
Claims (10)
- ウエファーフォーマットにおいてパッケージ化された集積回路ダイを製作する方法において、
頂表面及び底表面を有するウエファー基板を提供する工程と;
それぞれ罫書きレーンにより互いに分離された複数の集積回路を上記ウエファー基板の上記頂表面上に製作する工程と;
上記集積回路に関して上記基板を通して信号バイアを形成する工程と;
集積回路に電気的に接触する頂側ボンドパッドを、上記信号バイアに接触させて上記基板の上記頂表面上に付着する工程と;
上記信号バイアに接触させて上記基板の上記底表面上に裏側ボンドパッドを付着し、上記頂側パッドと上記裏側パッドとの間に電気的接続を形成する工程と;
上記頂側パッド及び上記集積回路を覆うように頂側保護層を上記ウエファー基板上に付着する工程と;
上記罫書きレーン内の基板材料の部分を、上記集積回路間で上記基板の底部から除去する工程と;
上記罫書きレーン内で除去された上記基板の部分を満たしかつ上記頂側保護層と接触するように、底側保護層を当該ウエファー基板上に付着する工程と;
上記裏側ボンドパッドに接触するように上記裏側保護層を通して信号バイアを形成する工程と;
パッケージ化されたダイの外表面がこれへの電気的な接続を形成するための露出した信号バイアを含むように、上記罫書きレーンに沿って上記ウエファー基板を切断して、上記パッケージ化されたダイに分離する工程と;
を有することを特徴とする方法。 - 上記基板を通って延び、上記集積回路の裏面金属層と電気的に接触する複数の接地バイアを形成する工程を更に有することを特徴とする請求項1に記載の方法。
- 上記裏側パッドに隣接しかつ上記接地バイアと電気的に接触して上記基板の上記底表面上に接地面を付着する工程を更に有することを特徴とする請求項2に記載の方法。
- 上記接地面に電気的に接触するように上記裏側層を通して接地バイアを形成する工程を更に有することを特徴とする請求項3に記載の方法。
- 基板材料の部分を除去する上記工程が、上記罫書きレーンの外側の信号バイア間の基板材料の部分を除去する工程を含むことを特徴とする請求項1に記載の方法。
- 基板材料の部分を除去する上記工程が、上記集積回路の下方の上記ウエファー基板の基板材料の除去を阻止する工程を含むことを特徴とする請求項1に記載の方法。
- 上記ウエファーを切断する前に上記集積回路の性能試験を行う工程を更に有することを特徴とする請求項1に記載の方法。
- 上記頂側パッドと電気的に接触するバイアを、上記頂側保護層を通して形成する工程を更に有することを特徴とする請求項1に記載の方法。
- 1つのダイ内の上記裏側層を通る上記バイアが別のダイ内の上記頂側層を通る上記バイアと電気的に接触するように、複数の上記パッケージ化されたダイを重ねる工程を更に有することを特徴とする請求項8に記載の方法。
- 上記頂側層及び上記裏側保護層がプラスチック層を含むことを特徴とする請求項1に記載の方法。
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US10/454,081 US6768189B1 (en) | 2003-06-04 | 2003-06-04 | High power chip scale package |
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JP2004363548A true JP2004363548A (ja) | 2004-12-24 |
JP4357278B2 JP4357278B2 (ja) | 2009-11-04 |
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EP (1) | EP1484795A1 (ja) |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008103387A (ja) * | 2006-10-17 | 2008-05-01 | Murata Mfg Co Ltd | 半導体装置 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050194698A1 (en) * | 2004-03-03 | 2005-09-08 | St Assembly Test Service Ltd. | Integrated circuit package with keep-out zone overlapping undercut zone |
JP4728708B2 (ja) * | 2005-06-17 | 2011-07-20 | 日本電気株式会社 | 配線基板及びその製造方法 |
KR101481571B1 (ko) * | 2007-08-21 | 2015-01-14 | 삼성전자주식회사 | 반도체 패키지 장치 및 그의 제작방법 |
US8018065B2 (en) * | 2008-02-28 | 2011-09-13 | Atmel Corporation | Wafer-level integrated circuit package with top and bottom side electrical connections |
US10651102B2 (en) | 2015-12-18 | 2020-05-12 | Intel IP Corporation | Interposer with conductive routing exposed on sidewalls |
US9704830B1 (en) * | 2016-01-13 | 2017-07-11 | International Business Machines Corporation | Semiconductor structure and method of making |
US10128169B1 (en) * | 2017-05-12 | 2018-11-13 | Stmicroelectronics, Inc. | Package with backside protective layer during molding to prevent mold flashing failure |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5436412A (en) * | 1992-10-30 | 1995-07-25 | International Business Machines Corporation | Interconnect structure having improved metallization |
US5741729A (en) * | 1994-07-11 | 1998-04-21 | Sun Microsystems, Inc. | Ball grid array package for an integrated circuit |
US5579207A (en) * | 1994-10-20 | 1996-11-26 | Hughes Electronics | Three-dimensional integrated circuit stacking |
US6521845B1 (en) * | 1997-06-12 | 2003-02-18 | Intel Corporation | Thermal spreading enhancements for motherboards using PBGAs |
US5945734A (en) * | 1997-09-19 | 1999-08-31 | Samsung Electronics Co., Ltd. | Wire-bond free input/output interface for GaAs ICs with means of determining known good die |
US6624505B2 (en) * | 1998-02-06 | 2003-09-23 | Shellcase, Ltd. | Packaged integrated circuits and methods of producing thereof |
US6137164A (en) * | 1998-03-16 | 2000-10-24 | Texas Instruments Incorporated | Thin stacked integrated circuit device |
AU5330899A (en) * | 1998-07-31 | 2000-02-21 | American Safety Razor Company | Utility knife with quick action quarter-turn connector |
US5987732A (en) | 1998-08-20 | 1999-11-23 | Trw Inc. | Method of making compact integrated microwave assembly system |
US6097265A (en) | 1998-11-24 | 2000-08-01 | Trw Inc. | Millimeter wave polymeric waveguide-to-coax transition |
US6194669B1 (en) | 1999-02-05 | 2001-02-27 | Trw Inc. | Solder ball grid array for connecting multiple millimeter wave assemblies |
US6316287B1 (en) * | 1999-09-13 | 2001-11-13 | Vishay Intertechnology, Inc. | Chip scale surface mount packages for semiconductor device and process of fabricating the same |
US6322903B1 (en) * | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
JP2001185519A (ja) * | 1999-12-24 | 2001-07-06 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6459039B1 (en) * | 2000-06-19 | 2002-10-01 | International Business Machines Corporation | Method and apparatus to manufacture an electronic package with direct wiring pattern |
TW496111B (en) * | 2000-08-24 | 2002-07-21 | Ind Tech Res Inst | Method of forming contact hole on multi-level circuit board |
WO2002039994A2 (en) * | 2000-11-20 | 2002-05-23 | University Of Kansas Medical Center | Methods for the treatment and prevention of urinary stone disease |
-
2003
- 2003-06-04 US US10/454,081 patent/US6768189B1/en not_active Expired - Lifetime
- 2003-11-20 EP EP03026821A patent/EP1484795A1/en not_active Withdrawn
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2004
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Cited By (1)
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JP2008103387A (ja) * | 2006-10-17 | 2008-05-01 | Murata Mfg Co Ltd | 半導体装置 |
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EP1484795A1 (en) | 2004-12-08 |
JP4357278B2 (ja) | 2009-11-04 |
US20040248342A1 (en) | 2004-12-09 |
US7135779B2 (en) | 2006-11-14 |
US6768189B1 (en) | 2004-07-27 |
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