JP2004362462A - Image detection processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image detection processor capable of extracting a characteristic amount of an input image from input image data at a high speed, and applying it to pattern recognition or the other image processing. <P>SOLUTION: In this image detection processor, a plurality of image detection processing elements each comprising a photodetector for performing photoelectric conversion, a converter for converting a signal from the photodetector into a digital signal, and an adder for allowing input of the digital signal are arranged on a plane. The image detection processor has: a characteristic amount extraction circuit for selectively taking AND of the digital signal of the image detection processing element to the digital signal from another adjacent image detection processing element, and inputting a result to the adder; a cumulative adder configured by sequentially connecting the adders of the plurality of image detection processing elements; a control circuit for selectively inputting the digital signals of the plurality of image detection processing elements to the cumulative adder; and an output part supplied with characteristic amount data outputted from the cumulative adder on the basis of the image data detected by the photodetectors. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital image detection processing device, and more particularly, to a digital image detection processing device capable of extracting a feature amount of an image from input image data at high speed.
[0002]
[Prior art]
Patent Literature 1 discloses an image detection processing device including a plurality of image detection processing elements arranged on a plane. When an image of a moving target object is input to the image detection processing device, a binary image of the moving target object is extracted from the background image, and the image area of the target object and its center of gravity can be calculated at high speed. However, Patent Document 1 does not disclose extracting a feature amount in input image data from input image data at high speed. However, in pattern recognition and other image processing, it is necessary to rapidly extract a feature amount of image data.
[0003]
[Patent Document 1]
JP 2001-195564 A
[Problems to be solved by the invention]
Accordingly, it is an object of the present invention to provide an image detection processing device that can extract a feature amount of input image data from input image data at high speed and apply it to pattern recognition and other image processing.
[0005]
[Means for Solving the Problems]
According to the first aspect of the present invention, an image includes a photodetector that performs photoelectric conversion, a converter that converts a signal from the photodetector into a digital signal, and an adder that can input the digital signal. An image detection processing device in which a plurality of detection processing elements are arranged on a plane, wherein the digital signal of the image detection processing element is selectively combined with the digital signal from another adjacent image detection processing element. A feature value extraction circuit for calculating a logical product and inputting a result of the logical product calculation to the adder; a cumulative adder sequentially connecting the adders of the plurality of image detection processing elements; A control circuit for selectively inputting the digital signal of the processing element to the accumulator.
[0006]
According to the image detection processing device of the first aspect, the feature extraction circuit selectively calculates the logical product of the digital signals from the adjacent image detection processing elements. That is, the feature extraction circuit outputs the output of its own image detection processing element to the adder as it is, or outputs the output of its own image detection processing element and the position of the right, immediately below, and lower right of its own image detection processing element. And the output of the image detection processing element is selectively ANDed, and the result of the AND operation is output to the adder. As a result, it is possible to extract the pattern features P0 to P9 of ten types of objects based on the ten types of pixel position patterns shown in FIG. 4 and output the number of each of the pattern features P0 to P9 at high speed. Therefore, it can be used for pattern recognition and other image processing.
[0007]
According to the second aspect of the present invention, based on the plurality of feature data output from the accumulator based on the image data detected by the photodetector supplied from the output unit, the image is obtained. An image detection device according to claim 1, wherein an Euler number of data is obtained.
[0008]
According to the image detection processing device of the second aspect, the number of objects in the input image data can be recognized at high speed by the Euler number, and can be used for pattern recognition and other image processing.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a schematic plan view for explaining one embodiment of an image detection processing device according to the present invention.
[0010]
The image detection processing device of the present embodiment is used for, for example, a visual sensor of a robot or a pattern recognition device of a control device, and extracts and calculates a feature amount of image data from input image data at high speed. is there.
[0011]
In FIG. 1, reference numerals 1-1 to 1-64 denote image detection processing elements, which are arranged in a plane as a 8.times.8 lattice array (array) structure, and which are targeted by an appropriate optical system (not shown). An image including the object is imaged to generate an input image consisting of 8 × 8 pixels. Note that the number of image detection processing elements can be appropriately selected depending on the application. As will be described later with reference to FIG. 2, each image detection processing element converts a photodetector and an analog electric signal from the photodetector based on an arbitrary threshold (set by an external signal VREF). A converter for digitally converting a binary signal of “0” and “1” is provided.
[0012]
Each image detection processing element outputs the above-mentioned binarized signal as a target image signal to four image detection processing elements adjacent vertically and horizontally. For example, the image detection processing element 1-11 outputs the binary signal as a target image signal to the image detection processing elements 1-3, 1-10, 1-12, and 1-19. The image detection processing element generates a window image signal for extracting a target (target object) from the background based on the target image signals from the four image detection processing elements and its own target image signal.
[0013]
Each image detection processing element includes a feature amount extraction circuit described later with reference to FIG. Each image detection processing element includes a first adder, which will be described later with reference to FIG. 5, and receives an output from the feature amount extraction circuit. The first adder of each image detection processing element is connected to the first adder of the image detection processing element on the right side thereof. For example, the output of the first adder of the image detection processing element 1-11 is image detection processing. Input to the first adder of processing element 1-12. As described above, the first adders of the image detection processing elements for each row are sequentially connected to form a first accumulator.
[0014]
To each of the image detection processing elements, CLOCK1, CLOCK2, LOAD, and SEL signals are input as common signals. The clock signal CLOCK1 and the signal LOAD are for initial image setting. For example, the clock signal CLOCK1 is a clock signal having a frequency of about 20 MHz to 100 MHz. The clock signal CLOCK2 and the signal SEL are signals for image calculation. For example, the clock signal CLOCK2 is a clock signal having a frequency of about 1 MHz to 10 MHz.
[0015]
Reference numerals 2-1 to 2-8 denote serial adders as second adders, which are arranged for each row of the image detection processing element and receive an output from the corresponding image detection processing element at one input. The output of each serial adder is sequentially connected to the other input of the adjacent serial adder on the lower side to form a second accumulator. In this embodiment, the serial type adder 2-1 corresponds to the image detection processing elements 1-1 to 1-8, and the output of the image detection processing element 1-8 is one of the serial type adders 2-1. Connected to the input of The output of the serial adder 2-1 is connected to the other input of the serial adder 2-2. The output of the serial adder 2-8 is the entire output signal, and constitutes an output unit to which processing data based on the image data detected by the photodetector is supplied. Details of the configuration of each serial adder will be described later in detail with reference to FIG.
[0016]
A row decoder circuit 3 controls output signals Y0 to Y7 by four row selection signals (not shown) in the present embodiment. Reference numeral 4 denotes a column decoder circuit. In this embodiment, although not shown, four column selection signals are used to control output signals X0 to X7, and the selection signal is set in the same manner as the row decoder 3 circuit. is there. The row decoder circuit 3 and the column decoder circuit 4 constitute a control circuit for selectively inputting the target image signal of the image detection processing element to the first accumulator. In the present embodiment, selection of an image detection processing element is performed by downloading a selection pattern from an external host (not shown) to the row decoder circuit 3 and the column decoder 4 circuit, but is not limited to this. For example, the ROM may be integrated on a single chip together with the image detection processing element, and the ROM may store a selection pattern corresponding to a target image operation and use the selected pattern for selection of the image detection processing element, or may respond to an external control signal. Then, a decoder for generating the selection pattern may be provided.
[0017]
Next, a part of the configuration of each of the image detection processing elements 1-1 to 1-64 according to the present embodiment will be described in detail with reference to FIG. Reference numeral 5 denotes a photoelectric conversion unit as a photodetector, which is composed of a photodiode and outputs an analog electric signal according to the intensity of incident light. Reference numeral 6 denotes a voltage holding unit that holds a voltage of an analog electric signal output from the photodetector 5. Numeral 7 denotes a conversion circuit which converts an analog electric signal into a binary signal and comprises a comparator, which receives an analog electric signal corresponding to the incident light from the photoelectric conversion unit 5 via a voltage holding unit 6 and outputs a threshold value. The value is converted into a value of either “0” or “1” according to whether it is smaller or larger, and binarized. In this embodiment, the threshold value input unit 8 sets an arbitrary threshold value in the binarization conversion circuit 7 under the control of the external signal VREF. In the present embodiment, an arbitrary threshold value can be set from the outside, and the binarization conversion circuit 7 compares the analog electric signal with, for example, the threshold value V1 or V0, and sets “1” when the analog electric signal is brighter than each threshold value. And outputs a signal of “0” when darker than the threshold value.
[0018]
The binarized data converted by the binarization conversion circuit 7 is supplied to the selector 9. The binarized data is output from the selector 9 by the control signal BW when the control signal BW is brighter than the threshold value and outputs a signal of "1", and when the data is darker than the threshold value, a signal of "0" is output. Is output to the AND circuit 10 as an output B.
[0019]
The logical product (AND) circuit 10 outputs “1” only when the binarized signal B from the selector 9 and the signal I from the 5-input logical sum (OR) circuit 12 described later are both “1”. It outputs a signal, but otherwise outputs "0". Reference numeral 13 denotes a multiplexer. In this embodiment, when the signal LOAD in FIG. 1 is “H” (or “1”, hereinafter the same), a signal from the AND circuit 10 is output and “L” is output. In the case of (or “0”, hereinafter the same), a signal is output from another AND circuit 11 described later. Reference numeral 14 denotes a flip-flop circuit which captures and outputs the signal of the multiplexer 13 by the clock signal CLOCK1 in FIG.
[0020]
The output of the flip-flop circuit 14 is output to the 5-input OR circuit 12 in its own image detection processing element and also to the 5-input OR circuit 12 in the four horizontally and vertically adjacent image detection processing elements. The five-input OR circuit 12 outputs a window image signal. This window image signal is for capturing an image of a moving target object and extracting it from a background image. In the present embodiment, the image of the moving target object can be extracted without extracting it from the background image, or the image of the moving target object can be extracted from the background image. If the moving target object is not extracted from the background, the signal LOAD is set to “L” for all of the image detection processing elements 1-1 to 1-64, and the flip-flop circuit 14 receives the signal LOAD via the multiplexer 13. What is necessary is just to take in the value of “H” (or “1”) from the AND circuit 11. Then, the output T of the flip-flop circuit 14 and the output I of the 5-input OR circuit 12 all become "H" (or "1"). Then, the AND circuit 10 outputs the output B itself from the selector 9. On the other hand, when extracting and processing the image of the moving target object from the background, the row decoder circuit 3 and the column decoder circuit 4 apply the signal LOAD only to a specific image detection processing element corresponding to the moving target object image. The level may be set to “L”, and the value of “H” (or “1”) may be taken into the flip-flop circuit 14 from the AND circuit 11 via the multiplexer 13. Then, the output T of the flip-flop circuit 14 and the output I of the 5-input OR circuit 12 of the specific image detection processing element corresponding to the image of the target object become “H” (or “1”), and a window image is generated. You.
[0021]
Next, the feature detection circuit 15 included in each image detection processing element connected to the output of the flip-flop circuit 14 of FIG. 2 will be described with reference to FIG. In the feature amount detection circuit 15, the output G (x, y) of the flip-flop circuit 14 of its own image detection processing element and the output G (x + 1, y) of the flip-flop circuit 14 of the image detection processing element on the right side. And the output G (x, y + 1) from the flip-flop circuit 14 of the image detection processing element immediately below and the output G (x + 1, y + 1) from the flip-flop circuit 14 of the lower right image detection processing element, respectively. The signals are selectively input to the AND circuit 15a through 15b to 15e, and the AND operation is selectively performed. The AND operation result output from the AND circuit 15a is input to the adder 66 of each image detection processing element shown in FIG. The selector circuits 15b to 15e have outputs G (x, y), G (x + 1, y), and G (x, y + 1) of the flip-flop circuit 14 of the image detection processing element from the right, right below, or right below. , Or G (x + 1, y + 1) and “1” of the binary signal are input. When each of the selector circuits 15b to 15e is selected by the control signals SEL0, SEL1, SEL2, and SEL3, the output G (x, y) of the flip-flop circuit 14 of the image detection processing element from itself, right next, right below, or right lower. ), G (x + 1, y), G (x, y + 1), or G (x + 1, y + 1) and the binary signal "1", and inputs the result to the AND circuit 15a. When not selected by the control signals SEL0, SEL1, SEL2, and SEL3, the selector circuits 15b to 15e output the outputs G (x, y), G (x + 1, y), G (x, y + 1), G (x, y + 1) of the flip-flop circuit 14, respectively. Alternatively, the logical product of G (x + 1, y + 1) and “0” obtained by inverting the binary signal “1” is obtained, and the result is input to the logical product circuit 15a.
[0022]
By controlling the control signals SEL0 to SEL3 to the selector circuits 15b to 15e, the feature amount detection circuit 15 has ten types of pixel patterns P0 having their own image detection processing elements arranged in the upper left corner as shown in FIG. Through P9. For example, the pixel pattern P0 selects the selector 15b by SEL0, calculates the logical product of the output of G (x, y) and the binary signal "1", and inputs the result to the logical product circuit 15a. And the other selectors 15c to 15e select G (x + 1, y), G (x, y + 1) or G (x + 1, y + 1) without selecting SEL1 to SEL3, and invert “1” of the binary signal. The logical product with 0 "is taken and the result is input to the logical product circuit 15a. Then, a binary signal "1" is output from the AND circuit 15a only when the pixel pattern matches the pixel pattern of P0 in FIG.
[0023]
Next, for example, for the pixel pattern P4, the selectors 15c and 15d are selected by SEL1 and SEL2, and the logical product of the output of G (x + 1, y) and G (x, y + 1) and the binary signal "1" is obtained. The result is input to the AND circuit 15a, and the other selectors 15b and 15e select G (x, y) or G (x + 1, y + 1) without selecting SEL0 and SEL3. The logical product of "1" and the inverted "0" is obtained, and the result is input to the AND circuit 15a. Then, the binary value signal "1" is output from the AND circuit 15a only when the pixel pattern matches the pixel pattern of P4 in FIG.
[0024]
Next, for example, in the pixel pattern P9, G (x, y), G (x + 1, y), G (x, y + 1), G (x + 1, y + 1) are selected by selecting all the selectors 15b to 15e by SEL0 to SEL3. And the binary signal "1" is calculated, and the result is input to the AND circuit 15a. Then, the binary circuit signal "1" is output from the AND circuit 15a only when the pixel pattern matches the pixel pattern P9 in FIG. In this way, it is understood that the feature detection circuit 15 outputs the binary signal "1" when there is a pattern match for all the pixel patterns P0 to P9 of the 2 × 2 pixels shown in FIG. it can. In this way, the feature amount detection circuit 15 controls the control signals SEL0 to SEL3 of the selector circuits 15b to 15e to detect the ten types of pixel patterns P0 to P9. And outputs the coded signal “1”.
[0025]
Using the pixel patterns P0 to P9, the number of isolated figures in the screen based on the Euler number can be calculated. Referring to FIG. 5, (a) of FIG. 5 corresponds to the pixel pattern P0, and each pixel is a vertex. (B) corresponds to the pixel patterns P1, P2, P3, and P4, respectively, and sets a pair of two adjacent pixels as a side. There are four types of minimum length sides (b). (C) corresponds to the pixel patterns P5, P6, P7, and P8, respectively, and sets a set of three pixels adjacent to each other as a plane (or a triangle). The four areas having the minimum area are shown in FIG. (D) corresponds to the pixel pattern P9 and is a solid (or tetrahedron).
[0026]
Any complicated figure, for example, (e), can be represented by a combination of figures of nine pixel patterns P0 to P8 of (a), (b), and (c). That is, when the image is finely divided to the end, a figure group of nine pixel patterns P0 to P8 is obtained.
[0027]
By Euler's theorem, the Euler number of connected planar figures is
[Number of vertices]-[Number of sides] + [Number of faces] = 1 (Equation 1)
It is. In the figure of (e), the number of vertices in (a) is 12, the number of sides in (b) is 18, and the number of faces in (c) is 7. Therefore,
12-18 + 7 = 1
It becomes. If the figures are not connected, the Euler number of each figure is 1, so if Equation 1 is applied to the entire screen, the number of separated figures can be calculated.
[0028]
In this manner, the feature amount detection circuit 15 detects the vertices P0, the sides P1 to P4, and the planes P5 to P8, calculates the numbers thereof, and applies them to the equation 1, whereby the number of separations in the screen is calculated. It is easily determined whether or not there is a figure that has been set.
[0029]
However, at this time, it is desired to calculate the pixel pattern of P9 of the tetrahedron (three-dimensional) in which the four vertices are adjacent to each other, with four vertices, five sides, and two faces, as shown in FIG. However, in actuality, as shown in FIG. 5E, the pixel pattern of the tetrahedron (solid) P9 in which the four vertices are adjacent to each other is counted as the vertex 4, the side 6, and the surface 4 by the feature amount detection circuit 15. . This means that the vertex 4, the side 6, and the surface 4 are tetrahedrons in a three-dimensional space. Then, this may be regarded as a tetrahedron projected on a two-dimensional plane. The Euler number of the polyhedron is two. If we extend Euler's theorem to a three-dimensional space,
[Number of vertices]-[Number of sides] + [Number of faces]-[Number of solids] = 1 (Equation 2)
Holds.
[0030]
Therefore, a set of four pixels adjacent to each other is defined as a three-dimensional (tetrahedron), and the pixel pattern P9 is added to the nine types of pixel patterns P0 to P8 so far, and the feature amount detection circuit 15 performs the ten types of pixel patterns. By detecting and calculating the respective numbers, the number of figures isolated on the screen can be obtained by using Euler's theorem of Equation 2.
[0031]
That is,
Euler number of plane = number of vertices (P0) −number of sides (P1 + P2 + P3 + P4) + number of planes (P5 + P6 + P7 + P8) = 1
Euler number of solid = number of vertices (P0)-number of sides (P1 + P2 + P3 + P4) + number of faces (P5 + P6 + P7 + P8) = 2
It is. Therefore, the number of objects can be detected by Expression 2 by treating a 2 × 2 local area as a three-dimensional object and treating the pattern in the area as a vertex, a side, a triangle, or a tetrahedron. That is,
[Number of objects] = [number of one point (vertex)] − [number of two consecutive points (sides)] + [number of three adjacent points (plane: triangle)] − [four adjacent points ( Number of solids: tetrahedron)]. That is,
The number of objects (considered as a solid for convenience) = total number of P0− (total number of P1 + total number of P2 + total number of P4 + total number of P4) + (total number of P5 + total number of P6 + total number of P7 + total number of P8) −total number of P9.
[0032]
In addition, what can be performed using the pixel patterns P0 to P9 is, for example, calculation of the vertical, horizontal, and oblique lengths of a convex object having no hole. That is,
Vertical length = total number of P0−total number of P1 Horizontal length = total number of P0−total number of P2 Length in lower right direction = (total number of P0−total number of P4) / √2 (part of width 1 dot) If not)
Length in the upper right direction = (total number of P0−total number of P3) / √2 (when there is no portion having a width of 1 dot)
As described above, it is possible to recognize patterns using the feature amounts of the ten types of pixel patterns P0 to P9.
[0033]
Next, the adder 66 included in each of the image detection processing elements 1-1 to 1-64 will be described with reference to FIG. The adder 66 is a logical product circuit, and outputs a signal of "1" when both the output of the characteristic quantity detecting circuit 15 and the output of the logical product circuit 11 of FIG. 3 are "1". . The AND circuit 11 outputs a signal of “1” when both the output of the row decoder 3 as the control circuit and the output of the column decoder 4 as the control circuit are “1”. For example, the image detection processing element 1-11 outputs a signal of "1" when the output Y1 of the row decoder 3 and the output X2 of the column decoder 4 are both "1".
[0034]
In this embodiment, a multiplexer 63 outputs a signal from the AND circuit 60 when the signal SEL in FIG. 1 is "H", and outputs a signal from a flip-flop circuit 64 described later when the signal SEL is "L". . The flip-flop circuit 64 captures and outputs the CARRY signal of the adder circuit 65 described later by the clock signal CLOCK2 in FIG. An addition circuit 65 composed of a half adder calculates an arithmetic sum of an output of the multiplexer 63 and a SUM signal of a half addition circuit of an adjacent image detection processing element, and outputs a SUM signal and a CARRY signal. For example, in the image detection processing element 1-11, if the output of the multiplexer 63 and the SUM signal of the addition circuit 65 in the image detection processing element 1-10 are both "L", both the SUM signal and the CARRY signal are "L". If one is “L” and the other is “H”, the SUM signal is “H” and the CARRY signal is “L”. If both are “H”, the SUM signal is “L” and the CARRY signal is “H”. ". A first adder 66 includes the AND circuit 60, the AND circuit 11, the multiplexer 63, the flip-flop 64, and the adding circuit 65. As described above, the first adders 66 of the image detection processing elements for each row are sequentially connected to form a first accumulator.
[0035]
Next, the configuration of the serial adders 2-1 to 2-8 will be described in detail with reference to FIG. FIG. 7 shows one of the serial adders, for example, 2-2. Reference numeral 16 denotes an addition circuit comprising a full adder, which performs an arithmetic addition operation of the SUM signal of the image detection processing element, a SUM signal of a flip-flop circuit 17 described later, and a SUM signal of a preceding-stage addition circuit 16, and outputs a SUM signal and a CARRY signal. Output. For example, in the case of the serial adder 2-2, the output of the image detection processing element 1-16, the output of the serial adder 2-1 and the output of the flip-flop circuit 17 are input, and the SUM signal is The signal is output to the serial adder, and the CARRY signal is output to the flip-flop circuit 17. When the state of the three inputs is all “L”, both the SUM signal and the CARRY signal are “L”. When only one of them is “H”, the SUM signal is “H” and the CARRY signal is “H”. When both are "H", the SUM signal is "L" and the CARRY signal is "H", and when all are "H", both the SUM signal and the CARRY signal are "H". Reference numeral 17 denotes a flip-flop circuit which captures and outputs the CARRY signal of the adder circuit 16 using the above-described clock signal CLOCK2.
[0036]
Next, a general operation of the image detection processing device according to the present embodiment will be described. First, in order to initialize the internal circuit, the row decoder 3 and the column decoder 4 are all set to be unselected, and the signal SEL is set so that the multiplexer 63 outputs a pixel selection signal. In this state, when the clock signal CLOCK2 is input for one or more clocks, the flip-flop latch circuit 64 in each image detection processing element is cleared. Further, when the clock signal CLOCK2 is input for 6 clocks or more while maintaining this state, the latch circuits 17 in the respective serial adders are also cleared.
[0037]
Next, a window image signal is set. The window image signal is for separating an image of a moving target (target object) from the background. The pixel selection signal is set to be output from the multiplexer 13 by the signal LOAD, and the window image is initialized by setting the row decoder 3 and the column decoder 4. When the row decoder 3 and the column decoder 4 are set so that all outputs are selected, the initial value of the window image is the entire screen.
[0038]
Next, an image is captured. An image of the target object is formed on an image detection processing element arranged in a plane using an appropriate imaging optical system. The image forming optical system may be a lens optical system used in a digital still camera or the like. In each of the image detection processing elements, first, the photoelectric conversion unit 5 converts the brightness information of the target object into an analog signal corresponding to the light amount of the formed image. This analog signal is converted into a binary image signal having a value of "L" (or "0", hereinafter the same) or "H" (or "1", the same hereinafter) by the binary conversion circuit 7 by the method described above. Is converted to
[0039]
The binarized image signal is converted into a target image signal by performing an AND operation with the above-described window image signal in the AND circuit 10. The target image signal is output to the flip-flop circuit 14 via the multiplexer 13, and is captured at the timing of the clock signal CLOCK1. The target image signal captured by the flip-flop circuit 14 is input to the 5-input OR circuit 12 to generate a window signal at the timing of the next clock signal CLOCK1, and is also input to the feature amount detection circuit 15. .
[0040]
The output of the flip-flop circuit 14 is output to the 5-input OR circuit 12 in its own image detection processing element and also to the 5-input OR circuit 12 in four adjacent image detection processing elements. The window image signal is output from the 5-input OR circuit 12.
[0041]
On the other hand, as described above, the output of the flip-flop circuit 14 input to the feature detection circuit 15 is used to detect the ten types of pixel patterns P0 to P9. The output is selectively ANDed with the output from the amplifier 14, and ten types of pixel patterns P0 to P9 are detected. When any of the ten pixel patterns is detected, the feature amount detection circuit 15 outputs a “1” (or “H”) binary signal to the first adder 66.
[0042]
Next, for each of the pixel patterns P0 to P1 detected by the feature amount detection circuit 15, an operation of calculating the total number by the image detection processing device is performed. This calculation operation is the same as the operation for calculating the pixel area (zero-order moment) of the target object (target) image, which is described in detail in Patent Document 1, and will not be described in detail.
[0043]
The total number of the respective pixel patterns P0 to P1 is supplied from the output unit (2-8) of the image detection processing device to a not-shown host computer or the like, where it is applied to Expression 2 to obtain the total number of separated graphics in the input image. Can be requested. Further, it can be used for other pattern recognition by a not-shown host computer or the like.
[0044]
【The invention's effect】
As described above, according to the first aspect of the present invention, a pattern feature of an object based on a pixel position pattern can be extracted, and the total number of each feature can be output at high speed. Therefore, it can be used for pattern recognition and other image processing.
[0045]
According to the second aspect of the present invention, the number of objects in the input image data can be quickly recognized by the Euler number, and can be used for pattern recognition and other image processing.
[Brief description of the drawings]
FIG. 1 is a schematic plan view illustrating the configuration of an image detection processing device according to one embodiment of the present invention.
FIG. 2 is a block diagram for explaining a part of image detection processing elements of the image detection processing device shown in FIG. 1;
FIG. 3 is a block diagram illustrating a feature amount detection circuit included in the image detection processing element shown in FIG. 1;
FIG. 4 is a diagram for explaining ten types of pixel patterns detected by the feature amount detection circuit shown in FIG. 3;
FIG. 5 is a view for explaining a method of calculating the number of figures in an image based on the ten types of pixel patterns shown in FIG. 4;
FIG. 6 is a block diagram for explaining a first adder included in the image detection processing element shown in FIG. 1;
FIG. 7 is a block diagram for explaining a serial adder included in the image detection processing device shown in FIG. 1;
[Explanation of symbols]
1-1 to 1-64 Image detection processing elements 2-1 to 2-8 Serial adder 3 Row decoder circuit (control circuit)
4 column decoder circuit (control circuit)
5 Photoelectric conversion unit (photodetector)
6 Voltage holding unit 7 Binary conversion circuit (converter)
Reference Signs List 8 threshold input device 9 selector 10 AND circuit 11 AND circuit 12 5-input OR circuit 13 multiplexer 14 flip-flop circuit 15 feature amount detection circuit 16 addition circuit (second adder, second accumulator)
17 Flip-flop circuit 65 Adder circuit 66 First adder (first accumulator)

Claims (2)

A plurality of image detection processing elements including a photodetector that performs photoelectric conversion, a converter that converts a signal from the photodetector into a digital signal, and an adder that can input the digital signal are arranged on a plane. An image detection processing device comprising:
A feature value extraction circuit that selectively ANDs the digital signal of the image detection processing element with the digital signal from the other adjacent image detection processing element and inputs the AND calculation result to the adder;
It further comprises a cumulative adder formed by sequentially connecting the adders of the plurality of image detection processing elements, and a control circuit for selectively inputting the digital signals of the plurality of image detection processing elements to the cumulative adder. An image detection processing device comprising: 2. The image detection device according to claim 1, wherein the Euler number of the image data is obtained based on a plurality of feature data output from the accumulator based on the image data detected by the photodetector.

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