JP2004362454A - Microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microprocessor provided with high processing capacity at low power consumption. <P>SOLUTION: Program counters (PCs) in the same number as that pipelines or more are prepared, and processing for successively fetching instructions of the address 0 of the PC 1 up to the address 0 of the PC 6 is performed. Then, the processing of fetching an instruction from the address 1 of the PC1 and so forth is performed. By the constitution and the processing, a pipeline stall is not generated in principle. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a microprocessor, and more particularly, to a technique that is effective when applied to a microprocessor that requires low power consumption.
[0002]
[Prior art]
According to the studies made by the present inventors, the following techniques can be considered for the microprocessor technique.
[0003]
At present, there are many microprocessors equipped with a pipeline function. These microprocessors usually have one program counter and execute pipeline processing. In addition, there is a type provided with another program counter and an arithmetic circuit associated therewith as a fill-in when a stall occurs.
[0004]
[Problems to be solved by the invention]
By the way, as a result of the present inventor's study on the above-described microprocessor technology, the following has become clear.
[0005]
At present, microprocessors are used in various devices such as personal computers and mobile phones. For example, a microprocessor of a mobile phone must perform processing of additional functions such as a browser function and recording and reproduction of moving images / still images, in addition to processing of an original telephone function.
[0006]
Therefore, microprocessors are required to have high processing power not only in personal computers and the like but also in mobile phones and the like. In particular, portable devices must also have low power consumption.
[0007]
However, in a microprocessor as in the prior art, if the pipeline is deepened to operate at a high clock, the performance is reduced due to a penalty at the time of branching. Also, if there is an instruction dependency such as using the result of the previous instruction in the next instruction, the execution of the next instruction is delayed, which also lowers the performance.
[0008]
Disturbance in pipeline processing as described above is referred to as pipeline stall or pipeline hazard. At present, in order to reduce this pipeline stall, processing such as branch prediction and speculative execution by a branch prediction circuit or the like, and processing of removing instruction dependencies by a circuit for changing the order of instructions are performed. However, in recent years, these circuit scales tend to be much larger, and increases in circuit area and power consumption cannot be ignored.
[0009]
Therefore, an object of the present invention is to provide a microprocessor with low power consumption.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
A microprocessor according to the present invention has at least as many program counters as the number of pipeline stages, and executes instructions indicated by the program counter by pipeline processing while sequentially switching the program counter every clock. . With this configuration, pipeline stall can be prevented in principle.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0014]
Embodiments of the present invention will be described in comparison with a conventional microprocessor which is a premise of the present invention, in order to make the features of the microprocessor of the embodiment of the present invention easy to understand.
[0015]
FIG. 1 is a schematic diagram showing an example of a pipeline processing method in a conventional microprocessor which is a premise of the present invention.
[0016]
A conventional microprocessor has one program counter (PC) and forms a pipeline in one process. In the example of FIG. 1, there are six pipelines, and five instructions existing at addresses 0 to 4 indicated by the PC are processed by the pipeline. Usually, these five instructions correspond to instructions in one process, so to speak, are included in one task.
[0017]
Each stage of the pipeline includes, for example, an IF (instruction fetch) stage, an ID (instruction decode) stage, an EX (instruction execution) stage, an MA (memory access) stage, and two mm (arithmetic processing) stages. Consists of
[0018]
FIG. 1 shows an ideal pipeline process. However, in actuality, pipeline stall occurs depending on the type of instruction, dependency, and the like. Although a specific example thereof will be described later with reference to FIG. 4 and the like, essentially, pipeline stall occurs because the processing of the next instruction is started before the processing of the previous instruction is completed.
[0019]
FIG. 2 is a schematic diagram illustrating an example of a pipeline processing method in the microprocessor according to the embodiment of the present invention.
[0020]
A microprocessor according to an embodiment of the present invention has a program counter of the same number or more as the number of stages of a pipeline, and sequentially switches the program counter every clock, while executing an instruction indicated by the program counter by pipeline processing. To do.
[0021]
That is, in FIG. 2, the number of pipeline stages and the number of PCs are the same, and as in FIG. 1, the pipeline has six pipelines and six PCs (PC 1 to 6), and differs for each PC. Assume that a process is assigned. In such a configuration, the processing procedure for each clock is, for example, as follows. In the following description, it is assumed that the value of the time t increases by +1 for each clock.
[0022]
At t = 1, the instruction at address 0 indicated by PC1 is fetched.
[0023]
At t = 2, the instruction at address 0 indicated by PC1 is decoded, and at the same time, the instruction at address 0 indicated by PC2 is fetched.
[0024]
At t = 3, execution of the instruction at address 0 indicated by PC1 and decoding of the instruction at address 0 indicated by PC2 are performed, and at the same time, the instruction at address 0 indicated by PC3 is fetched.
[0025]
Similarly, at t = 6, arithmetic processing of PC1 and PC2, memory access of PC3, instruction execution of PC4, instruction decoding of PC5, and instruction fetch of address 0 indicated by PC6 are performed.
[0026]
Then, at t = 7, the next instruction indicated by PC1, that is, the instruction at address 1 is fetched together with the processing for address 0 indicated by PC2 to PC6. Thereafter, at t = 8 to 12, the instruction fetch of the address 1 indicated by PC2 to PC6 is sequentially performed.
[0027]
The addresses 0 and 1 are not physical addresses but indicate logical addresses for each PC.
[0028]
Here, focusing on PC1, as shown in the lower part of FIG. 2, the processing of the instruction at address 1 is performed after the processing of the instruction at address 0 is completed. The same applies to other PCs, and the instructions in the same PC always execute the next instruction after the processing of the previous instruction is completed.
[0029]
That is, in the same PC, the processing of the next instruction is not started before the processing of the previous instruction is completed as in the related art, so that pipeline stall does not occur in principle. If the same PC is set as the same process and different processes are assigned to each PC, processing of a plurality of processes (multitask processing) can be performed without causing pipeline stall.
[0030]
As described above, when the pipeline stall does not occur in principle, the following effects (1) to (4) are further obtained.
[0031]
(1) Functions such as branch prediction become unnecessary, and the number of transistors and power consumption can be reduced.
[0032]
(2) The number of pipeline stages can be made very deep, and a high clock can be achieved.
[0033]
(3) A system in which each processing block operates in parallel, such as a moving picture expert group (MPEG), can particularly increase the use efficiency of a computing unit.
[0034]
That is, parallel processing is possible by assigning different processing blocks to each PC. Further, in image processing such as MPEG, generally, a branch instruction is frequently used in processing such as variable-length encoding / decoding, but a branch prediction error does not occur unlike the related art.
[0035]
(4) There is a case where a compiler or the like performs optimization processing of instructions related to pipeline processing, but such processing can be simplified.
[0036]
FIG. 3 is a schematic diagram showing an example of the configuration of the microprocessor according to the embodiment of the present invention.
[0037]
The microprocessor of FIG. 3 has, for example, six program counters (PC1 to 6) and six pipeline stages.
[0038]
The six pipeline stages include, for example, an instruction fetch (IF) stage, an instruction decode (ID) stage, an instruction execution (EX) stage, a memory access (MA) stage, and an arithmetic processing (mm) stage. , A register write back (WB) stage.
[0039]
A process having no dependency is assigned to each program counter, and an instruction code memory is assigned to each process. Then, the pipeline process is performed while switching each program counter in order for each clock.
[0040]
Here, the operation of the microprocessor shown in FIG. 3 will be described by comparing a conventional operation with a simple program example.
[0041]
First, FIG. 4 is a diagram showing an example of a conventional pipeline processing method for a simple program example in a microprocessor as a premise of the present invention. In FIG. 4, a program example constituted by instructions (1) to (8) is processed by a conventional pipeline. The contents of the instructions (1) to (8) will be briefly described as follows. Note that R0 to R3 are general-purpose registers.
[0042]
The data on the memory address indicated by R1 is transferred to R0 (instruction {circle around (1)}). One is added to the data of R0, and the result is stored in R0 (instruction {circle around (2)}). The data of R0 is written to the memory address indicated by R1 (instruction {circle around (3)}). The size of the data of R0 and the size of the data of R2 are compared (instruction {circle around (4)}). If the data in R0> the data in R2, the flow branches to instruction (8); otherwise, the flow proceeds to instruction (6) (instruction (5)). The data of R0 is multiplied by the data of R2, and the result is stored in the product-sum register MACL (instruction {circle around (6)}). The value of MACL is stored in R0 (instruction {circle around (7)}). The data of R0 is added to the data of R3, and the result is stored in R3 (instruction (8)).
[0043]
In such an instruction, the following pipeline stall occurs in the conventional pipeline processing.
[0044]
(1) In the instruction (2), a delay of one clock (stage) occurs because the result of the instruction (1) is used.
[0045]
(2) In the instruction (3), a delay of one clock (stage) occurs because the result of the instruction (2) is used.
[0046]
(3) In the instructions (6) and (7), the fetch is performed in the pipeline while the presence or absence of the branch by the instruction (5) is determined. If there is a branch, the instruction itself is discarded.
[0047]
In other words, in the pipeline processing, in the instructions (2) and (3), a delay occurs because the result of the previous instruction is used by the next instruction, and in the instructions (6) and (7), a branch is caused by the result of the previous instruction. This causes unnecessary processing to be performed. As a result, 6 instructions are executed in 11 stages.
[0048]
5 and 6 are diagrams showing an example of a method of processing a pipeline for a simple program example in the microprocessor according to the embodiment of the present invention. It is assumed that the same instructions as those in FIG. 4 are processed, and the processing of the instructions (1) to (4) is shown in FIG. 5, and the processing of the instructions (5) to (8) is shown in FIG.
[0049]
In FIG. 5, the instructions of PC2 and PC3 can be executed at the delay point of the instructions (2) and (3) in FIG. The instruction of the PC 4 can be executed at a position where the fetch of the instruction (4) is delayed due to the delay of the instruction (3). In other words, the stage originally waiting can be used as a stage of another process.
[0050]
In FIG. 6, there is no need to prefetch the unnecessary instructions (6) and (7) fetched in FIG. 4 but discarded by the branch.
[0051]
As described above, the microprocessor of FIG. 3 is configured to process an instruction of another PC until the processing of the instruction in one PC is completed. Therefore, there is no danger that a waiting time is required when the next instruction is processed in the certain PC, or that the instruction is discarded and becomes a useless instruction.
[0052]
As a result, for example, in FIG. 5, 13 instructions are executed in 16 stages, and the execution efficiency can be substantially increased to 1 instruction / 1 clock. That is, it is possible to realize a microprocessor that can have high processing capability and does not consume power by the branch prediction circuit and the like as described above.
[0053]
Also, by using these ideas, it is possible to construct an architecture using an arithmetic circuit in units of 1 bit, instead of the conventional arithmetic circuit in units of 32 bits. FIGS. 7 and 8 show an example of a configuration for realizing this architecture. Here, a 32-bit architecture is assumed.
[0054]
FIG. 7 is a circuit diagram showing an example of a configuration of a 1-bit adding circuit in the microprocessor according to the embodiment of the present invention.
[0055]
The adder circuit of FIG. 7 includes, for example, 32-bit shift registers 1 and 2 to which 32-bit inputs A and B are respectively input, a 1-bit adder 3 that adds each bit of the inputs A and B by 1 bit, and a 1-bit adder 3 It comprises a 32-bit shift register 4 for storing the output C of the adder 3 and the like. Although not shown in FIG. 7, 36 circuits are provided, and a different PC is assigned to each circuit. That is, 36 PCs (PC1 to 36) are provided.
[0056]
FIG. 8 is a circuit diagram showing an example of a configuration of a 1-bit unit comparison circuit in the microprocessor according to the embodiment of the present invention.
[0057]
The comparison circuit in FIG. 8 includes, for example, 32-bit shift registers 1 and 2 to which a 32-bit input A and an input B are respectively input, and a 1-bit comparator (subtractor) 5 for comparing each bit of the input A and the input B by 1 bit. Etc. Although not explicitly shown in FIG. 8, 36 circuits are provided, and a different PC is assigned to each circuit. That is, 36 PCs (PC1 to 36) are provided.
[0058]
In such circuits, the pipeline processing is performed while sequentially switching the PCs, as in the processing of FIG. Then, for example, after the instruction fetch of the address 0 of the PC1 is performed, the instruction fetch of the address 1 is performed 36 clocks later. Therefore, during this period, addition and comparison for 32 bits are performed in units of 1 bit / 1 clock by the addition circuit of FIG. 7 and the comparison circuit of FIG.
[0059]
The number of pipeline stages is a total of 35 stages of IF, ID, IE, and mm × 32. However, since the number of PCs (36) is larger than the number of pipeline stages, the pipeline installation is in principle required. Does not occur.
[0060]
As described above, a beneficial effect can be obtained by configuring the number of PCs to be equal to or more than the number of stages in the pipeline and equal to the number of data bits, and changing the arithmetic unit from the conventional 32-bit unit to the 1-bit unit. In other words, the operation that was conventionally performed simultaneously in 32 bits is distributed to a plurality of clocks in units of 1 bit, so that the delay time between gates in the operation unit per clock can be reduced. Becomes possible. Furthermore, as long as the delay time between gates in the arithmetic unit per clock is within an allowable range, the element drive voltage can be reduced, and power consumption can be reduced.
[0061]
In a general program, a branch instruction based on a comparison result or the like is often used. In this case, the result is often determined only by comparing the upper bits. In such a case, by using the comparison of 1 bit / 1 clock, the operation can be completed (the operation unit is stopped) when the result is found, and the current consumption can be reduced and the efficiency of the operation can be improved. it can.
[0062]
FIGS. 7 and 8 show an adder and a comparator as one mode of an arithmetic circuit such as an ALU (arithmetic and logical unit), and are not limited to the adder and the comparator.
[0063]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0064]
For example, in FIGS. 7 and 8, the number of PCs is equal to the number of data bits, but the number of PCs can be equal to or greater than the number of data bits as long as the number is equal to or greater than the number of stages in the pipeline.
[0065]
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0066]
(1) By providing the same number of PCs or more as the number of pipeline stages, pipeline stall does not occur in principle, and the execution efficiency of the pipeline can be substantially increased to one instruction / clock.
[0067]
(2) According to (1), functions such as branch prediction become unnecessary, and the number of transistors and power consumption can be reduced.
[0068]
(3) According to the above (1), the number of pipeline stages can be made very deep, and a high clock can be achieved.
[0069]
(4) By configuring the number of data bits and the number of PCs to be equal and changing the arithmetic unit in units of 1 bit, it is possible to reduce current consumption, increase the clock, and increase the efficiency of the operation.
[0070]
(5) By the above (1) to (4), a microprocessor with low power consumption and high processing capability can be realized.
[0071]
【The invention's effect】
By applying the present invention, a low-power microprocessor can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an example of a pipeline processing method in a conventional microprocessor which is a premise of the present invention.
FIG. 2 is a schematic diagram illustrating an example of a pipeline processing method in the microprocessor according to the embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating an example of a configuration of a microprocessor according to an embodiment of the present invention.
FIG. 4 is a diagram showing an example of a conventional pipeline processing method for a simple program example in a microprocessor as a premise of the present invention.
FIG. 5 is a diagram illustrating an example of a pipeline processing method for a simple program example in the microprocessor according to the embodiment of the present invention;
FIG. 6 is a diagram illustrating an example of a method of processing a pipeline for a simple program example following FIG. 5 in the microprocessor according to the embodiment of the present invention;
FIG. 7 is a circuit diagram illustrating an example of a configuration of an addition circuit in units of 1 bit in the microprocessor according to one embodiment of the present invention;
FIG. 8 is a circuit diagram illustrating an example of a configuration of a 1-bit unit comparison circuit in the microprocessor according to one embodiment of the present invention;
[Explanation of symbols]
1,2,4 32-bit shift register 3 1-bit adder 5 1-bit comparator

Claims (1)

It has more program counters than the number of pipeline stages,
A microprocessor which executes an instruction indicated by the program counter by pipeline processing while sequentially switching the program counter every clock.

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