JP2004355803A - Code conversion system, code conversion apparatus, code recording medium, code recording device, and code reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease low-frequency components of a signal recorded in a recording medium by controlling scramble data in such a manner that the divergence of DSV is sufficiently suppressed. <P>SOLUTION: A scrambler 12 scrambles main data from a memory 11 and outputs the scrambled main data to an 8/16 converter 13. The 8/16 converter 13 forms the main data for output by modulating the scrambled main data. A comparator 14 is inputted with the DSV determined by the 8/16 converter 13 and decides whether the amount of the change in the DSV exceeds the threshold or not. A controller 15 changes the scramble data until the DSV falls to the threshold or below and repeats the scramble and modulation of the main data. Unless the DSV exceeds the threshold, the controller delivers the main data from the 8/16 converter 13 to a recording and reproducing device. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a code conversion method and a code conversion apparatus for scrambling and modulating main data in order to record main data at high density, and a code recording medium for recording the scrambled and modulated main data together with scrambled data. The present invention relates to a recording apparatus and a reproducing apparatus for scrambling and modulating main data, recording the main data on a recording medium, and reproducing the main data recorded on the recording medium.

  As is well known, an optical disk has been widely used as a recording medium for recording various software such as video data, audio data, and data for a computer. This optical disk includes a laser disk (LD), a compact disk (CD), a CD-ROM, etc. as a read-only one, and a magneto-optical disk, a phase change disk, a CD-R Etc.

  On the other hand, in recent years, high-efficiency coding technology has been developed, and even video data is band-compressed and converted into data that can be easily handled as digital data, so that all kinds of data are handled as digital data. It is becoming. Along with this, it is required to increase the capacity of the optical disc and to improve the recording density.

  However, when the recording density of the recording medium is improved, the difference between the signal 1 and the signal 0 read from the recording medium is small, the reading margin is reduced, and the quality of the reproduced signal is likely to deteriorate.

  In order to avoid such deterioration of the quality of the reproduced signal, for example, when a signal is recorded on a recording medium, the low-frequency component of the recorded signal must be suppressed. This is because a signal reproduced from an optical disk contains a lot of low-frequency noise, and this low-frequency noise is removed by a filter to improve the S / N. Therefore, a necessary low-frequency component of the reproduced signal is reduced. Therefore, the low frequency component of the signal to be recorded is suppressed in advance to avoid the effect.

  For this reason, a data encoding method capable of suppressing low frequency components has been proposed. However, even if this encoding method is applied, data patterns in which low-frequency components cannot be suppressed may continue for a long time. Therefore, it is effective to scramble data to reduce this probability.

  By the way, when recording data on a recording medium and reproducing the data, recording and reproduction are performed in units of data of an appropriately defined size, and this unit is called a sector. Further, the run length of the code recorded in this sector is limited in order to narrow the frequency bandwidth of communication of the recording and reproducing apparatus.

  It is known that, when recording and reproducing data in a sector whose run length is limited in this way, once an error occurs, the error propagates not only to the error location but also to the subsequent data portion. I have. To prevent this, a predetermined pattern that can be distinguished from the recording data is recorded in the sector at regular intervals, and this pattern is called a sync code. Further, each part of the sector divided by each sync code is called a frame.

  As described above, when recording data, it is necessary to suppress low-frequency components of the data. For this reason, the data is converted before recording. This conversion is performed by, for example, a code converter as shown in FIG.

  In FIG. 1, when main data is input, a scrambler 101 scrambles the main data based on a pseudo-random number sequence, and adds the scrambled main data to an 8/16 converter 102. The 8/16 converter 102 receives the scrambled main data, modulates the main data, and outputs the modulated main data. The modulated main data is transmitted to a recording and reproducing device and recorded on a recording medium.

  Further, the scrambler 101 inputs the upper 4 bits of the logical address (8 bits) associated with the input of the main data as a seed selection signal, and outputs the scrambled data for each of the 16 logical addresses (every 16 sectors). Has changed. This scrambled data indicates one of 16 different types of pseudo-random number sequences different from each other, and for each sector, each pseudo-random number sequence is sequentially selected by the scrambled data. Then, in response to the sector start signal, the data of one sector is scrambled by the selected pseudo-random number sequence.

  The scramble by the scrambler 101 calculates an exclusive OR of the main data and data (random number) generated from an M sequence (Maximum length sequence) represented by a generator polynomial of the following equation (1). This is performed by obtaining for each bit.

  FIG. 19 shows the configuration of the scrambler 101. In the figure, a seed ROM 111 previously stores initial bit patterns of each of 16 types of pseudo-random numbers, and selects one of these initial bit patterns in response to a seed selection signal. The shift register 112 receives the initial bit pattern selected by the seed ROM 111 in response to the seed load signal, and sequentially shifts the initial bit pattern in synchronization with a bit clock. The exclusive OR circuit 113 calculates the exclusive OR of the bit output from the shift register 112 and the fourth bit from the left in the shift register 112, and returns the operation result to the shift register 112. The lower 8 bits in the shift register 112 are latched by the flip-flop 114 in synchronization with the word clock, and the 8-bit bit string in the flip-flop 114 is applied to each exclusive OR circuit 115. These exclusive OR circuits 115 receive 8-bit (one word) main data together with an 8-bit bit string, and obtain exclusive logic of each bit. These calculation results are output.

  On the other hand, the 8/16 converter 102 performs two-stage conversion to form main data for output from the scrambled main data. The first stage modulates the scrambled data by PPM (Pit Position Modulation) to form 16-bit main data from the 8-bit main data, and the second stage executes the 16-bit main data. The data is modulated by PWM (Pulse Width Modulation), and the main data for output is formed from the 16-bit main data.

  FIG. 20 shows the configuration of the 8/16 converter 102. 8, the scrambled 8-bit main data from the scrambler 101 is added to a main table 122 and a sub-table 123 via a flip-flop 121 and also to a DSV control circuit 124. The main table 122 receives the main data and is instructed by the selector circuit 125 for the next state. Similarly, the sub table 123 receives the main data and the selector circuit 125 designates the next state.

  The main table 122 has main data as shown in Table 1 below, and refers to the main data to search for 8-bit main data and 16-bit main data corresponding to the next state. Outputs 16-bit main data. Similarly, the sub-table 123 has sub-data as shown in Table 2 below, and refers to this sub-data to retrieve 8-bit main data and 16-bit main data corresponding to the next state. Then, the 16-bit main data is output.

  However, since the value range of the 8-bit main data is 0 to 255, in the main table 122, each 16-bit main data is stored in advance in correspondence with each value (0 to 255) of the 8-bit main data. Although defined, Table 1 shows only a part (0 to 45) of each value of 8-bit main data and 16-bit main data corresponding to these values. Further, in the sub table 123, unlike the main table 122, each 16-bit main data is predetermined in correspondence with only a part (0 to 87) of each value of the 8-bit main data. Shows a further part (0 to 45) of each value of the 8-bit main data and 16-bit main data corresponding to these values. Further, in each of the tables 122 and 123, the next state corresponding to each main data is predetermined, and when searching for 16-bit main data, the next state corresponding to the 16-bit main data is determined. Is also read.

  In the main table 122, if the value of the 8-bit main data is included in the range of 0 to 87, according to the next state specified by the selector circuit 125, among the states S1 to S4 in Table 1, One of the 16-bit main data corresponding to the value of the 8-bit main data is selected from the 16-bit main data belonging to this state, and the 16-bit main data DM is transmitted to the crossbar switch 126. Output to Further, in the main table 122, the value of the 8-bit main data is included in the range of 88 to 255, and one of the two states S1 and S4 in Table 1 depends on the next state specified by the selector circuit 125. Is selected, each of the 16-bit main data corresponding to the value of the 8-bit main data is selected from each of the two states S1 and S4 in Table 1, and these main data D1 and D4 are transferred to the crossbar switch 126. Output to Further, in the main table 122, the value of the 8-bit main data is included in the range of 88 to 255, and one of the two states S2 and S3 in Table 1 depends on the next state specified by the selector circuit 125. Is selected, 16-bit main data corresponding to the 8-bit main data value is selected from the specified state, and this main data is output to the crossbar switch 126.

  Similarly, in the sub-table 123, if the value of the 8-bit main data is included in the range of 0 to 87, each of the states S1 to S4 in Table 2 according to the next state specified by the selector circuit 125. Is selected, 16-bit main data corresponding to the 8-bit main data value is selected from this state, and the 16-bit main data DS is output to the crossbar switch 126.

  At this time, not only the 16-bit main data is read from each of the tables 122 and 123, but also the next states corresponding to these main data are read and output to the crossbar switch 126.

  At the beginning of the frame, the next state is initialized to 1 in response to the sync code.

  When the DSV control circuit 124 receives the 8-bit main data and the next state from the selector circuit 125, the DSV control circuit 124 makes a determination based on the value of the 8-bit main data and the next state, and generates a crossbar switch switching signal according to the determination result. Output to the crossbar switch 126.

  In response to the crossbar switch switching signal, the crossbar switch 126 selects one to two of the 16-bit main data from the main table 122 and the 16-bit main data from the sub-table 123. And outputs one or two 16-bit main data to at least one of the first DSV operation circuit 127 and the second DSV operation circuit 128.

  For example, if the value of the 8-bit main data is 87 or less, and the 16-bit main data corresponding to the 8-bit main data value exists in both the main table 122 and the sub-table 123, the DSV control is performed. When determined by the circuit 124, the crossbar switch 126 converts the 16-bit main data DM from the main table 122 and the 16-bit main data DS from the sub-table 123 in response to the crossbar switch switching signal. And outputs the 16-bit main data DM and DS to the first and second DSV operation circuits 127 and 128.

  Further, the value of the 8-bit main data is 88 or more, and the 16-bit main data corresponding to the value of the 8-bit main data exists only in the main table 122 and the next data from the selector circuit 125 When the DSV control circuit 124 determines that one of the states 1 and 4 is designated by the state, the crossbar switch 126 responds to the crossbar switch switching signal by sending the 16 from the main table 122. The main data D1 and D4 are output to the first and second DSV operation circuits 127 and 128, respectively.

  Further, the value of the 8-bit main data is 88 or more, each 16-bit main data corresponding to the value of the 8-bit main data exists only in the main table 122, and the next data from the selector circuit 125 When the DSV control circuit 124 determines that one of the states 2 and 3 is designated by the state, the crossbar switch 126 responds to the crossbar switch switching signal by outputting the 16 from the main table 122. Only one bit of main data (16-bit main data read from one of the states 2 and 3 specified by the next state) is selected, and the 16-bit main data is output to the first DSV operation circuit 127. I do.

  The following table (3) summarizes the choices of the 16-bit main data DM, D1, D4, DS by such a crossbar switch 126.

  However, when the value of the 8-bit main data is 88 or more and one of the states 1 and 4 is specified by the next state from the selector circuit 125, If the run length of the same code continuous between the word of the 8-bit main data and the immediately preceding word is out of the range of 2 to 10, the DSV control circuit 124 determines whether the 16-bit main data D1, D4 The crossbar switch 126 is controlled so that only the 16-bit main data of the state whose run length falls within the range of 2 to 10 is output. Therefore, in order to output the 16-bit main data D1 and D4 from the main table 122 to the first and second DSV operation circuits 127 and 128, the 16-bit main data D1 and D4 must be consecutively inserted between the 8-bit main data word and the immediately preceding word. The condition is that the run length of the same code is within the range of 2 to 10.

  Each time the 16-bit main data is input, the first and second DSV calculation circuits 127 and 128 calculate a DSV (Digital Sum Value) related to the 16-bit main data. The calculation method of this DSV is as follows.

  For example, when 16-bit (1 word) main data as shown in FIG. 21A is input from the crossbar switch 126 to the PWM conversion circuit 129 through the selector circuit 125, the PWM conversion circuit 129 outputs the 16-bit main data. The data is subjected to pulse width modulation to form main data for output as shown in FIG. 21B, and this main data is output.

  21A and 21B, the number of values 1 and the number of values 0 in one-word output main data can be derived from 16-bit main data of one word. it can. Therefore, every time 16-bit main data is input, the number of values 1 and the number of values 0 in one-word output main data corresponding to the 16-bit main data are obtained, and the difference between the two numbers is obtained. This difference is added for each word, and the integrated value is obtained as DSV. The respective DSVs obtained by the first and second DSV calculation circuits 127 and 128 are provided to the selector circuit 125 and the comparator 130. Actually, the value 1 in the one-word output main data is replaced with +1, the value 0 is replaced with -1, and the sum of the value +1 and the value -1 in the one-word output main data is obtained. The DSV is obtained by integrating the sum for each word.

  The operations by the first and second DSV operation circuits 127 and 128 are performed on a sector-by-sector basis, and are performed continuously from the start time to the end time of one sector. At the time of disclosure of the sector, the first bit LSB of the sector is input from the PWM conversion circuit 129 to the first and second DSV operation circuits 127 and 128, and in response to the bit LSB, the first value of the main data for output is output. Is initialized to 0.

  When the comparators 130 receive the respective DSVs from the first and second DSV operation circuits 127 and 128, the comparator 130 selects the one with the lower absolute value of the DSV, and sends the operation circuit on the side that has obtained the DSV to the selector circuit 125. Instruct. In response to this, the selector circuit 125 selects the operation circuit instructed by the comparator 130, outputs the 16-bit main data for which the DSV is obtained by the operation circuit to the PWM conversion circuit 129, and outputs the 16-bit main data to the PWM conversion circuit 129. The next state associated with the main bit data is output to the main table 122, the sub table 123, and the DSV control circuit 124.

  That is, in the 8/16 converter 102, the 8-bit main data is converted into 16-bit main data, and the DSV of each output main data corresponding to the 16-bit main data is obtained in advance. The 16-bit main data that can lead to a small DSV is selected, and the 16-bit main data is converted into output main data and output. However, as described above, each of the 16-bit main data corresponding to the value of the 8-bit main data exists only in the main table 122, and depending on the next state from the selector circuit 125, any one of the states 2 and 3 can be used. If is specified, only 16-bit main data from the main table 122 (16-bit main data read from any of the states 2 and 3 specified by the next state) is selected. Therefore, the conversion from the 16-bit main data to the main data for output is uniquely performed.

  A series of processes performed by such a transcoder will be described below in accordance with the flowcharts shown in FIGS. 22 and 23.

  First, when the head of the frame is identified by counting each bit of the input main data, a sync code is added to the head of this frame (steps 201 and 202), and the selector circuit of the 8/16 converter 102 The next state output from 125 is initialized to 1 (step 203). If it is not the end of the sector (step 204, NO), the process returns to step 201.

  Subsequently, scrambling of the input main data frame is started, and the scrambled main data frame is converted into an output main data frame word by word (steps 205 and 206). When the next frame is identified, a sync code is added to the beginning of this frame, the next state is initialized to 1 again, and scrambling and conversion are performed. Thereafter, similarly, the processing of each frame is repeated, and the processing of one sector is completed (step 204, YES).

  In step 206, it is determined whether or not the value of 8 bits (one word) is less than 88. If the value is less than 88 (step 301, YES), the 16-bit main data DM from the main table 122 is determined. And the one having the smaller DSV is selected from the 16-bit main data DS from the sub-table 123 (step 302).

  If the 8-bit (1 word) value is 88 or more (step 301, NO), one of one or two 16-bit main data from the main table 122 is selected (step 303).

  By forming the main data for output so that the DSV is always small, the low-frequency component of the main data is suppressed. For this reason, in a recording / reproducing apparatus which records this main data on a recording medium and reproduces the same, low-frequency components of the reproduced signal are suppressed, and bias of the envelope (envelope) of the reproduced signal is suppressed. It is possible to prevent reproduction errors.

  However, in the above-mentioned conventional transcoder, although it is possible to suppress the low-frequency component of a reproduced signal to be recorded and reduce the probability that an abnormal increase in the low-frequency component occurs, the probability is sufficiently reduced. It did not, and sometimes caused playback errors.

  Specifically, in the 8/16 converter 102 shown in FIG. 20, if there are M types of 16-bit main data, among these main data, those including a bit pattern that causes DSV divergence are N When 16-bit main data including such a bit pattern is continuous, the DSV increases and decreases and diverges, and the low-frequency component of the main data for output increases.

  Here, M = 256, N = 168, and when the value of the 8-bit main data is 0 to 87, the DSV converges, but when the value of the 8-bit main data is 88 to 255, , DSV diverge. In practice, divergence of DSV occurs in about 10% of the total of each main data. The graph of FIG. 24A shows the variation of the value of the 8-bit main data in one sector, and the graph of FIG. 24B corresponds to the variation of the value of the main data of FIG. It shows the increase and decrease of DSV. As is clear from these graphs, if the value of the main data of 8 bits continues to be included in the range of 88 to 255, the DSV diverges.

  That is, in the conventional transcoder, the input main data is scrambled and the scrambled main data is subjected to 8/16 conversion. However, the low-frequency component of the main data cannot be reduced sufficiently. For this reason, when reproducing from the recording medium on which the main data is recorded, the low-frequency component of the reproduction signal increases, and the envelope (envelope) of the reproduction signal fluctuates rapidly, thereby causing a reproduction error. . This reproduction error cannot be prevented even if the envelope of the reproduction signal is corrected or the main data is corrected by an ECC (Error Correction Code) added to the main data.

  Further, since each pseudo-random number sequence of the scrambled data is changed in a predetermined sequence, there is a sufficient possibility that substantially the same signal is repeatedly rewritten in the same sector. In this case, since the characteristics of the recording medium portion in this sector change non-uniformly, the S / N of the reproduction signal is reduced, which may cause a reproduction error.

  It is considered that such a reproduction error can be prevented by improving the method of scrambling the main data.

  Therefore, the present invention solves the above-mentioned conventional problems, and reduces a low-frequency component of a signal recorded on a recording medium by controlling a pseudo-random number sequence so that divergence of DSV is sufficiently suppressed. The purpose is to do.

  It is another object of the present invention to control a pseudo-random number sequence so that substantially the same signal is not repeatedly rewritten in the same sector.

  In order to solve the above-mentioned conventional problem, the invention according to claim 1 scrambles input main data based on one of a plurality of types of pseudo-random numbers, and converts the scrambled main data into a plurality of types of pseudo-random numbers. The main data for output is formed from the converted main data, and an operation value indicating the difference between the number of values 0 and the number of values 1 indicated by the main data for output is converted. Determining whether the amount of change in the calculated value exceeds a predetermined threshold value in a code conversion method for selecting any one of the converted data according to the calculated value; When it is determined that the change amount exceeds the threshold value, a step of changing the pseudo-random number sequence used for scrambling, and based on the changed pseudo-random number sequence, re-input the main data again. And a step of crumbles.

  As described above, when the amount of change in the calculation value indicating the difference between the number of values 0 and the number of values 1 indicated by the main data for output, that is, the change in DSV exceeds the threshold value, the pseudo-random number sequence is changed. Since the input main data is scrambled again, the change of the pseudo random number sequence and the scrambling are repeated until the DSV falls below the threshold value. As a result, an increase in DSV is reliably suppressed, and low-frequency components of the main data for output are reduced. Therefore, when the main data for output is recorded on a recording medium and a signal is reproduced from the recording medium, the reproduced signal has a small low-frequency component, and a reproduction error can be sufficiently prevented.

  As described in claim 2, the conversion of the main data may be performed by the first modulation having M types of conversion data, and the formation of the main data for output may be performed by the second modulation. Here, it is assumed that N types of converted data among the M types of converted data cause an increase in the calculated value.

  As described in claim 3, the first modulation may be pit position modulation having M types of conversion data, and the second modulation may be pulse width modulation.

  When the amount of change of the operation value becomes equal to or greater than the threshold value K in the first period L, the operation value is output in each word of the main data for output in the first period L. Each word having the bit pattern that caused it is included. If the pseudo-random number sequence at this time is defined as a first pseudo-random number sequence, the first pseudo-random number sequence may be any one of a plurality of predetermined second pseudo-random number sequences. These second pseudo-random number sequences include, as main data for output in a first period L formed by re-scramble, each word having no bit pattern as (M- A pseudo-random number sequence that can be derived from N) / M or more may be used.

  Here, as the second pseudo-random number sequence used for the re-scramble, a word that can lead each word having no bit pattern causing an increase in DSV at least at a rate of (M−N) / M or more is set. ing. By guiding each word having no bit pattern at least at a rate of (M−N) / M or more, the amount of change in DSV is reduced to a practical level.

  Assuming that a period of a series of main data for output formed along with scrambling based on the first pseudo-random number sequence is a second period H, each second pseudo-random number sequence is represented by H / At least as many types as L = J may be set.

  That is, if a period in which scrambling based on the same first pseudo-random number sequence is continued is defined as a second period H, and during a first period L shorter than the second period H, the DSV exceeds the threshold value, 2. Pseudo random number sequences are set for at least the same number of types as H / L = J. By applying one second pseudo-random number sequence, even if the DSV exceeds the threshold value in a certain first period L, the DSV increases through the second period H among the J second pseudo-random number sequences. A second pseudo-random number sequence that does not need to be performed can be obtained.

  As described in claim 6, when the amount of change in the operation value exceeds the threshold value, the part of the main data of a predetermined length input before this point is changed to the pseudo random number sequence of the part. You may scramble again afterwards.

  Alternatively, as described in claim 7, an operation value of the main data for output corresponding to the input main data having a predetermined length is obtained, and a change amount of the operation value exceeds a threshold value. In some cases, the input main data may be re-scrambled after changing the pseudo-random number sequence to obtain a pseudo-random number sequence in which the amount of change in the calculated value is within the threshold value.

  According to the code conversion method described in claims 8 to 14, instead of determining whether the amount of change of the operation value has exceeded the threshold value as in claims 1 to 7, the absolute value of the operation value is equal to the threshold value. The only difference is that it is determined whether or not the value has been exceeded.

  The code conversion device according to claims 15 to 22 is an embodiment of the code conversion method.

  Next, according to a twenty-third aspect of the present invention, in a recording medium for recording and reproducing main data in sector units, scrambled data and scrambled main data are recorded for each sector. Indicates one of predetermined initial values of each pseudo-random number sequence for scrambling the data.These pseudo-random number sequences are respective random numbers starting from the respective initial values, and the main data is the scrambled data. It is scrambled by sequentially performing a logical operation on the pseudo random number sequence and the main data.

  If the scrambled data and the scrambled main data are recorded for each sector in this manner, the scrambled data and the scrambled main data are read from the sector, and the main data is restored based on the scrambled data. Can be. Therefore, any of the initial values of each pseudo-random number sequence may be recorded as scramble data for each sector. In addition, the scrambled data indicates the initial value of the pseudo random number sequence, and since the pseudo random number sequence is a random number starting from the initial value, the main data is recorded after the main data is sufficiently scrambled. be able to. As a result, the low frequency component of the signal recorded in the sector can be suppressed, and substantially the same signal is not repeatedly rewritten in the same sector.

  As described in claim 24, the pseudo random number sequence may be a maximum long period sequence.

  As set forth in claim 25, the scramble data may indicate whether to scramble the main data of the sector.

  In this case, it is not necessary to scramble the main data, and the main data can be recorded and reproduced as it is.

  As set forth in claim 26, the scramble data may be set based on a random number, or as set forth in claim 27, the scramble data may be set based on the number of times of rewriting main data in the same sector. .

  Thereby, the scramble data can be changed irregularly.

  The code recording device according to claims 28 to 32 is for recording main data on the recording medium according to claim 23.

  A code reproducing apparatus according to a thirty-third aspect is for reproducing main data from the recording medium according to the twenty-third aspect.

  As described above, according to the code conversion method and the code conversion apparatus of the present invention, the amount of change in the operation value indicating the difference between the number of values 0 and the number of values 1 indicated by the main data for output, that is, the DSV When the variation exceeds the threshold, the input main data is re-scrambled after changing the scrambled data. Therefore, the change and scramble of the scrambled data are repeated until the DSV falls below the threshold. As a result, an increase in DSV is reliably suppressed, and low-frequency components of the main data for output are reduced.

  Therefore, when the main data for output is recorded on a recording medium and a signal is reproduced from the recording medium, the reproduced signal has a small low-frequency component, and a reproduction error can be sufficiently prevented.

  Also, no matter what pattern is input as the main data, the DSV can be kept within the allowable range, and the reproduction error can be sufficiently prevented.

  According to the code recording medium, the code recording device, and the code reproducing device of the present invention, the scrambled data and the scrambled main data are recorded for each sector. The main data can be restored based on the scrambled data. Therefore, it is possible to freely select a scrambling method for the main data, and it is possible to effectively suppress abnormal fluctuation of the low frequency component of the reproduction signal. As a result, the reproduction signal can be accurately binarized, and the probability of causing a reproduction error can be extremely reduced. Also, since the scrambled data is changed according to the number of rewrites to the same sector of the optical disk, even if the same main data is repeatedly written to the same sector, the uniformity of the characteristics of the recording medium in this sector deteriorates. Without reducing the S / N of the reproduction signal, the reliability of repeated recording and reproduction can be improved.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 shows a first embodiment of the code conversion apparatus of the present invention. In FIG. 1, a memory 11 is for inputting and storing main data, and can store main data of at least two sectors. When the main data is input from the memory 11, the scrambler 12 scrambles the main data and outputs the scrambled main data to the 8/16 converter 13. The 8/16 converter 13 modulates the scrambled data by PPM to form 16-bit main data from the 8-bit main data in order to form main data for output from the scrambled main data. Further, the 16-bit main data is modulated by PWM, main data for output is formed from the 16-bit main data, and the main data for output is output. The comparator 14 receives the DSV obtained by the 8/16 converter 13 and determines whether or not the amount of change (differential value) of the DSV has exceeded a predetermined threshold value. Output to the controller 15. The controller 15 generally controls the code conversion apparatus, and specifies a write address for writing main data to the memory 11, a read address for reading main data from the memory 11, and a scrambler. The initial bit pattern of the pseudo random number sequence of the blur 12 is changed, a conversion failure signal is output, and the like.

  The scrambler 12 is configured similarly to the scrambler 101 shown in FIG. 19, and includes a seed ROM 111, a shift register 112, an exclusive OR circuit 113, a flip-flop 114, and each exclusive OR circuit 115, and has an 8-bit (1 word) main data is input and scrambled, and the scrambled main data is output.

  The 8/16 converter 13 is configured similarly to the 8/16 converter 102 shown in FIG. 20, and includes a flip-flop 121, a main table 122, a sub-table 123, a DSV control circuit 124, a selector circuit 125, a crossbar switch 126, It includes first and second DSV operation circuits 127 and 128, a PWM conversion circuit 129, and a comparator 130, converts 8-bit main data into 16-bit main data, and converts the 16-bit main data into an output main data. Converted to data and output.

The operation of the transcoder having such a configuration will be described with reference to the sequence chart shown in FIG.
First, the controller 15 is in an idle state (state 401), and when the data enable signal is asserted, sets the memory 11 to a write state (state 402) and starts storing main data of one sector. When the sector start signal is asserted, the controller 15 starts reading main data of one sector from the memory 11 and supplies the main data to the scrambler 12 and also transmits a seed selection signal and a seed load signal to the scrambler 12. Output (state 403). The scrambler 12 pre-stores a predetermined initial bit pattern of each pseudo-random number sequence, selects one of these initial bit patterns in response to a seed selection signal, and responds to a seed load signal. To generate a series of random numbers starting from the selected initial bit pattern, sequentially scramble each word of the main data, and convert each word of the scrambled main data to an 8/16 converter 13. Are output sequentially.
Note that the initial bit pattern of the pseudo-random number sequence set first may be set based on the upper 4 bits of the logical address associated with the input of the main data, as in the conventional device shown in FIG.

  The 8/16 converter 13 sequentially modulates each word of the scrambled main data by the PPM, forms 16-bit main data from the 8-bit main data for each word, and further forms the 16-bit main data. The main data is modulated by PWM, the main data for output is formed from the 16-bit main data, and the main data for output is output. The 8/16 converter 13 integrates and calculates the DSV for each word of the main data, and outputs the DSV to the comparator 14. The comparator 14 determines whether or not the amount of change in the DSV has exceeded a threshold value, and outputs the result of the determination to the controller 15.

  When the main data of one sector is read out from the memory 11 and the scrambling and modulation of the main data are performed, the data of the next one sector main data is input to the memory 11 and stored (state 404). .

  When the main data of one sector is read from the memory 11, only the writing of the main data of the next one sector to the memory 11 is continued (state 405), and this writing is completed, and the sector start signal is asserted. Then, the process returns to the state 404, where the main data of this one sector is read out, and the main data is scrambled and modulated.

  In state 404, if main data of the next one sector is not input, only reading of main data of one sector from memory 11 continues (state 406). When reading of main data of one sector is completed, controller The state 15 is a standby state for the main data of the next one sector (state 407), the read address and the write address are matched, and the state returns to the idle state (state 401).

  Therefore, the main data of each sector is sequentially stored in the memory 11, and accordingly, the main data of these sectors are sequentially read from the memory 11, and the main data of these sectors are sequentially scrambled, modulated, and output. . The respective sync codes are inserted between the frames of the main data output in this way, an error correction code is added, and the main data is input to the recording unit 24 of the recording / reproducing apparatus (shown in FIG. 3). In this recording / reproducing apparatus, main data is recorded on a recording medium in sector units.

  On the other hand, during the scrambling and modulation of the main data of one sector (steps 404 and 406), if the comparator 14 determines that the amount of change in the DSV exceeds the threshold, that is, the DSV diverges. Then, when the low-frequency component of the main data output from the 8/16 converter 13 increases, the controller 15 responds to this by initializing the write address and the read address to the memory 11 and, at the same time, converting the conversion failure signal. Is output (state 408). This conversion failure signal is output to the 8/16 converter 13, the drive control unit 26 and the error correction code modulation unit 22 of the recording / reproducing device (shown in FIG. 3).

  This conversion failure signal is input to the 8/16 converter 13 as a reset signal, and the 8/16 converter 13 is initialized. In addition, in response to the conversion failure signal, the recording / reproducing apparatus suspends recording for this sector and enters a state in which recording for this sector is restarted. Further, in response to the conversion failure signal, the preceding circuit (the error correction code modulator 22 of the recording / reproducing apparatus) restarts the main data supply from the sector.

  Then, the controller 15 waits for writing to the memory 11 to be disabled (state 409), returns to the state 402 via the state 401, and starts reading the main data of one sector in which the DSV has diverged earlier. The main data is supplied to the scrambler 12, and the seed selection signal and the seed load signal are output to the scrambler 12 (state 410). In this state 410, the controller 15 indicates the initial bit pattern of the different pseudo-random number sequence so that the main data of this one sector is scrambled by a pseudo-random number sequence different from the one that caused the divergence of DSV. A seed selection signal is output to the scrambler 12. In response, the scrambler 12 generates a series of random numbers starting from the different initial bit patterns, sequentially scrambles the main data with this series of random numbers, and converts the scrambled main data into an 8/16 transform. Output to the device 13 sequentially. The 8/16 converter 13 modulates the scrambled main data to form main data for output, and outputs the main data for output. Further, the 8/16 converter 13 integrates and obtains the DSV, and outputs the DSV to the comparator 14.

  Thereafter, similarly, each of the states 401 to 410 is repeated, the initial bit pattern of the pseudo-random number sequence is changed until the DSV becomes equal to or less than the threshold value, and the scrambling and modulation of the main data in the same sector are repeated. As a result, the main data of this sector is converted in a state where the DSV does not exceed the threshold value, that is, in a state where the low frequency component of the main data of the sector output from the 8/16 converter 13 is sufficiently suppressed. Then, the main data of this sector is recorded on the recording medium by the recording / reproducing device. Therefore, when a signal is reproduced from this recording medium, the low-frequency component of the reproduced signal is sufficiently small, and a reproduction error can be sufficiently prevented.

  In the 8/16 conversion described above, the input main data is in 8-bit units (word units), and the value of the main data corresponds to any of 0 to 255. The value of 16-bit main data must be set in advance according to the value 0 to 255. That is, it is necessary to preset 256 types of conversion data of the main data.

  On the other hand, the DSV tends to converge for a bit pattern in which the upper two bits of the 16-bit main data are 00 or a part of each bit pattern in which the upper two bits are 01, and For a bit pattern in which 2 bits are 00 or a part of each bit pattern in which the upper 2 bits are 01, DSV divergence tends to occur. There are 168 types of bit patterns that easily cause the divergence of DSV. Therefore, 168 types of converted data among the 256 types of converted data tend to cause DSV divergence.

  Here, the number of each word in a predetermined first period L (which is shorter than the period of the main data of one sector) is G, and all the converted data of the main data are M types, and DSV is likely to diverge. Assuming that the number of converted data of the main data is N, if the number of each word that does not include a bit pattern that easily causes the divergence of the DSV is larger than the ratio of G × (M−N) / M, the DSV in the first period L Does not diverge. For example, if the number of each word in the first period L is 45, then 45 × (256-168) / 256 ≒ 16, and 16 of the 45 words are bit patterns that are likely to cause DSV divergence. Is not included, DSV divergence in the first period L can be suppressed to a practical level.

  Therefore, when the scramble and the modulation are repeated two or more times for the main data in the same sector, if the first pseudo-random number sequence is the first pseudo-random number sequence and the next pseudo-random number sequence is the second pseudo-random number sequence, As the pseudo-random number sequence, a pseudo-random number sequence in which the number of words that do not include a bit pattern that easily causes DSV divergence is greater than the ratio of G × (M−N) / M is desirable.

  Further, assuming that the period of the main data of one sector is a second period H, by setting each second pseudo-random number sequence for at least the same number of types as H / L = J, one second pseudo-random number sequence is obtained. When applied, even if DSV divergence is caused in a certain first period L, divergence of DSV in the first period L can be suppressed by any of the other second pseudo-random number sequences.

  That is, each random number generated based on the first pseudo-random number sequence for each word in the first period L, and each random number generated based on the second pseudo-random number sequence for each word in the first period L When the random numbers are sequentially compared, the second pseudo-random number sequence is set such that the number of mismatches between the random numbers is at least greater than the ratio of G × (M−N) / M. A pseudo-random number sequence is obtained for each first period L. This makes it possible to set at least the same number of second pseudo random number sequences as H / L = J. Normally, in the first period L in which the DSV is diverged, since the divergence of the DSV is caused by all of the words, the number of mismatches of each random number between the first and second pseudo-random number sequences is at least G × (M If the ratio is more than (N) / M, these words can be sufficiently scrambled to suppress the DSV in the first period L. Further, even if the divergence of the DSV is caused in the other first period L, the divergence of the DSV in the other first period L can be suppressed by any of the other second pseudo-random number sequences.

  However, the random number of the first pseudo-random number sequence and the random number of the second pseudo-random number sequence that do not match the first pseudo-random number sequence must be able to scramble each bit pattern which is likely to cause divergence of DSV contained in a word by different methods. No.

  For example, the scrambler 12 may apply the generator polynomial of the following equation (2) to set the first pseudo-random number sequence and each of J types of second pseudo-random number sequences. However, it is necessary to increase the capacity of the seed ROM 111, the shift register 112, and the flip-flop 114.

  In the transcoder according to the first embodiment, it is determined whether or not the amount of change in DSV has exceeded a threshold, but whether or not the absolute value of DSV has exceeded a predetermined threshold is determined. May be determined, and based on this determination, the main data of the same one sector may be re-scrambled.

FIG. 3 shows a recording and reproducing apparatus to which the code conversion apparatus of FIG. 1 is applied.
In FIG. 1, when inputting data to be recorded, an external communication unit 21 supplies the data to an error correction code modulation unit 22. The error correction code modulator 22 temporarily stores the data, separates the data into sector units, adds an error correction code to each sector data, and modulates the data and error correction code of each sector. 23. The modulating section 23 includes the code conversion apparatus shown in FIG. 1 and performs scrambling and modulation of data and an error correction code for each sector to form main data for output. And outputs the result to the recording unit 24. The recording unit 24 converts one sector of main data and each sync code into serial data, forms a recording signal corresponding to the serial data, and outputs the recording signal to the optical head 25. The optical head 25 converts the recording signal into an optical signal (laser light), and irradiates the optical signal to the optical disk 28.

  The drive control unit 26 controls the recording / reproducing apparatus as a whole and synchronizes the processing of the modulation unit 23 and the recording unit 24 with the recording of the main data of one sector and each sync code. Instruct 27. In response to this, the head controller 27 controls the motor 29 that drives the optical disk 28 to rotate, and controls the actuator of the optical head 25 so that the optical head 25 traces the track of the optical disk 28.

  As a result, one sector of main data and each sync code are recorded in one sector (storage area) of the optical disk 28.

  Here, as described above, when the DSV diverges while scrambling and modulating one sector of main data, the code conversion apparatus of FIG. 1 outputs a conversion failure signal. When the main data of the same sector is received again, the pseudo random number sequence is changed, and then the scrambling and modulation of the main data of this sector are performed again.

  In this recording / reproducing apparatus, the conversion failure signal is input to the error correction code modulator 22 and the drive controller 26. In response to the conversion failure signal, the error correction code modulator 22 supplies the main data of the same sector to the modulator 23 again. Further, the drive control unit 26 instructs the head control unit 27 to re-record the main data of this sector and each sync code. In response to this, the head control unit 27 controls the motor 29 that drives the optical disk 28 to rotate, controls the movement of the optical head 25, and stores the main data of this sector and each sync code in the recording area of the optical disk 28. When the main data and the respective sync codes of the same sector are again input after that, the data is written again in the same recording area of the optical disk 28. Therefore, in this recording / reproducing apparatus, the main data of one sector where the DSV converges is input, and the main data of this sector and each sync code are written to the same recording area of the optical disk 28 until the main data and each sync code are written to the same recording area. Will be repeated.

  In this recording / reproducing apparatus, when data reproduction is instructed from outside via the external communication unit 21, the drive control unit 26 notifies the head control unit 27 of this. In response, the head control unit 27 controls the motor 29 that drives the optical disk 28 to rotate, and controls the movement of the optical head 25. Accordingly, the optical head 25 reads an optical signal indicating main data and each sync code from the optical disk 28 in sector units, and outputs a reproduced signal corresponding to the optical signal to the reproducing unit 31. The reproducing unit 31 performs sampling and binarization of the reproduced signal to form serial data, further converts the serial data into parallel data, and outputs one sector of main data and each sync code to the demodulating unit 32. Output. The demodulation unit 32 demodulates the main data while detecting each sync code, and outputs the demodulated main data to the error correction code demodulation unit 33. The error correction code demodulation unit 33 detects and corrects an error of the main data based on the error correction code of the main data, and outputs the corrected main data to the outside through the external communication unit 21.

  FIG. 4 shows a second embodiment of the transcoder according to the present invention. In the transcoder of the second embodiment, a sector counter 41 is added to the apparatus of FIG. 1 and a scrambler switching unit 42 is applied instead of the scrambler 12, so that when the DSV diverges, each sector The scramble and the modulation are redone in units, and the scramble method is changed only for the frame that causes the divergence of the DSV.

  When the sector start signal is asserted, that is, when the reading of the main data of one sector from the memory 11 is started, the sector counter 41 sequentially counts each frame of this sector based on the bit clock or the word clock, The position of the frame being processed by the scrambler switching unit 42 and the 8/16 converter 13, that is, the position of the frame from the head of the sector, is detected, and the position of the frame is notified to the comparator 14 and the controller 15.

  As shown in FIG. 5, the scrambler switching unit 42 includes a first scrambler 43, a second scrambler 44, an AND circuit 45, and exclusive OR operators 46 and 47. The first scrambler 43 has substantially the same configuration as the scrambler 101 shown in FIG. 19, and includes a seed ROM 111, a shift register 112, an exclusive OR circuit 113, and a flip-flop 114 (each exclusive OR circuit 115 is an exclusive OR circuit). (Corresponding to the logical sum operator 47), and outputs data (random numbers) generated from the M-sequence represented by the generator polynomial of the above equation (1). Also, the second scrambler 44 is configured substantially in the same manner as the scrambler 101 shown in FIG. 19, and includes a seed ROM 111, a shift register 112, an exclusive OR circuit 113, and a flip-flop 114 (each of the exclusive OR circuits 115 (Corresponding to the exclusive OR operation unit 47), and outputs data (random numbers) generated from the M-sequence represented by the generator polynomial of the above equation (2). However, in the case of the second scrambler 44, the capacities of the seed ROM 111, the shift register 112, and the flip-flop 114 need to be larger than those of the first scrambler 43.

  Normally, the frame signal from the controller 15 is negated, and a signal having a value of 0 is input to the AND circuit 45. Therefore, the data of the second scrambler 44 is output to the exclusive OR calculator 46. Never. Therefore, the exclusive OR calculator 47 obtains the exclusive OR of the data output from the first scrambler 43 and the 8-bit main data, and outputs the calculation result. In this case, the scrambler switching unit 42 performs the same function as the scrambler 101 shown in FIG.

  When a frame signal from the controller 15 is asserted during an arbitrary frame of one sector, a signal having a value of 1 is input to the AND circuit 45. In this case, the exclusive OR of the data of the first scrambler 43 and the data of the second scrambler 44 is obtained by the exclusive OR calculator 46, and the exclusive OR of the calculation result and the 8-bit main data is obtained. The sum is obtained by the exclusive OR operator 47. Thus, only this frame has a different scrambling method from other frames.

The operation of the transcoder having such a configuration will be described with reference to the sequence chart shown in FIG.
First, the controller 15 is in an idle state (state 501), and when the data enable signal is asserted, sets the memory 11 to a write state (state 502) and starts storing main data of one sector. When the sector start signal is asserted, the controller 15 starts reading main data of one sector from the memory 11, supplies the main data to the scrambler switching unit 42, and transmits the seed selection signal and the seed load signal to the scrambler switching unit 42. Output to the blur switching unit 42 (state 503). The first and second scramblers 43 and 44 of the scrambler switching unit 42 set initial bit patterns of the respective pseudo-random number sequences and output respective data in response to the seed selection signal and the seed load signal. . At this time, since the frame signal is negated, each word of the main data is sequentially scrambled by the data output from the first scrambler 43, and each word of the scrambled main data is converted to the 8/16 converter 13. Are sequentially output. The 8/16 converter 13 sequentially modulates each word of the scrambled main data by the PPM to form 16-bit main data from the 8-bit main data for each word. Is modulated by PWM, main data for output is formed from the 16-bit main data, and the main data for output is output. The 8/16 converter 13 integrates and calculates the DSV for each word of the main data, and outputs the DSV to the comparator 14. The comparator 14 determines whether or not the amount of change in the DSV has exceeded a threshold value, and outputs the result of the determination to the controller 15.

  When the main data of one sector is read from the memory 11 and the scrambling and modulation of the main data are performed, the main data of the next one sector is input to the memory 11 and stored. Further, the frame signal is negated (state 504).

  When the main data of one sector is read from the memory 11, the reading is temporarily interrupted, and only writing of the main data of the next one sector to the memory 11 is continued (state 505), and this writing is completed. When the sector start signal is asserted, the process returns to the state 504, where the main data of this one sector is read, and scrambling and modulation of this main data are performed.

  In the state 504, if the main data of the next one sector is not input, only reading of the main data of the one sector from the memory 11 is continued (state 506), and the state of waiting for the main data of the next one sector is entered (state 506). 507) When the memory 11 becomes empty, it returns to the idle state (state 501).

  Therefore, the main data of each sector is sequentially stored in the memory 11, and accordingly, the main data of these sectors are sequentially read from the memory 11, and the main data of these sectors are sequentially scrambled, modulated, and output. .

  On the other hand, during the scrambling and modulation of the main data of one sector (steps 504 and 506), when the comparator 14 determines that the amount of change in the DSV exceeds the threshold value, that is, the DSV diverges. Then, when the low-frequency component of the main data output from the 8/16 converter 13 increases, the controller 15 identifies and stores the frame that caused the divergence of the DSV based on the notification from the sector counter 41. After that, the write address and the read address to the memory 11 are initialized, and a conversion failure signal is output (state 508). This conversion failure signal is output to the 8/16 converter 13, the drive control unit 26 and the error correction code modulation unit 22 of the recording / reproducing device (shown in FIG. 3).

  This conversion failure signal is input to the 8/16 converter 13 as a reset signal, and the 8/16 converter 13 is initialized. In addition, in response to the conversion failure signal, the recording / reproducing apparatus suspends recording for this sector and enters a state in which recording for this sector is restarted. Further, in response to the conversion failure signal, the preceding circuit (the error correction code modulator 22 of the recording / reproducing apparatus) restarts the main data supply from the sector.

  Then, the controller 15 waits for writing to the memory 11 to be disabled (state 509), returns to the state 502 via the state 501, and when the recording of the main data of one sector in which the DSV has diverged first starts again. The main data of this one sector is started to be read, and the main data is supplied to the first and second scramblers 43 and 44 of the scrambler switching unit 42, and the seed selection signal and the seed load signal are supplied to the first and second scramblers. 2 It outputs to the scramblers 43 and 44 (state 510). In this state 510, the controller 15 indicates the initial bit pattern of the different pseudo-random number sequence so that the main data of this one sector is scrambled by a pseudo-random number sequence different from the one that caused the divergence of the DSV. The seed selection signal is output to the first and second scramblers 43 and 44.

  Here, when the previous frame that caused the divergence of DSV is the first frame, the controller 15 asserts the frame signal only during this first frame period. In response to this, the scrambler switching unit 42 scrambles the frame with the respective data output from the first and second scramblers 43 and 44 and sends the scrambled frame to the 8/16 converter 13. Output (state 511). Subsequently, from the next frame, the frame signal is negated, the main data is scrambled only by the data output from the first scrambler 43 of the scrambler switching section 42, and each word of the scrambled main data is changed to 8 bits. The signals are sequentially output to the / 16 converter 13 (state 504).

  If the previous frame that caused the divergence of the DSV is not the first frame, the frame signal is kept negated, and the main signal is output only from the first scrambler 43 of the scrambler switching unit 42. The data is scrambled, and each word of the scrambled main data is sequentially output to the 8/16 converter 13 (state 504). On the way, when the frame that has caused the divergence of the previous DSV is reached, the frame signal is asserted only during this frame period, and in response to this, the scrambler switching unit 42 causes the first and second scramblers 43, The frame is scrambled by the respective data output from 44, and the scrambled frame is output to the 8/16 converter 13 (state 511). Subsequently, from the next frame, the frame signal is negated, and the main data is scrambled only by the data output from the first scrambler 43 of the scrambler switching unit 42 (state 504).

  In the state 504, the main data of the next one sector is not input, and only reading of the main data of the one sector from the memory 11 is continued (state 506). When the frame is reached, the frame signal is asserted only during this frame period, and in response to this, the scrambler switching unit 42 converts the frame by the respective data output from the first and second scramblers 43 and 44. It is scrambled (state 512). Then, from the next frame, the frame signal is negated, and the main data is scrambled only by the data output from the first scrambler 43 of the scrambler switching unit 42 (state 506).

  Similarly, while the main data of one sector is being scrambled and modulated (steps 504 and 506), as long as the DSV diverges, the states of the same sector are passed through the states 508, 509, 501, 502 and 510. Repeats scrambling and modulation of main data.

  In the second embodiment, when the divergence of the DSV is caused, the pseudo-random number sequence of the sector is changed, and the pseudo-random number sequence of the frame that causes the divergence of the DSV is also changed. Is repeated, but the scramble and modulation may be repeated by changing only the pseudo-random number sequence of the frame that caused the divergence of DSV.

  Further, similarly to the first embodiment, the number of each word in the first period L is G, all the converted data of the main data are M types, and the converted data of the main data which is likely to cause the divergence of the DSV is N types. Then, it is desirable that the number of each word that does not include a bit pattern that easily causes divergence of DSV be larger than the ratio of G × (M−N) / M as the changed second pseudo random number sequence.

  Further, assuming that the period of the main data of one sector is the second period H, it is desirable to set at least the same number of types as H / L = J and only the second pseudo random number sequences.

  Furthermore, instead of determining whether or not the amount of change in DSV has exceeded a threshold, it may be determined whether or not the absolute value of DSV has exceeded a predetermined threshold.

  FIG. 7 shows a third embodiment of the transcoder according to the present invention. The code conversion apparatus according to the third embodiment is obtained by adding an output control unit 48 for blocking or passing the output of the 8/16 converter 13 to the apparatus shown in FIG.

  Here, first, the controller 15 makes the output control unit 48 cut off the output of the 8/16 converter 13 by negating the output enable signal to the output control unit 48. In this state, when the data enable signal is asserted, the controller 15 sets the memory 11 to a write state, and inputs and stores one sector of main data into the memory 11. Subsequently, when the sector start signal is asserted, the controller 15 reads the main data of one sector from the memory 11 and supplies the main data to the scrambler 12, and also transmits the seed selection signal and the seed load signal to the scrambler 12. Output. In response, the scrambler 12 selects one of the initial bit patterns of each pseudo-random number sequence, generates a series of random numbers starting from the selected initial bit pattern, and generates a series of random numbers based on the series of random numbers. The data is scrambled, and the scrambled main data is output to the 8/16 converter 13. The 8/16 converter 13 modulates the scrambled main data by PPM to form 16-bit main data from the 8-bit main data, and further modulates the 16-bit main data by PWM. The main data for output is formed from the 16-bit main data, and the main data for output is output.

  This output main data is blocked by the output control unit 48 and is not transmitted to the recording unit 24 of the recording / reproducing apparatus.

  The 8/16 converter 13 integrates and calculates the DSV for each word of the main data, and outputs the DSV to the comparator 14. The comparator 14 determines whether or not the amount of change in the DSV has exceeded a threshold value, and outputs the result of the determination to the controller 15.

  If it is determined that the change amount of the DSV is equal to or smaller than the threshold value, the controller 15 asserts the output enable signal to the output control unit 48, thereby controlling the output of the 8/16 converter 13 to output control. Section 48. Further, the controller 15 reads again the main data of the same one sector as that of the previous one from the memory 11 and supplies this main data to the scrambler 12 and scrambles the same seed selection signal and seed load signal as those of the previous one. Output to blur 12. As a result, the same scrambled main data as the previous one is again supplied from the scrambler 12 to the 8/16 converter 13, which outputs the same main data for output as the previous one. Data is output.

  The main data for output passes through the output control unit 48 and is provided to the recording unit 24 of the recording / reproducing apparatus.

  When it is determined that the change amount of the DSV has exceeded the threshold value, the controller 15 keeps the output enable signal to the output control unit 48 negated and outputs the output of the 8/16 converter 13. It is shut off by the control unit 48. In this state, the controller 15 reads again the main data of the same one sector from the memory 11 from the memory 11 and supplies the main data to the scrambler 12 and changes the seed selection signal to change the seed selection signal. The signal is output to the scrambler 12 together with the seed load signal. In response, the scrambler 12 changes the initial bit pattern of the pseudo-random number sequence, generates a series of random numbers, scrambles the main data with the series of random numbers, and converts the scrambled main data into 8 / 16 to the converter 13. The 8/16 converter 13 modulates the scrambled main data and outputs main data for output. The main data for output is cut off by the output control unit 48 and is not transmitted to the recording unit 24 of the recording / reproducing apparatus.

  The 8/16 converter 13 integrates and calculates the DSV for each word of the main data, and outputs the DSV to the comparator 14. The comparator 14 determines whether or not the amount of change in the DSV has exceeded a threshold value, and outputs the result of the determination to the controller 15.

  If the change amount of the DSV exceeds the threshold value, the main data in the same sector as the previous one is read out again from the memory 11 while keeping the output enable signal to the output control unit 48 negated, and the pseudo random number is output. The sequence is changed, the main data is scrambled, and the main data is modulated to obtain a DSV. Until the DSV becomes equal to or less than the threshold, the pseudo random number sequence is repeatedly changed, scrambled, and modulated.

  As a result, when the change amount of the DSV becomes equal to or less than the threshold value, the output enable signal to the output control unit 48 is asserted, the main data in the same sector as the previous one is read out again from the memory 11, and this main data is set to 1 The main data is again scrambled by the same pseudo-random number sequence as in the previous process, the main data is modulated, and the main data for output is output via the output control unit 48.

  Therefore, as long as the amount of change in the DSV exceeds the threshold, the output control unit 48 keeps shutting off the output of the 8/16 converter 13 and repeats the change, scramble, and modulation of the pseudo-random number sequence. When the change amount of the DSV becomes equal to or less than the threshold value, the cutoff of the output of the 8/16 converter 13 by the output control unit 48 is released, and the pseudo-random number sequence is set to the same value as in the immediately preceding process. After that, scramble and modulation are performed to form again main data for output in which the amount of change in DSV is equal to or less than the threshold value, and the main data for output is output via the output control unit 48. In this case, only the main data whose change amount of the DSV is equal to or less than the threshold value is output in sector units. Therefore, in the recording / reproducing apparatus, the main data only needs to be written once to the recording area of the optical disk 28. There is no need to repeat writing to the same recording area.

  Also in the third embodiment, as the second pseudo-random number sequence, the number of each word that does not include a bit pattern that tends to cause DSV divergence is larger than the ratio of G × (M−N) / M. desirable.

  It is preferable to set at least the same number of types as H / L = J and only the second pseudo random number sequences.

  Further, instead of determining whether or not the amount of change in DSV has exceeded a threshold value, it may be determined whether or not the absolute value of DSV has exceeded a threshold value.

  Next, an optical disc which is an embodiment of the code recording medium of the present invention will be described with reference to FIGS.

  FIG. 8 shows a configuration of a data unit of the optical disc of this embodiment. FIG. 9 shows a sector format of this optical disc. FIG. 10 shows a sync frame format of the optical disc. The sync frame format includes the data unit of FIG. 9, and the sync frame format is included in the sector format of FIG. FIG. 11 schematically shows an optical disc on which the sector format shown in FIG. 9 is recorded.

  In an optical disc, main data such as video data, audio data, and data for a computer are divided into sectors and recorded and reproduced. As shown in FIG. 11, the sector on the optical disk is composed of a HEADER section, a MIRROR section 91, and a RECORDING section 92, and these sectors are recorded alternately.

  As shown in FIG. 9, one sector includes a HEADER section, a MIRROR section, and a RECORDING section, and has a total of 2697 bytes. The HEADER section and the MIRROR section are defined on the optical disc. The RECORDING section actually records and reproduces data. The RECORDING section includes a GAP section, a GUARD section, a VFO section, a PS section, a DATA section, a PA section, and a BUFFER section, and occupies 2567 bytes. The DATA part of these is 2418 bytes, which corresponds to the sync frame mat of FIG. 10, and is composed of 26 sync frames (93 bytes).

  As shown in FIG. 8, the data unit is a total of 2064 bytes (172 bytes × 12), a 4-byte DATAID section, a 2-byte IED section, a 6-byte SCL section, a 2048-byte MAINDATA section, and a 4-byte Of the EDC unit. The DATAID portion records a tracking type, that is, data indicating a groove track or a land track, data indicating a read area or a lead-out area, a sector address, or the like. In the IED section, a code for detecting an error in the DATAID section is recorded, in the SCL section, scramble data is recorded, and in the EDC section, an error of another part of 2060 bytes excluding the EDC section is detected. The code to perform is recorded.

  The scramble data of the SCL section and the sector address of the DATAID section indicate one of predetermined initial bit patterns of a plurality of pseudo-random number sequences. By performing a logical operation (for example, exclusive OR) on the main data to be recorded in the main data, a scramble process is performed on the main data.

  The scrambled main data is used as a MAINDATA part, and the data unit shown in FIG. 8 is obtained by adding scrambled data and the like. When an error correction code is added to this data unit, the data unit becomes 2366 bytes. After digital modulation, the data unit is inserted into a 2-byte synchronization signal (sync code) every 91 bytes to obtain 26 sync frames shown in FIG. Is composed. Each of the synchronization signals SY0, SY1,..., SY7 is composed of a combination of “0” and “1” and has a respective pattern.

  As a result, the total length is 2,418 bytes, which corresponds to the DATA section in the sector format of FIG.

  In this embodiment, a pseudo-random number sequence is selected based on not only scramble data but also sector addresses. This is because, if the sector address is ignored, there is a possibility that each signal having strong correlation scrambled by the same random number sequence is recorded on each adjacent track of the optical disk 28, and in this case, tracking or the like becomes unstable. For this purpose, different pseudo-random number sequences are selected for adjacent tracks in consideration of the sector address.

  In the scramble data of the SCL unit, for example, normally all 6 bits are set to “0”, and when the low frequency component of the recorded signal abnormally increases (when DSV diverges), one of the 6 bits is set to “0”. It is set to a value other than "0". When all six bits of the scrambled data are set to "0", scrambling is not performed. When any of the six bits is set to a value other than "0", scrambling is performed.

  Further, as the scramble data, at the time of data rewriting, data corresponding to the number of times of rewriting, data obtained based on random numbers, data obtained by combining them, or the like may be set.

  FIG. 12 shows a first embodiment of the code recording apparatus of the present invention. In this code recording device, main data is recorded on the optical disk shown in FIG.

  Main data such as digitized audio data, video data, and computer data are input through the input IF 51. This main data is provided to the logical operation unit 50. The logical operation unit 50 inputs a random number together with the main data from the pseudo-random number generator 52 and performs a logical operation (for example, exclusive OR) on the random number and the main data, thereby performing a scrambling process on the main data. Is applied.

The pseudo random number generator 52 generates a pseudo random number sequence based on a primitive polynomial. The primitive polynomial includes, for example, 15th-order X ¹⁵ + X ⁴ +1 (shown in the above equation (1)) or 31st-order X ³¹ + X ³ +1 in the maximum periodic sequence. For example, when generating a pseudo-random number sequence based on the 15th-order X ¹⁵ + X ⁴ +1, the pseudo-random number generator 52 includes 15 registers RE and one exclusive OR circuit EX as shown in FIG. , R0 are set in each register RE, the bits of these registers RE are sequentially shifted as indicated by arrows, and the values of these register RE bits are sequentially changed. To generate a series of random numbers starting from the initial bit pattern.

  Therefore, the pseudo-random number generator 52 must be provided with an initial bit pattern. The initial value data generator 53 stores an initial bit pattern of a plurality of pseudo-random number sequences, and receives an instruction from the system controller 54 each time main data of each sector is input, and receives an initial bit of each pseudo-random number sequence. One of the patterns is selected and given to the pseudo random number generator 52.

  Conventionally, a data table in which 16 kinds of values (bit strings) and 16 kinds of initial bit patterns (initial values) of 16 kinds of pseudo-random number sequences as shown in FIG. 14 are previously stored in the initial value data generator 53 in advance. The address indicating the sector (storage area) of the optical disk is given from the system controller 54 to the initial value data generator 53. In response, the initial value data generator 53 extracts specific four bits from the address of the sector, selects an initial bit pattern corresponding to the value of the four bits from the data table, and simulates the initial bit pattern. It was given to the random number generator 52.

  However, when data is recorded in the same sector (storage area) of the optical disk, the same initial bit pattern of the same pseudo-random number sequence is always selected. In this case, if the same main data is repeatedly written in the same sector, the characteristics of the recording medium in this sector become non-uniform, and the S / N of the reproduced signal decreases.

  Therefore, in the embodiment of the present invention, the initial bit pattern of the pseudo random number sequence is selected in consideration of not only the address of the sector but also other data. As the other data, for example, the number of times of rewriting for the same sector can be applied. In this case, instead of the data table shown in FIG. 14, for each rewrite number, as shown in FIG. 15, the initial bit pattern (initial value) of each of the 16 types of pseudo-random numbers corresponding to the 16 types of values (bit strings) ) Is stored in the initial value data generator 53 in advance, the number of rewrites is selected from this data table, and a pseudo-code corresponding to the address of the sector is referred to by referring to the column of the selected number of rewrites. What is necessary is just to select the initial bit pattern of a random number series.

  Alternatively, a random number may be generated by a random number generator instead of the number of rewrites, and one of the data tables may be selected according to the random number. Furthermore, if the number of rewrites and the rewrite date and time are given to the random number generator as the initial value of the random number generated by the random number generator, the random number can be combined with the number of rewrites and the rewrite time.

  The number of times of rewriting and the rewriting time are obtained by the system controller 54 and given to the initial value data generator 53.

  The main data scrambled in this way is input to the first multiplexer 56 as the MAINDATA section in FIG. Further, the first additional signal generator 55 receives the initial bit pattern of the pseudo-random number sequence as scrambled data from the initial value data generator 53, and also receives a sector address, a code for detecting an error, and the like from the system controller 54, These are given to the first multiplexer 56 as a DATAID section, an IED section, an SCL section, and an EDC section in FIG. The first multiplexer 56 receives and arranges the respective units, and forms and outputs the data unit of FIG. The data unit is input to an error correction code generator 57, where an error correction code is calculated, and the error correction code is added to the data unit.

  Upon receiving the data unit and the error correction code, the digital modulator (for example, 8/16 modulation) 58 digitally modulates the data unit and the error correction code and outputs the result to the second multiplexer 61. On the other hand, the second additional signal generator 59 receives necessary data from the system controller 54 and forms synchronization signals (sync codes) and the like in the VFO, PS, PA, and DATA sections in FIG. Output to the second multiplexer 5a. The second multiplexer 61 receives and arranges each unit, and forms and outputs data of one sector in FIG.

  The data of one sector is input to the semiconductor laser modulator 62, where it is modulated, and the modulation output of the semiconductor laser modulator 62 is applied to the optical head 63. Laser light emitted from the laser is controlled. The laser light is applied to the optical disk 64, and data of one sector is recorded on the optical disk 64.

FIG. 16 shows a second embodiment of the code recording apparatus of the present invention. In this code recording apparatus, a DSV calculator 70 is added to the apparatus shown in FIG.
Note that, in FIG. 16, the same reference numerals are given to portions that perform the same operations as in FIG.

  In this device, main data is input through an input IF 51, and a logical operation unit 50 scrambles the main data with a random number from a pseudo-random number generator 52, and uses the scrambled main data as a MAINDATA part in FIG. The signal is output to the 1 multiplexer 56. Further, the first additional signal generator 55 gives the DATAID unit, the IED unit, the SCL unit, and the EDC unit in FIG. The first multiplexer 56 receives and arranges the respective units, and forms and outputs the data unit of FIG. The data unit is input to an error correction code generator 57, where an error correction code is calculated, and the error correction code is added to the data unit. Upon input of the data unit and the error correction code, the digital modulator (for example, 8/16 modulation) 58 digitally modulates the data unit and the error correction code and outputs the result.

  The operation so far is the same as that of the apparatus of FIG. 12, and sets the initial bit pattern of the pseudo-random number sequence used for scrambling based on not only the address of the sector but also the number of times of rewriting, the rewriting time, or a random number.

  Next, the DSV calculator 70 calculates the DSV of the data output from the digital modulator 58, and notifies the system controller 54 of the DSV. The system controller 54 determines, for example, whether the absolute value of DSV is larger than a predetermined threshold.

  On the other hand, the second additional signal generator 59 supplies the second multiplexer 61 with the synchronization signals in the VFO unit, PS unit, PA unit and DATA unit in FIG. The second multiplexer 61 receives and arranges each unit, and forms and outputs data of one sector in FIG.

  The data of one sector is input to the semiconductor laser modulator 62. The semiconductor laser modulator 62 modulates one sector of data and applies a modulation output to the optical head 63. The laser beam emitted from the semiconductor laser in the optical head 63 is controlled by the modulation output, and one sector of data is recorded on the optical disc 64.

  Here, when the absolute value of the DSV is larger than the threshold, if the data output from the digital modulator 58 is recorded as it is on the optical disk, inconvenience may occur when the data is reproduced from the optical disk. There is. Therefore, the system controller 54 instructs the semiconductor laser modulator 62 to start recording again in the same sector.

  At the same time, the system controller 54 instructs the initial value data generator 53 to change the initial bit pattern of the pseudo-random number sequence, and instructs the pseudo-random number generator 52 to re-scramble. Further, the system controller 54 performs processing on the input IF 51, the error correction code generator 57, the digital modulator 58, the rotation driving device (not shown) of the optical disk 64, the moving device of the optical head 63 (not shown), and the like. Instruct redo.

As a result, the main data in the same sector is scrambled and modulated again, and the DSV of the data output from the digital modulator 58 is obtained again. Then, the scramble, modulation and recording of the main data in the same sector are repeated until the DSV becomes equal to or less than the threshold value. Move on to sector processing.
The main data of the same sector may be repeatedly supplied from the circuit at the preceding stage, and the processing of the main data of the same sector may be repeated. Alternatively, the main data of the same sector may be temporarily stored in the input IF 51 and the same sector may be stored. May be repeatedly supplied from the input IF 51 to repeat the processing.

  Instead of repeating the recording of the main data in the same sector, the data output from the digital modulator 58 is temporarily stored in a buffer, and when the DSV exceeds the threshold, the data in this buffer is transmitted to the semiconductor laser modulator 62. If the DSV is less than or equal to the threshold value, the data in this buffer may be truncated.

  Further, in the devices shown in FIGS. 12 and 16, a semiconductor laser is illustrated, but a gas laser may be applied.

  FIG. 17 shows an embodiment of the code reproducing apparatus according to the present invention. In this code reproducing apparatus, the main data recorded on the optical disk shown in FIG. 11 is reproduced by the code recording apparatus shown in FIGS.

  In FIG. 17, when an optical disk 71 is irradiated with light (laser light), the light is modulated and reflected by the optical disk 71 and is incident on the light receiving element of the optical head 72 as an optical signal having a change in intensity. The light receiving element of the optical head 72 photoelectrically converts the optical signal having the intensity change, and outputs an electric signal indicating the intensity change of the optical signal to the head amplifier 73. The head amplifier 73 amplifies the weak electric signal and outputs it to the binarizer 74. The binarizer 74 converts the output of the head amplifier 73 into a digital signal indicating “0” and “1”, and outputs the digital signal to the reproduction signal processor 75. The reproduction signal processor 75 removes a synchronization signal in the HEADER section, MIRROR section, GAP section, GUARD section, VFO section, PS section, PA section, BUFFER section, DATA section from the digital signal (shown in FIG. 9), The data thus obtained is output to the digital demodulator 76. Upon receiving the data, the digital demodulator 76 digitally demodulates the data and outputs the demodulated data to the error corrector 77.

  The error corrector 77 corrects an error of the data based on the error correction code included in the data, and outputs the corrected data to the error detector 79. If the error of the data cannot be corrected, the data is not output to the error detector 79, and the error corrector 77 notifies the system controller 80 of the fact. In response to this, the system controller 80 instructs the rotation driving device (not shown) of the optical disk 71, the moving device (not shown) of the optical head 72, and the like to perform the processing again. As a result, reading from the same sector of the optical disk 71 is performed again, and the data of this sector is again input to the error corrector 77, and the error of this data is corrected.

  When the corrected data (shown in FIG. 8) is input, the error detector 79 detects an error in the data based on the IED unit and the EDC unit included in the data. As a result, although the probability is low, an error in the error correction by the error corrector 77 is detected. When this error is detected, the fact is notified from the error detector 79 to the system controller 80. In response to this, the system controller 80 instructs re-processing in the same manner as described above. As a result, reading from the same sector of the optical disk 71 is performed again, and the data of this sector is again input to the error detector 79, and error detection of error correction is performed.

  If the error detector 79 cannot detect an error in the data, it outputs this data to the data distributor 81. The data distributor 81 separates the data into a DATAID section, an IED section, an SCL section, a MAINDATA section, and an EDC section, outputs the SCL section to the initial value data generator 82, and outputs the main data of the MAINDATA section to a logical operation unit. 83.

  The initial value data generator 82 stores the same data table as the initial value data generator 53 of FIG. 12, and when the SCL unit from the data distributor 81 is input, the same as the initial value data generator 53 of FIG. The initial bit pattern of the pseudo-random number sequence indicated by the scramble data of the SCL unit is selected, and the initial bit pattern of the pseudo-random number sequence is output to the pseudo random number generator 84. When the pseudo-random number generator 84 receives the initial bit pattern of the pseudo-random number sequence, the same random number generated by the pseudo-random number generator 52 when the main data of the MAINDATA section is scrambled by the code recording apparatus of FIG. And outputs it to the logical operation unit 83.

  The logical operation unit 83 performs a logical operation on the main data from the data distributor 81 and the random number from the pseudo-random number generator 84, descrambles the main data, and outputs the descrambled main data through the output I / F 85. Output as playback data to outside.

  The main data scrambled at the time of recording is descrambled at the time of reproduction and returned.

FIG. 1 is a block diagram showing a first embodiment of a transcoder according to the present invention. Sequence chart showing an operation procedure of the code conversion device of FIG. FIG. 2 is a block diagram showing a recording / reproducing apparatus to which the code conversion apparatus of FIG. 1 is applied. FIG. 2 is a block diagram showing a second embodiment of the transcoder according to the present invention. FIG. 4 is a block diagram showing a scrambler switching unit of the transcoder of FIG. 4 is a sequence chart showing an operation procedure of the code conversion device in FIG. FIG. 3 is a block diagram showing a third embodiment of the transcoder according to the present invention. FIG. 1 is a diagram showing a configuration of a data unit of an optical disc which is an embodiment of a code recording medium of the present invention. FIG. 3 is a diagram showing a sector format of the optical disc of the embodiment. FIG. 3 is a diagram showing a sync frame format of the optical disc of the embodiment. FIG. 1 is a diagram schematically showing an optical disk of this embodiment. FIG. 1 is a block diagram showing a first embodiment of a code recording apparatus according to the present invention. FIG. 12 is a block diagram schematically showing a pseudo random number generator in the code recording device of FIG. The figure which shows an example of the data table of the initial value data generator in the code | cord recording apparatus of FIG. The figure which shows the other example of the data table of the initial value data generator in the code | cord recording apparatus of FIG. Block diagram showing a second embodiment of the code recording device of the present invention. 1 is a block diagram showing an embodiment of a code reproducing apparatus according to the present invention. Block diagram showing a conventional transcoder FIG. 18 is a block diagram showing a scrambler in the transcoder shown in FIG. FIG. 18 is a block diagram showing an 8/16 converter in the code converter of FIG. (A) is a diagram showing main data of 16 bits, and (b) is a diagram showing main data for output obtained by modulating (a) by PWM. Flowchart showing processing of a conventional transcoder Flowchart showing another process of a conventional transcoder (A) is a graph showing a change in the value of main data in the conventional transcoder, and (b) is a graph showing an increase or decrease in DSV according to the change in (a).

Explanation of reference numerals

Reference Signs List 11 memory 12 scrambler 13 8/16 converter 14 comparator 15 controller 21 external communication unit 22 error correction code modulation unit 23 modulation unit 24 recording unit 25 optical head 26 drive control unit 27 head control unit 28 optical disk 29 motor 31 reproduction unit 32 Demodulation unit 33 Error correction code demodulation unit 41 Sector counter 42 Scrambler switching unit 48 Output control unit 50 Logical operation unit 51 Input IF
52 Pseudo random number generator 53 Initial value data generator 54 System controller 55 First additional signal generator 56 First multiplexer 57 Error correction code generator 58 Digital modulator 59 Second additional signal generator 61 Second multiplexer 62 semiconductor laser modulator 63 optical head 64 optical disk 70 DSV calculator 71 optical disk 72 optical head 73 head amplifier 74 binarizer 75 reproduction signal processor 76 digital demodulator 77 error corrector 79 error detector 80 system controller 81 data distribution Unit 82 initial value data generator 83 logical operation unit 84 pseudo-random number generator 85 output I / F

Claims (13)

Scrambling the main data based on one of a plurality of types of pseudo-random numbers;
Modulating the scrambled main data based on any of the plurality of types of modulation data;
Generating main data for output from the modulated main data;
Obtaining an operation value representing a difference between the number of 0 bits and the number of 1 bits included in the main data for output;
Determining whether the amount of change in the calculated value is within a predetermined allowable range,
When it is determined that the amount of change in the operation value is not within the predetermined allowable range, the pseudo random number sequence used in the step of scrambling the main data is selected from the plurality of types of pseudo random number sequences. A new selecting step;
Re-scrambling the main data based on the newly selected pseudo-random number sequence;
A step of newly selecting modulation data used in the step of modulating the scrambled main data from the plurality of types of modulation data in accordance with the operation value;
Re-modulating the re-scrambled main data based on the newly selected modulation data. Modulating the scrambled main data is performed by a first modulation having M types of modulation data;
Generating the main data for output is performed by a second modulation;
The code conversion method according to claim 1, wherein N types of modulated data among the M types of modulated data cause the increase of the operation value. The first modulation is a pit position modulation having M types of modulation data,
The code conversion method according to claim 2, wherein the second modulation is pulse width modulation. When the change amount of the operation value becomes equal to or larger than the threshold value K during the first period L, the main data for output having the bit pattern causing the increase of the operation value is output during the first period L. Are included in multiple key data to be
When the pseudo-random number sequence applied to the main data that has caused the increase in the operation value is a first pseudo-random number sequence, the first pseudo-random number sequence is a plurality of predetermined second pseudo-random number sequences. Changed to one of
The plurality of second pseudo-random number sequences are main data to be generated in the re-scrambling step, and are main data to be output in the first period at a rate of (M−N) / M or more. The code conversion method according to claim 2, wherein the code conversion method is a pseudo-random number sequence that enables acquisition of a plurality of pieces of main data having no bit pattern.   In the scrambling step, when a period in which a series of main data for output is generated using the first pseudo-random number sequence is a second period H, the number of the second pseudo-random number sequences is at least H 5. The method of claim 4, wherein / L = J.   When the amount of change in the calculated value exceeds the threshold value, a part of the main data having a predetermined length, which is a part of the main data input before that time, is included in the part. The code conversion method according to claim 1, wherein scrambling is performed again after another pseudo-random number sequence is newly selected. Obtaining an operation value of main data for output corresponding to the input main data having a predetermined length;
When the change amount of the operation value exceeds the threshold value, a step of newly selecting another pseudo-random number sequence, and re-scrambling the input main data,
The code conversion method according to claim 1, further comprising: obtaining a pseudo-random number sequence that makes the amount of change in the operation value equal to or smaller than the threshold value.   The code conversion method according to claim 1, wherein an absolute value of the operation value is used as the amount of change of the operation value. Storage means for storing main data;
A scrambling unit for scrambling the main data stored in the storage unit, based on one of a plurality of types of pseudo-random sequences;
Modulating means for modulating the scrambled main data based on one of a plurality of types of modulation data and generating main data for output from the modulated main data,
Calculating means for calculating a calculation value representing a difference between the number of 0 bits and the number of 1 bits included in the main data for output generated by the modulation means;
Comparing means for determining whether the amount of change in the calculated value obtained by the calculating means is within a predetermined allowable range,
Control means for controlling at least the scrambling means and the modulation means,
The control means is used when scrambling the main data stored in the storage means when the comparison means determines that the amount of change in the operation value is not within the predetermined allowable range. A new pseudo-random number sequence is selected from the plurality of types of pseudo-random number sequences, and the scramble unit is instructed to re-scramble the main data based on the newly selected pseudo-random number sequence,
The control means newly selects modulation data to be used when modulating the scrambled main data according to the operation value from among the plurality of types of modulation data, and further comprises the newly selected modulation data. A code conversion device for instructing the modulation means to re-modulate the main data re-scrambled based on the data. Recording means for recording output data of the modulation means,
The control means outputs a conversion failure signal when the comparison means determines that the amount of change in the operation value is not within the predetermined allowable range,
10. The transcoder according to claim 9, wherein said recording means re-records output data of said modulating means in response to said conversion failure signal. Further comprising a detecting means for detecting the position of the main data read from the storage means,
The control unit is configured to determine that the amount of change in the calculated value is not within the predetermined allowable range, and that the main unit positioned before the position of the main data detected by the detection unit when the comparison unit determines that the change amount is not within the predetermined allowable range. 10. The transcoder according to claim 9, wherein the scrambler is instructed to scramble the data portion again. The detection unit detects the position of each frame of the main data stored in the storage unit each time the frame is read from the storage unit,
The control means may include at least one of the frames located before the position of the frame detected by the detection means when the comparison means determines that the amount of change in the operation value is not within the predetermined allowable range. 12. The transcoder according to claim 11, wherein the scramble unit is instructed to scramble one frame again.   The transcoder according to claim 9, wherein the scrambling means scrambles the main data in sector units and re-scrambles the main data in sector units.

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