JP2004355644A - Layout compaction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the degree of integration by performing layout compaction with an optical proximity effect taken into consideration, even for layout patterns of irregular arrangements included in circuit design data. <P>SOLUTION: A compaction condition is generated in a compaction control step 2, an OPC condition is generated in an OPC condition generation step 8, compaction of an input layout pattern is performed in a layout compaction step 3, optical proximity effect correction is performed in an optical proximity effect correction step 4, the layout pattern after the optical proximity effect correction is held in a corrected layout pattern preservation step 5, circuit operation is confirmed with the layout pattern subjected to compaction and optical proximity effect correction in verification steps 6 and 10, the layout pattern is held in an error data preservation step 7 when having trouble, and a compaction condition with the optical proximity effect and error data taken into consideration is generated again in the compaction control step 2, and these steps are repeated. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a layout compaction method for improving the degree of integration of a semiconductor integrated circuit. This method also includes a method of correcting a mask pattern in which a semiconductor mask pattern used in manufacturing a semiconductor integrated circuit is deformed in advance so as to obtain a transfer image close to a desired design pattern.

  In recent years, the circuit scale has increased due to the diversification of functions of the semiconductor integrated circuit, and the area of the semiconductor integrated circuit has also increased in proportion to the circuit scale. 2. Description of the Related Art In recent years, it has been rapidly progressing to suppress an increase in area in order to reduce the production unit price and to miniaturize the manufacturing process in order to realize high-speed operation. For that purpose, considering the required circuit scale and circuit area, it is essential to improve the degree of integration at the design stage and realize a fine pattern near the limit of the manufacturing capability. Further, when an integrated circuit is manufactured near the limit of the manufacturing capability, an optical proximity effect (Optical Proximity Effect) becomes prominent.

  A layout pattern typified by a static random access memory (SRAM) or a dynamic random access memory (DRAM) that can be realized by repeating the same pattern on a layout pattern or by a two-dimensional arrangement of a single pattern In order to reduce the area, a layout considering the optical proximity effect is indispensable. In a layout in which the same pattern is repeatedly arranged vertically and horizontally, such as an SRAM or a DRAM, the layout considering the optical proximity effect is relatively easy. Can be designed.

  In this case, the layout pattern is not always designed based on the process standard, and there are many cases where the layout pattern is designed with a smaller dimension than the normal process standard.

  On the other hand, the layout pattern of a circuit that performs a logical operation is designed with a different layout pattern according to each function, and the layout pattern arranged around may be different depending on the function to be realized, and the number of combinations is enormous. It becomes a number. Therefore, in general, in a layout in which the influence of the optical proximity effect is considered, optical proximity correction (Optical Proximity Correction, hereinafter abbreviated as OPC) is performed by computer-aided design (CAD). One example of the optical proximity effect correction is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-80486.

  Layout compaction is also performed by computer-aided design (CAD). FIG. 18 shows a conventional flow for compressing layout data of an existing semiconductor integrated circuit and converting it into a mask pattern.

  First, the layout data file 11 is subjected to layout data compaction processing in a compaction step 12, and the layout data after compaction is stored in a layout data file 13. The compaction processing is to reduce the interval between polygonal figures included in the layout data, and in some cases also to reduce the width of the pattern, and to reduce the area of the semiconductor integrated circuit.

  In the verification step 14, it is verified whether the layout data included in the layout data file 13 is data according to the process standard, and whether or not the layout data has the same connection relationship as the layout data included in the layout data file 11, Perform a transistor operation simulation to confirm that the circuit operates normally.

If the simulation result is not a correct result, the layout data included in the layout data file 11 is corrected, or the compaction process performed in the compaction step 12 is changed and the compaction process is performed again. If the simulation result is good, the layout data file 13 is transferred to the optical proximity effect correction step 15, where OPC processing suitable for the manufacture of a semiconductor integrated circuit is performed, and mask layout data is created. 16 are stored. The compaction criteria in this case are limited to the process criteria.
JP-A-5-80486

  However, in large-scale semiconductor integrated circuits, not only repetition of the same pattern as in SRAM and DRAM exists, but also random logic circuits become large-scale. It is impossible as a practical problem to perform a layout in consideration of the optical proximity effect.

  Performing the layout in consideration of the optical proximity effect means that the layout needs to be modified when the manufacturing conditions of the semiconductor integrated circuit are changed, resulting in a layout design with low production efficiency.

  Therefore, an object of the present invention is to improve the degree of integration of a semiconductor integrated circuit device by performing layout compaction in consideration of the optical proximity effect even on an irregularly arranged layout pattern included in design data of a semiconductor integrated circuit. It is to provide a layout compaction method that can be performed.

  Another object of the present invention is to provide a layout compaction method capable of generating compaction conditions for performing a layout compaction process optimized for manufacturing conditions of a semiconductor integrated circuit device.

  Still another object of the present invention is to compare the result of layout compaction with the data before compaction, so that a difference occurs in electrical characteristics and whether a malfunction occurs in the operation of the semiconductor integrated circuit. Is to provide a layout compaction method capable of confirming the following.

  The layout compaction method according to claim 1 of the present invention comprises a layout input means, a compaction control means, an optical proximity effect correction condition generating means, a layout compression means, a first verification means for verifying data after compaction, and an optical proximity method. A method of compacting a semiconductor layout by taking into account the optical proximity effect by a programmed computer comprising an effect correction unit, a second verification unit for verifying layout data after the optical proximity correction, and an error storage unit. A compaction control step in which the control means generates a compaction condition suitable for the input layout pattern; and an optical proximity effect in which the optical proximity effect correction condition generating means generates an optical proximity effect correction condition in consideration of the compaction condition generated in the compaction control step. Correction conditions A layout compression step in which the layout compression means compacts the input layout pattern according to the compaction conditions to generate a compacted layout pattern, and the first verification means receives the input layout pattern and the compacted layout pattern as data, and A first verification step of comparing the pattern and the compacted layout pattern to confirm that the compacted layout pattern operates correctly and outputting first error data when a failure occurs, and an optical proximity effect correction Means for performing an optical proximity effect correction on the compacted layout pattern according to the optical proximity effect correction condition to generate an optical proximity effect corrected layout pattern. A correcting step, wherein the second verification means receives the compacted layout pattern and the optical proximity effect corrected layout pattern as data, obtains a finished pattern formed on the wafer by the optical proximity effect corrected layout pattern, and obtains the compacted layout pattern. A second verification step of confirming that the layout pattern corrected for the optical proximity effect is properly formed by comparing the finished pattern and outputting a second error data when a failure occurs; and storing the error. Means for storing the first error data and the second error data and controlling generation of a compaction condition.

  According to this method, compaction of the layout pattern can be performed under the condition in which the influence of the optical proximity effect is also taken into consideration, and the area can be made smaller than the compaction condition limited by the process standard. Furthermore, since the compaction is performed while comparing and verifying the electrical characteristics of the initial input layout pattern and the compacted layout pattern by using simulation, a large difference occurs between the electrical characteristics of the initial layout pattern and the electrical characteristics after the layout compaction. As a result, a circuit configuration exhibiting desired electrical characteristics can be realized with a layout pattern having a smaller area. Further, the finished pattern formed on the wafer by the optical proximity effect corrected layout pattern is obtained by simulation, and the optical proximity corrected layout pattern is appropriately formed by comparing the compacted layout pattern and the finished pattern. Since the compaction is performed while confirming that the compaction is performed, compaction conditions for performing the layout compaction process optimized for the manufacturing conditions of the semiconductor integrated circuit device can be generated. It is also possible to confirm whether the layout pattern corrected for the optical proximity effect is properly formed.

  A layout compaction method according to a second aspect of the present invention is the layout compaction method according to the first aspect, wherein the compaction control step includes a minimum layout condition extracting step of extracting a minimum layout condition that can be manufactured based on the optical proximity effect information. , A basic pattern extraction step for decomposing an input layout pattern into a plurality of basic patterns, and a compaction for generating a compaction condition from the minimum layout conditions extracted by the minimum layout condition extraction step and the multiple basic patterns extracted by the basic pattern extraction step And a condition extracting step.

  According to this method, the minimum layout condition is extracted from the optical proximity effect information, the minimum dimension of a manufacturable layout pattern is calculated from the minimum layout condition, and the lower limit value of the compaction is set to take the optical proximity effect into consideration. Compaction conditions can be generated. Further, by decomposing the layout pattern for compaction into a plurality of basic patterns, compaction conditions can be individually set for each basic pattern, and highly effective compaction can be realized.

  A layout compaction method according to a third aspect of the present invention is the layout compaction method according to the first aspect, wherein the first verification step includes a pattern comparison step of extracting a difference pattern between the input layout pattern and the compacted layout pattern. A delay conversion step of calculating a capacitor capacity from the difference pattern extracted in the pattern comparison step and converting the capacitor capacity into a delay value, and a delay for confirming an operation failure due to a delay variation based on the delay value calculated in the delay conversion step. And a verification step.

  According to this method, it is not necessary to extract the parasitic capacitance from the compacted layout pattern and simulate the circuit to confirm the operation of the circuit. The parasitic capacitance is calculated from the differential pattern, converted into a delay value, and the circuit operation due to the delay is reduced. High-speed circuit operation verification can be performed by comparing with a delay value boundary condition indicating a limit value that has no influence.

  A layout compaction method according to a fourth aspect of the present invention is the layout compaction method according to the first aspect, wherein the compaction control step includes a capacitance conversion step of converting an allowable delay time variation value in the input layout pattern into a capacitor capacitance variation allowable value. And a compaction condition extracting step of generating a compaction condition from the layout variation allowable pattern obtained by the pattern conversion step.

  According to this method, by focusing on the variation of the delay time in the electric circuit, the variation range of the delay time in which the operation of the electrical circuit is guaranteed is converted into the capacitance of the capacitor, and the variation width of the capacitor capacitance is converted into the difference in the layout pattern. By converting to a pattern, the amount of pattern variation due to compaction can be determined, and compaction conditions can be set accordingly, so that highly efficient compaction can be realized.

  A layout compaction method according to a fifth aspect of the present invention is the layout compaction method according to the first aspect, wherein the compaction control step includes a minimum layout condition extracting step of extracting a minimum layout condition that can be manufactured based on the optical proximity effect information. A first compaction condition candidate from a basic pattern extraction step of decomposing an input layout pattern into a plurality of basic patterns, and a plurality of basic patterns extracted by the minimum layout condition extraction step and the basic pattern extraction step. A first compaction condition extracting step of generating a delay time variation allowable value in an input layout pattern into a capacitor capacitance variation allowable value, and a capacitor capacitance variation allowable value of a layout variation allowable value. A pattern conversion step for converting into a turn, a second compaction condition extraction step for generating a second compaction condition candidate from the layout variation allowable pattern obtained in the pattern conversion step, and a first compaction condition extraction step A compaction condition selecting step of selecting a looser one as a compaction condition from the first compaction condition candidates and the second compaction condition candidates obtained from the second compaction condition extracting step.

  According to this method, by selecting a looser one of the first and second compaction condition candidates as the compaction condition, it is possible to set a condition that can be manufactured and guarantees a normal operation of the electric circuit. Steps can be omitted, and the processing time of the entire layout compaction can be reduced.

  In a layout compaction method according to a sixth aspect of the present invention, in the layout compaction method according to the first aspect, the compaction control step outputs the compaction condition as data pairing a width of the layout pattern and an interval between adjacent layout patterns. It is characterized by the following.

  According to this method, the same operation as the layout compaction method according to the first aspect is obtained.

  A layout compaction method according to a seventh aspect of the present invention is the layout compaction method according to the first aspect, wherein the compaction conditions are changed according to a result of the first and second verification steps.

  According to this method, the same operation as the layout compaction method according to the first aspect is obtained.

A computer-readable recording medium according to claim 8 of the present invention is a computer-readable recording medium for generating a layout of a semiconductor integrated circuit.
Means for inputting the designed layout;
Compaction control means for generating compaction conditions suitable for the input layout pattern;
An optical proximity correction condition generation unit configured to generate an optical proximity correction condition in consideration of the compaction condition generated by the compaction control unit;
Layout compression means for compacting an input layout pattern according to compaction conditions and generating a compacted layout pattern;
The input layout pattern and the compacted layout pattern are received as data, and the input layout pattern and the compacted layout pattern are compared to confirm that the compacted layout pattern operates correctly. If a failure occurs, a first error occurs. First verification means for outputting data,
Optical proximity correction means for performing optical proximity correction on the compacted layout pattern in accordance with the optical proximity correction condition to generate an optical proximity corrected layout pattern;
Receives the compacted layout pattern and the optical proximity corrected layout pattern as data, obtains the finished pattern formed on the wafer by the optical proximity corrected layout pattern, and compares the compacted layout pattern and the finished pattern to achieve optical proximity. Second verification means for confirming that the effect-corrected layout pattern is properly formed and outputting second error data when a problem occurs;
A layout design program for storing the first error data and the second error data and functioning as an error storage unit for controlling generation of a compaction condition is recorded.

  According to this configuration, the same operation as the layout compaction method according to the first aspect is provided.

  Since the present invention is configured as described above, it has the following effects.

  According to the layout compaction method of the first aspect of the present invention, compaction of a layout pattern can be performed under a condition in which the influence of the optical proximity effect is also taken into consideration, and the area can be made smaller than the compaction condition limited by the process standard. Can be. Furthermore, since the compaction is performed while comparing and verifying the electrical characteristics of the initial input layout pattern and the compacted layout pattern by using simulation, a large difference occurs between the electrical characteristics of the initial layout pattern and the electrical characteristics after the layout compaction. As a result, a circuit configuration exhibiting desired electrical characteristics can be realized with a layout pattern having a smaller area. Further, the finished pattern formed on the wafer by the optical proximity effect corrected layout pattern is obtained by simulation, and the optical proximity corrected layout pattern is appropriately formed by comparing the compacted layout pattern and the finished pattern. Since the compaction is performed while confirming that the compaction is performed, compaction conditions for performing the layout compaction process optimized for the manufacturing conditions of the semiconductor integrated circuit device can be generated.

  According to the layout compaction method of the present invention, a minimum layout condition is extracted from the optical proximity effect information, a minimum dimension of a manufacturable layout pattern is calculated from the minimum layout condition, and a lower limit value of the compaction is set. By doing so, it is possible to generate compaction conditions that take into account the optical proximity effect. Further, by decomposing the layout pattern for compaction into a plurality of basic patterns, compaction conditions can be individually set for each basic pattern, and highly effective compaction can be realized.

  According to the layout compaction method according to the third aspect of the present invention, it is not necessary to extract the parasitic capacitance from the compacted layout pattern and perform a simulation to confirm the operation of the circuit. By performing conversion and comparing with a delay value boundary condition indicating a limit value that does not affect the circuit operation due to the delay, high-speed circuit operation verification can be performed.

  According to the layout compaction method according to the fourth aspect of the present invention, by focusing on the variation of the delay time in the electric circuit, the fluctuation range of the delay time in which the operation of the electric circuit is guaranteed is converted into the capacitance of the capacitor. By converting the variation width of the capacitance into a difference pattern in the layout pattern, the amount of pattern variation due to compaction can be determined, and compaction conditions can be set thereby, so that highly efficient compaction can be realized.

  According to the layout compaction method according to the fifth aspect of the present invention, by selecting a looser one of the first and second compaction condition candidates as the compaction condition, the condition that can be manufactured and guarantees the normal operation of the electric circuit. Can be set, the verification step can be omitted, and the processing time of the entire layout compaction can be reduced.

(First Embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a layout compaction method according to an embodiment of the present invention. An input layout pattern 1, a compaction control step 2, a layout compression step 3, an optical proximity effect correction step 4, a corrected layout pattern storage step 5, a first verification step 6, an error data storage step 7, an OPC condition generation step 8, an optical proximity effect information 9, and a second verification step 10.

  First, layout pattern data of a semiconductor integrated circuit composed of a plurality of rectangular patterns is set as an input layout pattern 1.

  In the compaction control step 2, a compaction lower limit value is calculated based on the optical proximity effect information 9 and the data stored in the error data storing step 7, and a compaction condition is generated and stored from the compaction lower limit value and the layout pattern.

  Here, the optical proximity effect information 9, the data stored in the error data storage step 7, the compaction lower limit value, and the compaction condition will be described.

  As shown in FIG. 19A, when two rectangular patterns having a width L arranged in parallel at a pattern interval S are formed on a wafer, a pattern to be formed is determined by the pattern width L and the pattern interval S. Dimensions vary. FIG. 19B is a graph showing the relationship between the pattern interval S and the variation ΔL of the pattern width on the wafer, and FIG. 19C is the relationship between the width L of the layout pattern and the pattern width L ′ on the wafer. FIG.

  For example, when the pattern interval S is very small, the pattern width L becomes large due to the optical proximity effect. That is, in the graph of FIG. 19B, when the pattern interval S is small, the variation ΔL of the pattern width increases. The information on the dimensional variation at this time is called proximity effect information 9.

  Next, the data stored in the error data storage step 7 will be described. The above-described optical proximity effect information 9 is a condition when two rectangular patterns are arranged in parallel, and is significantly different from an actual pattern. For example, in the case of the pattern shown in FIG. 20, when the optical proximity effect information 9 is applied and the optical proximity effect correction processing is performed, correct correction for obtaining the pattern of FIG. 20 is not performed on the wafer. This can be confirmed in a first verification step and a second verification step. At this time, the pattern that could not be correctly corrected and its location are stored as error data.

Next, the compaction lower limit value is normally set for each of the basic pattern (width L ₁ , interval S ₁ ) shown in FIG. 21 and the error data pattern (width L ₂ , interval S ₂ ) shown in FIG. It is the limit value that can be compressed. In the basic pattern, the value is L ₁ ′ and the pattern interval is S ₁ ′. In the error data pattern, the pattern width is L ₂ ′ and the pattern interval is S ₂ ′.

The compaction conditions are
ΔL _C1 = L ₁ −L ₁ ′, ΔS _C1 = S ₁ −S ₁ ′
ΔL _C2 = L ₂ −L ₂ ′, ΔS _C2 = S ₂ −S ₂ ′
Is obtained. Here, L ₁ and L ₂ are pattern widths, S ₁ and S ₂ are pattern intervals, L ₁ ′ and L ₂ ′ are pattern widths on a wafer, and S ₁ ′ and S ₂ ′ are pattern intervals on a wafer.

  The layout compression step 3 receives data by using the input layout pattern 1 and the compaction condition generated in the compaction control step 2 as input, compacts the input layout pattern 1 according to the compaction condition, and performs a compacted layout pattern (hereinafter, a compressed layout pattern). To save).

  The optical proximity effect correction step 4 receives data by inputting the compressed layout pattern compressed in the layout compression step 3 and the optical proximity effect correction condition generated in the OPC condition generation step 8, and performs compaction in the layout compression step 3. Optical proximity effect correction is performed on the compressed layout pattern thus obtained.

  Here, the optical proximity effect correction condition will be described. The optical proximity correction condition is a condition for deforming the original layout pattern so that a certain layout pattern is formed as a similar pattern on the wafer.

When the original layout pattern is two parallel rectangular patterns (width L and spacing S) as shown in FIG. 23A, the layout pattern after deformation is as shown in FIG. In addition, the inner side is wider by ΔL _C than the width L of the original pattern, and as a result, the interval S is narrowed by 2 × ΔL _C.

In this case, the value of ΔL _C differs depending on the value of the interval S, for example, as follows.

0 ≦ S <260 nm, ΔL _C = 20 nm
260 nm ≦ S <540 nm, ΔL _C = 10 nm
540 nm ≦ S <1400 nm, ΔL _C = 0 nm
When the original layout pattern is a single rectangular pattern (having a width of L) as shown in FIG. 24A, the layout pattern after deformation is changed to the original layout pattern as shown in FIG. The tip is wider and longer than the pattern. In this case, the value of d differs depending on the value of the width L, for example, as follows.

0 ≦ L <200 nm, d = 30 nm
200 nm ≦ L <400 nm, d = 20 nm
400 nm ≦ L <800 nm, d = 10 nm
However, P = 40 nm and H = 200 nm, which are constant irrespective of the value of the interval L.

  The corrected layout pattern storing step 5 stores the data of the optical proximity effect corrected layout pattern (hereinafter, referred to as a corrected layout pattern) generated in the optical proximity effect correction step 4.

  The first verification step 6 receives data with the input layout pattern 1 and the compressed layout pattern as inputs, compares and verifies the connection relationship and electrical characteristics of both layout patterns, and confirms that the compressed layout pattern operates correctly. When a failure occurs, first error data is output.

  The second verification step 10 receives data with the compressed layout pattern and the corrected layout pattern as inputs, executes lithography simulation in the semiconductor integrated circuit manufacturing process on the corrected layout pattern, and finishes the compression layout pattern on the silicon wafer. And verify that the corrected layout pattern is appropriate, and output a second error data when a problem occurs.

  The error data storage step 7 stores the error data detected in the first and second verification steps 6 and 10, and outputs the data to the compaction control step 2.

  The OPC condition generation step 8 receives the data with the input layout pattern 1 and the optical proximity effect information 9 as inputs, and generates an optimal optical proximity effect correction condition in consideration of the compaction condition generated in the compaction control step 2.

  Here, what kind of optical proximity correction condition is generated by the input layout pattern 1, the optical proximity effect information 9, and the compaction condition will be specifically described.

  For example, as shown in FIG. 25, when two rectangular patterns are arranged in parallel, when the interval S is 260 nm and the width L is 180 mm, the conditions described in FIGS. If they are the same, the relationship between the interval S and the variation ΔL of the width L on the wafer is as shown in FIG. FIG. 27 shows the relationship between the pattern width L and the variation ΔL of the pattern width L on the wafer.

For example, the compaction conditions are uniformly set to ΔL _C = −10 nm and ΔS _C = −20 nm for all patterns.
Then, the pattern is deformed from the optical proximity effect information 9 as shown in FIG. That is, S = 260−20 = 240 nm,
L = 180−10 × 2 = 160 nm
It becomes.

  Here, differences in compaction conditions due to differences in width L and interval S are shown below.

0 ≦ L <180nm
0 ≦ S <240 nm, ΔL _C = + 35 nm
240 nm ≦ S <260 nm, ΔL _C = + 30 nm
260 nm ≦ S <540 nm, ΔL _C = + 20 nm
540 nm ≦ S <1400 nm, ΔL _C = + 10 nm
‥‥‥
When 180 ≦ L
0 ≦ S <240 nm, ΔL _C = + 25 nm
240 nm ≦ S <260 nm, ΔL _C = + 20 nm
260 nm ≦ S <540 nm, ΔL _C = + 10 nm
540 nm ≦ S <1400 nm, ΔL _C = 0 nm
‥‥‥
With the above configuration, layout compaction is performed. The processing procedure at that time will be described with reference to a flowchart. FIG. 2 is a flowchart illustrating a processing procedure of the layout compaction method. This processing is started in a state where the input layout pattern 1 and the optical proximity effect information 9 are given to the configuration shown in FIG.

  First, in step 121, the input layout pattern 1, the optical proximity effect information 9, and the pattern stored in the error data storage step 7 are input to the compaction control step 2, and a compaction condition suitable for the input layout pattern 1 is generated. .

  In step 122, compaction (compression) of the input layout pattern 1 is performed according to the compaction conditions generated in compaction control step 2 in layout compression step 3.

  In step 123, the compressed layout pattern obtained in the layout compression step 3 is input to the first verification step 6, and an electric circuit simulation is performed to determine whether the compressed layout pattern operates correctly as an electric circuit in the same manner as the input layout pattern 1. Verification is performed from the aspect of electrical characteristics using. The verification at this time is performed by comparison with the input layout pattern 1.

  In step 124, if the operation verification is correct, the compressed layout pattern is passed to the optical proximity effect correction step 4. If the operation verification is not correct, a layout pattern in which an operation failure occurs is extracted, stored in an error data base in an error data storage step in step 128, returned to the compaction control step 2, and the above procedure is repeated.

  In step 125, the compressed layout pattern is input to the optical proximity effect correction step 4, and the optical proximity effect correction is performed.

  In step 126, the corrected layout pattern subjected to the optical proximity effect correction in the second verification step 10 is input, and the pattern formed on the silicon wafer is simulated by performing lithography simulation and process simulation. Verify the finished pattern. The verification is performed by comparison with a compressed layout pattern.

  If there is no problem with the finished pattern, that is, the corrected layout pattern in step 127, the processing flow ends. If there is a problem with the finished pattern, a layout pattern having a problem is extracted, and in step 128, error data is saved. In step 7, the data is stored in the error database, and the process returns to compaction control step 2 to perform control so that the above procedure is repeated.

  Next, an example is shown using a specific circuit pattern. FIG. 3 is a schematic diagram showing an example of a pattern change according to the first embodiment. Layout patterns 131 to 134 in FIG. 3A indicate circuit layout patterns designed in advance. Compressed layout patterns 136 to 139 in FIG. 3B indicate circuit layout patterns obtained by compressing the layout patterns 131 to 134. Corrected layout patterns 141 to 144 in FIG. 3C show corrected compaction circuit layout patterns obtained by performing optical proximity correction on the compressed layout patterns 136 to 139.

  Note that, in the present embodiment, an example of compaction based on the layout pattern 132 in FIG. 3A has been described in determining compaction conditions. However, different compaction conditions may be generated based on an arbitrary layout pattern. Is also possible. Further, a plurality of arbitrary layout patterns may be used as a reference.

  According to the present embodiment, compaction of a layout pattern can be performed under a condition in which the influence of the optical proximity effect is also taken into consideration, and the area can be made smaller than under compaction conditions limited by process standards. Furthermore, by performing compaction while comparing the electrical characteristics of the initial layout pattern and the layout pattern after compaction using simulation, there is no significant difference between the electrical characteristics of the initial layout pattern and the electrical characteristics after layout compaction. As a result, a circuit configuration exhibiting desired electrical characteristics can be realized with a layout pattern having a smaller area. In addition, the finished pattern in which the optical proximity effect corrected layout pattern is formed on the wafer by simulation is obtained, and the optical proximity effect corrected layout pattern is appropriately formed by comparing the compacted layout pattern and the finished pattern. Since the compaction is performed while confirming that the compaction is performed, compaction conditions for performing the layout compaction process optimized for the manufacturing conditions of the semiconductor integrated circuit device can be generated.

(Second embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. The present embodiment provides a compaction control method in which the optical proximity effect is sufficiently considered.

  FIG. 4 is a block diagram schematically showing a first example of the compaction control step 2 of FIG.

  Layout data 201 is input, and basic pattern data 202 is extracted from layout data 201 in basic pattern extraction step 211.

  The optical proximity effect information 203 is input to a minimum layout condition extraction step 212, and outputs a minimum layout condition 204. The first compaction condition extraction step 213 receives the basic pattern data 202 and the minimum layout condition 204 and outputs compaction control information 205 composed of a set of compaction conditions. The compaction condition is generated for each basic pattern data 202.

  Here, the minimum layout condition will be described. FIG. 33 (a) shows two rectangular patterns arranged in parallel. The interval S between these two patterns and the variation ΔL of the pattern width are as shown in FIG. 33 (b). When S <2 × ΔL, two adjacent patterns are in contact with each other. Therefore, S> 2 × ΔL is a condition that can be manufactured.

  The relationship between the width L of the layout pattern and the variation ΔL of the pattern width L on the wafer is as shown in FIG. 34. However, when the width L is small, the pattern may not be formed on the wafer, and its limit is limited. Lth, which is the minimum width.

  The compaction has two conditions of reducing the pattern interval S and decreasing the pattern width L, and these two conditions must satisfy the above-described conditions of the minimum interval and the minimum width.

  With the above-described configuration, generation of compaction conditions that can be manufactured in consideration of the optical proximity effect can be realized.

  Next, a processing procedure at that time will be described with reference to a flowchart. 6 is a flowchart illustrating a processing procedure of a first example of compaction control step 2 illustrated in FIG. 5. This process is started in a state where layout data 201 and optical proximity effect information 203 are given to the configuration shown in FIG.

  In step 221, a basic pattern is extracted from the layout data 201 and classified according to the width / interval of the basic pattern. The basic pattern is a set of a space between an arbitrary polygon pattern and an arbitrary polygon pattern and an adjacent pattern. The basic pattern group extracted from the layout data 201 is output to the basic pattern database as basic pattern data 202 in step 222. This process is executed in the basic pattern extraction step 211.

  In step 223, information (width, interval) of the minimum pattern achievable in manufacturing is extracted from the optical proximity effect information 202. The extracted information is output as the minimum layout condition 203. This processing is executed in the minimum layout condition extraction step 212.

  In step 224, compaction conditions are generated for each basic pattern belonging to the basic pattern data 202 from the minimum layout condition 203, and output as compaction control information 205 in step 225. This processing is executed in the compaction condition generation step 213.

  FIG. 6 is a flowchart showing a processing procedure of the compaction condition generation step 213 shown in FIG. This process is started with the minimum layout condition 203 and the basic pattern data 202 given.

  In step 231, the minimum pattern interval and the minimum pattern width that are achievable in manufacturing represented by the minimum layout condition 203 are set as compaction conditions.

  In step 232, compaction is performed on the basic pattern data 202 under the compaction conditions set previously.

  In step 233, a photolithography simulation is performed on the compacted basic pattern data to generate a pattern to be formed on the silicon wafer in step 234.

  In step 235, the difference between the pattern generated by the photolithography simulation and the basic pattern data 202 is extracted. An OPC condition is determined based on the extracted difference pattern.

  More specifically, the basic pattern is changed in the reverse of the differential pattern by the difference pattern (for example, when the differential pattern is outside the basic pattern, a part of the basic pattern is deleted, and when the differential pattern is inside the basic pattern, Is added to the basic pattern) to set the OPC condition.

  For example, as a result of performing a lithography simulation on the basic pattern shown in FIG. 29A, the generated pattern becomes as shown in FIG. 29B, and the difference pattern between the basic pattern and the generated pattern is shown in FIG. ) And exists inside the basic pattern.

  In such a case, the basic pattern is deformed as follows. That is, when there is a basic pattern and a difference pattern as shown in FIG. 30A, the difference pattern is folded back and added to the basic pattern as shown in FIG. ) Is obtained, and a pattern as shown in FIG. 30D is obtained by linearly approximating the pattern.

  On the other hand, as a result of performing a lithography simulation on the basic pattern shown in FIG. 31A, if the generated pattern is as shown in FIG. 31B, the difference pattern between the basic pattern and the generated pattern is as shown in FIG. ) And exists outside the basic pattern.

  In such a case, the basic pattern is deformed as follows. That is, as shown in FIG. 32A, when there is a basic pattern and a difference pattern, as shown in FIG. 32B, the difference pattern is folded back from the basic pattern and the portion is deleted from the basic pattern. A pattern as shown in FIG. 32C is obtained, and a pattern as shown in FIG. 32D is obtained by linearly approximating the pattern.

  In step 236, the OPC process is performed on the basic pattern data 202 based on the determined OPC condition. In step 237, the pattern shape after OPC is determined, and the OPC-processed data is output.

  In step 238, it is determined whether or not the basic pattern data after the OPC processing has a pattern that can be realized in manufacturing. Specifically, this is as described with reference to FIGS.

  If the determination result is a pattern that can be realized in manufacturing, the compaction condition and the OPC condition are output, and the process ends.

  If the result of the determination is a pattern that cannot be manufactured, the initial compaction condition is relaxed in step 239, and compaction processing is executed again.

  Next, the basic pattern extraction step 211 will be described using a specific circuit pattern. FIG. 7 is a diagram showing a first example of the compaction control step 6.

  FIG. 7 is a diagram showing an input layout pattern, and 241 to 244 show respective layout patterns.

  The layout patterns 241 to 244 are decomposed into basic patterns 245 to 248 as a set of a space between an arbitrary polygon pattern and an adjacent pattern to the arbitrary polygon pattern. In the basic patterns 245 to 248, compaction conditions for reducing only the space portion according to each basic pattern are set. When each compaction condition is applied to the basic patterns 245 to 248, for example, the compaction is performed to the patterns 249 to 252.

  Information tabulated based on each compaction condition is output as compaction control information.

  FIG. 8 is a diagram showing the relationship between compaction and OPC, where 261 is a layout pattern, 262 is a compacted layout pattern, and 263 is a pattern obtained by performing OPC processing on compacted layout data. Reference numerals 264 to 266 indicate patterns when the patterns 261 to 263 are formed on the silicon wafer, respectively.

  First, the basic pattern 261 is formed in a shape like the pattern 264 on a silicon wafer. The pattern 264 has no problem in shape and electrical connection.

  Next, the basic pattern 262 is in contact with the left and right patterns like the pattern 265 on the silicon wafer. This is because the optical proximity effect appeared more conspicuously as a result of the interval between the patterns 262 being shortened due to the compaction processing.

  Next, the basic pattern 263 is correctly formed on the silicon wafer like the pattern 266. The enhancement of the optical proximity effect due to compaction was offset by OPC.

  FIG. 9 is a diagram showing the concept of the minimum layout condition extraction step 212 for outputting the minimum layout condition 204 from the optical proximity effect information 203. Reference numeral 271 denotes a pattern in which two rectangular patterns are arranged in parallel with each other; Indicates one rectangular pattern. 273 is a graph obtained by measuring the pattern deformation of the pattern 271 due to the optical proximity effect. 274 is a graph obtained by measuring the pattern deformation due to the optical proximity effect in the pattern 272. In the graphs 273 and 274 of FIG. 9, S indicates a pattern interval, W indicates a pattern width, and + δW and -δW indicate fluctuations (variations) of the pattern width. The graph 273 shows that when the pattern interval S changes, the finish of the pattern width on the wafer changes. Further, the graph 274 shows that when the pattern width W changes, the finish of the pattern width changes.

  Data is stored as a graph or a table showing the relationship between the width of a pattern formed on a silicon wafer and the interval between adjacent patterns. In addition, data is stored as a graph or a table of the relationship between the width of the pattern formed on the silicon wafer and the width of the layout pattern.

  From the optical proximity effect information, the minimum layout pattern width that can be formed on the silicon wafer can be extracted, and the minimum layout pattern interval that can be formed on the silicon wafer can be extracted.

  When the pattern interval is reduced, the pattern width on the wafer increases. If the interval is too small, it contacts the next pattern. This non-contact limit is the minimum interval. In addition, when the pattern width is small, the finish is small. If the width is too small, it cannot be formed on the wafer. The limit that can be formed is the minimum width. These can be detected from the graph of FIG.

  The pattern image formed on the silicon wafer can be generated by performing a photolithography simulation on each basic pattern. The OPC condition is determined from the difference between the pattern image and the basic pattern.

  Note that, in the present embodiment, the above-described example is given as the compaction control method, but it is also possible to apply a process condition that does not consider the optical proximity effect to the compaction control information. In this case, the area reduced by the compaction processing is small, but the overall processing time is short.

  According to the present embodiment, in addition to the first embodiment, the minimum dimension of a manufacturable layout pattern is calculated from the optical proximity effect information, and the lower limit value of the compaction is set to take the optical proximity effect into account. Compaction conditions can be generated. Further, by decomposing the layout pattern for compaction into a plurality of basic patterns, compaction conditions can be individually set for each basic pattern, and highly effective compaction can be realized.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the compaction verification method is limited to the layout change.

  FIG. 10 is a block diagram illustrating an outline of the first verification step 6 in the first embodiment. A layout pattern (data) 301 and a compacted layout pattern (data) 302 are provided as inputs, pattern comparison is performed in a pattern comparison step 311, and a difference between them is output as a layout difference pattern (data) 303.

  The layout difference pattern 303 is provided as an input, and the value of the parasitic capacitance due to layout variation is calculated from the area and dimensions of the layout difference pattern 303 in the delay conversion step 312, and further converted to a delay value and output as delay variation data 304.

  With the delay variation data 304 and the delay boundary condition 305 as inputs, the delay verification step 313 determines whether or not the delay variation data 304 falls within the allowable range of the delay boundary condition 305, and confirms an operation failure due to the delay variation. .

  With the above configuration, it is possible to verify whether the layout pattern after compaction operates correctly.

  Next, a processing procedure at that time will be described with reference to a flowchart.

  FIG. 11 is a flowchart showing a processing procedure of the first verification step 6. First, in step 321, a layout pattern (data) 301 and a compacted layout pattern (data) 302 are read.

  In step 322, a difference pattern is calculated from the layout pattern 301 and the compacted layout pattern 302, and stored as a layout difference pattern (data) 303. This processing is executed in the pattern comparison step 311.

  In step 323, the layout difference pattern 303 is input, and the area and dimensions of each polygon pattern included in the layout difference pattern 303 are converted into a parasitic capacitance value.

  Further, it converts the parasitic capacitance value into a delay value and outputs it as delay variation data 304.

  In step 324, the delay variation data 304 and the delay boundary condition 305 are input, and it is determined whether or not the delay variation data 304 falls within the allowable range of the delay boundary condition 305. Ends. If the operation is affected, the compaction condition is corrected in step 325, and the process ends.

  Next, the pattern comparison step 311 will be described using a specific circuit pattern. FIG. 12 is a diagram showing an example of the pattern comparison step 311. A graphical exclusive logical operation is performed on the layout patterns (data) 331 to 334 shown in FIG. 12A and the compacted layout patterns (data) 335 to 337 to obtain a layout difference pattern shown in FIG. (Data) 338 to 340 are extracted. The amount of change in the capacitance of the capacitor can be calculated from the width of the layout difference patterns 338 to 340, and is converted into the amount of change in the delay value.

  According to the present embodiment, in addition to the first embodiment, it is not necessary to extract the parasitic capacitance from the layout pattern after compaction and perform a simulation to confirm the operation of the circuit. High-speed circuit operation verification can be performed by calculating and converting to a delay value and comparing with a delay value boundary condition indicating a limit value that does not affect the circuit operation due to the delay.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIGS. The present embodiment provides a compaction control method in a form in which delay time is sufficiently considered.

  FIG. 13 is a block diagram schematically illustrating a second example of compaction control step 2 according to the first embodiment. In this example, a delay variation condition 401 indicating a condition under which the operation of the electric circuit is guaranteed even when the delay time varies is input. The value (delay variation condition 401) is converted into a capacitor capacitance variation allowable value, and a capacitor capacitance variation allowable value 402 is output.

  In the pattern conversion step 412, the capacitor capacitance variation allowable value 402 is converted into a layout variation allowable pattern 403. In the second compaction condition extraction step 413, the layout variation allowable pattern 403 is converted into a second compaction condition 404 according to each pattern shape.

  With the above configuration, generation of the second compaction condition that can operate as an electric circuit in consideration of the delay time can be realized.

  Next, the processing procedure will be described with reference to the flowchart of FIG.

In step 421, the delay fluctuation condition 401 is configured by a table representing an upper limit / reference value / lower limit, and calculates each allowable fluctuation width.
In step 422, the allowable range of the delay time variation is converted into the variation range of the capacitor capacitance to obtain a capacitor capacitance variation value 402.

  In step 423, the capacitor capacitance fluctuation value 402 is converted into a layout fluctuation allowable pattern 403 according to the shape of the adjacent pattern.

  In step 424, the line width of the layout variation allowable pattern 403 is detected and output as the second compaction condition, and the process ends.

Next, a specific method will be described with reference to equations and the drawing of FIG. In the delay variation condition 401, the condition of the delay variation that can operate correctly as an electric circuit is represented by {tmin, tstd, tmax}, respectively, with {upper limit, reference value, lower limit}, and the upper limit allowable variation value δta, The lower limit fluctuation value δtb is
δta = tmax−tstd
δtb = tstd−tmin
Can be calculated.

Next, the relationship between the parasitic capacitance Cp and the delay time tp is Cp = f (tp)
Expressed as a function of

Here, the upper limit value δCa and the lower limit value δCb of the capacitor fluctuation value are δCa = f (δta)
δCb = f (δtb)
Can be obtained at

  Next, the upper limit value δCa and the lower limit value δCb of the capacitor variation value are converted into a layout variation allowable pattern. The layout variation allowable pattern is generated according to the adjacent pattern shape. In this case, as shown in FIGS. 15A to 15C, pattern generation is performed so as to always maintain a constant area.

  Finally, the width of the generated layout variation allowable pattern is measured and output as the second compaction condition.

  According to the present embodiment, in addition to the first embodiment, by focusing on the delay time fluctuation in the electric circuit, the fluctuation range of the delay time in which the operation of the electric circuit is guaranteed is converted into the capacitor capacity. However, the variation width of the capacitor capacitance can be expressed as a difference pattern in the layout pattern, the pattern variation due to compaction can be determined, and compaction conditions can be set, so that highly effective compaction can be realized.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIGS. The present embodiment provides a compaction control method in a form in which the optical proximity effect and the delay time are sufficiently considered.

  FIG. 16 is a block diagram schematically illustrating a third example of compaction control step 2 in the first embodiment. In this example, 501 indicates the same first compaction condition candidate as the compaction condition shown in the second embodiment, and 502 indicates the same second compaction condition candidate as the compaction condition shown in the fourth embodiment. Show. Reference numeral 503 denotes a compaction condition comparing step of comparing the first compaction condition candidate 501 and the second compaction condition candidate 502 and selecting a smaller one as the compaction condition. Reference numeral 504 denotes the compaction condition selected in the compaction condition comparison step 503.

  With the above configuration, it is possible to generate a compaction condition that can operate as an electric circuit in consideration of the optical proximity effect and the delay time.

Next, the processing procedure will be described with reference to the flowchart in FIG.
In step 521, a first compaction condition candidate is calculated by the first compaction control step described in the second embodiment.

  In step 522, a second compaction condition is calculated in the second compaction control step described in the fourth embodiment.

  In step 523, the first compaction condition candidate is compared with the second compaction condition candidate, and the less compact condition is selected as the compaction condition and output.

  According to the present embodiment, of the compaction condition candidates generated in the second embodiment and the fourth embodiment, the compaction condition is selected as a looser compaction condition, thereby enabling manufacturability and normal operation of the electric circuit. Can be set, the verification step can be omitted, and the processing time of the entire layout compaction can be reduced.

  The layout compaction method according to the present invention has the effect that the compaction of the layout pattern can be performed under the condition in which the influence of the optical proximity effect is also taken into consideration, and the area can be made smaller than the compaction condition limited by the process standard. However, it is useful in the field of semiconductor integrated circuit manufacturing and the like.

FIG. 2 is a block diagram illustrating a schematic configuration of a layout compaction method according to the first embodiment of the present invention. 5 is a flowchart illustrating a processing procedure of a layout compaction method. FIG. 5 is a schematic diagram illustrating an example of a change in a pattern according to the first embodiment. FIG. 4 is a block diagram schematically illustrating a first example (second embodiment) of compaction control step 2 in FIG. 1. 9 is a flowchart illustrating a processing procedure of a first example of compaction control step 2. It is a flowchart which shows the processing procedure of the compaction condition generation step 213. It is a schematic diagram which shows the example of the pattern of a compaction control step. It is a schematic diagram which shows the relationship between compaction and OPC. FIG. 9 is a schematic diagram illustrating the concept of a minimum layout condition extraction step 212 for outputting a minimum layout condition 204 from the optical proximity effect information 203. FIG. 9 is a block diagram illustrating an outline (third embodiment) of a verification step 6 in FIG. 1. It is a flowchart which shows the processing procedure of a delay time verification step. FIG. 9 is a diagram illustrating an example of a change in a pattern in a pattern comparison step 311. FIG. 13 is a block diagram illustrating an outline (fourth embodiment) of a second example of compaction control step 2 in FIG. 1. 10 is a flowchart illustrating a processing procedure of a second example of the second compaction control step 2. FIG. 9 is a schematic diagram illustrating a generation example of a layout variation allowable pattern. FIG. 13 is a block diagram schematically illustrating a third example (fifth embodiment) of compaction control step 2 in FIG. 1. 13 is a flowchart illustrating a processing procedure of a third example of compaction control step 2. 9 is a flowchart in the case where layout data of a conventional semiconductor integrated circuit is compacted and converted into a mask pattern. (A) is a schematic diagram showing a layout pattern, (b) is a graph showing the relationship between the layout pattern interval and the variation of the pattern on the wafer, and (c) is a graph showing the relationship between the layout pattern width and the pattern width on the wafer. It is. It is a schematic diagram which shows an error pattern. FIG. 5 is a schematic diagram for explaining a compaction lower limit value in a basic pattern. It is a schematic diagram for explaining the compaction lower limit in an error pattern. FIG. 5 is a schematic diagram for explaining an optical proximity effect correction condition. FIG. 5 is a schematic diagram for explaining an optical proximity effect correction condition. It is a schematic diagram of the rectangular pattern arrange | positioned in parallel. 6 is a graph illustrating a relationship between a layout pattern interval and a variation in a pattern width on a wafer. 6 is a graph showing a relationship between a layout pattern width and a pattern width on a wafer. It is a schematic diagram which shows the pattern after correction. It is a schematic diagram which shows the basic pattern, the pattern generated by simulation, and the difference pattern of both. It is a schematic diagram which shows a mode of deformation | transformation of a basic pattern. It is a schematic diagram which shows the basic pattern, the pattern generated by simulation, and the difference pattern of both. It is a schematic diagram which shows a mode of deformation | transformation of a basic pattern. (A) is a schematic diagram showing a rectangular layout pattern, and (b) is a graph showing the relationship between the layout pattern interval and the amount of change in the layout pattern width. 6 is a graph showing a relationship between a layout pattern width and a pattern width on a wafer.

Explanation of reference numerals

1 Input Layout Pattern 2 Compaction Control Step 3 Layout Compression Step 4 Optical Proximity Effect Correction Step 5 Corrected Layout Pattern Saving Step 6 Verification Step 7 Error Data Saving Step 8 OPC Condition Generation Step 9 Optical Proximity Effect Information

Claims (8)

Means for inputting a layout, compaction control means, optical proximity correction condition generation means, layout compression means, first verification means for verifying the data after compaction, optical proximity correction means, and layout data after optical proximity effect correction. A method of compacting a semiconductor layout in consideration of an optical proximity effect by a programmed computer including a second verification unit for verifying and an error storage unit,
A compaction control step in which the compaction control means generates compaction conditions suitable for an input layout pattern;
An optical proximity effect correction condition generating step in which the optical proximity effect correction condition generation unit generates an optical proximity effect correction condition in consideration of the compaction condition generated in the compaction control step;
A layout compression step in which the layout compression unit compacts the input layout pattern according to the compaction condition to generate a compacted layout pattern;
The first verification means receives the input layout pattern and the compacted layout pattern as data, and confirms that the compacted layout pattern operates correctly by comparing the input layout pattern and the compacted layout pattern. Performing a first verification step of outputting first error data when a failure occurs,
An optical proximity correction step in which the optical proximity effect correction unit performs an optical proximity effect correction on the compacted layout pattern according to the optical proximity effect correction condition to generate an optical proximity effect corrected layout pattern;
The second verification means receives the compacted layout pattern and the optical proximity effect corrected layout pattern as data, obtains a finished pattern formed on a wafer by the optical proximity effect corrected layout pattern, and obtains the compacted layout. A second verification step of confirming that the optical proximity effect corrected layout pattern is properly formed by comparing the pattern and the finished pattern, and outputting second error data when a failure occurs. ,
An error storing step of storing the first error data and the second error data and controlling generation of the compaction condition. The compaction control step includes:
Extracting a minimum layout condition that can be manufactured based on the optical proximity effect information;
A basic pattern extraction step of decomposing the input layout pattern into a plurality of basic patterns;
2. A compaction condition extracting step of generating a compaction condition from a minimum layout condition extracted by the minimum layout condition extracting step and a plurality of basic patterns extracted by the basic pattern extracting step. Layout compaction method. The first verification step includes:
A pattern comparing step of extracting a difference pattern between the input layout pattern and the compacted layout pattern;
A delay conversion step of calculating a capacitor capacity from the difference pattern extracted in the pattern comparison step and converting the capacitor capacity into a delay value;
2. The layout compaction method according to claim 1, further comprising: a delay verification step of confirming an operation failure due to a delay variation based on the delay value calculated in the delay conversion step. The compaction control step includes:
A capacitance conversion step of converting the delay time variation allowable value in the input layout pattern into a capacitor capacitance variation allowable value;
A pattern conversion step of converting the capacitor capacitance variation allowable value into a layout variation allowable pattern,
A compaction condition extracting step of generating a compaction condition from the layout variation allowable pattern obtained in the pattern conversion step. The compaction control step includes:
Extracting a minimum layout condition that can be manufactured based on the optical proximity effect information;
A basic pattern extraction step of decomposing the input layout pattern into a plurality of basic patterns;
A first compaction condition extracting step of generating a first compaction condition candidate from the minimum layout condition extracted by the minimum layout condition extracting step and a plurality of basic patterns extracted by the basic pattern extracting step;
Capacitance conversion step of converting the delay time variation allowable value in the input layout pattern into a capacitor capacitance variation allowable value,
A pattern conversion step of converting the capacitor capacitance variation allowable value into a layout variation allowable pattern,
A second compaction condition extraction step of generating a second compaction condition candidate from the layout variation allowable pattern obtained by the pattern conversion step;
Of the first compaction condition candidates obtained in the first compaction condition extracting step and the second compaction condition candidates obtained in the second compaction condition extracting step, a looser one is selected as the compaction condition. 2. The layout compaction method according to claim 1, further comprising: a compaction condition selecting step. The compaction control step includes:
The layout compaction method according to claim 1, wherein the compaction condition is output as data that pairs the width of the layout pattern with the interval between adjacent layout patterns. The compaction conditions are:
2. The layout compaction method according to claim 1, wherein the method is changed according to a result of the first and second verification steps. A computer for generating a layout of a semiconductor integrated circuit;
Means for inputting the designed layout;
Compaction control means for generating compaction conditions suitable for the input layout pattern;
An optical proximity correction condition generation unit configured to generate an optical proximity correction condition in consideration of the compaction condition generated by the compaction control unit;
Layout compression means for compacting the input layout pattern according to the compaction condition to generate a compacted layout pattern;
When the input layout pattern and the compacted layout pattern are received as data, the input layout pattern and the compacted layout pattern are compared to confirm that the compacted layout pattern operates correctly, and a failure occurs. First verification means for outputting first error data to
Optical proximity correction means for performing optical proximity correction on the compacted layout pattern according to the optical proximity correction condition to generate an optical proximity corrected layout pattern,
Receiving the compacted layout pattern and the optical proximity corrected layout pattern as data, obtaining a finished pattern formed on a wafer by the optical proximity corrected layout pattern, and comparing the compacted layout pattern and the finished pattern A second verifying means for confirming that the layout pattern corrected for the optical proximity effect is properly formed and outputting second error data when a problem occurs;
A computer-readable storage medium storing a layout design program for storing the first error data and the second error data and functioning as an error storage unit that controls generation of the compaction condition.

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