JP2004355365A - Cache management device and cache memory management method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decide whether caching is necessary or not according to the past use frequency of data. <P>SOLUTION: The access frequency of each data is counted on a high order level memory 2. The access frequency of data being the target of displacement invalidated by the high order level memory 2 is set in the access frequency log 3c of a low order level memory 3. In the case of the mistaken hit of the high order level memory 2, when the value of the access frequency log corresponding to the data being the target of access is a predetermined value or more, the data being the target of access are stored in the high order level memory 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a cache management device and a cache memory management method, and more particularly to a cache management device and a cache memory management method capable of storing frequently used data in an upper level memory.
[0002]
[Prior art]
Generally, a cache memory is used for speeding up a computer system. The cache memory is arranged between the CPU and the main storage device. As the cache memory, a memory faster than the memory used for the main storage device is used. Therefore, the CPU can access the data stored in the cache memory at high speed. The cache memory is managed by being divided into areas in units of blocks, and processes such as data writing and writing are performed in units of blocks.
[0003]
By the way, data caching is performed not only when reading data (read cache) but also when writing data (write cache).
There are a write-through method and a write-back method for writing data to the main storage device. In the write-through method, when the CPU writes data, the data is written to the main memory at the same time as the data is written to the cache memory. On the other hand, in the write-back method, when the CPU writes data, the writing is performed to the cache memory. Then, the data written in the cache memory is written to the main storage device at an arbitrary timing. It is also possible to select a write-through method and a write-back method as appropriate, and to write data according to the selected method (for example, see Patent Documents 1 and 2).
[0004]
[Patent Document 1]
U.S. Pat. No. 5,469,555
[Patent Document 2]
U.S. Pat. No. 5,522,057
[0005]
[Problems to be solved by the invention]
However, in the related art, when a cache miss occurs, all blocks including data to be accessed are cached indiscriminately. Therefore, even if the cache is cached, a block that is evicted without being referred to is also stored in the cache memory. Putting such non-reusable blocks into the cache memory has the following disadvantages.
[0006]
-By storing data that is hardly referred to in the cache memory, data that is more frequently referred to than that data is evicted, and the chance of gaining the benefit of improved access speed is reduced.
[0007]
-The time and the bandwidth used by the bus are used for transferring blocks that do not contribute to a reduction in the average access time, thereby lowering the processing efficiency of the system.
Note that it is possible for a programmer to intentionally specify not to cache data that is known not to be reusable at the stage of building a program. However, the reusability of a cache block depends on the cache capacity, data size, and the like, and in many cases, it cannot be ascertained except during execution.
[0008]
As described above, writing data that is rarely used to the cache memory adversely affects the performance of the computer system. Therefore, there is a demand for a system that can write data (or a block including the data) to a cache memory only when accessing data that has been frequently used in the past.
[0009]
In the techniques described in Patent Literature 1 and Patent Literature 2, the frequency of data use is not considered when switching the data writing method. Therefore, during the operation of the system, it is not possible to switch the data writing method according to the frequency of use of each data.
[0010]
The present invention has been made in view of such a point, and an object of the present invention is to provide a cache management device and a cache memory management method that can determine whether or not caching is necessary according to the past use frequency of data.
[0011]
[Means for Solving the Problems]
In the present invention, in order to solve the above problems, a cache management device as shown in FIG. 1 is provided. The cache management device according to the present invention controls a cache process in response to an access request from the CPU 1. The cache management device includes the following elements.
[0012]
The upper level memory 2 is connected to the CPU 1. The counter 2c counts the number of times of accessing each data stored in the upper level memory 2. The lower-level memory 3 is connected to the CPU 1 and the upper-level memory 2 and stores data corresponding to each data stored in the upper-level memory 2. The access count log 3c is provided in association with each data stored in the lower level memory 3. When the access target data specified by the access request output from the CPU 1 hits the upper-level memory 2, the memory controller 1a counts up the value of the counter 2c corresponding to the access target data, and When the data is invalidated, the value of the counter 2c corresponding to the data to be replaced is set in the access count log 3c corresponding to the data to be replaced in the lower level memory 3, and the data to be accessed misses the upper level memory 2. At this time, if the value of the access count log 3c of the access target data in the lower level memory 3 is larger than a predetermined value, the access target data is stored in the upper level memory.
[0013]
According to such a cache management device, the number of times of accessing each data in the upper level memory 2 is counted. The access count of the replacement target data invalidated in the upper level memory 2 is set in the access count log 3c of the lower level memory 3. Then, in the case of a mishit in the upper level memory 2, if the value of the access count log corresponding to the access target data is equal to or greater than a predetermined value, the access target data is stored in the upper level memory 2.
[0014]
According to another aspect of the present invention, there is provided a cache management device for controlling a cache process in response to an access request from a CPU, comprising: an upper level memory connected to the CPU; A counter for counting the number of accesses, a lower level memory connected to the CPU and the upper level memory for storing data corresponding to each data stored in the upper level memory, and an access request output by the CPU. When the specified access target data hits the upper level memory, the value of the counter corresponding to the access target data is counted up, and when the access request is a data write request, the data is transferred to the upper level memory. Write, and the access request is a data write And a memory controller for writing data to the lower-level memory when the value of the counter of the access target data is equal to or smaller than the predetermined value. Is done.
[0015]
According to such a cache management device, when the access target data specified by the access request output by the CPU hits the upper level memory, the value of the counter corresponding to the access target data is counted up. When the access request is a data write request, data is written to the upper level memory. Further, when the access request is a data write request and the value of the counter of the data to be accessed is equal to or smaller than a predetermined value, data is written to the lower-level memory.
[0016]
Further, in order to solve the above-described problem, a cache process is controlled in response to an access request from a CPU to an upper-level memory and a lower-level memory that stores data corresponding to data stored in the upper-level memory. A cache memory management method, when an access target data specified by an access request output by the CPU hits the upper level memory, increments a counter value corresponding to the access target data, and When the data to be replaced in is invalidated, the value of the counter corresponding to the data to be replaced is set in an access count log corresponding to the data to be replaced in the lower level memory, and the data to be accessed is When a miss occurs in the upper level memory, the lower If the value of the access count log of the access target data within the bell memory is greater than a predetermined value, storing the access target data to the upper level memory, the cache memory management method, characterized in that there is provided.
[0017]
According to such a cache memory management method, the number of accesses to each data is counted in the upper level memory. The access count of the replacement target data invalidated in the upper level memory is set in the access count log of the lower level memory. When a miss occurs in the upper-level memory, if the value of the access count log corresponding to the access target data is equal to or more than a predetermined value, the access target data is stored in the upper-level memory.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, an outline of the invention applied to the embodiment will be described, and then, specific contents of the embodiment will be described.
[0019]
FIG. 1 is a conceptual diagram of the invention applied to the embodiment. As shown in FIG. 1, the cache management device controls data input / output between the CPU 1, the upper level memory 2, and the lower level memory 3. That is, the cache management device controls a cache process in response to an access request from the CPU 1. The upper level memory 2 is a cache memory. Further, the lower-level memory 3 may be a main memory or a secondary cache memory.
[0020]
The upper level memory 2 is connected to the CPU 1. The upper level memory 2 is provided with tag information 2a. The tag information 2a is provided with a tag 2b for each input / output unit data stored in the upper level memory 2, and the tag 2b is associated with a counter 2c. In the tag 2b, information such as a memory address of corresponding data is set.
[0021]
The counter 2c counts the number of times of accessing each data stored in the upper level memory 2. Note that the number of accesses can be counted in units of blocks. The block referred to here is a processing unit in the cache processing. That is, the data is stored in the upper-level memory 2 in units of blocks composed of a plurality of data.
[0022]
The lower-level memory 3 is connected to the CPU 1 and the upper-level memory 2 and stores data corresponding to each data stored in the upper-level memory 2. That is, part of the data stored in the lower level memory 3 is also stored in the upper level memory 2. The corresponding data is data having a common memory address. The lower level memory 3 is provided with tag information 3a. The tag information 3a is provided with a tag 3b for each data stored in the lower-level memory 3, and the tag 3b is associated with an access count log 3c.
[0023]
The access count log 3c is provided in association with each data stored in the lower level memory 3. The access count log 3c is provided, for example, for each block. The access count log 3c stores the access count for the corresponding data. This access count is at least the number of accesses made on the upper level memory 2.
[0024]
When the access target data specified by the access request output from the CPU 1 hits the upper level memory 2, the memory controller 1a counts up the value of the counter 2c corresponding to the access target data. When invalidating the replacement target data in the upper level memory 2, the memory controller 1 a stores the value of the counter 2 c corresponding to the replacement target data in the access count log 3 c corresponding to the replacement target data in the lower level memory 3. Set to. Note that the replacement target data in the upper level memory 2 is invalidated when data in the lower level memory 3 is taken into the upper level memory 2 in a state where there is no free space in the upper level memory 2.
[0025]
Further, when the data to be accessed mis-hits the upper level memory 2 and the value of the access count log 3c of the data to be accessed in the lower level memory 3 is larger than a predetermined value, the memory controller 1a Store in memory.
[0026]
According to such a cache management device, the number of times of accessing each data in the upper level memory 2 is counted. The access count of the replacement target data invalidated in the upper level memory 2 is set in the access count log 3c of the lower level memory 3. Then, in the case of a mishit in the upper level memory 2, if the value of the access count log 3c corresponding to the access target data is larger than a predetermined value, the access target data is stored in the upper level memory 2. That is, even if a miss occurs in the upper-level memory 2, if the value of the access count log 3c corresponding to the data to be accessed is equal to or smaller than the predetermined value, the data to be accessed is not stored in the upper-level memory 2.
[0027]
In this way, the number of accesses on the upper level memory 2 is counted, and after the data is evicted from the upper level memory 2, only when the number of accesses is greater than the predetermined value, the lower level memory 3 is transferred to the upper level memory 2. Added caching. Therefore, caching limited to highly reusable data becomes possible. That is, by knowing whether reusability is good or bad when a mishit occurs, it is possible to dynamically switch whether or not to put the data in the cache memory. As a result, waste of storage resources and waste of time due to block transfer can be prevented.
[0028]
The above processing may be applied only to data reference (read), or may be applied to both data read and write. When applied to a data write access request, the data write mode is switched. That is, a method of taking data into the upper level memory 2 when a data write miss occurs (a write allocating method) and a method of not taking data into the upper level memory 2 even when a data miss occurs during a data write (a no write allocating method). Can be switched. Thereby, according to the value of the access count log 3c indicating the reusability of the block, it is possible to dynamically select a more appropriate one of the write allocate method and the no write allocate method as the operation at the time of a write miss. Become.
[0029]
Also, if the number of times of data writing to the upper level memory is counted by a counter, the frequency of data writing can be obtained. By utilizing this, it is possible to select a more appropriate one of the write-through method and the write-back method as a method at the time of writing to the data, according to the data listening frequency.
[0030]
Further, in a system in which the lower-level memory 3 is shared by a plurality of CPUs, an access count log corresponding to each CPU can be associated with a tag of the lower-level memory. This allows the lower-level memory 3 to record how many times the CPU has referred to the block. As a result, for each data, the number of accesses during staying in the upper level memory can be known for each CPU. If the number of accesses for each CPU can be known, blocks with low reusability from each CPU can be detected, and the effectiveness of caching can be determined. When it is determined that the block is not valid, caching of the block is suppressed for each CPU, so that block transfer due to caching and eviction of a valid block from the cache memory can be avoided.
[0031]
Hereinafter, embodiments of the present invention will be specifically described. In the embodiment, the number of accesses is counted for each block which is a processing unit of the cache processing. In the system described in the embodiment, a two-stage cache memory (a primary cache and a secondary cache) is provided between the CPU and the main storage device, and data between the primary cache and the secondary cache is stored. The present invention is applied to input / output control.
[0032]
[First Embodiment]
FIG. 2 is a diagram illustrating an example of a system configuration according to the first embodiment. This example is an example of a computer system in which a plurality of CPU modules each having a two-stage cache memory are mounted. Each CPU module has a CPU 110, 210, 310, 410, respectively. Here, the identifier of the CPU 110 is “CPU0”, the identifier of the CPU 210 is “CPU1”, the identifier of the CPU 310 is “CPU2”, and the identifier of the CPU 410 is “CPU3”.
[0033]
A primary cache 120 for CPU0 and a secondary cache 130 for CPU0 are connected to the CPU110. The CPU 110 has a built-in memory controller 111. The memory controller 111 controls import of data to the CPU 110 and writing of data. The primary cache 120 for CPU0 has tag information 121. The tag information 121 is information for managing data stored in a storage area in the primary cache 120 in block units. The secondary cache 130 for CPU0 has tag information 131. The tag information 131 is information for managing data stored in the storage area in the secondary cache 130 in block units.
[0034]
The CPU 210 is connected with a primary cache 220 for the CPU 1 and a secondary cache 230 for the CPU 1. The CPU 210 has a memory controller 211. The primary cache 220 has tag information 221. The secondary cache 230 has tag information 231.
[0035]
A primary cache 320 for the CPU 2 and a secondary cache 330 for the CPU 2 are connected to the CPU 310. The CPU 310 has a memory controller 311. The primary cache 320 has tag information 321. The secondary cache 330 has tag information 331.
[0036]
A primary cache 420 for the CPU 2 and a secondary cache 430 for the CPU 2 are connected to the CPU 410. The CPU 410 has a memory controller 411. The primary cache 420 has tag information 421. The secondary cache 430 has tag information 431.
[0037]
Each of the secondary caches 130, 230, 330, and 430 is connected to the main storage device 10.
The primary caches 120, 220, 320, and 420 are memories that can be accessed faster than the secondary caches 130, 230, 330, and 430. The secondary caches 130, 230, 330, and 430 are memories that can be accessed faster than the main storage device 10.
[0038]
FIG. 3 is a diagram illustrating a data structure example of tag information of the primary cache. FIG. 3 representatively shows tag information 121 of primary cache 120 for CPU0. In the tag information 121, tags 122a, 122b,... Are provided for each block in the primary cache 120. The tags 122a, 122b,... Indicate the addresses (block frame addresses) of the data stored in the corresponding blocks. Are associated with the tags 122a, 122b,... And the counters 124a, 124b,.
[0039]
The states 123a, 123b,... Are information indicating the states of the data stored in the corresponding blocks. For example, whether data is valid, whether data is written, and the like are set. The contents of the states 123a, 123b,... Are set by the memory controller 111 in the CPU 110.
[0040]
Each of the counters 124a, 124b,... Is set to a numerical value (access number information) indicating the number of times the data stored in the corresponding block has been accessed (referenced or written). The values of the counters 124a, 124b,... Are updated by the memory controller 111 in the CPU 110. Specifically, the values of the counters 124a, 124b,... Are incremented by one each time data in the corresponding block is accessed.
[0041]
FIG. 3 shows an example of the tag information 121 of the primary cache 120 for the CPU 0, but the tag information 221, 321 and 421 for the other CPUs have the same data structure.
[0042]
FIG. 4 is a diagram illustrating a data structure example of tag information of the secondary cache. FIG. 4 representatively shows tag information 131 of the secondary cache 130 for CPU0. In the tag information 131, tags 132a, 132b,... Are provided for each block in the secondary cache 130. Tags 132a, 132b,... Indicate addresses (block frame addresses) of data stored in corresponding blocks. The statuses 133a, 133b,... And the access count logs 134a, 134b,.
[0043]
The states 133a, 133b, ... are information indicating the states of the data stored in the corresponding blocks. For example, whether data is valid, whether data is written, and the like are set. The contents of the states 133a, 133b,... Are set by the memory controller 111 in the CPU 110.
[0044]
Each of the access count logs 134a, 134b,... Stores a numerical value (reference count) indicating the number of times data stored in the corresponding block has been accessed on the primary cache. The values of the access count logs 134a, 134b,... Are updated by the memory controller 111 in the CPU 110. Specifically, when the corresponding block is evicted from the primary cache 120, the value of the counter in the primary cache 120 of the block is added to the value of the access count logs 134a, 134b,.
[0045]
FIG. 4 shows an example of the tag information 131 of the secondary cache 130 for CPU0, but the tag data 231, 331 and 431 for other CPUs have the same data structure.
[0046]
Using such tag information, the memory controllers 111, 211, 311 and 411 control data access processing. Hereinafter, the contents of the data access process according to the access request will be described using an example of the memory controller 111. In the following example, it is assumed that data to be accessed is stored in the secondary cache 130.
[0047]
FIG. 5 is a flowchart illustrating a procedure of an access process according to the first embodiment. Hereinafter, the processing illustrated in FIG. 5 will be described along with step numbers.
[Step S11] The memory controller 111 receives a data reference access request from the CPU 110.
[0048]
[Step S12] The memory controller 111 determines whether or not the primary cache 120 has been hit. That is, it is determined whether or not the address specified in the access request exists in the primary cache 120. Specifically, the memory controller 111 compares the block frame address portion of the address specified by the access request with each of the tags 121a, 121b,... In the tag information 121. If there is a tag having a matching value, it is determined that the primary cache 120 has been hit.
[0049]
If the primary cache 120 has been hit, the process proceeds to step S13. If the primary cache 120 has not been hit (miss hit), the process proceeds to step S15.
[0050]
[Step S13] The memory controller 111 reads data from the primary cache 120. Specifically, the memory controller 111 reads the data at the address specified by the access request from the corresponding block in the primary cache. The position of the corresponding data in the block can be determined by the offset address portion (the value obtained by removing the block frame address from the address) in the address. The read data is passed to the CPU 110.
[0051]
[Step S14] The memory controller 111 updates (counts up by 1) a counter corresponding to the block to be accessed in the primary cache 120. Thereafter, the process ends.
[0052]
[Step S15] When there is a mishit in the primary cache 120, the memory controller 111 compares the value (N2) of the access count log of the corresponding block of the secondary cache 130 with a preset threshold (T). If the value (N2) of the access count log is larger than the threshold (T), the process proceeds to step S17. If the value (N2) of the access count log is equal to or smaller than the threshold (T), the process proceeds to step S16.
[0053]
[Step S16] If the value (N2) of the access count log is equal to or smaller than the threshold (T), the blocks are not replaced. Therefore, the memory controller 111 reads data from the secondary cache 130 and passes the data to the CPU 110. Thereafter, the process ends.
[0054]
[Step S17] If the value (N2) of the access count log is larger than the threshold (T), the blocks are replaced. Therefore, the memory controller 111 first refers to the counter of each block of the primary cache 120.
[0055]
[Step S18] The memory controller 111 selects one block corresponding to the counter having the smallest value among the counters of the blocks of the primary cache 120, and drives out the block. The eviction of a block is to invalidate the block so that another block can be stored. For example, a value indicating invalid is set in the state of the corresponding block.
[0056]
[Step S19] The memory controller 111 adds the value of the counter in the tag information 121 in the primary cache 120 of the evicted block to the access count log in the tag information 131 in the secondary cache 130 of the evicted block.
[0057]
[Step S20] The memory controller 111 reads the data at the address specified by the access request from the secondary cache 130 and passes the data to the CPU 110. [Step S21] The memory controller 111 writes the block to be accessed to the primary cache 120. The writing location is the area where the block that was evicted in step S18 was stored. Thereafter, the process ends.
[0058]
As described above, when a read miss occurs in the primary cache 120 and there is access to the secondary cache 130, if the counter value in the secondary cache 130 is large, the block is referred to more (the reference frequency is higher). It is determined and put into the primary cache 120. If the counter value is small, it is determined that the block is not referred to much (the reference frequency is low), and the data is sent directly to the CPU 110 without entering the primary cache 120.
[0059]
In the related art, when a miss occurs in the primary cache, it is general that the least recently referenced block is evicted by referring to an LRU (Least Recently Used) table. Each block is shown in the LRU table, and is arranged according to the elapsed time since the most recent access. This LRU table is rearranged when the primary cache is hit. As described above, when the block to be evicted is determined with reference to the LRU table, even if the block has a high access frequency, the block is accidentally evicted if there is enough space from the most recent access.
[0060]
As in the first embodiment, a block with a low access frequency in the past is evicted, so that a block with a high access frequency can be continuously held in the primary cache.
[0061]
Next, a description will be given of an example of updating tag information in a case where a large number of accesses have been made to an arbitrary block and in a case where the block information has not been frequently accessed.
FIG. 6 is a diagram illustrating an example of updating tag information when many accesses are made on the primary cache. In this example, when the counter is 3 bits (counts up to a maximum of 7), the change of the content of the tag information when the number of times of reference on the primary cache 120 is large is shown in chronological order.
[0062]
(ST1) Here, it is assumed that the primary cache 120 and the secondary cache 130 miss-hit and block transfer occurs. In this case, the corresponding block is stored in the primary cache 120 and the secondary cache 130. Thus, the tag 122a, the state 123a, and the counter 124a corresponding to the stored block are registered in the tag information 121 of the primary cache 120. Similarly, in the tag information 131 of the secondary cache 130, a tag 132a, a state 133a, and an access count log 134a corresponding to the stored block are registered. At this time, the counter 124a of the written block is reset to 0. Thereafter, the value of the counter 124a is incremented every time the CPU 110 refers to the value.
[0063]
(ST2) If the corresponding block is accessed seven times or more, the count value in the tag information 121 of the primary cache 120 becomes 7 (upper limit).
(ST3) When the corresponding block is evicted from the primary cache 120, the value of the access count log 134a on the secondary cache 130 is updated to 7. That is, the value of the counter 124a in the primary cache 120 of the evicted block is added to the access count log 134a in the secondary cache 130 of the block.
[0064]
Thereafter, when the block in the secondary cache 130 is accessed due to a read miss in the primary cache 120, the access count log 134a is referred to. If the value (N2) of the access count log 134a is larger than the threshold value (T), it is determined that there is reusability when placed on the primary cache 120, and block transfer to the primary cache 120 is permitted. As a result, the data specified by the access request is sent to the CPU 110, and the block containing the data is transferred to the primary cache 120.
[0065]
FIG. 7 is a diagram illustrating an example of updating tag information when the number of accesses on the primary cache is small. In this example, when the counter is 3 bits (counts up to a maximum of 7), the change of the content of the tag information when the number of accesses on the primary cache 120 is small is shown in a time series.
[0066]
(ST11) A block transfer occurs due to a mishit in the primary cache 120 and the secondary cache 130, and a block is stored in the primary cache 120 and the secondary cache 130. The value of the counter 124a of the block stored in the primary cache 120 is reset to zero. The value of the access count log 134a of the block stored in the secondary cache 130 is reset to 0.
[0067]
(ST12) When the corresponding block is not accessed, the count value remains 0.
(ST13) When the relevant block is evicted from the primary cache 120, the value of the access count log 134a on the secondary cache 130 is not changed and remains “0”.
[0068]
Thereafter, when the block in the secondary cache 130 is accessed due to a mishit in the primary cache 120, the access count log 134a is referred to. If the value (N2) of the access count log 134a is equal to or less than the threshold value (T), it is determined that there is no reusability when placed on the primary cache 120, block transfer to the primary cache 120 is prohibited, and data is directly transmitted to the CPU 110. Sent.
[0069]
In this way, by storing only the blocks having high reusability in the upper cache, the processing efficiency and the cache hit rate can be improved.
That is, even if a non-reusable block is put in the cache, the effect cannot be obtained. Conversely, it takes time and bus bandwidth to transfer blocks, resulting in performance degradation. Therefore, as shown in the first embodiment, by counting the number of times a block is accessed when stored in the primary cache and associating the number of accesses even when the block is evicted from the secondary cache, Blocks having no reusability can be determined from the secondary cache. As a result, useless block transfer can be suppressed, and time and bus usage bandwidth can be saved.
[0070]
In addition, in the conventional technique, a block having no reusability is stored in the primary cache, and a block having reusability may be expelled instead. In the first embodiment, since blocks without reusability are not put in the cache, blocks with reusability can be kept in the primary cache. As a result, the cache hit rate is improved.
[0071]
In the first embodiment, the number of times of data read (reference) and data write (write) access to a block is counted, but only the data read access request may be counted. For example, when the write-through method is fixedly adopted as the data writing method, it can be determined that the reusability is low if the frequency of reference to the block is low, even if the frequency of writing to a certain block is high.
[0072]
[Second embodiment]
Next, a second embodiment will be described. The second embodiment is an example of a computer in which individual primary caches are mounted on a plurality of CPU modules and a shared secondary cache is separately provided.
[0073]
FIG. 8 is a diagram illustrating an example of a system configuration of a computer according to the second embodiment. In this example, each CPU module has a CPU 610, 710, 810, 910, respectively. Here, the identification information of the CPU 610 is “CPU0”, the identification information of the CPU 710 is “CPU1”, the identification information of the CPU 810 is “CPU2”, and the identification information of the CPU 910 is “CPU3”.
[0074]
The CPU 610 is connected to the primary cache 620 for the CPU 0. The CPU 610 has a built-in memory controller 611. The memory controller 611 controls taking in of data and writing of data to the CPU 610. The primary cache 620 for CPU0 has tag information 621. The tag information 621 is information for managing data stored in a block-based storage area in the primary cache 620.
[0075]
A primary cache 720 for the CPU 1 is connected to the CPU 710. The CPU 710 has a memory controller 711. The primary cache 720 has tag information 721.
[0076]
A primary cache 820 for the CPU 2 is connected to the CPU 810. The CPU 810 has a memory controller 811. The primary cache 820 has tag information 821.
[0077]
A primary cache 920 for the CPU 3 is connected to the CPU 910. The CPU 910 has a memory controller 911. The primary cache 920 has tag information 921.
[0078]
Each of the primary caches 620, 720, 820, 920 is connected to the secondary cache 20. The secondary cache 20 has tag information 21. The secondary cache 20 is connected to the main storage device 30.
[0079]
The primary caches 620, 720, 820, 920 are memories that can be accessed at a higher speed than the secondary cache 20. The secondary cache 20 is a memory that can be accessed faster than the main storage device 30.
[0080]
Here, the data structure of the tag information 621, 721, 821, 921 of each primary cache 620, 720, 820, 920 is the same as that of the tag information 121 in the first embodiment shown in FIG. On the other hand, the tag information 21 of the secondary cache 20 is provided with a storage area of a counter indicating the reference frequency in the plurality of primary caches 620, 720, 820, 920.
[0081]
FIG. 9 is a diagram illustrating a data structure example of tag information of the secondary cache. In the tag information 21, tags 22a, 22b,... Are provided for each block in the secondary cache 20. The tags 22a, 22b,... Indicate the addresses (block frame addresses) of the data stored in the corresponding blocks. The status 22a and a plurality of access count logs 24a, 25a, 26a, 27a are associated with the tag 22a. Similarly, a state 23b and a plurality of access count logs 24b, 25b, 26b, 27b are associated with the tag 22b.
[0082]
The states 23a, 23b, ... are information indicating the states of data stored in the corresponding blocks. For example, whether data is valid, whether data is written, and the like are set. The contents of the states 23a, 23b,... Are set by the memory controllers 611, 711, 811 and 911 in the CPUs 610, 710, 810 and 910.
[0083]
In the access count log, a numerical value (access frequency information) indicating the number of times data stored in the corresponding block has been accessed is set. Here, the access count logs 24a, 24b,... Are values indicating the number of accesses from the CPU 610 to the corresponding block between the primary cache 620 and the secondary cache 20. The access count logs 25a, 25b,... Are values indicating the number of accesses from the CPU 710 to the corresponding block between the primary cache 720 and the secondary cache 20. The access count logs 26a, 26b,... Are values indicating the number of accesses from the CPU 810 to the corresponding blocks of the primary cache 820 and the secondary cache 20. The access count logs 27a, 27b,... Are values indicating the number of accesses from the CPU 910 to the corresponding block between the primary cache 920 and the secondary cache 20. As described above, the number of accesses from each CPU to each block is associated with each tag.
[0084]
The values of the access count logs 24a, 24b,... Are updated by the memory controller 611 in the CPU 610. Specifically, when the corresponding block is evicted from the primary cache 620, the value of the counter in the primary cache 620 of the block is added to the value of the access count logs 24a, 24b,. Then, when the secondary cache 20 is accessed from the CPU 610, the value of the access count log corresponding to the accessed block is counted up.
[0085]
Similarly, the values of the counters 25a, 25b,... Are updated by the memory controller 711 in the CPU 710. The values of the counters 26a, 26b,... Are updated by the memory controller 811 in the CPU 810. The values of the counters 27a, 27b,... Are updated by the memory controller 911 in the CPU 910.
[0086]
As described above, the updating of the counter is performed by the memory controllers 611, 711, 811 and 911 in accordance with the memory access from the CPUs 610, 710, 810 and 910. The processing of the memory controllers 611, 711, 811 and 911 at that time is the same as the processing of the first embodiment shown in FIG.
[0087]
Next, a description will be given of an example of updating tag information in a case where a large number of accesses have been made to an arbitrary block and in a case where the block information has not been frequently accessed.
FIG. 10 is a diagram illustrating an example of updating tag information when many accesses are made on the primary cache. In this example, when the counter is 3 bits (counts up to a maximum of 7), a change in the contents of the tag information when the number of accesses on the primary cache 620 is large is shown in chronological order.
[0088]
(ST21) Here, it is assumed that a mishit occurs in the primary cache 620, block transfer occurs, and data is stored in the primary cache 620. In this case, the corresponding block is stored in the primary cache 620. As a result, the tag 622a, the state 623a, and the counter 624a corresponding to the block stored in the primary cache 620 are registered in the tag information 621. Similarly, the tag 22a, the state 23a, and the counter 24a corresponding to the block stored in the secondary cache 20 are registered in the tag information 21. At this time, the counter of the written block is reset to 0. Thereafter, the value of the counter 624a is incremented every time the CPU 610 refers to the value.
[0089]
(ST22) If the block is accessed seven times or more for reference, the count value in the tag information 621 of the primary cache 620 becomes 7 (upper limit).
[0090]
(ST23) When the corresponding block is evicted from the primary cache 620 or invalidated by the cache protocol, the value of the access count log 24a on the secondary cache 20 is updated to 7. That is, the value of the counter 624a in the primary cache 620 of the evicted block is added to the access count log 24a in the secondary cache 20 of the block.
[0091]
(ST24) Similarly, in the other CPUs 710, 810, and 910, the corresponding block is accessed seven times or more for reference, etc., and is ejected from the primary caches 720, 820, 920 or invalidated by the cache protocol. , The values of the counters 25a, 26a, 27a on the secondary cache 20 are updated to 7.
[0092]
Thereafter, when the block in the secondary cache 20 is accessed due to a read miss in the primary cache 620 for the CPU0, the value of the access count log 24a for the CPU0 is referred to, and the data is stored in the primary cache 620 or It is determined whether data is sent directly to CPU 610 without entering cache 620. In the example of FIG. 10, since the value of the access count log 24a is "7", it is determined that there is reusability when it is placed in the primary cache 620, and block transfer to the primary cache 620 is permitted.
[0093]
FIG. 11 is a diagram illustrating an example of updating tag information when the number of accesses on the primary cache is small. In this example, when the counter is 3 bits (counts up to a maximum of 7), the change of the content of the tag information when the number of accesses on the primary cache 620 is small is shown in a time series.
[0094]
(ST31) In response to a read request from the CPU 610, a mishit occurs in the primary cache 620 to cause block transfer, and a block is stored in the primary cache 620. The value of the counter 624a of the corresponding block is reset to 0.
[0095]
(ST32) When the CPU 610 does not access the corresponding block such as reference, the count value remains 0.
(ST33) The corresponding block is evicted from the primary cache 620, or the block is invalidated by the cache protocol. In this case, the value of the access count log 24a for the CPU 0 on the secondary cache 20 remains 0.
[0096]
(ST34) Here, it is assumed that there have been many (seven or more) accesses from other CPUs 710, 810, 910, such as referring to the corresponding block. Then, when the corresponding block is evicted from the primary cache 720, 820, 920 of each of the CPUs 710, 810, 910 or is invalidated, the access count logs 25a, 26a, 27a corresponding to the respective blocks in the secondary cache 20 are stored. Be updated. In this example, the values of the access count logs 25a, 26a, 27a are all "7".
[0097]
Thereafter, when there is an access to the block on the secondary cache 20 due to a mishit in the primary cache 620 in response to a read request from the CPU 610, the access count log 24a is referred to. If the value (N2) of the access count log 24a is equal to or less than the threshold value (T), it is determined that there is no reusability when placed on the primary cache 620, block transfer to the primary cache 620 is prohibited, and data is directly transmitted to the CPU 610. Sent.
[0098]
As described above, even when the secondary cache 20 is shared, the access frequency log for each CPU is associated with the tag information 21 of the secondary cache 20 so that the reference frequency for each CPU can be known. . As a result, when each CPU accesses the secondary cache, it is possible to determine whether to store the data in the primary cache according to the frequency of reference to the corresponding block in the CPU.
[0099]
[Third Embodiment]
Next, a third embodiment will be described. The third embodiment is based on the configuration shown in the first embodiment, and counts the frequency of access to blocks in the secondary cache.
[0100]
That is, in the first embodiment, the access count log is associated with the tag for each block of the secondary caches 130, 230, 330, and 430. The access count log is updated when the corresponding block is evicted from the primary cache, and is not updated even if the secondary cache is accessed. Therefore, when the value of the access count log is small, there is no chance that the corresponding block is taken from the secondary cache to the primary cache. If the corresponding block is also evicted from the secondary cache, the access to the corresponding block is made to the main storage device, and can be taken into the primary cache and the secondary cache.
[0101]
Therefore, in the third embodiment, the number of accesses in each block on the secondary cache is counted and added to the number of accesses in the primary cache (the value of the access count log in the first embodiment).
[0102]
The system configuration according to the third embodiment is substantially the same as the configuration according to the first embodiment shown in FIG. However, the data structure of the tag information in the secondary cache and the processing of the memory controller are different. Hereinafter, the data structure of the tag information in the secondary cache 130 for the CPU 0 will be described using the reference numerals of the respective elements (excluding the secondary cache tag information) of the first embodiment shown in FIG.
[0103]
FIG. 12 is a diagram illustrating an example of tag information of the secondary cache according to the third embodiment. FIG. 12 representatively shows the tag information 131a of the secondary cache 130 for CPU0.
[0104]
In the tag information 131a, tags 132c, 132d,... Are provided for each block in the secondary cache 130. The tags 132c, 132d,... Indicate the addresses (block frame addresses) of the data stored in the corresponding blocks. Are associated with the tags 132c, 132d,... And the counters 134c, 134d,.
[0105]
The states 133c, 133d,... Are information indicating the states of the data stored in the corresponding blocks. For example, whether data is valid, whether data is written, and the like are set. The contents of the states 133c, 133d,... Are set by the memory controller 111 in the CPU 110.
[0106]
Each of the counters 134c, 134d,... Is set with a numerical value (access number information) indicating the number of times data stored in the corresponding block in the secondary cache 130 has been accessed (referenced or written). Further, when the corresponding block is evicted from the primary cache, the counters 134c, 134d,... Are incremented by a numerical value (the number of references) indicating the number of times the block has been accessed on the primary cache. The values of the counters 134c, 134d,... Are updated by the memory controller 111 in the CPU 110.
[0107]
As described above, the access count log associated with each block of the secondary cache 130 in the first embodiment is replaced by the counters 134c and 134d in the third embodiment. The function of each of the counters 134c and 134d is a function of storing information, similarly to the function of the access count log, but is called a counter because it is counted up according to access to the secondary cache.
[0108]
FIG. 13 is a flowchart illustrating a procedure of an access process of the memory controller according to the third embodiment. Since this flowchart is almost the same as the access processing of the first embodiment shown in FIG. 5, the same processing is denoted by the same step number, and the description is omitted.
[0109]
In the third embodiment, the process of step S15 in FIG. 5 is changed as follows.
[Step S31] When a miss occurs in the primary cache 120, the memory controller 111 compares the counter value (N2) of the corresponding block of the secondary cache 130 with a preset threshold (T). If the value (N2) of the access count log is larger than the threshold (T), the process proceeds to step S17. If the value of the access count log (N2) is equal to or smaller than the threshold (T), the process proceeds to step S16.
[0110]
Further, in the third embodiment, processing after reading data from the secondary cache 130 is different from that of the first embodiment. That is, in the first embodiment, when data is read from the secondary cache 130, the process ends (step S16), but in the third embodiment, the following step S31 follows the processing of step S16. Is performed.
[0111]
[Step S32] The memory controller 111 updates the counter of the secondary cache. That is, the value of the counter corresponding to the block in which the read target data is stored is increased by one. Thereafter, the process ends.
[0112]
Further, in the third embodiment, the process of step S19 in FIG. 5 is changed as follows.
[Step S32] The memory controller 111 adds the value of the counter of the block evicted from the primary cache 120 to the counter of the corresponding block in the secondary cache 130.
[0113]
As described above, in the third embodiment, all of the tags of the primary cache and the secondary cache include the counter for recording the number of accesses, and this count value is set each time the cache is referred to in each cache. Increased by one. Thereafter, when a secondary cache access occurs due to a primary cache read miss, the CPU counter value on the secondary cache is looked at, and the data is placed in the primary cache or directly to the CPU without entering the primary cache. It is determined whether to send data.
[0114]
As a result, in the first embodiment, a block that has been determined not to be reusable on the secondary cache cannot be reversed without leaving the secondary cache and cannot enter the primary cache. . On the other hand, in the third embodiment, similarly to the primary cache, when the secondary cache is accessed, the counter on the secondary cache is increased. Therefore, even if a block is determined to have no reusability, if it is accessed a lot on the secondary cache, it can be transferred to the primary cache when a read miss occurs.
[0115]
[Fourth Embodiment]
Next, a fourth embodiment will be described. The fourth embodiment is based on the configuration shown in the second embodiment, and counts the frequency of access to blocks in the secondary cache.
[0116]
That is, in the second embodiment, the access count log is associated with the tag of each block of the secondary cache 20. The access count log is updated when the corresponding block is evicted from the primary cache, and is not updated even if the secondary cache is accessed. Therefore, when the value of the access count log is small, there is no chance that the corresponding block is taken from the secondary cache to the primary cache. If the corresponding block is also evicted from the secondary cache, the access to the corresponding block is made to the main storage device, and can be taken into the primary cache and the secondary cache.
[0117]
Therefore, in the fourth embodiment, the number of accesses in each block on the secondary cache is added to the number of accesses in the primary cache (the value of the access count log in the first embodiment) and counted.
[0118]
The system configuration of the fourth embodiment is almost the same as the configuration of the second embodiment shown in FIG. However, the data structure of the tag information in the secondary cache and the processing of the memory controller are different. The data structure of the tag information in the fourth embodiment is as follows.
[0119]
FIG. 14 is a diagram illustrating an example of tag information of the secondary cache according to the fourth embodiment.
In the tag information 21a, tags 22c, 22d,... Are provided for each block in the secondary cache 20. The tags 22c, 22d,... Indicate the addresses (block frame addresses) of the data stored in the corresponding blocks. Are associated with the tags 22c, 22d,... And the counters 24c, 24d,.
[0120]
The states 23c, 23d,... Are information indicating the states of the data stored in the corresponding blocks. For example, whether data is valid, whether data is written, and the like are set. The contents of the states 23c, 23d,... Are set by the memory controller 611 in the CPU 610.
[0121]
Each of the counters 24c, 24d,... Is set to a numerical value (access frequency information) indicating the number of times data stored in the corresponding block in the secondary cache 20 has been accessed (referenced or written). The values of the counters 24c, 24d,... Are updated by the memory controller 611 in the CPU 610. Specifically, the values of the counters 24c, 24d,... Are incremented by one each time data in the corresponding block is referred to.
[0122]
The processing of the memory controller according to the fourth embodiment is the same as the access processing according to the third embodiment shown in FIG.
As described above, each block of the primary cache and the secondary cache has a tag as shown in FIGS. 3 and 14, respectively. All primary cache and secondary cache tags include a counter that records the number of accesses, and this count value is incremented by one each time the block is referenced in each cache. When the block is evicted from the primary cache or invalidated by the cache protocol, this value is added to the counter for the CPU in the secondary cache.
[0123]
Then, when a secondary cache access occurs due to a primary cache read miss, the CPU counter value on the secondary cache is checked and the data is placed in the primary cache or the data is directly sent to the CPU without entering the primary cache. Judge whether to send.
[0124]
In the second embodiment, a block determined to be non-reusable on the secondary cache cannot be reversed unless leaving the secondary cache, and cannot enter the primary cache. On the other hand, in the fourth embodiment, similarly to the primary cache, when the secondary cache is accessed, the counter on the secondary cache is increased (for example, when the secondary cache is accessed by a request from CPU 0). By increasing the value of the counter corresponding to CPU0), even if a block is determined to have no reusability, it can be transferred to the primary cache upon a read miss if a large number of accesses are made on the secondary cache. .
[0125]
[Fifth Embodiment]
Next, a fifth embodiment will be described. In the fifth embodiment, based on the first embodiment, a processing method when a write miss occurs in the primary cache is determined according to the number of block accesses in the primary cache.
[0126]
The processing method when a write miss occurs includes, for example, a write allocate and a no write allocate. Here, the write allocate is a processing method for loading a block from the secondary cache into the primary cache when a write miss occurs in the primary cache. The no-write allocate is a processing method in which when a write miss occurs in the primary cache, data is read from the secondary cache and the corresponding block is not loaded into the primary cache.
[0127]
The system configuration of the fifth embodiment is almost the same as the configuration of the first embodiment shown in FIG. However, the data write process of the memory controller is different. Note that the processing at the time of data reading (referencing) of the memory controller is the same as that of the first embodiment shown in FIG. Therefore, the processing at the time of data writing in the processing of the memory controller will be described with reference to the configuration shown in FIG.
[0128]
FIG. 15 is a flowchart illustrating a procedure of a write process according to the fifth embodiment. Hereinafter, the processing illustrated in FIG. 15 will be described along the step numbers.
[Step S41] The memory controller 111 receives a data write access request from the CPU 110.
[0129]
[Step S42] The memory controller 111 determines whether or not the primary cache 120 has been hit. That is, it is determined whether or not the address specified in the access request exists in the primary cache 120. If there is a hit in the primary cache 120, the process proceeds to step S43. If the primary cache 120 has not been hit (miss hit), the process proceeds to step S45.
[0130]
[Step S43] The memory controller 111 writes data from the primary cache 120. Specifically, the memory controller 111 writes the data sent from the CPU 110 from the corresponding block in the primary cache to the data area of the address specified by the access request.
[0131]
[Step S44] The memory controller 111 updates the counter of the primary cache 120 corresponding to the block in which the data has been written. That is, the value of the counter is increased by one. Thereafter, the process ends.
[0132]
[Step S45] When there is a mishit in the primary cache 120, the memory controller 111 compares the value (N2) of the access count log of the corresponding block of the secondary cache 130 with a preset threshold (T). If the value of the access count log (N2) is larger than the threshold (T), the process proceeds to step S47. If the value (N2) of the access count log is equal to or smaller than the threshold (T), the process proceeds to step S46.
[0133]
[Step S46] If the value (N2) of the access count log is equal to or smaller than the threshold (T), a no-write allocate process is performed. Therefore, the memory controller 111 writes the data sent from the CPU 110 to the storage area of the data corresponding to the address specified by the write request in the secondary cache 130. Thereafter, the process ends.
[0134]
[Step S47] If the value (N2) of the access count log is larger than the threshold (T), the blocks are replaced. Therefore, the memory controller 111 first refers to the counter of each block of the primary cache 120.
[0135]
[Step S48] The memory controller 111 evicts a block corresponding to one of the counters with the lowest reference frequency among the counters of each block of the primary cache 120.
[0136]
[Step S49] The memory controller 111 adds the value of the counter in the tag information 121 in the primary cache 120 of the evicted block to the access count log in the tag information 131 in the secondary cache 130 of the evicted block. .
[0137]
[Step S50] The memory controller 111 writes the corresponding block of the secondary cache 130 to the area of the primary cache 120 where the flushed block is stored.
[0138]
[Step S51] The memory controller 111 writes the data sent from the CPU 110 to the data area of the address specified by the write request in the primary cache 120. Thereafter, the process ends.
[0139]
As described above, in the fifth embodiment, the counter for recording the number of accesses is associated with the tag of the primary cache, and the count value is incremented by one each time the block is referred to. When the block is evicted from the primary cache, this value is added to the counter of the secondary cache. Thereafter, when a write miss occurs in the primary cache 120 and the secondary cache 130 is accessed, the value of the access count log on the secondary cache 130 is checked to determine whether write allocation or no-write allocation is to be performed. Will be determined.
[0140]
In this way, only blocks having high reusability can be write-allocated. As a result, blocks with high reusability can be preferentially stored in the primary cache, and data access efficiency can be improved.
[0141]
[Sixth Embodiment]
Next, a sixth embodiment will be described. In the sixth embodiment, based on the second embodiment, a processing method when a write miss occurs in the primary cache is determined according to the number of block accesses in the primary cache. The processing method when a write miss occurs includes, for example, a write allocate and a no write allocate.
[0142]
The system configuration according to the sixth embodiment is substantially the same as the configuration according to the second embodiment shown in FIG. However, the data write process of the memory controller is different. Note that the processing at the time of data reading (referencing) of the memory controller is the same as that of the first embodiment shown in FIG. The processing at the time of data writing of the memory controller is the same as that of the fifth embodiment shown in FIG.
[0143]
As a result, all the primary cache tags include a counter that records the number of accesses, and this count value is incremented by one each time the block is referenced. When the block is evicted from the primary cache or invalidated by the cache protocol, this value is added to the counter for the CPU in the secondary cache. Thereafter, when a write miss occurs in the primary cache and there is a secondary cache access, the CPU counter value in the secondary cache is checked to determine whether to perform write allocate or no-write allocate.
[0144]
[Seventh Embodiment]
Next, a seventh embodiment will be described. The seventh embodiment is based on the third embodiment, and determines a processing method when a write miss occurs in the primary cache according to the number of block accesses in the primary cache and the secondary cache. It is. The processing method when a write miss occurs includes, for example, a write allocate and a no write allocate.
[0145]
The system configuration of the seventh embodiment is almost the same as the configuration of the first embodiment shown in FIG. However, the data structure of the tag information of the secondary cache is the same as the tag information of the third embodiment shown in FIG. The processing at the time of data reading (reference) of the memory controller is the same as that of the third embodiment shown in FIG. The processing at the time of data writing of the memory controller is the same as that of the fifth embodiment shown in FIG.
[0146]
Thus, all the primary cache and secondary cache tags include a counter for recording the number of accesses, and this count value is incremented by one each time the cache refers to the block. Thereafter, when a write miss occurs in the primary cache and the secondary cache is accessed, the counter value on the secondary cache is checked to determine whether to perform write allocate or no-write allocate.
[0147]
In the fifth embodiment, a block that has been determined not to be reusable on the secondary cache cannot reverse its determination unless it leaves the secondary cache, and cannot enter the primary cache. Therefore, in the seventh embodiment, similarly to the primary cache, when the secondary cache is accessed, the counter on the secondary cache is increased. As a result, even if a block once determined to have no reusability is accessed a lot on the secondary cache, writing can be performed after transfer to the primary cache at the time of a write miss (write allocate method).
[0148]
[Eighth Embodiment]
Next, an eighth embodiment will be described. In the eighth embodiment, based on the fourth embodiment, a processing method when a write miss occurs in the primary cache is determined according to the number of block accesses in the primary cache and the secondary cache. It is. The processing method when a write miss occurs includes, for example, a write allocate and a no write allocate.
[0149]
The system configuration of the eighth embodiment is almost the same as the configuration of the second embodiment shown in FIG. However, the data structure of the tag information of the secondary cache is the same as the tag information of the fourth embodiment shown in FIG. The processing at the time of data reading (reference) of the memory controller is the same as that of the fourth embodiment shown in FIG. The processing at the time of data writing of the memory controller is the same as that of the fifth embodiment shown in FIG.
[0150]
Thus, all the primary cache and secondary cache tags include a counter for recording the number of accesses, and this count value is incremented by one each time the block is referenced in each cache. When the block is evicted from the primary cache or invalidated by the cache protocol, this value is added to the counter for the CPU in the secondary cache. Thereafter, when a write miss occurs in the primary cache and a secondary cache access occurs, the CPU counter value on the secondary cache is checked to determine whether to perform write allocate or no-write allocate.
[0151]
In the sixth embodiment, a block that has been determined not to be reusable on the secondary cache cannot be reversed unless leaving the secondary cache, and cannot enter the primary cache. Therefore, in the eighth embodiment, similarly to the primary cache, when the secondary cache is accessed, the counter on the secondary cache is increased (for example, the access to the secondary cache is made by a request from the CPU 610). In this case, the value of the counter corresponding to the CPU 610 is increased), so that even if the block is determined to have no reusability, if a large number of accesses are made on the secondary cache, writing is performed after transfer to the primary cache at the time of a write miss. (Light allocation method).
[0152]
[Ninth embodiment]
Next, a ninth embodiment will be described. The ninth embodiment is based on the first embodiment, and dynamically switches a data writing method according to a write request in accordance with the number of block accesses in the primary cache.
[0153]
Data writing methods include, for example, write-back and write-through. Here, in the write-back, data is written to a block of the primary cache in response to a write request. Then, when the block is evicted from the primary cache, the data of the block is written to the secondary cache. In write-through, data is written to both the primary cache and the secondary cache in response to a write request.
[0154]
The system configuration of the ninth embodiment is almost the same as the configuration of the first embodiment shown in FIG. However, the data write process of the memory controller is different. Note that the processing at the time of data reading (referencing) of the memory controller is substantially the same as that of the first embodiment shown in FIG. However, the update process of the primary cache counter in step S14 is not performed. That is, the counters 124a and 124b shown in FIG. 3 are used as counters for counting only the number of times of writing. Similarly, values indicating the number of times of writing are stored in the access number logs 134a and 134b shown in FIG.
[0155]
Therefore, the processing at the time of data writing in the processing of the memory controller will be described with reference to the configuration shown in FIG.
FIG. 16 is a flowchart illustrating the procedure of the write process according to the ninth embodiment. Hereinafter, the processing illustrated in FIG. 16 will be described along with step numbers.
[0156]
[Step S61] The memory controller 111 receives a data write access request from the CPU 110.
[Step S62] The memory controller 111 determines whether or not the primary cache 120 has been hit. That is, it is determined whether or not the address specified in the access request exists in the primary cache 120. If the primary cache 120 has not been hit (miss hit), the process proceeds to step S63. If there is a hit in the primary cache 120, the process proceeds to step S64.
[0157]
[Step S63] If there is a mishit in the primary cache 120, the memory controller 111 writes the data sent from the CPU 110 to a storage area of the secondary cache 130 that stores data corresponding to the address specified by the write request. Thereafter, the process ends.
[0158]
[Step S64] When a hit occurs in the primary cache 120, the memory controller 111 writes data to the primary cache 120. Specifically, the memory controller 111 writes the data sent from the CPU 110 from the corresponding block in the primary cache to the data area of the address specified by the access request.
[0159]
[Step S65] The memory controller 111 updates the counter of the primary cache 120 corresponding to the block in which the data has been written. That is, the value of the counter is increased by one. Thereafter, the process ends.
[0160]
[Step S66] The memory controller 111 compares the counter value (N1) of the corresponding block of the primary cache 120 with a preset threshold value (T1). If the value of the counter (N1) is larger than the threshold value (T1), the write-back method is adopted, and the process ends. If the counter value (N1) is equal to or smaller than the threshold value (T1), the write-through method is adopted, and the process proceeds to step S67.
[0161]
[Step S67] The memory controller 111 writes the data sent from the CPU 110 to the storage area of the data corresponding to the address specified by the write request in the secondary cache 130. Thereafter, the process ends.
[0162]
As described above, the tag of the primary cache includes the counter for recording the write frequency information, and this count value is incremented by one each time a write is performed on the block. When the block is evicted from the primary cache, this value is added to the counter of the secondary cache. Thereafter, when a write request is issued and the primary cache is hit, if the value of the counter is larger than a predetermined threshold value (N), it can be determined that the block is a block to which writing is frequently performed, and writing is performed by a write-back method. Otherwise, writing by the write-through method is performed.
[0163]
As described above, the write-back method and the write-through method can be dynamically changed according to the value (N1) of the counter. For a block that is frequently accessed, the number of times of writing to the secondary cache can be reduced by adopting the write-back method. As a result, the average access time is reduced. In addition, for a block with few accesses, the write-through method can be used to maintain consistency between the primary cache and the secondary cache.
[0164]
In the ninth embodiment, a counter is used to count the number of times of writing data. However, a tag for writing and a counter for reference are provided in the tag information 121 of the primary cache 120. You can also. In this case, the tag information 131 of the secondary cache 130 is provided with an access frequency log for writing and an access frequency log for reference. Thus, in one system, it is possible to determine the writing method according to the number of times of writing and to judge whether writing to the primary cache is necessary according to the number of times of accessing.
[0165]
In the description of the ninth embodiment, it is assumed that the process at the time of data read (reference) of the memory controller is substantially the same as that of the first embodiment shown in FIG. Therefore, when a block is evicted from the primary cache, the counter value of that block is added to the access count log of the corresponding block in the secondary cache. Therefore, when a block is read into the primary cache, the writing method can be determined according to the value of the access count log. In this case, if the value of the access count log is larger than a predetermined threshold, a write-back method is adopted for writing data to the corresponding block read into the primary cache. On the other hand, if the value of the access count log is equal to or smaller than the predetermined threshold, a write-through method is adopted for writing data to the corresponding block read into the primary cache.
[0166]
When a new block is fetched into the primary cache, a write-through method may be adopted as an initial setting of a writing method for the block. If the block has a high frequency of reference, it can be switched to the write-back method when the number of counters exceeds the threshold value.
[0167]
[Tenth embodiment]
Next, a tenth embodiment will be described. In the tenth embodiment, whether or not a block is fetched from the secondary cache into the primary cache is determined using the counter value of the block to be evicted. Specifically, the counter value of the block having the smallest counter value on the primary cache is compared with the value of the access count log of the block to be fetched on the secondary cache. If the value of the access count log of the fetch target block on the secondary cache is larger, the block is fetched into the primary cache.
[0168]
FIG. 17 is a flowchart illustrating a procedure of an access process according to the tenth embodiment. Note that among the processing shown in FIG. 17, processing other than steps S71 and S72 is the same as the access processing in the first embodiment shown in FIG. 5, and thus the same step numbers are assigned and description thereof is omitted.
[0169]
[Step S71] The memory controller 111 refers to the counter of each block in the primary cache 120.
[Step S72] Then, the memory controller 111 sets the block having the smallest counter value among the blocks of the primary cache 120 as the eviction target block. Then, the counter value (N1) of the block is compared with the value (N2) of the access count log of the access target block in the secondary cache 130. If the counter value (N1) of the eviction target block is larger, it is determined that block replacement is unnecessary, and the process proceeds to step S16. If the counter value (N1) of the eviction target block is equal to or less than the access count log value (N2) of the access target block, it is determined that the blocks need to be replaced, and the process proceeds to step S18.
[0170]
In this way, by storing only the blocks having the access count log larger than the minimum counter value of the primary cache in the primary cache, it is possible to take only the blocks with a high access frequency into the primary cache.
[0171]
In each of the above embodiments, the counter is provided for each block which is the minimum unit to be stored in the cache memory control, but the size of this block can be set arbitrarily. Therefore, the size of the block can be made equal to the data length of data input / output to / from the CPU. Generally, the block size is set to a value that minimizes the average access time in the memory access processing.
[0172]
Even if a non-reusable block is cached as in the conventional technology, the effect of increasing the hit ratio cannot be obtained, and conversely, time and bus bandwidth are spent for block transfer, resulting in a decrease in performance. I will. On the other hand, in the present embodiment, useless block transfer can be suppressed by detecting a block having no reusability, and time and the bandwidth used by the bus can be saved.
[0173]
If a non-reusable block is put in the cache, the reusable block may be evicted instead. In the above embodiment, such a case does not occur because a block having no reusability is not cached.
[0174]
The cache writing method is roughly classified into a write-through method and a write-back method. Conventionally, the two cannot be switched, but in the above embodiment, the two can be switched to flexibly handle blocks with many writes, blocks with few writes, and blocks that show both properties depending on time. Can be.
[0175]
(Supplementary Note 1) In a cache management device that controls a cache process according to an access request from a CPU,
An upper level memory connected to the CPU;
A counter for counting the number of accesses to each data stored in the upper level memory;
A lower-level memory connected to the CPU and the upper-level memory and storing data corresponding to each data stored in the upper-level memory;
An access count log provided in association with each data stored in the lower level memory,
When the access target data specified by the access request output by the CPU hits the upper level memory, the value of the counter corresponding to the access target data is counted up, and the replacement target data in the upper level memory is invalidated. When the data is replaced, the value of the counter corresponding to the data to be replaced is set in the access count log corresponding to the data to be replaced in the lower level memory, and the data to be accessed misses the upper level memory. If the value of the access count log of the access target data in the lower level memory is larger than a predetermined value, a memory controller that stores the access target data in the upper level memory;
A cache management device comprising:
[0176]
(Supplementary note 2) The cache memory device according to supplementary note 1, wherein the counter counts the number of accesses for each block that is a minimum unit of storage management of the upper level memory.
[0177]
(Supplementary Note 3) The supplementary note 1, wherein when there are a plurality of CPUs, the CPU includes the upper-level memory, the counter, the lower-level memory, the access count log, and the memory controller corresponding to each of the CPUs. Cache memory device.
[0178]
(Supplementary Note 4) When there are a plurality of CPUs, the CPU includes the upper-level memory, the counter, the access count log, and the memory controller corresponding to each of the CPUs, and the lower-level memory is shared by the plurality of CPUs. 3. The cache memory device according to claim 1, wherein:
[0179]
(Supplementary Note 5) The cache management device according to Supplementary Note 1, wherein the memory controller counts the number of accesses to each data stored in the lower-level memory and adds the number of accesses to the access count log.
[0180]
(Supplementary Note 6) When the access request is a write request, the memory controller determines that the number of accesses of the access target data in the lower level memory is a predetermined number when the access target data miss-hits the upper level memory. 2. The cache management device according to claim 1, wherein if the value is larger than the value, the access target data is stored in the upper level memory.
[0181]
(Supplementary Note 7) The memory controller replaces the value of the access count log of the access target data in the lower level memory in the upper level memory when the access target data misses the upper level memory. 2. The cache management device according to claim 1, wherein the access target data is stored in the upper level memory if the value is larger than a value of a counter corresponding to the data to be accessed.
[0182]
(Supplementary Note 8) In a cache management device that controls a cache process according to an access request from a CPU,
An upper level memory connected to the CPU;
A counter for counting the number of accesses to each data stored in the upper level memory;
A lower-level memory connected to the CPU and the upper-level memory and storing data corresponding to each data stored in the upper-level memory;
When the access target data specified by the access request output by the CPU hits the upper level memory, the value of the counter corresponding to the access target data is counted up, and the access request is a data write request. Writing data to the upper-level memory, and writing the data to the lower-level memory if the access request is a data write request and the value of the counter of the access target data is equal to or smaller than the predetermined value. A memory controller that performs
A cache management device comprising:
[0183]
(Supplementary Note 9) A cache memory management method for controlling a cache process in response to an access request from a CPU to an upper-level memory and a lower-level memory that stores data corresponding to data stored in the upper-level memory In the above, when the access target data specified by the access request output by the CPU hits the upper level memory, the value of a counter corresponding to the access target data is counted up,
When the replacement target data in the upper level memory is invalidated, the value of the counter corresponding to the replacement target data is set in an access count log corresponding to the replacement target data in the lower level memory,
When the access target data miss-hits the upper level memory, if the value of the access count log of the access target data in the lower level memory is larger than a predetermined value, the access target data is stored in the upper level memory. Do
A cache memory management method, characterized in that:
[0184]
(Supplementary Note 10) A cache memory management method for controlling cache processing in response to an access request from a CPU to an upper-level memory and a lower-level memory that stores data corresponding to data stored in the upper-level memory At
When the access target data specified by the access request output by the CPU hits the upper level memory, the value of the counter corresponding to the access target data is counted up,
If the access request is a data write request, write data to the upper level memory;
If the access request is a data write request, and the value of the counter of the data to be accessed is equal to or less than the predetermined value, data is also written to the lower-level memory.
A cache memory management method, characterized in that:
[0185]
【The invention's effect】
As described above, in the present invention, the number of accesses in the upper-level memory is counted, and after the data is evicted from the upper-level memory, the data is transferred from the lower-level memory to the upper-level memory only when the number of accesses is larger than a predetermined value. Is performed, so that caching limited to highly reusable data can be performed.
[0186]
In another invention, the number of accesses to the upper level memory is counted, and when a data write request is issued, writing to the lower level memory is performed only when the number of accesses is equal to or less than a predetermined value. For highly usable data, high-speed access by the write-back method becomes possible.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram of the invention applied to an embodiment.
FIG. 2 is a diagram illustrating a system configuration example according to the first embodiment;
FIG. 3 is a diagram illustrating an example of a data structure of tag information of a primary cache.
FIG. 4 is a diagram illustrating an example of a data structure of tag information of a secondary cache.
FIG. 5 is a flowchart illustrating a procedure of an access process according to the first embodiment.
FIG. 6 is a diagram illustrating an example of updating tag information when many accesses are made on the primary cache;
FIG. 7 is a diagram illustrating an example of updating tag information when the number of accesses on the primary cache is small.
FIG. 8 is a diagram illustrating an example of a system configuration of a computer according to a second embodiment.
FIG. 9 is a diagram illustrating an example of a data structure of tag information of a secondary cache.
FIG. 10 is a diagram showing an example of updating tag information when many accesses are made on the primary cache.
FIG. 11 is a diagram illustrating an example of updating tag information when the number of accesses on the primary cache is small.
FIG. 12 is a diagram illustrating an example of tag information of a secondary cache according to the third embodiment.
FIG. 13 is a flowchart illustrating a procedure of an access process of the memory controller according to the third embodiment;
FIG. 14 is a diagram illustrating an example of tag information of a secondary cache according to the fourth embodiment.
FIG. 15 is a flowchart illustrating a procedure of a write process according to a fifth embodiment.
FIG. 16 is a flowchart illustrating a procedure of a write process according to a ninth embodiment;
FIG. 17 is a flowchart illustrating a procedure of an access process according to the tenth embodiment.
[Explanation of symbols]
1 CPU
1a Memory controller
2 Upper level memory
2a Tag information
2b tag
2c counter
3 Lower level memory
3a Tag information
3b tag
3c Access count log
10 Main storage device
110, 210, 310, 410 CPU
111, 211, 311, 411 Memory controller
120, 220, 320, 420 Primary cache
121,221,321,421 Tag information
130, 230, 330, 430 Secondary cache
131, 231, 331, 431 Tag information

Claims (5)

In a cache management device that controls cache processing according to an access request from a CPU,
An upper level memory connected to the CPU;
A counter for counting the number of accesses to each data stored in the upper level memory;
A lower-level memory connected to the CPU and the upper-level memory and storing data corresponding to each data stored in the upper-level memory;
An access count log provided in association with each data stored in the lower level memory,
When the access target data specified by the access request output by the CPU hits the upper level memory, the value of the counter corresponding to the access target data is counted up, and the replacement target data in the upper level memory is invalidated. When the data is replaced, the value of the counter corresponding to the data to be replaced is set in the access count log corresponding to the data to be replaced in the lower level memory, and the data to be accessed misses the upper level memory. If the value of the access count log of the access target data in the lower level memory is larger than a predetermined value, a memory controller that stores the access target data in the upper level memory;
A cache management device comprising: 2. The cache management device according to claim 1, wherein the memory controller counts the number of accesses of each data stored in the lower-level memory and adds the number of accesses to the access number log. The memory controller, when the access request is a write request, when the access target data miss-hits the upper level memory, when the number of accesses of the access target data in the lower level memory is larger than a predetermined value. The cache management device according to claim 1, wherein the access target data is stored in the upper level memory. In a cache management device that controls cache processing according to an access request from a CPU,
An upper level memory connected to the CPU;
A counter for counting the number of accesses to each data stored in the upper level memory;
A lower-level memory connected to the CPU and the upper-level memory and storing data corresponding to each data stored in the upper-level memory;
When the access target data specified by the access request output by the CPU hits the upper level memory, the value of the counter corresponding to the access target data is counted up, and the access request is a data write request. Writing data to the upper-level memory, and writing the data to the lower-level memory if the access request is a data write request and the value of the counter of the access target data is equal to or smaller than the predetermined value. A memory controller that performs
A cache management device comprising: A cache memory management method for controlling a cache process in response to an access request from a CPU to an upper-level memory and a lower-level memory that stores data corresponding to data stored in the upper-level memory,
When the access target data specified by the access request output by the CPU hits the upper level memory, the value of a counter corresponding to the access target data is counted up,
When the replacement target data in the upper level memory is invalidated, the value of the counter corresponding to the replacement target data is set in an access count log corresponding to the replacement target data in the lower level memory,
When the access target data miss-hits the upper level memory, if the value of the access count log of the access target data in the lower level memory is larger than a predetermined value, the access target data is stored in the upper level memory. Do
A cache memory management method, characterized in that:

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