JP2004349978A - Analog switch circuit and signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog switch circuit which doesn't make a difference in pedestal potential occur even when video signals are switched by equalizing the pedestal potentials of a plurality of video signals. <P>SOLUTION: First and second video signals inputted from first and second input terminals Vin1 and Vin2 are clamped by first and second clamp circuits 18 and 19 respectively. The first clamp circuit 18 clamps a first video signal at an output voltage of a second buffer circuit 3 to which a bias potential Vb is connected, and the second clamp circuit 19 clamps a second video signal at an output voltage of a first buffer circuit 2 to which a voltage source Vb is connected. The first and second video signals are outputted from an output terminal Vo selected by a first selection switch SW3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an analog switch circuit that switches a plurality of video signals at high speed.
[0002]
[Prior art]
Generally, a television receives a video signal from a video transmission station and displays the received video signal on a television screen.
[0003]
The television screen has a function of not only displaying a video signal but also informing a viewer of information (for example, a station number and a volume) of the television screen by text. In addition, the menu of the television can be displayed while the video signal is being displayed. In this way, the information of the television can be displayed over the video signal from the video transmission station. Such television processing is called OSD (On Screen Display).
[0004]
There is also a television having a function in which a small child screen is provided on a television screen (parent screen), two images are respectively displayed on the parent screen and the child screen, and two images can be simultaneously viewed on one television screen. Such television processing is called PIP (Picture In Picture).
[0005]
As described above, the image displayed on the screen does not need to display only one video signal, but also needs to display a plurality of videos in an overlapping manner.
[0006]
Therefore, a method of switching a different video signal at high speed and displaying a plurality of images on a screen using an analog switch circuit has been used.
[0007]
For example, the analog switch circuit illustrated in FIG. 6 inputs different video signals from a first input terminal Vin1 and a second input terminal Vin2. Signals input from the first input terminal Vin1 and the second input terminal Vin2 are input to the first and second input units 102 and 103 of the switch SW3 through the first and second clamp circuits, respectively. You. The changeover switch SW3 selects the first or second video signal and outputs it to the output terminal Vo via the buffer circuit 101.
[0008]
The first and second clamp circuits respectively control the first and second clamp capacitors C1 and C2, the first and second clamp resistors R1 and R2, and the ON / OFF of the first and second clamp circuits. It is composed of first and second switches SW1 and SW2.
[0009]
When the first and second switches SW1 and SW2 are turned on, the video signals input from the first and second input terminals Vin1 and Vin2 are activated by the first and second clamp circuits, and set to the bias potential Vb. Clamped.
[0010]
Since the first clamp circuit and the second clamp circuit are clamped to the same bias potential Vb, the clamp potential is the same. In this case, the clamp potential is a pedestal potential serving as a black level reference potential of the video signal. Even if the first video signal and the second video signal are switched by the changeover switch SW3, there is no difference in pedestal potential, so that the brightness of the video after switching does not change unnaturally.
[0011]
However, when the clamp capacitance is designed to be small in accordance with the recent miniaturization of the semiconductor integrated circuit, the input capacitance of the buffer circuit 101 cannot be ignored with respect to the first and second clamp capacitances C1 and C2, and is accumulated in the input capacitance. The switched charge flows into the other clamp capacitor due to the switching of the video signal. As a result, there is a problem in that switching between the first video signal and the second video signal causes interference between the signals.
[0012]
In order to solve this problem, a second switch and a second clamp circuit are provided between the first and second input units 107 and 108 of the changeover switch SW3 and the first and second clamp circuits, respectively, as in an analog switch circuit shown in FIG. The third buffer circuits 105 and 106 are inserted. As a result, the input capacitance of the first buffer circuit 104 is driven by the second and third buffer circuits 105 and 106 so that the input capacitance of the first buffer circuit 104 does not interfere with each other's signals ( For example, see Patent Document 1.)
[0013]
[Patent Document 1]
JP-A-6-237397
[Problems to be solved by the invention]
However, the buffer circuit has a voltage offset between input and output. It is desirable that all the voltage offsets of the buffers have a constant value, but some differences occur between the buffers.
[0015]
The first and second video signals clamped to the bias potential Vb by the first and second clamp circuits are supplied to the first and second switches SW3 via the second and third buffer circuits 105 and 106, respectively. Are input to the input terminals 107 and 108 of.
[0016]
Here, assuming that the voltage offset of the second buffer circuit 105 is ΔV2 and the voltage offset of the third buffer circuit 106 is ΔV3, the signal input from the first input terminal Vin1 is set to the bias potential Vb by the second buffer circuit. The voltage obtained by adding the voltage offset ΔV2 of 105 becomes the first clamp potential (Vb + ΔV2). The signal input from the second input terminal Vin2 has a voltage obtained by adding the voltage offset ΔV3 of the third buffer circuit 106 to the bias potential Vb, and becomes a second clamp potential (Vb + ΔV3).
[0017]
Assuming that the voltage difference between the voltage offset ΔV2 of the second buffer circuit 105 and the voltage offset ΔV3 of the third buffer circuit 106 is ΔVp (= ΔV2−ΔV3), the first and second video signals are switched by the switch SW3. Then, a voltage difference ΔVp occurs in the clamp potential. That is, a difference in the pedestal potential, which is the reference potential of the black level of the video, occurs, and a brightness difference occurs in the video signal after switching.
[0018]
Therefore, an object of the present invention is to provide an analog switch circuit in which the pedestal potentials of a plurality of video signals are made the same, the pedestal potentials do not differ even when the video signals are switched, and the input video signals do not interfere with each other. And
[0019]
[Means for Solving the Problems]
According to one embodiment of the present invention to solve the above problem, a first capacitor connected to one of the first and second input terminals, a first capacitor connected to the first input terminal and one of the first input terminal, A first selection switch having the other input terminal connected to the first input terminal; a first short-circuit switch having one end connected to the first input terminal of the first selection switch; A voltage source connected to a second input terminal; a first signal processing circuit having an input terminal connected to an output terminal of the first selection switch; and a second signal terminal having one of the second input terminals connected to the second input terminal. A second selection switch having a first input terminal connected to the other of the second capacitors, a second input terminal connected to the voltage source, and a second selection switch connected to the voltage source. A second short switch to which one input terminal is connected, and an output terminal of the second selection switch to which an input terminal is connected. A first resistor connected to the other end of the first short-circuit switch, the other end connected to the output terminal of the second signal processing circuit, and one end connected to the other end of the first short-circuit switch. A second resistor connected to the other of the second short switches, the other connected to an output terminal of the first signal processing circuit, and a first input terminal output terminal of the first signal processing circuit; And a third selection switch circuit having a second input terminal connected to the output terminal of the second signal processing circuit, and an output terminal connected to the output terminal. .
[0020]
According to another aspect of the present invention, the first and second input terminals, a first capacitor having one end connected to the first input terminal, and a first input terminal having the first capacitor A first selection switch connected to the other end of the first selection switch, a first signal processing circuit having an input terminal connected to the output terminal of the first selection switch, and a second input terminal of the first selection switch A second capacitor having one end connected to the second input terminal, a first input terminal connected to the other end of the second capacitor, and a second input terminal connected to the second input terminal. A second selection switch connected to the voltage source; a second signal processing circuit having an input terminal connected to an output terminal of the second selection switch; and one end connected to a first terminal of the first selection switch. A first short-circuit switch connected to the input terminal and the other end connected to the output terminal of the second signal processing circuit; A second short switch connected to a first input terminal of a second selection switch and the other end connected to an output terminal of the first signal processing circuit; and a first input terminal connected to the first signal terminal. A third selection switch circuit connected to an output terminal of the processing circuit, a second input terminal connected to an output terminal of the second signal processing circuit, and an output terminal connected to an output terminal; The first and second short switches and the first to third selection switches are constituted by transfer gates of complementary CMOS transistors, and the on-impedance of the transfer gates constituting the first and second short switches is the second impedance. An analog switch circuit is provided which is higher than the transfer gates forming the first to third selection switches.
[0021]
According to still another aspect, the step of clamping to an output voltage of a second signal processing circuit which receives a bias potential for a first signal and the bias potential for a second signal. Clamping the output voltage of the first signal processing circuit to an output voltage, inputting the first signal to the first signal processing circuit, and inputting the second signal to the second signal processing circuit; Selecting the output signal of the first signal processing circuit to which the first signal has been input and the output signal of the second signal processing circuit to which the second signal has been input. A method is provided.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a circuit diagram of an analog switch circuit according to an embodiment of the present invention. A signal is input from a first input terminal Vin1 and a second input terminal Vin2 of this analog switch circuit, and a signal is output from an output terminal Vo.
[0023]
The first input terminal Vin1 is connected to one end 5 of the first short switch SW1 and the first input terminal 12 of the second selection switch SW4 via the first clamp capacitor C1. The second input terminal 13 of the second selection switch SW4 is connected to the voltage source Vb. The potential of the voltage source Vb is a clamp potential.
[0024]
The output terminal 6 of the first short switch SW1 is connected to one end of the clamp resistor R1, and the other end of the clamp resistor R1 is connected to the output terminal of the second buffer circuit 3.
[0025]
The output terminal 14 of the second selection switch SW4 is connected to the input terminal of the first buffer circuit 2, and the output terminal of the first buffer circuit 2 is connected to the first input terminal 9 of the first selection switch SW3. You.
[0026]
The second input terminal Vin2 is connected to one end 7 of the second short switch SW2 and the first input terminal 15 of the third selection switch SW5 via the second clamp capacitor C2. The second input terminal 16 of the third selection switch SW5 is connected to the voltage source Vb.
[0027]
The other end 8 of the second short switch SW2 is connected to one end of the clamp resistor R2, and the other end of the clamp resistor R2 is connected to the output end of the first buffer circuit 2.
[0028]
The output terminal 17 of the third selection switch SW5 is connected to the input terminal of the second buffer circuit 3, and the output terminal of the second buffer circuit 3 is connected to the second input terminal 10 of the first selection switch SW3. You.
[0029]
The output terminal 11 of the first selection switch SW3 is connected to the input terminal of the third buffer circuit 4, and the output terminal of the third buffer circuit 4 is connected to the output terminal Vo.
[0030]
FIG. 2A is a configuration diagram of the first and second short switches SW1 and SW2, and FIG. 2B is a configuration diagram of the first to third selection switches SW3, SW4, and SW5.
[0031]
The short switch is composed of a transfer gate formed of a complementary CMOS transistor combining an nMOS transistor M1 and a pMOS transistor M2.
[0032]
The selection switch is also formed of a transfer gate of a complementary CMOS transistor combining nMOS transistors M3 and M5 and pMOS transistors M4 and M6.
[0033]
The transfer gate using the complementary CMOS transistor as shown in FIG. 2 has a feature that the change in the on-impedance due to the signal is small and the transfer gate control pulse has little influence on the signal as compared with the transfer gate of one nMOS. I have.
[0034]
Next, FIG. 3 shows an example of the waveforms of the first and second video signals for one line input to the first and second input terminals Vin1 and Vin2.
[0035]
A period immediately after the horizontal synchronization signal is a pedestal period. In the pedestal period, a predetermined pedestal potential is always maintained. The pedestal potential determines the black level, and is constant even in a video signal corresponding to a dark screen or a video signal of a bright screen. If the pedestal potential is different, the brightness of a video image is different.
[0036]
After the pedestal period, a picture period occurs, and a signal in the picture period is an actual video signal displayed on the screen. The brightness of an image is determined by the potential in the picture period with respect to the pedestal potential described above.
[0037]
The signal processing of the analog switch circuit 1 shown in FIG. 1 will be described with reference to the flowchart shown in FIG.
[0038]
First, the first and second video signals are input to the first and second input terminals Vin1 and Vni2, respectively (step 1).
[0039]
Next, the first and second short switches SW1 and SW2 are turned on. Further, the second and third selection switches SW4 and SW5 select the bias potential Vb side (second input terminals 13 and 16) during the pedestal period (step 2).
[0040]
In step 2, the first and second video signals input from the first and second input terminals Vin1 and Vin2 are clamped.
[0041]
The first clamp circuit 18 includes a first clamp capacitor C1 and a first clamp resistor R1 when the first short switch SW1 is turned on, and the second buffer circuit 3 having the bias potential Vb as an input voltage. Output voltage.
[0042]
The second clamp circuit 19 includes a second clamp capacitor C2 and a second clamp resistor R2 when the second short switch SW2 is turned on, and a first buffer having the bias potential Vb as an input voltage. The output voltage of the circuit 2 is clamped.
[0043]
Here, the voltage offset of the first buffer circuit 2 is ΔV1, and the voltage offset of the second buffer circuit 3 is ΔV2.
[0044]
The first clamp circuit 18 is clamped at Vb + ΔV2 obtained by adding the voltage offset ΔV2 of the second buffer circuit 3 to the bias potential Vb. Further, the second clamp circuit 19 is clamped at Vb + ΔV1 obtained by adding the voltage offset ΔV1 of the first buffer circuit 2 to the bias potential Vb.
[0045]
Therefore, the first clamp potential of the first video signal during the pedestal period is Vb + ΔV2, and the second clamp potential of the second video signal is Vb + ΔV1.
[0046]
Next, the first and second short switches SW1 and SW2 are turned off. Further, the second selection switch SW4 is selected on the first input terminal Vin1 side, and the third selection switch SW5 is selected on the second input terminal Vin2 side (first input terminals 12, 15) (step 3).
[0047]
The first video signal is clamped to the first clamp potential Vb + ΔV2 before reaching the first input terminal 9 of the first selection switch SW3, and passes through the first buffer circuit 2, so that the voltage of the first buffer circuit 2 The offset ΔV1 is added. That is, the black level reference voltage of the first video signal is Vb + ΔV1 + Δ2.
[0048]
Further, the second video signal is clamped to the second clamp potential Vb + ΔV1 before reaching the second input terminal 10 of the first selection switch SW3 and passes through the second buffer circuit 3, so that the second buffer circuit 3 Will be added. That is, the black level reference voltage of the second video signal is also Vb + ΔV1 + ΔV2.
[0049]
Before reaching the input terminals 9 and 10 of the first selection switch SW3, both the black level reference voltage of the first video signal and the black level reference voltage of the second video signal become the same potential (Vb + ΔV1 + ΔV2).
[0050]
Next, the first selection switch SW3 is controlled (step 4). When the first input terminal 9 is selected, a first video signal is output, and when the second input terminal 10 is selected, a second video signal is output.
[0051]
The selected first or second video signal is output from the output terminal 11 of the first selection switch SW3 via the output terminal Vo via the third buffer circuit 4.
[0052]
As described above, according to the analog switch circuit 1 shown in FIG. 1, the first clamp potential Vb + ΔV2 by the first clamp circuit 18 and the second clamp potential Vb + ΔV1 by the second clamp circuit 19 during the pedestal period are different.
[0053]
However, since the first video signal always passes through the first buffer circuit 2, the output of the first video signal is a signal obtained by adding the voltage offset of the first buffer circuit 2 to the first clamp potential.
[0054]
Also, since the second video signal always passes through the second buffer circuit 3, the output of the second video signal is a signal obtained by adding the voltage offset of the second buffer circuit 3 to the second clamp potential.
[0055]
Since the final reference voltage of the black level is Vb + ΔV1 + ΔV2 for both the first and second video signals by the analog switch circuit 1, the switching between the first video signal and the second video signal is performed by the first selection switch SW3. There is no difference in the black level standard even if it is performed.
[0056]
Therefore, even if two video signals are switched during the scanning of one line, the brightness of the video does not fluctuate unnaturally.
[0057]
Further, since the first and second video signals input to the first selection switch SW3 pass through the first and second buffer circuits 2 and 3, respectively, the signal caused by the input capacitance of the third buffer circuit 4 Thus, the selected video signal can be output without being affected by unselected video signals without interference between the video signals.
[0058]
Even if a difference occurs in the voltage offset between the first buffer circuit 2 and the second buffer circuit 3 of the analog switch circuit 1, the two video signals can be switched without being affected by the difference.
[0059]
In the related art, as the difference between the voltage offsets of the buffer circuits increases, the difference in the black level at the time of video switching becomes significant, and the brightness of the video may fluctuate. By using the analog switch circuit of the present embodiment, there is no influence of the voltage offset of the buffer circuit, so that it is possible to prevent a change in the brightness of an image due to the difference in the voltage offset.
[0060]
In the embodiment described above, the analog switch circuit 1 for displaying two video signals on one screen has been described. However, by using the analog switch circuit of the present invention, three or more video signals can be displayed on one screen. You can also.
[0061]
For example, FIG. 5 shows a first video signal to be displayed on a main screen from a first input terminal Vin1, a second video signal to be displayed on a subscreen from a second input terminal Vin2, and a character display from a third input terminal Vin3. This is an analog switch circuit for switching a signal when a character signal for inputting is input.
[0062]
The first selection switch SW3 selects the first video signal and the second video signal, and the fourth selection switch SW9 selects the first or second video signal selected by the first selection switch SW3 and the second video signal. 3 is selected.
[0063]
The circuit 1 surrounded by a dotted line in FIG. 5 is the analog switch circuit (hereinafter, referred to as a “two-selection switch circuit”) 1 in FIG.
[0064]
The third clamp circuit 32 connected in series to the output of the two-selection switch circuit 1 is a clamp circuit that re-clamps the video signal selected by the two-selection switch circuit 1.
[0065]
The fourth clamp circuit 33 is a clamp circuit that clamps the third video signal from the third input terminal Vin3. The clamp resistor R4 of the fourth clamp circuit 33 is connected to the output of the two-selection switch circuit 1 via the clamp capacitor C3 and the sixth buffer circuit.
[0066]
The voltage offset of the sixth buffer circuit 34 is ΔV3, and the voltage offset of the fourth buffer circuit 20 is ΔV4.
[0067]
When the fifth selection switch SW8 selects the bias potential Vb, the clamp potential by the third clamp circuit 32 is Vb + ΔV4.
[0068]
On the other hand, when the sixth selection switch SW10 selects the bias potential Vb, the clamp potential of the fourth clamp circuit 33 is changed according to the signal selected by the first selection switch SW3 in the two-selection switch circuit 1 for the first image. In the case of a signal, it is Vb + ΔV1 + ΔV3, and in the case where the first selection switch SW3 selects the second video signal, it is Vb + ΔV2 + ΔV3.
[0069]
The third clamp potential Vb + Δ4 is added before the first or second video signal selected by the two-selection switch circuit 1 reaches the first input terminal 29 of the fourth selection switch SW9. That is, the voltage of Vb + (Δ1 or ΔV2) + ΔV3 + ΔV4 is added to the first or second video signal.
[0070]
Further, the third video signal passes through the fourth clamp potential Vb + (ΔV1 or ΔV2) + ΔV3 and the fourth buffer circuit 20 until reaching the second input terminal 30 of the fourth selection switch SW9. The voltage offset ΔV4 of the circuit 20 will be added. That is, the voltage of Vb + (ΔV1 or ΔV2) + ΔV3 + ΔV4 is added to the third video signal.
[0071]
Therefore, no voltage offset occurs between the two video signals reaching the input terminals 29 and 30 of the fourth selection switch SW9, and the brightness of the video does not become unnatural.
[0072]
As described above, when the analog switch circuit of the present invention is used, the brightness of three or more video signals can be displayed on one screen without unnaturally changing the brightness.
[0073]
In this embodiment, the complementary CMOS transfer gate shown in FIG. 2 is used for both the short switch and the selection switch. However, the present invention is not limited to this, and another switch circuit such as an nMOS transistor may be used.
[0074]
Further, the clamp resistance of the clamp circuit can be eliminated by increasing the on-impedance of the short switches SW1, SW2, SW6, and SW7 in order to reduce the circuit scale of the analog switch circuit. Usually, a resistor requires a relatively large area, which is advantageous for reducing the circuit scale. In order to increase the on-impedance of the short switch, for example, it is conceivable to shorten the gate width of the transfer gate or increase the gate length.
[0075]
In this embodiment, the buffer circuit is used to amplify the video signal. However, the present invention is not limited to this, and another signal processing circuit such as an amplifier circuit may be used.
[0076]
【The invention's effect】
As described above in detail, the present invention can provide an analog switch circuit in which the pedestal potentials of a plurality of video signals are the same and the pedestal potentials do not differ even when the video signals are switched.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an analog switch circuit according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a short switch and a selection switch of the analog switch circuit of FIG. 1;
FIG. 3 is a waveform diagram of a video signal for one line input to the analog switch circuit of FIG. 1;
FIG. 4 is a flowchart at the time of operation of the analog switch circuit of FIG. 1;
FIG. 5 is a modification of the circuit diagram of the analog switch circuit according to the embodiment of the present invention.
FIG. 6 is a circuit diagram showing an example of a conventional analog switch circuit.
FIG. 7 is a circuit diagram showing an example of a conventional analog switch circuit.
[Explanation of symbols]
SW1, SW2, SW6, SW7 ... Short switches SW3, SW4, SW5, SW8, SW9, SW10 ... Selection switches C1, C2, C3, C4 ... Clamp capacitances R1, R2, R3, R4 ... Clamp resistors Vin1, Vin2, Vin3 ... input terminal Vb ... bias potential 1 ... analog switch circuit 2 ... first buffer circuit 3 ... second buffer circuit 4 ... third Buffer circuits 5, 7, 22, 24 ... One end of short switch 6, 8, 23, 25 ... The other end of short switch 9, 12, 15, 26, 29, 35 ... First of selection switch , Input terminals 10, 13, 16, 27, 30, 36,... Second input terminals 11, 14, 17, 17, 28, 31, 37,. of Ramp circuit 19 second clamp circuit 20 fourth buffer circuit 21 fifth buffer circuit 32 third clamp circuit 33 fourth clamp circuit 34 .Sixth buffer circuit

Claims (5)

First and second input terminals;
A first capacitor having one end connected to the first input terminal;
A first selection switch connected to the other of the first capacitors and a first input terminal;
A first short-circuit switch, one of which is connected to a first input terminal of the first selection switch;
A voltage source connected to the second input of the first selection switch;
A first signal processing circuit having an input terminal connected to the output terminal of the first selection switch;
A second capacitor, one of which is connected to the second input terminal;
A second selection switch having a first input terminal connected to the other of the second capacitors, and a second input terminal connected to the voltage source;
A second short switch to which a first input terminal of the second selection switch is connected;
A second signal processing circuit having an input connected to the output of the second selection switch;
A first resistor having one connected to the other of the first short-circuit switch and the other connected to an output terminal of the second signal processing circuit;
A second resistor having one connected to the other of the second short-circuit switches and the other connected to an output terminal of the first signal processing circuit;
A first input terminal is connected to an output terminal of the first signal processing circuit, a second input terminal is connected to an output terminal of the second signal processing circuit, and an output terminal is connected to an output terminal. An analog switch circuit comprising: the selection switch circuit according to (3). 2. The analog switch circuit according to claim 1, wherein said first and second short switches and said first to third selection switches are constituted by transfer gates made of complementary CMOS transistors. First and second input terminals;
A first capacitor having one end connected to the first input terminal;
A first selection switch having a first input terminal connected to the other end of the first capacitor;
A first signal processing circuit having an input terminal connected to the output terminal of the first selection switch;
A voltage source connected to a second input of the first selection switch;
A second capacitor having one end connected to the second input terminal;
A second selection switch having a first input terminal connected to the other end of the second capacitor, and a second input terminal connected to the voltage source;
A second signal processing circuit having an input connected to the output of the second selection switch;
A first short switch having one end connected to a first input end of the first selection switch and the other end connected to an output end of the second signal processing circuit;
A second short switch having one end connected to a first input end of the second selection switch and the other end connected to an output end of the first signal processing circuit;
A first input terminal is connected to an output terminal of the first signal processing circuit, a second input terminal is connected to an output terminal of the second signal processing circuit, and an output terminal is connected to an output terminal. 3 selection switch circuits,
The first and second short switches and the first to third selection switches are constituted by transfer gates of complementary CMOS transistors, and the on-impedance of the transfer gates constituting the first and second short switches is An analog switch circuit, which is higher than a transfer gate forming the first to third selection switches. 4. The analog switch circuit according to claim 1, wherein the signal processing circuit is a buffer circuit. 5. Clamping the first signal to an output voltage of a second buffer circuit that receives a bias potential as an input;
Clamping a second signal to an output voltage of a first buffer circuit that receives the bias potential as an input;
Inputting the first signal to the first buffer circuit and inputting the second signal to the second buffer circuit;
A signal processing method comprising: selecting an output signal of the first buffer circuit to which the first signal has been input and an output signal of the second buffer circuit to which the second signal has been input.

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