JP2004349352A - Semiconductor storage device, its operating method, semiconductor device, and portable electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device that can be miniaturized easily. <P>SOLUTION: In the semiconductor storage device, a gate electrode 104 is formed on a p-type well region 102 formed on the surface of a semiconductor substrate 101 through a gate insulating film 103. The portions of silicon nitride films 109 on both sides of the gate electrode 104 function as memory function groups 105a and 105b which hold charges. Source/drain diffusion regions 107a and 107b are formed in active regions formed by dividing the surface portion of the p-type well region 102 by an element separating region. Each active region is formed in a matrix-like state having a direction of rows in which a word line is extended and a direction of columns in which a bit line is extended. The word line functions as the gate electrode 104 on a channel region provided between the source/drain diffusion regions 107a and 107b. Since the memory function groups 105a and 105b are positioned on both sides of the gate electrode 104 separately from the gate insulating film 103, the semiconductor storage device can be miniaturized effectively. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０１８８】
表１から明らかなように、本実施形態のメモリセルアレイは、ランダムアクセス（１ビット毎の読出しおよび書換え動作）が可能である。このため、一括消去しなければならないデバイスに比較し、アクセス効率を上げることが可能である。また、メモリ状態の一時記憶、一括消去、書き込みといったシーケンスも不要となるため制御回路が簡単になるという効果がある。
【０１８９】
上記読出し動作時によれば、あるメモリ素子の２ビットの記憶を連続して読み出そうとする場合（例えば、メモリ素子Ｍ２２のメモリ機能体Ｗ１、Ｗ２を連続して読み出すなど）、近傍のビット線の電位を全て反転しなければならない（上の例ではビット線ＢＬ１〜ＢＬ４の電位を全て反転する）ため、効率が悪い。そのため、後述のように、アドレスデコーダー回路などの工夫を行い、左右のメモリ機能体のアクセスのためのアドレスを離すなどの対策を行うことにより連続して交互に読み出す状態を回避することが好ましい。
【０１９０】
（第１３実施形態）
本発明の第１３実施形態を、図３０〜３２を用いて説明する。図３０は、第１３実施形態となるメモリセルアレイの概略平面図であり、図３１は図３０の切断面線Ｅ−Ｅ’における概略断面図である。図３２は、このメモリセルアレイの第１層メタル配線の配置を説明する図である。ただし、図３０においては、上部配線構造（ビット線およびコンタクト）は簡略のため結線図として表現している。また、図３０〜３２では、３行×３列のメモリセルアレイを示しているが、行数および列数は任意である。また、図３２においては、第１層メタル配線の下層部に対する位置関係を明らかにするため、素子分離領域１１０８も描かれている。
【０１９１】
本実施形態のメモリセルアレイが第１２実施形態のメモリセルアレイと異なるのは、拡散領域とビット線との接続パターンであり、以下で説明する。
【０１９２】
ここで、隣接する３本のビット線（例えばＢＬ１、ＢＬ２、ＢＬ３）を選び、並び順に、ビット線１（ＢＬ１）、ビット線２（ＢＬ２）、ビット線３（ＢＬ３）とする。ビット線１が本発明の第１のビット線に相当し、ビット線２が本発明の第２のビット線に相当し、ビット線３が本発明の第３のビット線に相当する。
【０１９３】
このとき、上記ビット線１（ＢＬ１）とビット線２（ＢＬ２）との間に存する活性領域を活性化領域１（Ａ１）とする。同様に、ビット線２（ＢＬ２）とビット線３（ＢＬ３）との間に存する活性領域を活性化領域２（Ａ２）とする。このとき、上記ビット線２（ＢＬ２）は、上記活性領域１（Ａ１）および活性領域２（Ａ２）に属する上記ソース／ドレイン領域の一方と接続される。また、上記ビット線１（ＢＬ１）は、上記活性領域１（Ａ１）に属する上記ソース／ドレイン領域の他方と接続される。また、上記ビット線３（ＢＬ３）は、上記活性領域２（Ａ２）に属する上記ソース／ドレイン領域の他方と接続される。つまり、上記活性領域１が本発明の第１の活性領域に相当し、上記活性領域２が本発明の第２の活性領域に相当する。
【０１９４】
更には、隣接する２本の上記ワード線（例えば、ＷＬ１、ＷＬ２）を選んだとき、上記活性領域１（Ａ１）に属し、かつ、上記２本のワード線に挟まれた拡散領域と、上記活性領域２（Ａ２）に属し、かつ、上記２本のワード線に挟まれた拡散領域とは、共にビット線２（ＢＬ２）に接続されるか、またはそれぞれビット線１（ＢＬ１）およびビット線３（ＢＬ３）に接続されている。言い換えると、上記活性領域１（Ａ１）に属し、かつ、上記選択された２本のワード線（ＷＬ１およびＷＬ２）に挟まれた拡散領域が、上記ソース／ドレイン領域の一方であるならば、上記活性領域２（Ａ２）に属し、かつ、上記選択された２本のワード線に挟まれた上記拡散領域もまた、上記ソース／ドレイン領域の一方となるのである。
【０１９５】
本実施形態のメモリセルアレイによれば、図３２と図２９とを比較すれば明らかなように、紙面横方向のピッチを小さくしても第１層メタル配線１１３２間のマージンを大きくとることができる。これは、拡散領域とビット線との接続パターンを上記のようにしたため、第１層メタル配線１１３２の一部が統合され、その数が減少したためである。図２９と図３２の例では、図２９においては第１層メタル配線１１３２が１２個存在するが、図３２においては８個に減少している。したがって、更に大幅にメモリ素子の面積を縮小して製造コストを削減することができる。
【０１９６】
本実施形態のメモリセルアレイの回路図は、図２８と同じとなる。したがって、動作方法も第１２実施形態のメモリセルアレイと同じでよい。
【０１９７】
（第１４実施形態）
以上説明したメモリセルアレイを、以下の様に用いて半導体装置を構成することができる。図３３は、本実施形態の半導体装置のハードウェアブロック図を示している。
【０１９８】
本実施形態の半導体装置１３は、第１０〜１３実施形態のメモリセルアレイ１３０１を含んで構成されており、アクセス対象のメモリ素子を特定するためのカラムアドレスバッファ１３０２、ロウアドレスバッファ１３０３、カラムアドレスデコーダー１３０４、ロウアドレスデコーダー１３０５、センスアンプ１３０６および、これらの各部を制御する制御回路１３０７等を含む。
【０１９９】
第１０〜１３実施形態のメモリセルアレイを用い、かつ各種回路を上記の様に構成することによって、大容量かつ低コストの半導体装置を提供が提供される。
【０２００】
ところで、上記のような半導体装置を設計する際に、メモリセルアレイ１３０１の読み出し動作の効率を考えると、前述したように、あるメモリ素子の２ビットの記憶を連続して読み出そうとするのは効率が悪い。なぜなら、前述のように、メモリ素子の２ビット情報を連続して読み出そうとすれば、読み出し電流の向きを反対にする（ソースとドレインを入れ替える）必要があり、近傍のビット線の電位を全て反転しなければならないからである。それゆえ、あるメモリ素子に記憶される２ビットのアドレスは、互いに離しておくのが好ましい。例えば、同一のワード線に属し互いに隣接するメモリ素子の記憶ビットの一方を連続したアドレスにしておき、同一メモリ素子内の記憶ビットの一方と他方のアドレスは離しておけばよい。
【０２０１】
（第１５実施形態）
本実施形態では、第１０〜１３実施形態のメモリセルアレイを用いた携帯電子機器の一例を示す。図３４は、本実施形態の携帯電子機器のブロック図を示す。携帯電子機器１４は、中央演算装置１４０１、メモリ部１４０２、電源１４０３、入出力部１４０４、画像出力部１４０５から構成されている。メモリ部１４０２は、第１０〜１３実施形態のメモリセルアレイを含んでいる。
【０２０２】
メモリ部１４０２の機能としては、メインメモリの機能の他に、書き換え可能なファームウェア記憶装置（ハードウェアの基本的なシーケンスなどを記憶する）としての機能、システムの設定を記憶する記憶装置としての機能を持たせることができる。このメモリ部１４０２は、特に、携帯電話、電子手帳などの携帯機器、ゲーム機器の記憶装置として使用するのが好ましい。
【０２０３】
上記メモリ部１４０２は、第１０〜１３実施形態のメモリセルアレイからなるので、高集積化が容易であり、携帯電子機器の製造コストを削減することができる。また、中央演算装置１４０１などとメモリ部１４０２とを１つのチップ上に混載するのが容易であるため、更に製造コストを削減することもできる。なお、上記メモリ部１４０２は、第１４実施形態の半導体装置のメモリセルアレイで構成してもよい。本発明の携帯電子機器は、本発明の半導体装置を搭載することにより、部品点数をさらに削減して、製造コストを更に低減することができる。
【０２０４】
【発明の効果】
以上より明らかなように、本発明の半導体記憶装置によれば、半導体基板の表面部分に、素子分離領域と、この素子分離領域が形成されていない活性領域とが形成され、上記活性領域は、第１の方向と、この第１の方向と交差する第２の方向とで定義されるマトリクス状に複数個配置されており、上記各活性領域には、ソースまたはドレインとして働く２つのソース／ドレイン拡散領域が形成されて、この２つのソース／ドレイン拡散領域の間にチャネル領域が定められ、上記半導体基板上に、上記第２の方向に延在する複数のワード線が設けられ、このワード線は、上記第２の方向に並ぶ活性領域のチャネル領域上に、絶縁体を介して設けられおり、上記半導体基板上に、上記第１の方向に延在する複数の第１のビット線と、上記第１の方向に延在する複数の第２のビット線とが設けられ、上記第１のビット線は、上記第１の方向に並ぶ活性領域に形成された上記ソース／ドレイン拡散領域の一方と接続され、上記第２のビット線は、上記第１の方向に並ぶ活性領域に形成された上記ソース／ドレイン拡散領域の他方と接続され、上記ワード線は、上記チャネル領域上でゲート電極として機能し、上記ゲート電極について、上記ソース／ドレイン拡散領域の一方の側と他方の側との側壁には、電荷を保持する機能または分極を保持する機能を有するメモリ機能体が各々形成され、所定のワード線および第１のビット線および第２のビット線を選択して特定される上記メモリ機能体に保持された電荷または分極の多寡により、上記所定のワード線および第１のビット線および第２のビット線を選択して特定される上記チャネル領域を流れる電荷量を変化させるように構成されてなるので、所定のワード線および第１のビット線および第２のビット線を選択することにより、特定のメモリ機能体の記憶情報を書換え、または読み出すことが可能となる。また、上記ゲート電極の側壁に設けられたメモリ機能体は、上記チャネル領域とワード線とを隔てる絶縁体とは分離されて形成されているので、上記絶縁体を容易に薄膜化して短チャネル効果を抑制でき、その結果、素子を微細化し、製造コストを削減することができる。
【図面の簡単な説明】
【図１】本発明の第１実施形態のメモリ素子の概略断面図である。
【図２】第１実施形態のメモリ素子の変形例を示す図である。
【図３】第１実施形態のメモリ素子の書込み動作を説明する図である。
【図４】第１実施形態のメモリ素子の書込み動作を説明する図である。
【図５】第１実施形態のメモリ素子の消去動作を説明する図である。
【図６】第１実施形態のメモリ素子の消去動作を説明する図である。
【図７】第１実施形態のメモリ素子の読出し動作を説明する図である。
【図８】第２実施形態のメモリ素子の概略断面図である。
【図９】図８のメモリ素子の部分の断面図である。
【図１０】第２実施形態のメモリ素子の変形例を示す部分断面図である。
【図１１】第２実施形態のメモリ素子の電気特性を示す図である。
【図１２】第２実施形態のメモリ素子の変形例を示す部分断面図である。
【図１３】第３実施形態のメモリ素子の部分断面図である。
【図１４】第４実施形態のメモリ素子の部分断面図である。
【図１５】第５実施形態のメモリ素子の部分断面図である。
【図１６】第６実施形態のメモリ素子の部分断面図である。
【図１７】第７実施形態のメモリ素子の部分断面図である。
【図１８】第８実施形態のメモリ素子の部分断面図である。
【図１９】第９実施形態のメモリ素子の電気特性を示す図である。
【図２０】第１０実施形態の半導体記憶装置を示す平面図である。
【図２１】図２０の切断面線Ａ−Ａ’における断面図である。
【図２２】図２０の切断面線Ｂ−Ｂ’における断面図である。
【図２３】第１０実施形態の半導体記憶装置の回路図である。
【図２４】第１１実施形態の半導体記憶装置の平面図である。
【図２５】図２４の切断面線Ｃ−Ｃ’における断面図である。
【図２６】第１２実施形態の半導体記憶装置の平面図である。
【図２７】図２６の切断面線Ｄ−Ｄ’における断面図である。
【図２８】第１２実施形態の半導体記憶装置の回路図である。
【図２９】第１２実施形態の半導体記憶装置の第１層メタル配線の配置を説明する図である。
【図３０】第１３実施形態の半導体記憶装置の平面図である。
【図３１】図３０の切断面線Ｅ−Ｅ’における断面図である。
【図３２】第１３実施形態の半導体記憶装置の第１層メタル配線の配置を説明する図である。
【図３３】第１４実施形態の半導体装置を示すブロック図である。
【図３４】第１５実施形態の携帯電子機器を示すブロック図である。
【図３５】従来のフラッシュメモリセルアレイの概略平面図である。
【図３６】図３５の切断面線Ｆ−Ｆ’における断面図である。
【図３７】従来のフラッシュメモリの電気特性を示す図である。
【符号の説明】
１ メモリ素子
１０１ 半導体基板
１０２ Ｐ型ウェル領域
１０３ ゲート絶縁膜
１０４ ゲート電極
１０５ａ，１０５ｂ メモリ機能体
１０７ａ，１０７ｂ ソース／ドレイン拡散領域
１０９ シリコン窒化膜[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and an operation method thereof, a semiconductor device, and a portable electronic device. More specifically, a semiconductor memory device having a field effect transistor having a memory function body having a function of retaining electric charge or polarization and an operation method thereof, and a semiconductor device having the semiconductor memory device and a portable device Related to electronic equipment.
[0002]
[Prior art]
A flash memory will be described below as an example of a conventional nonvolatile memory. FIG. 35 is a schematic plan view of an example of a flash memory cell array (for example, see Patent Document 1). FIG. 36 is a schematic sectional view taken along section line FF 'in FIG. 35 and 36, 901 denotes a semiconductor substrate, FG denotes a floating gate, WL denotes a word line, SL denotes a source line, BL denotes a bit line, 908 denotes an element isolation region, and 931 denotes an insulating film.
[0003]
Each memory element forming the memory cell array has a floating gate, and stores data as the amount of charge in the floating gate. According to the memory cell array shown in FIG. 35 in which memory elements are arranged, a specific word line or bit line is selected and a predetermined voltage is applied to perform a desired memory element rewrite and read operation. Can be.
[0004]
FIG. 37 is a diagram schematically showing a characteristic of drain current (Id) versus gate voltage (Vg) when the amount of charge in the floating gate of the flash memory changes. The solid line shows the characteristics at the time of erasing, and the dotted line shows the characteristics at the time of writing. As the amount of negative charge in the floating gate increases, the threshold increases, and the Id-Vg curve moves substantially in parallel in the direction of increasing Vg.
[0005]
[Patent Document 1]
JP 05-304277 A
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional flash memory, a floating gate is provided between a word line (gate electrode) and a channel region, and an insulating film separating the floating gate and the word line is provided to prevent charge leakage from the floating gate. Also, it is difficult to reduce the thickness of the insulating film separating the floating gate and the channel region. Therefore, it is difficult to reduce the thickness of an effective gate insulating film, which hinders miniaturization of a memory element.
[0007]
The present invention has been made in view of the above problems, and has as its object to provide a semiconductor memory device that can be easily miniaturized.
[0008]
[Means for Solving the Problems]
In order to solve the above problem, in a semiconductor memory device of the present invention, an element isolation region and an active region where the element isolation region is not formed are formed on a surface portion of a semiconductor substrate,
A plurality of the active regions are arranged in a matrix defined by a first direction and a second direction intersecting the first direction,
In each of the active regions, two source / drain diffusion regions serving as a source or a drain are formed, and a channel region is defined between the two source / drain diffusion regions.
A plurality of word lines extending in the second direction are provided on the semiconductor substrate, and the word lines are provided on a channel region of the active region arranged in the second direction via an insulator. Yes,
A plurality of first bit lines extending in the first direction and a plurality of second bit lines extending in the first direction are provided on the semiconductor substrate;
The first bit line is connected to one of the source / drain diffusion regions formed in the active region arranged in the first direction;
The second bit line is connected to the other of the source / drain diffusion regions formed in the active region arranged in the first direction;
The word line functions as a gate electrode on the channel region,
With respect to the gate electrode, memory function bodies having a function of retaining charge or a function of retaining polarization are formed on sidewalls on one side and the other side of the source / drain diffusion region, respectively.
The predetermined word line, the first bit line, and the second bit line are selected and selected, and the predetermined word line, the first bit line, It is characterized in that the amount of charge flowing through the channel region specified by selecting the second bit line is changed.
[0009]
According to the above configuration, by selecting the predetermined word line, the first bit line, and the second bit line, it is possible to rewrite or read the storage information of the specific memory function body.
[0010]
Further, a memory function body having a function of retaining charge or a function of maintaining polarization is formed on a side wall of the gate electrode of the word line. The memory function body connects the channel region and the word line. It is formed separately from the insulator that separates it. Therefore, it is easy to suppress the short channel effect by reducing the thickness of the insulator. Therefore, the element can be miniaturized, and the manufacturing cost can be reduced.
[0011]
Further, in the semiconductor memory device of the present invention, an element isolation region and an active region where the element isolation region is not formed are formed on a surface portion of the semiconductor substrate,
The active region extends in a first direction and is arranged in a plurality in a second direction intersecting the first direction.
A plurality of source / drain diffusion regions serving as a source or a drain are formed in the active region, and channel regions are respectively defined between the adjacent source / drain diffusion regions in the same active region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate on channel regions of the plurality of active regions via an insulator,
A plurality of first bit lines extending in the first direction and a plurality of second bit lines extending in the first direction are provided on the semiconductor substrate;
The first bit line is connected to one of the source / drain diffusion regions formed on the same active region;
The second bit line is connected to the other of the source / drain diffusion regions formed on the same active region;
The word line functions as a gate electrode on the channel region,
With respect to the gate electrode, memory function bodies having a function of retaining charge or a function of retaining polarization are formed on sidewalls on one side and the other side of the source / drain diffusion region, respectively.
The predetermined word line, the first bit line, and the second bit line are selected and selected, and the predetermined word line, the first bit line, It is characterized in that the amount of charge flowing through the channel region specified by selecting the second bit line is changed.
[0012]
According to the above configuration, by selecting the predetermined word line, the first bit line, and the second bit line, it is possible to rewrite or read the storage information of the specific memory function body.
[0013]
Further, a memory function body having a function of retaining charge or a function of maintaining polarization is formed on a side wall of the gate electrode of the word line. The memory function body connects the channel region and the word line. It is formed separately from the insulator that separates it. Therefore, it is easy to suppress the short channel effect by reducing the thickness of the insulator. Therefore, the element can be miniaturized, and the manufacturing cost can be reduced.
[0014]
Further, a memory element adjacent to the first direction (the gate element, the memory function body formed on both side walls of the gate electrode, and the source / drain diffusion regions adjacent to the gate electrode) ), The area of the memory element can be greatly reduced. Therefore, the degree of integration of the semiconductor memory device can be further improved, and the manufacturing cost can be reduced.
[0015]
Further, in the semiconductor memory device of the present invention, an element isolation region and an active region where the element isolation region is not formed are formed on a surface portion of the semiconductor substrate,
The active region extends in a first direction and is arranged in a plurality in a second direction intersecting the first direction.
A plurality of source / drain diffusion regions serving as a source or a drain are formed in the active region, and channel regions are respectively defined between the adjacent source / drain diffusion regions in the same active region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate on channel regions of the plurality of active regions via an insulator,
A plurality of bit lines extending in the first direction are provided on the semiconductor substrate;
In the active region connected to two adjacent bit lines, one of the two bit lines is connected to one of the source / drain diffusion regions formed on the active region, and the two bit lines are connected to one another. The other of the bit lines is connected to the other of the source / drain diffusion regions formed in the active region,
The word line functions as a gate electrode on the channel region,
With respect to the gate electrode, memory function bodies having a function of retaining charge or a function of retaining polarization are formed on sidewalls on one side and the other side of the source / drain diffusion region, respectively.
A memory element is constituted by the gate electrode, the memory function body formed on the side walls on both sides of the gate electrode, and the source / drain diffusion regions adjacent to the gate electrode;
The predetermined word line and the two bit lines adjacent to each other are selected, and the predetermined word line and the two adjacent bit lines are determined by the amount of charge or polarization held in the memory function body specified and specified. It is characterized in that it is configured to change the amount of charge flowing through the channel region specified by selecting a bit line.
[0016]
According to the above configuration, by selecting a predetermined word line and two bit lines adjacent to each other, it is possible to rewrite or read the storage information of a specific memory function body.
[0017]
Further, a memory function body having a function of retaining charge or a function of maintaining polarization is formed on a side wall of the gate electrode of the word line. The memory function body connects the channel region and the word line. It is formed separately from the insulator that separates it. Therefore, it is easy to suppress the short channel effect by reducing the thickness of the insulator. Therefore, the element can be miniaturized, and the manufacturing cost can be reduced.
[0018]
Further, since one bit line extending in the first direction is shared by two active regions extending in the first direction, the area of the memory element can be significantly reduced. Therefore, the degree of integration of the semiconductor memory device can be further improved, and the manufacturing cost can be reduced.
[0019]
Further, in the semiconductor memory device of the present invention, an element isolation region and an active region where the element isolation region is not formed are formed on a surface portion of the semiconductor substrate,
The active region extends in a first direction and is arranged in a plurality in a second direction intersecting the first direction.
A plurality of source / drain diffusion regions serving as a source or a drain are formed in the active region, and channel regions are respectively defined between the adjacent source / drain diffusion regions in the same active region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate on channel regions of the plurality of active regions via an insulator,
A plurality of bit lines extending in the first direction are provided on the semiconductor substrate;
With respect to a first bit line, a second bit line, and a third bit line, which are sequentially adjacent to each other, the first active region connected to the first bit line and the second bit line; 2 and the second active region connected to the third bit line,
The second bit line is connected to one of the source / drain diffusion regions formed in the first active region, and is connected to one of the source / drain diffusion regions formed in the second active region. Connected to
The first bit line is connected to the other of the source / drain diffusion regions formed in the first active region;
The third bit line is connected to the other of the source / drain diffusion regions formed in the second active region;
The word line functions as a gate electrode on the channel region,
With respect to the gate electrode, memory function bodies having a function of retaining charge or a function of retaining polarization are formed on sidewalls on one side and the other side of the source / drain diffusion region, respectively.
A memory element is constituted by the gate electrode, the memory function body formed on the side walls on both sides of the gate electrode, and the source / drain diffusion regions adjacent to the gate electrode;
The predetermined word line and the two bit lines adjacent to each other are selected, and the predetermined word line and the two adjacent bit lines are determined by the amount of charge or polarization held in the memory function body specified and specified. It is characterized in that it is configured to change the amount of charge flowing through the channel region specified by selecting a bit line.
[0020]
According to the above configuration, by selecting a predetermined word line and two bit lines adjacent to each other, it is possible to rewrite or read the storage information of a specific memory function body.
[0021]
Further, a memory function body having a function of retaining charge or a function of maintaining polarization is formed on a side wall of the gate electrode of the word line. The memory function body connects the channel region and the word line. It is formed separately from the insulator that separates it. Therefore, it is easy to suppress the short channel effect by reducing the thickness of the insulator. Therefore, the element can be miniaturized, and the manufacturing cost can be reduced.
[0022]
Further, if the predetermined source / drain diffusion region belonging to the first active region is one of a source / drain, the source / drain diffusion region adjacent to the predetermined source / drain diffusion region in the second direction. A source / drain diffusion region that is a region and belongs to the second active region also becomes one of the source / drain. That is, a source / drain diffusion region sandwiched between two adjacent word lines, the source / drain diffusion region belonging to the first active region and the source / drain diffusion region belonging to the second active region. The region has the same operation as a source or a drain. Therefore, the wiring connecting the bit line and the source / drain diffusion region can be simplified, and as a result, the degree of integration of the semiconductor memory device can be further improved and the manufacturing cost can be reduced.
[0023]
Further, in the operation method of the semiconductor memory device according to the present invention, the operation method of the semiconductor memory device is
Regarding a selected memory element which is a memory element to which a memory function body to be operated belongs, before applying a potential for performing an operation to a word line connected to the selected memory element,
One of the two bit lines connected to the selected memory element is precharged to a first potential and the other is precharged to a second potential;
Precharging a bit line adjacent to the one bit line on the side opposite to the other bit line to the first potential;
A bit line adjacent to the other bit line on the side opposite to the one bit line is precharged to the second potential.
[0024]
According to the operation method of the semiconductor memory device, one of the two bit lines connected to the selected memory element is precharged to the first potential and the other is precharged to the second potential. After a potential for performing an operation is applied to a word line connected to the selected memory element, information of a desired memory function body can be quickly read.
[0025]
Further, a bit line adjacent to the one bit line on the side opposite to the other bit line is precharged to the first potential, and a bit line adjacent to the other bit line on the side opposite to the one bit line is precharged. Precharge the line to a second potential. This makes it possible to reduce the noise current when detecting the current flowing through the selected memory element. As a result, a semiconductor memory device with less malfunction can be obtained.
[0026]
In one embodiment of the present invention, the memory function bodies formed on the side walls on both sides of the gate electrode perform a rewrite operation and a read operation as independent storage units.
[0027]
According to the above embodiment, since the memory rewrite operation and the read operation are independently performed on each of the memory function bodies formed on the side walls on both sides of the word line, it is easy to make one memory element multi-valued. Realize. Therefore, the capacity of the semiconductor memory device can be further increased, and the manufacturing cost can be reduced.
[0028]
In one embodiment, at least a part of the memory function body is formed so as to overlap a part of the source / drain diffusion region.
[0029]
According to the embodiment, the read speed of the semiconductor memory device can be made sufficiently high.
[0030]
In one embodiment, the memory function body includes a charge holding film having a function of holding charge,
The charge retention film has a portion substantially parallel to the surface of the gate insulating film.
[0031]
According to the above embodiment, the variation in the memory effect of the memory elements constituting the semiconductor memory device can be reduced, so that the variation in the read current in the semiconductor memory device can be suppressed. Furthermore, since the change in the characteristics of the memory element during storage can be reduced, the storage characteristics of the semiconductor memory device are improved.
[0032]
In one embodiment, the charge storage film has a portion substantially parallel to a side surface of the gate electrode.
[0033]
According to the embodiment, the rewrite operation of the semiconductor memory device can be performed at high speed.
[0034]
In one embodiment, the semiconductor storage device further includes a portion of the charge retention film substantially parallel to a surface of the gate insulating film, and an insulating film separating the semiconductor substrate,
The film thickness of the insulating film is smaller than the film thickness of the gate insulating film and is 0.8 nm or more.
[0035]
According to the above embodiment, it is possible to reduce the voltage of the write operation and the erase operation of the semiconductor memory device, or to increase the speed of the write operation and the erase operation. Further, since the memory effect of the memory element included in the semiconductor memory device is increased, the read speed of the semiconductor memory device can be increased.
[0036]
In one embodiment, the semiconductor storage device further includes a portion of the charge retention film substantially parallel to a surface of the gate insulating film, and an insulating film separating the semiconductor substrate,
The thickness of the insulating film is larger than the thickness of the gate insulating film and is not more than 20 nm.
[0037]
According to the above embodiment, since the holding characteristics can be improved without deteriorating the short channel effect of the memory element constituting the semiconductor memory device, sufficient memory holding performance can be obtained even when the semiconductor memory device is highly integrated. be able to.
[0038]
In one embodiment of the present invention, the memory function body has a structure in which a silicon nitride film is sandwiched between silicon oxide films.
[0039]
According to the above embodiment, during the rewriting operation, the efficiency of charge injection into the memory functional unit is increased, and higher-speed operation becomes possible.
[0040]
Further, the semiconductor device of the present invention is characterized in that the above-mentioned semiconductor memory device and at least one of a column decoder, a sense amplifier and a row decoder are formed on the same semiconductor substrate.
[0041]
According to the above configuration, since the semiconductor memory device of the present invention, the column decoder, the sense amplifier, and the row decoder are provided, a specific memory element can be selected to perform the rewrite and read operations. Further, since ordinary transistors constituting logic circuits and analog circuits such as column decoders, sense amplifiers, and row decoders can be easily mixed with the semiconductor memory device of the present invention, the semiconductor device can be manufactured by a simple manufacturing process. Offered at cost.
[0042]
According to another aspect of the invention, a portable electronic device includes the above-described semiconductor storage device.
[0043]
According to the above configuration, by using the semiconductor memory device of the present invention, the capacity of the nonvolatile memory included in the control circuit can be increased, and the function of the portable electronic device can be enhanced.
[0044]
According to another aspect of the invention, a portable electronic device includes the semiconductor device.
[0045]
According to the above configuration, since the manufacturing cost of the control circuit is reduced by using the semiconductor device of the present invention, the cost of the portable electronic device can be reduced.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
The semiconductor memory device (memory cell array) of the present invention can store 2-bit information, and is configured by arranging memory elements that can be easily miniaturized and that can be easily formed.
[0047]
The memory element constituting the semiconductor memory device of the present invention is mainly arranged across a first conductivity type region, which is a diffusion region, a second conductivity type region, and a boundary between the first and second conductivity type regions. Or a gate electrode formed on a gate insulating film, a gate electrode formed on the gate insulating film, and both sides of the gate electrode. Memory function body, a source / drain region (diffusion region) disposed on the opposite side of the memory function body from the gate electrode, and a channel region disposed below the gate electrode.
[0048]
This memory element functions as a memory element for storing quaternary or more information by storing binary or more information in one charge holding film, and also has a variable resistance effect by a memory function body. , Also functions as a memory element having both functions of a selection transistor and a memory transistor. However, this memory element does not necessarily need to store and function quaternary information or more. For example, the memory element may store and function binary information.
[0049]
The semiconductor memory device of the present invention is preferably formed on a semiconductor substrate, preferably on a first conductivity type well region formed in the semiconductor substrate.
[0050]
The semiconductor substrate is not particularly limited as long as it is used for a normal semiconductor device. For example, silicon, an element semiconductor such as germanium, or a compound semiconductor such as silicon germanium, GaAs, InGaAs, ZnSe, or GaN is used. Bulk substrates. Further, as a substrate having a semiconductor layer on its surface, various substrates such as an SOI (Silicon on Insulator) substrate or a multilayer SOI substrate, or a substrate having a semiconductor layer over a glass or plastic substrate may be used. Among them, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor substrate or the semiconductor layer may have a small amount of current flowing therein, but may be single crystal (for example, by epitaxial growth), polycrystal, or amorphous.
[0051]
An element isolation region is preferably formed on this semiconductor substrate or semiconductor layer. Further, elements such as a transistor, a capacitor, and a resistor, a circuit formed by these elements, a semiconductor device, and an interlayer insulating film are combined to form a single or multiple element. It may be formed in a layer structure. The element isolation region can be formed by various element isolation films such as a LOCOS film, a trench oxide film, and an STI film. The semiconductor substrate may have a P-type or N-type conductivity type, and it is preferable that at least one first conductivity type (P-type or N-type) well region is formed in the semiconductor substrate. . The impurity concentration of the semiconductor substrate and the well region can be in a range known in the art. Note that when an SOI substrate is used as the semiconductor substrate, a well region may be formed in the surface semiconductor layer, or a body region may be provided below the channel region.
[0052]
The gate insulating film or the insulating film is not particularly limited as long as it is used for a normal semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film; an aluminum oxide film, a titanium oxide film, A single-layer film or a stacked film of a high dielectric film such as a tantalum oxide film or a hafnium oxide film can be used. Among them, a silicon oxide film is preferable. The thickness of the gate insulating film is, for example, about 1 to 20 nm, preferably about 1 to 6 nm. The gate insulating film may be formed only immediately below the gate electrode, or may be formed larger (wider) than the gate electrode.
[0053]
The gate electrode or the electrode is formed on the gate insulating film in a shape usually used for a semiconductor device or a shape having a concave portion at a lower end. Note that a single gate electrode means a gate electrode which is formed as an integral shape without being separated by a single-layer or multilayer conductive film. Further, the gate electrode may have a sidewall insulating film on a sidewall. The gate electrode is not particularly limited as long as it is generally used for a semiconductor device, and a conductive film, for example, a metal such as polysilicon: copper and aluminum: a high melting point metal such as tungsten, titanium, and tantalum: A single-layer film such as a silicide with a high-melting-point metal or a laminated film may be used. The gate electrode is preferably formed to have a thickness of, for example, about 50 to 400 nm. Note that a channel region is formed below the gate electrode.
[0054]
The memory functional unit includes at least a film or a region having a function of retaining charges, having a function of storing and retaining charges, trapping charges, or retaining a charge polarization state. Silicon nitride; silicon; silicate glass containing impurities such as phosphorus and boron; silicon carbide; alumina; high dielectric substances such as hafnium oxide, zirconium oxide, and tantalum oxide; zinc oxide; Body; metal and the like. The memory function body includes, for example, an insulator film including a silicon nitride film; an insulator film including a conductive film or a semiconductor layer therein; an insulator film including one or more conductors or semiconductor dots; It can be formed by a single layer or a laminated structure such as an insulating film including a ferroelectric film in which the state is maintained. Above all, the silicon nitride film has a large hysteresis characteristic due to the presence of many levels for trapping electric charges, and has a long charge retention time and does not cause a problem of charge leakage due to generation of a leak path. Is preferable, and is a material used as a standard in the LSI process.
[0055]
By using an insulating film including an insulating film having a charge holding function, such as a silicon nitride film, as a memory function body, reliability regarding storage and holding can be improved. This is because, since the silicon nitride film is an insulator, even if a charge leaks to a part of the silicon nitride film, the charge of the entire silicon nitride film is not immediately lost. Furthermore, when a plurality of memory elements are arranged, even if the distance between the memory elements is reduced and the adjacent memory function bodies come into contact with each other, the memory function bodies are stored in the respective memory function bodies as in the case where the memory function bodies are made of a conductor. No lost information is lost. Further, the contact plug can be arranged closer to the memory function body, and in some cases, can be arranged so as to overlap with the memory function body, which facilitates miniaturization of the memory element.
[0056]
In order to further increase the reliability of memory retention, the insulating film having a function of retaining charges does not necessarily have to be in the form of a film, and insulators having a function of retaining charges are discretely present in the insulating film. Is preferred. Specifically, it is preferable that the material is dispersed in a dot shape in a material that does not easily retain charge, for example, silicon oxide.
[0057]
In addition, by using an insulator film including a conductive film or a semiconductor layer therein as a memory function body, the amount of charge injected into the conductor or the semiconductor can be freely controlled;
[0058]
Further, by using an insulator film containing one or more conductors or semiconductor dots as a memory function body, writing and erasing by direct tunneling of electric charges can be easily performed, which has an effect of reducing power consumption.
[0059]
Further, a ferroelectric film such as PZT or PLZT whose polarization direction changes by an electric field may be used as the memory function body. In this case, electric charges are substantially generated on the surface of the ferroelectric film due to the polarization, and are maintained in that state. Therefore, a hysteresis characteristic similar to that of a film that is supplied with electric charge from outside the film having a memory function and traps electric charge can be obtained, and the charge retention of the ferroelectric film does not require charge injection from outside the film. Since the hysteresis characteristic can be obtained only by the polarization of the electric charge in the film, there is an effect that writing / erasing can be performed at high speed.
[0060]
That is, it is preferable that the memory function body further include a region that makes it difficult for the charge to escape or a film that has a function of making the charge hard to escape. As a material that functions to make it difficult for electric charge to escape, a silicon oxide film or the like can be given.
[0061]
The charge retaining film included in the memory function body is formed directly or on both sides of the gate electrode via an insulating film, and is directly formed on the semiconductor substrate (well region, body region or via a gate insulating film or insulating film). (Source / drain region or diffusion region). It is preferable that the charge holding films on both sides of the gate electrode are formed so as to cover all or a part of the side wall of the gate electrode directly or via an insulating film. As an application example, when the gate electrode has a concave portion at the lower end, the gate electrode may be formed to completely or partially fill the concave portion directly or via an insulating film.
[0062]
The gate electrode is preferably formed only on the side wall of the memory function body, or does not cover the upper part of the memory function body. With such an arrangement, the contact plug can be arranged closer to the gate electrode, so that miniaturization of the memory element is facilitated. Further, a memory element having such a simple arrangement is easy to manufacture and can improve the yield.
[0063]
In the case where a conductive film is used as the charge holding film, the charge holding film is provided with an insulating film interposed therebetween so as not to directly contact the semiconductor substrate (the well region, the body region, the source / drain region, or the diffusion region) or the gate electrode. Is preferred. For example, a stacked structure of a conductive film and an insulating film, a structure in which a conductive film is dispersed in a dot shape or the like in an insulating film, a structure in which a part is arranged in a side wall insulating film formed on a side wall of a gate, and the like are given. .
[0064]
The source / drain regions are arranged as diffusion regions of a conductivity type opposite to that of the semiconductor substrate or the well region on the opposite side of the charge holding film from the gate electrode. The junction between the source / drain region and the semiconductor substrate or well region preferably has a steep impurity concentration. This is because hot electrons and hot holes are efficiently generated at a low voltage, and a high-speed operation can be performed at a lower voltage. The junction depth of the source / drain regions is not particularly limited, and can be appropriately adjusted according to the performance of the semiconductor memory device to be obtained. Note that in the case where an SOI substrate is used as the semiconductor substrate, the source / drain regions may have a junction depth smaller than the thickness of the surface semiconductor layer; It is preferable to have the following junction depth.
[0065]
The source / drain region may be arranged so as to overlap with the gate electrode end, may be arranged so as to coincide with the gate electrode end, or may be arranged offset from the gate electrode end. You may. In particular, in the case of offset, when a voltage is applied to the gate electrode, the easiness of inversion of the offset region below the charge retaining film greatly changes depending on the amount of charge accumulated in the memory function body, and the memory effect is reduced. It is preferred because it increases and brings about a reduction in the short channel effect. However, if the offset is too much, the drive current between the source and the drain becomes extremely small. Therefore, the offset is larger than the thickness of the charge retention film in the direction parallel to the gate length direction, that is, one gate electrode end in the gate length direction. It is preferable that the distance from the nearer source / drain region is shorter. What is particularly important is that at least a part of the charge storage region in the memory function body overlaps with a part of the source / drain region which is a diffusion region. The essence of the memory element constituting the semiconductor memory device of the present invention is that the memory is rewritten by the electric field crossing the memory function body due to the voltage difference between the gate electrode and the source / drain region existing only on the side wall of the memory function body. That's why.
[0066]
The source / drain region may partially extend to a position higher than the surface of the channel region, that is, the lower surface of the gate insulating film. In this case, it is appropriate that a conductive film integrated with the source / drain region is laminated on the source / drain region formed in the semiconductor substrate. Examples of the conductive film include semiconductors such as polysilicon and amorphous silicon, silicide, the above-mentioned metals, and high-melting point metals. Among them, polysilicon is preferable. This is because polysilicon has a much higher impurity diffusion rate than a semiconductor substrate, so that it is easy to reduce the junction depth of the source / drain regions in the semiconductor substrate, and it is easy to suppress the short channel effect. . In this case, it is preferable that a part of the source / drain region is disposed so as to sandwich at least a part of the memory function body together with the gate electrode.
[0067]
The memory element of the present invention can be formed by an ordinary semiconductor process, for example, by a method similar to the method of forming a single-layer or laminated sidewall spacer on the side wall of a gate electrode. Specifically, after forming a gate electrode or an electrode, a single layer including a charge holding film such as a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, and an insulating film / charge holding film / insulating film. A method of forming a film or a laminated film, etching back under appropriate conditions to leave these films in the form of sidewall spacers; forming an insulating film or a charge retaining film, etching back under appropriate conditions, and forming a sidewall. A method in which a charge retaining film or an insulating film is formed in the form of a spacer and then further etched back to form a sidewall spacer; a semiconductor substrate including a gate electrode formed of an insulating film material in which a particulate charge retaining material is dispersed A method of coating or depositing on the upper surface and etching back under appropriate conditions to leave the insulating film material in the shape of a side wall spacer; after forming a gate electrode, forming the single layer film or the laminated film , And a method of patterning with a mask. Before forming a gate electrode or an electrode, a charge holding film, a charge holding film / insulating film, an insulating film / charge holding film, an insulating film / charge holding film / insulating film, and the like are formed. An opening is formed in a region to be formed, a gate electrode material film is formed over the entire surface, and the gate electrode material film is patterned into a shape including the opening and larger than the opening.
[0068]
When a memory cell array is configured by arranging the memory elements of the present invention, the best mode of the memory element is, for example, (1) a gate electrode of a plurality of memory elements is integrated to have a word line function. A memory function body is formed on both sides of the word line. (3) An insulator, particularly a silicon nitride film, holds electric charges in the memory function body. (4) An ONO (Oxide) memory function body is used. The silicon nitride film has a surface substantially parallel to the surface of the gate insulating film. (5) The silicon nitride film in the memory function unit is formed of a silicon oxide film and a word line and a channel region. (6) the silicon nitride film in the memory function body and the diffusion region overlap each other, (7) a silicon oxide film having a surface substantially parallel to the surface of the gate insulating film. (8) The writing and erasing operations of one memory element are performed by a single word line, and the thickness of the insulating film separating the con-nitride film from the channel region or the semiconductor layer is different from the thickness of the gate insulating film. 9) There is no electrode (word line) having a function of assisting the writing and erasing operations on the memory function body. (10) A portion opposite to the conductivity type of the diffusion region is provided directly below the memory function body in contact with the diffusion region. It has a region having a high impurity concentration of the mold, which satisfies the following requirement. The best mode is the case where all the above requirements are satisfied. However, it is needless to say that all the above requirements need not be satisfied.
[0069]
When a plurality of the above requirements are satisfied, a particularly preferable combination exists. For example, (3) an insulator, particularly a silicon nitride film, holds electric charges in the memory function body, and (9) an electrode (word line) having a function of assisting a write and erase operation on the memory function body. (6) The case where the insulating film (silicon nitride film) in the memory function body and the diffusion region overlap. If the insulator holds the electric charge in the memory function body and there is no electrode having a function of assisting the writing and erasing operations on the memory function body, the insulating film ( It has been found that the writing operation is performed favorably only when the silicon nitride film) and the diffusion region overlap. That is, it has been found that when the requirements (3) and (9) are satisfied, the requirement (6) must be satisfied. On the other hand, when the electric charge is held in the memory function body by the conductor, the writing operation can be performed even when the conductor in the memory function body and the diffusion region do not overlap (the conductor in the memory function body). Is to assist writing by capacitive coupling with the writing electrode). Further, when an electrode having a function of assisting the writing and erasing operations was provided on the memory function body, the writing operation could be performed even when the insulating film and the diffusion region in the memory function body did not overlap. .
[0070]
However, in the case where it is an insulator, not a conductor, that retains electric charge in the memory function body, and there is no electrode having a function of assisting writing and erasing operations on the memory function body, A very large effect can be obtained.
[0071]
First, the bit line contact can be arranged closer to the memory function body on the side wall of the word line, or even if the distance between the memory elements is short, a plurality of memory function bodies can hold the stored information without interference. This facilitates miniaturization of the memory element. When the charge holding region in the memory function body is a conductor, interference occurs between the charge holding regions as the memory elements approach each other due to capacitive coupling, and storage information cannot be held.
[0072]
When the charge holding region in the memory function body is an insulator (for example, a silicon nitride film), it is not necessary to make the memory function body independent for each memory element. For example, memory function bodies formed on both sides of one word line shared by a plurality of memory elements need not be separated for each memory element, and memory function bodies formed on both sides of one word line. Can be shared by a plurality of memory elements sharing a word line. Therefore, a photo and etching process for separating the memory function body is not required, and the manufacturing process is simplified. Further, since a margin for photo alignment and a margin for reducing the film thickness of etching are not required, a margin between memory elements can be reduced. Therefore, as compared with the case where the charge holding region in the memory function body is a conductor (for example, a polycrystalline silicon film), even if formed at the same fine processing level, there is an effect that the memory element occupation area can be reduced (memory When the charge holding region in the functional body is a conductor, a photo and etching process for separating the memory functional body for each memory element is required, and a photo alignment margin and an etching film reduction margin are required.
[0073]
Furthermore, since there is no electrode having a function of assisting the writing and erasing operations on the memory function body and the element structure is simple, the number of steps is reduced, the yield is improved, and the transistors constituting the logic circuit and the analog circuit are formed. Can be easily combined.
[0074]
Further, as a very important design matter, when the charge holding region in the memory function body is an insulator and there is no electrode having a function of assisting the writing and erasing operations on the memory function body (the above two conditions). Is very effective in reducing the cell occupation area, improving the yield by simplifying the manufacturing method, and reducing the cost). We have found that wrapping allows writing and erasing at very low voltages. Specifically, it was confirmed that the writing and erasing operations were performed at a low voltage of 5 V or less. This function has a very large effect on circuit design. That is, since it is not necessary to generate a high voltage in a chip as in a flash memory, it is possible to omit a charge pumping circuit requiring an enormous occupation area or to reduce the scale. In particular, when a small-capacity memory is built in a logic LSI for adjustment, the occupied area of the memory section is more dominated by the peripheral circuit driving the memory element than the memory element. Eliminating or reducing the scale of the booster circuit is most effective for reducing the chip size.
[0075]
As described above, it is particularly preferable to satisfy the requirements (3), (9), and (6).
[0076]
INDUSTRIAL APPLICABILITY The semiconductor storage device and the semiconductor device of the present invention can be used for a battery-driven portable electronic device, particularly a portable information terminal. Examples of the portable electronic device include a mobile phone, a game device, and the like, in addition to the portable information terminal.
[0077]
In the following embodiments, the memory device will be described in more detail.
[0078]
(1st Embodiment)
FIG. 1 is a cross-sectional view showing an example of a memory element constituting a semiconductor memory device of the present invention. This memory element 1 is formed on a P-type well region 102 formed on the surface of a semiconductor substrate 101. A gate electrode 104 is formed on the P-type well region 102 via a gate insulating film 103. On both sides of the gate electrode 104, memory function bodies 105a and 105b are formed. Here, the memory functional unit refers to a portion where charges are actually accumulated by a rewrite operation.
[0079]
In the example shown in FIG. 1, the upper surface and the side surface of the gate electrode 104 are covered with a silicon nitride film 109 having a trap level for retaining charges and serving as a charge retaining film. Both side wall portions of the electrode 104 serve as memory function bodies 105a and 105b, respectively, which actually hold electric charges. The diffusion regions 107a and 107b each function as a source region or a drain region. A channel region 122 is defined between the diffusion regions 107a and 107b functioning as the source region or the drain region.
[0080]
The diffusion region of the memory element 1 has an offset structure. That is, the diffusion regions 107a and 107b do not reach the lower region 121 of the gate electrode, and the offset regions 120 and 120 separating the gate electrode 104 and the diffusion regions 107a and 107b form the memory function bodies 105a and 105b. It is located below. The channel region 122 is constituted by the gate electrode lower region 121 and the offset regions 120 and 120.
[0081]
FIG. 2 shows another example of the memory element. The memory element 2 of FIG. 2 is different from the memory element 1 of FIG. 1 in that each of the memory function bodies 131a and 131b has a trap level for retaining charges, and the silicon nitride film 113 serving as a charge retention film is The point is that it has a structure sandwiched between the silicon oxide films 111 and 112. As shown in FIG. 2, by adopting a structure in which the silicon nitride film is sandwiched between the silicon oxide films, the charge injection efficiency at the time of the rewrite operation is increased, and higher-speed operation is possible.
[0082]
In FIG. 2, the silicon nitride film 113 may be replaced with a ferroelectric. Further, in FIG. 1, each of the memory function bodies 105a and 105b may have a structure in which fine particles made of a conductor or a semiconductor having a nanometer size are distributed in a scattered manner in an insulating film. At this time, if the particle size is less than 1 nm, the quantum effect is too large, so that it is difficult for charges to tunnel through the dots. If it exceeds 10 nm, a remarkable quantum effect does not appear at room temperature. Therefore, the diameter of the fine particles is preferably in the range of 1 nm to 10 nm. Further, the memory function bodies 131a and 131b do not necessarily have to be in the shape of a sidewall spacer as in the memory element 2 (FIG. 2). For example, in the memory element 1 (FIG. 1), the silicon nitride film 109 having a trap level for retaining charges covers the side and top surfaces of the gate electrode 104, but substantially functions as a memory function body for retaining charges. Are the side wall portions (105a, 105b) of the gate electrode. That is, it is only necessary that a substance that retains the function of retaining electric charge or the polarization is disposed in these regions.
[0083]
The principle of the write operation of the memory elements 1 and 2 will be described with reference to FIGS. Here, a case where the memory function bodies 131a and 131b have a function of holding electric charges will be described.
[0084]
Here, writing refers to injecting electrons into the memory function bodies 131a and 131b when the memory elements 1 and 2 are of the N-channel type. Hereinafter, description will be made on the assumption that the memory elements 1 and 2 are of the N-channel type.
[0085]
In order to inject (write) electrons into the second memory function body 131b, as shown in FIG. 3, the first diffusion region 107a (having N-type conductivity) is used as a source electrode and the second diffusion region 107a is used as a second electrode. The diffusion region 107b (having N-type conductivity) is used as a drain electrode. For example, 0V may be applied to the first diffusion region 107a and the P-type well region 102, + 5V may be applied to the second diffusion region 107b, and + 5V may be applied to the gate electrode 104. According to such a voltage condition, the inversion layer 226 extends from the first diffusion region 107a (source electrode) but does not reach the second diffusion region 107b (drain electrode), and a pinch-off point occurs. The electrons are accelerated by a high electric field from the pinch-off point to the second diffusion region 107b (drain electrode), and become so-called hot electrons (high-energy conduction electrons). The writing is performed by injecting the hot electrons into the second memory function body 131b. Note that no writing is performed in the vicinity of the first memory function body 131a because hot electrons do not occur.
[0086]
Thus, writing can be performed by injecting electrons into the second memory function body 131b.
[0087]
On the other hand, in order to inject (write) electrons into the first memory function body 131a, as shown in FIG. 4, the second diffusion region 107b is used as a source electrode, and the first diffusion region 107a is used as a drain electrode. I do. For example, 0V may be applied to the second diffusion region 107b and the P-type well region 102, + 5V may be applied to the first diffusion region 107a, and + 5V may be applied to the gate electrode 104. As described above, when electrons are injected into the second memory function body 131b, writing can be performed by injecting electrons into the first memory function body 131a by exchanging the source / drain regions.
[0088]
Next, the erasing operation principle of the memory element will be described with reference to FIGS.
[0089]
In the first method of erasing information stored in the first memory function body 131a, as shown in FIG. 5, a positive voltage (for example, + 5V) is applied to the first diffusion region 107a, and 0V is applied to the P-type well region 102. , A reverse bias is applied to the PN junction between the first diffusion region 107 a and the P-type well region 102, and a negative voltage (for example, −5 V) is applied to the gate electrode 104. At this time, in the vicinity of the gate electrode 104 of the PN junction, the potential gradient becomes particularly steep due to the influence of the gate electrode to which the negative voltage is applied. Therefore, hot holes (high-energy holes) are generated on the P-type well region 102 side of the PN junction due to the band-to-band tunnel. The hot holes are drawn toward the gate electrode 104 having a negative potential, and as a result, holes are injected into the first memory function body 131a. Thus, the first memory function body 131a is erased. At this time, 0 V may be applied to the second diffusion region 107b.
[0090]
When erasing information stored in the second memory function body 131b, the potentials of the first diffusion region and the second diffusion region may be exchanged in the above.
[0091]
In the second method for erasing information stored in the first memory function body 131a, as shown in FIG. 6, a positive voltage (for example, +4 V) is applied to the first diffusion region 107a and a voltage is applied to the second diffusion region 107b. 0 V, a negative voltage (for example, −4 V) to the gate electrode 104, and a positive voltage (for example, +0.8 V) to the P-type well region 102 may be applied. At this time, a forward voltage is applied between the P-type well region 102 and the second diffusion region 107b, and electrons are injected into the P-type well region 102. The injected electrons diffuse to the PN junction between the P-type well region 102 and the first diffusion region 107a, where they are accelerated by a strong electric field to become hot electrons. The hot electrons generate electron-hole pairs at the PN junction. That is, when a forward voltage is applied between the P-type well region 102 and the second diffusion region 107b, electrons injected into the P-type well region 102 serve as a trigger, and the PN junction located on the opposite side is triggered. Causes hot holes. Hot holes generated at the PN junction are drawn toward the gate electrode 104 having a negative potential, and as a result, holes are injected into the first memory function body 131a.
[0092]
According to the second method, even when only a voltage sufficient to generate a hot hole due to an interband tunnel is applied to the PN junction between the P-type well region and the first diffusion region 107a, the second diffusion is performed. The electrons injected from the region 107b serve as a trigger for generating an electron-hole pair at the PN junction, and can generate a hot hole. Therefore, the voltage at the time of the erase operation can be reduced. In particular, when the offset region 120 (see FIGS. 1 and 2) exists, the effect that the PN junction is sharpened by the gate electrode to which the negative potential is applied is small. Therefore, it is difficult to generate a hot hole due to the band-to-band tunnel. However, the second method can compensate for the disadvantage and realize the erasing operation at a low voltage.
[0093]
When erasing information stored in the first memory function body 131a, in the first erasing method, +5 V had to be applied to the first diffusion region 107a, but in the second erasing method, , + 4V was sufficient. As described above, according to the second method, the voltage at the time of erasing can be reduced, so that power consumption is reduced and deterioration of the memory element due to hot carriers can be suppressed.
[0094]
Regardless of the erasing method, the memory element of the present invention has a feature that over-erasing hardly occurs. Over-erasing is a phenomenon in which the threshold value decreases without saturation as the amount of holes stored in the memory function body increases. This is a serious problem in EEPROMs typified by flash memories. In particular, when the threshold value becomes negative, a fatal operation failure occurs, in which selection of a memory element becomes impossible. In the memory element of the present invention, even when a large amount of holes are accumulated in the memory function body, only electrons are induced under the memory function body, and the potential of the channel region under the gate insulating film is hardly affected. Do not give. Since the threshold value at the time of erasing is determined by the potential under the gate insulating film, over-erasing hardly occurs.
[0095]
Next, the principle of the read operation of the memory element will be described with reference to FIG.
[0096]
When reading the information stored in the first memory function body 131a, as shown in FIG. 7, the transistor is operated by using the first diffusion region 107a as a source electrode and the second diffusion region 107b as a drain electrode. For example, 0V may be applied to the first diffusion region 107a and the P-type well region 102, + 2V may be applied to the second diffusion region 107b, and + 2V may be applied to the gate electrode 104. At this time, when electrons are not accumulated in the first memory function body 131a, a drain current easily flows. On the other hand, when electrons are accumulated in the first memory function body 131a, an inversion layer is not easily formed near the first memory function body 131a, so that a drain current does not easily flow. Therefore, by detecting the drain current, information stored in the first memory function body 131a can be read. In particular, when reading by applying a voltage that causes a pinch-off operation, the state of charge accumulation in the second memory function body 131a can be determined with higher accuracy without being affected by the presence or absence of charge accumulation in 131b. It becomes.
[0097]
When reading information stored in the second memory function body 131b, the transistor is operated using the second diffusion region 107b as a source electrode and the first diffusion region 107a as a drain electrode. For example, 0V may be applied to the second diffusion region 107b and the P-type well region 102, + 1.8V may be applied to the first diffusion region 107a, and + 2V may be applied to the gate electrode 104. As described above, when the information stored in the first memory function body 131a is read, the information stored in the second memory function body 131b can be read by exchanging the source / drain regions. .
[0098]
Note that in the case where a channel region (offset region 120) not covered by the gate electrode 104 is left, an inversion layer is formed in the channel region not covered by the gate electrode 104 depending on the presence or absence of excess charge of the memory function bodies 131a and 131b. It disappears or forms, resulting in a large hysteresis (change in threshold). However, if the width of the offset region 120 is too large, the drain current is greatly reduced, and the reading speed is significantly reduced. Therefore, it is preferable to determine the width of the offset region 102 so that sufficient hysteresis and reading speed can be obtained.
[0099]
Even when the diffusion regions 107a and 107b reach the end of the gate electrode 104, that is, even when the diffusion regions 107a and 107b and the gate electrode 104 overlap, the threshold value of the transistor hardly changes due to the writing operation. However, the parasitic resistance at the source / drain ends was greatly changed, and the drain current was greatly reduced (one digit or more). Therefore, reading can be performed by detecting the drain current, and a function as a memory can be obtained. However, when a larger memory hysteresis effect is required, it is preferable that the diffusion regions 107a and 107b do not overlap with the gate electrode 104 (the offset region 120 exists).
[0100]
With the above operation method, two bits can be selectively written and erased per transistor. The word line WL is connected to the gate electrode 104 of the memory element, the first bit line BL1 is connected to the first diffusion region 107a, and the second bit line BL2 is connected to the second diffusion region 107b. By arranging, a memory cell array can be formed.
[0101]
Further, in the above operation method, two bits are written and erased per transistor by exchanging the source electrode and the drain electrode. However, the source electrode and the drain electrode may be fixed to operate as a one-bit memory. In this case, one of the source / drain regions can be set to a common fixed voltage, and the number of bit lines connected to the source / drain regions can be reduced by half.
[0102]
As is clear from the above description, according to the memory element, the memory function body is formed independently of the gate insulating film and formed on both sides of the gate electrode. Therefore, a two-bit operation is possible. Further, since each memory function body is separated by the gate electrode, interference at the time of rewriting is effectively suppressed. Further, since the gate insulating film is separated from the memory function body, the short channel effect can be suppressed by reducing the thickness of the gate insulating film. Therefore, miniaturization of the memory element is facilitated.
[0103]
(2nd Embodiment)
The memory element according to this embodiment includes a region where the memory function bodies 261 and 262 hold charges (a region that stores charges and may be a film having a function of holding charges) and a region where the charges hardly escape. (May be a film having a function of preventing charge from escaping). For example, as shown in FIG. 8, it has an ONO structure. That is, the silicon nitride film 242 is interposed between the silicon oxide film 241 and the silicon oxide film 243 to form the memory function bodies 261 and 262. Here, the silicon nitride film 242 performs a function of retaining charges. In addition, the silicon oxide films 241 and 243 play a role of a film having a function of making it difficult for the charges stored in the silicon nitride film to escape.
[0104]
Further, the regions (silicon nitride films 242) of the memory function bodies 261 and 262 which hold the charges overlap with the diffusion regions 212 and 213, respectively. Here, the term “overlap” means that at least a part of the charge holding region (silicon nitride film 242) exists on at least a part of the diffusion regions 212 and 213. In the present embodiment, the tip of the horizontal portion 281 of the silicon nitride film 242 exists above the end on the opposite side of the diffusion regions 212 and 213. Note that 211 is a semiconductor substrate, 214 is a gate insulating film, 217 is a gate electrode, and 271 is an offset region (between the gate electrode and the diffusion region). The outermost surface of the semiconductor substrate 211 between the diffusion regions 212 and 213 is a channel region 272.
[0105]
The effect of overlapping the charge holding region 242 (silicon nitride film 242) and the diffusion regions 212 and 213 in the memory function bodies 261 and 262 will be described.
[0106]
FIG. 9 is an enlarged view of the periphery of the memory function body 262 on the right side of FIG. W1 indicates an offset amount between the gate electrode 214 and the diffusion region 213. W2 indicates the width of the memory function body 262 at the cut surface of the gate electrode in the channel length direction. Here, the end of the memory function body 262 on the side of the silicon nitride film 242 remote from the gate electrode 217 (the tip of the horizontal portion 281 of the silicon nitride film 242) is connected to the memory function body 262 on the side remote from the gate electrode 217. , The width of the memory function body 262 is defined as W2. W2-W1 is the amount of overlap between the memory function body 262 and the diffusion region 213. What is particularly important is that the silicon nitride film 242 of the memory function body 262 overlaps with the diffusion region 213, that is, satisfies the relationship of W2> W1.
[0107]
As shown in FIG. 10, when the end of the silicon nitride film 242a of the memory function body 262a remote from the gate electrode does not coincide with the end of the memory function body 262a remote from the gate electrode. , W2 may be defined from the end of the gate electrode to the end of the silicon nitride film 142a farther from the gate electrode 217a.
[0108]
FIG. 11 shows the drain current Id when the width W2 of the memory function body 262 is fixed to 100 nm and the offset amount W1 is changed in the structure of FIG. Here, the drain current was obtained by device simulation using the memory function body 262 in an erased state (having holes stored therein) and using the diffusion regions 212 and 213 as a source electrode and a drain electrode, respectively.
[0109]
As is clear from FIG. 11, when W1 is 100 nm or more (that is, when the silicon nitride film 242 and the diffusion region 213 do not overlap), the drain current decreases rapidly. Since the drain current value is almost proportional to the read operation speed, the memory performance is rapidly deteriorated when W1 is 100 nm or more. On the other hand, in a range where the silicon nitride film 242 and the diffusion region 213 overlap, the drain current decreases slowly. Therefore, in consideration of variations in mass production, if at least a part of the silicon nitride film 242, which is a film having a function of retaining electric charges, and the source / drain regions do not overlap, a memory function can be obtained effectively. Have difficulty.
[0110]
Based on the results of the device simulation described above, W2 was fixed at 100 nm, and memory cell arrays were fabricated with W1 of 60 nm and 100 nm as design values. When W1 is 60 nm, the silicon nitride film and the diffusion region overlap by 40 nm at the design value, and when W1 is 100 nm, they do not overlap by the design value. As a result of measuring the read time of these memory cell arrays, the read access time was 100 times faster when W1 was set to 60 nm as the design value, compared with the worst case in which the variation was considered. In practice, the read access time is preferably 100 nanoseconds or less per bit, but it has been found that this condition cannot be achieved at all when W1 = W2. In addition, it has been found that W2-W1> 10 nm is more preferable in consideration of manufacturing variations.
[0111]
As in the first embodiment, the information stored in the memory function body 261 is read by forming the diffusion region 212 as a source electrode and the diffusion region 213 as a drain region to form a pinch-off point on the channel region near the drain region. Is preferred. That is, when reading information stored in one of the two memory function bodies, it is preferable to form a pinch-off point in a region within the channel region and close to the other memory function body. Thereby, regardless of the storage state of the memory function body 262, the storage information of the memory function body 261 can be detected with high sensitivity, which is a major factor that enables the 2-bit operation.
[0112]
On the other hand, when information is stored only on one side of the two memory function bodies or when the two memory function bodies are used in the same storage state, it is not always necessary to form a pinch-off point at the time of reading.
[0113]
Although not shown in FIG. 8, it is preferable to form a well region (a P-type well in the case of an N-channel element) on the surface of the semiconductor substrate 211. By forming the well region, it is easy to control the other electrical characteristics (breakdown voltage, junction capacitance, short channel effect) while optimizing the impurity concentration of the channel region for the memory operation (rewrite operation and read operation). .
[0114]
It is preferable that the memory function body includes a charge holding film having a function of holding charges and an insulating film from the viewpoint of improving the holding characteristics of the memory. In this embodiment, a silicon nitride film 242 having a level for trapping charges is used as a charge holding film, and silicon oxide films 241 and 243 having a function of preventing dissipation of charges accumulated in the charge holding film are used as insulating films. . Since the memory function body includes the charge holding film and the insulating film, the charge can be prevented from dissipating and the holding characteristics can be improved. Furthermore, the volume of the charge holding film can be appropriately reduced as compared with the case where the memory function body is composed of only the charge holding film. By appropriately reducing the volume of the charge holding film, the movement of charges in the charge holding film can be limited, and a change in characteristics due to the charge transfer during storage can be suppressed.
[0115]
Further, it is preferable that the memory function body includes a charge holding film disposed substantially parallel to the surface of the gate insulating film. In other words, it is preferable that the charge retention film in the memory function body is disposed at an equal distance from the height corresponding to the upper surface of the gate insulating film. Specifically, as shown in FIG. 12, the charge holding film 242a of the memory function body 262 is substantially parallel to the surface of the gate insulating film 214. In other words, it is preferable that the charge holding film 242a be formed at a uniform height from the height corresponding to the surface of the gate insulating film 214. The presence of the charge holding film 242a substantially parallel to the surface of the gate insulating film 214 in the memory function body 262 reduces the likelihood of the inversion layer being formed in the offset region 271 due to the amount of charge accumulated in the charge holding film 242a. Effective control can be achieved, and the memory effect can be increased. Further, by making the charge holding film 242a substantially parallel to the surface of the gate insulating film 214, even when the offset amount (W1) varies, the change in the memory effect can be kept relatively small, and the variation in the memory effect can be suppressed. can do. In addition, the movement of charges in the upper direction of the charge holding film 242a is suppressed, so that a change in characteristics due to the movement of charges during storage can be suppressed.
[0116]
Further, the memory function body 262 is formed of an insulating film (for example, a portion of the silicon oxide film 244 on the offset region 271 which separates the charge holding film 242 a substantially parallel to the surface of the gate insulating film 214 from the channel region (or well region). ) Is preferable. With this insulating film, dissipation of the charge accumulated in the charge holding film is suppressed, and a memory element with better holding characteristics can be obtained.
[0117]
The thickness of the charge holding film 242a is controlled, and the thickness of the insulating film below the charge holding film 242a (the portion of the silicon oxide film 244 on the offset region 271) is controlled to be constant, so that the surface of the semiconductor substrate is controlled. It is possible to keep the distance from to the charge stored in the charge holding film approximately constant. That is, the distance from the surface of the semiconductor substrate to the charge stored in the charge holding film is determined from the minimum film thickness of the insulating film below the charge holding film 242a to the maximum film thickness of the insulating film below the charge holding film 242a. The control can be performed up to the sum of the maximum thickness value of the film 242a. As a result, the density of lines of electric force generated by the electric charges stored in the charge holding film 242a can be substantially controlled, and the variation in the memory effect of the memory element can be greatly reduced.
[0118]
(Third embodiment)
In this embodiment, the charge retaining film 242 of the memory function body 262 has a substantially uniform film thickness and a horizontal portion 281 substantially parallel to the surface of the gate insulating film 214 as shown in FIG. Further, it has a vertical portion 282 substantially parallel to the side surface of the gate electrode 217.
[0119]
When a positive voltage is applied to the gate electrode 217, the lines of electric force in the memory function body 262 divide the silicon nitride film 242 twice by the vertical portion 282 and the horizontal portion 281 as shown by an arrow 283. pass. When a negative voltage is applied to the gate electrode 217, the direction of the lines of electric force is on the opposite side. Here, the relative permittivity of the silicon nitride film 242 is about 6, and the relative permittivity of the silicon oxide films 241 and 243 is about 4. Therefore, the effective relative dielectric constant of the memory function body 262 in the direction of the electric flux lines 283 is larger than that in the case where the charge holding film has only the horizontal portion 281, and the potential difference at both ends of the electric flux lines is smaller. be able to. That is, most of the voltage applied to the gate electrode 217 is used to increase the electric field in the offset region 271.
[0120]
The charge is injected into the silicon nitride film 242 during the rewrite operation because the generated charge is drawn by the electric field in the offset region 271. Therefore, when the charge retaining film includes the horizontal portion 282, the charge injected into the memory function body 262 during the rewriting operation increases, and the rewriting speed increases.
[0121]
When the silicon oxide film 243 is also formed of the silicon nitride film, that is, when the charge holding film is not uniform with respect to the height corresponding to the surface of the gate insulating film 214, the charge in the upward direction of the silicon nitride film is Movement becomes conspicuous, and the holding characteristics deteriorate.
[0122]
It is more preferable that the charge retention film is formed of a high dielectric material such as hafnium oxide having a very large relative dielectric constant instead of the silicon nitride film.
[0123]
Further, the memory function body may further include an insulating film (a portion of the silicon oxide film 241 on the offset region 271) separating the charge holding film substantially parallel to the surface of the gate insulating film and the channel region (or well region). preferable. With this insulating film, dissipation of the charges accumulated in the charge holding film is suppressed, and the holding characteristics can be further improved.
[0124]
In addition, the memory function body may further include an insulating film (a portion of the silicon oxide film 241 that is in contact with the gate electrode 217) separating the gate electrode and the charge holding film extending in a direction substantially parallel to the side surface of the gate electrode. preferable. With this insulating film, it is possible to prevent electric charges from being injected from the gate electrode into the charge holding film and to prevent the electrical characteristics from changing, thereby improving the reliability of the memory element.
[0125]
Further, similarly to the second embodiment, the thickness of the insulating film (the portion of the silicon oxide film 241 above the offset region 271) under the charge holding film 242 is controlled to be constant, and furthermore, it is disposed on the side surface of the gate electrode. It is preferable to control the thickness of the insulating film (the portion of the silicon oxide film 241 in contact with the gate electrode 217) to be constant. Thus, the density of lines of electric force generated by the electric charges stored in the electric charge holding film 242 can be substantially controlled, and electric charge leakage can be prevented.
[0126]
(Fourth embodiment)
This embodiment relates to optimization of a distance between a gate electrode, a memory function body, and a source / drain region.
[0127]
As shown in FIG. 14, A is the gate electrode length in the cut surface in the channel length direction, B is the distance between the source / drain regions (channel length), and C is the end of one memory function body to the other memory function body. , That is, the charge in the other memory function body from the end of the film having the function of holding the charge in one memory function body (the side away from the gate electrode) in the cut surface in the channel length direction. It shows the distance to the end of the film having the function of performing the function (the side away from the gate electrode).
[0128]
First, it is preferable that B <C. An offset region 271 exists between a portion of the channel region below the gate electrode 217 and the source / drain regions 212 and 213. Due to B <C, the charge accumulated in the memory function bodies 261 and 262 (silicon nitride film 242) effectively changes the ease of inversion in the entire offset region 271. Therefore, the memory effect increases, and particularly, the speed of the read operation is increased.
[0129]
In addition, when the gate electrode 217 is offset from the source / drain regions 212 and 213, that is, when A <B is satisfied, it is difficult to invert the offset region when a voltage is applied to the gate electrode. It changes greatly depending on the amount of electric charge stored in the memory function body, so that the memory effect increases and the short channel effect can be reduced. However, as long as the memory effect appears, it is not always necessary to exist. Even when there is no offset region 271, if the impurity concentration of the source / drain regions 212 and 213 is sufficiently low, a memory effect can be exhibited in the memory function bodies 261 and 262 (silicon nitride film 242).
[0130]
Therefore, it is most preferable that A <B <C.
[0131]
(Fifth embodiment)
As shown in FIG. 15, the memory element of this embodiment has substantially the same configuration as that of the second embodiment except that the semiconductor substrate in the second embodiment is an SOI substrate.
[0132]
In this memory element, a buried oxide film 288 is formed on a semiconductor substrate 286, and an SOI layer is further formed thereon. Diffusion regions 212 and 213 are formed in the SOI layer, and the other regions are body regions 287.
[0133]
This memory element also has the same function and effect as the memory element of the second embodiment. Further, the junction capacitance between the diffusion regions 212 and 213 and the body region 287 can be significantly reduced, so that the speed of the element can be increased and the power consumption can be reduced.
[0134]
(Sixth embodiment)
The memory device of this embodiment is different from the second embodiment in that a P-type high-concentration region 291 is added adjacent to the channel side of the N-type source / drain regions 212 and 213 as shown in FIG. , Has substantially the same configuration as the second embodiment.
[0135]
That is, the P-type impurity (for example, boron) concentration in the P-type high concentration region 291 is higher than the P-type impurity concentration in the region 292. The P-type impurity concentration in the P-type high concentration region 291 is, for example, 5 × 10 ¹⁷ ~ 1 × 10 ¹⁹ cm ^-3 The degree is appropriate. The P-type impurity concentration of the region 292 is, for example, 5 × 10 ¹⁶ ~ 1 × 10 ¹⁸ cm ^-3 It can be.
[0136]
As described above, by providing the P-type high-concentration region 291, the junction between the diffusion regions 212 and 213 and the semiconductor substrate 211 becomes steep immediately below the memory function bodies 261 and 262. Therefore, hot carriers are easily generated at the time of writing and erasing operations, and the voltage of the writing and erasing operations can be reduced, or the speed of the writing and erasing operations can be increased. Further, since the impurity concentration of region 292 is relatively low, the threshold value when the memory is in the erased state is low, and the drain current is large. Therefore, the reading speed is improved. Therefore, a memory element having a low rewrite voltage or a high rewrite speed and a high read speed can be obtained.
[0137]
In FIG. 16, the P-type high-concentration region 291 is provided near the source / drain region and below the memory function body (that is, a position not directly below the gate electrode). To rise. The degree of this increase is significantly greater than when the P-type high concentration region 291 is immediately below the gate electrode. When the write charge (electrons when the transistor is an N-channel type) is accumulated in the memory function body, the difference is further increased. On the other hand, when sufficient erase charge (holes when the transistor is an N-channel type) is accumulated in the memory function body, the threshold value of the transistor as a whole is determined by the impurity concentration of the channel region (region 292) below the gate electrode. It falls to the determined threshold. That is, the threshold value at the time of erasing does not depend on the impurity concentration of the P-type high concentration region 291, while the threshold value at the time of writing is greatly affected. Therefore, by disposing the P-type high-concentration region 291 under the memory functioning body and in the vicinity of the source / drain region, only the threshold value at the time of writing fluctuates very greatly, and the memory effect (at the time of writing and erasing). Threshold difference) can be significantly increased.
[0138]
(Seventh embodiment)
In the memory element of this embodiment, as shown in FIG. 17, in the second embodiment, the thickness (T1) of the insulating film separating the charge holding film (silicon nitride film 242) from the channel region or the well region is equal to the gate. Except that it is thinner than the thickness (T2) of the insulating film, it has substantially the same configuration as the second embodiment.
[0139]
The thickness T2 of the gate insulating film 214 has a lower limit due to demand for withstand voltage at the time of a memory rewrite operation. However, the thickness T1 of the insulating film can be made smaller than T2 regardless of the demand for the withstand voltage.
[0140]
In the memory element according to the present embodiment, the degree of freedom of design for T1 is high as described above for the following reason. In the memory element of the present embodiment, the insulating film that separates the charge holding film from the channel region or the well region is not sandwiched between the gate electrode and the channel region or the well region. Therefore, a high electric field acting between the gate electrode and the channel region or the well region does not directly act on the insulating film separating the charge retention film and the channel region or the well region, and a relatively weak electric field spreading laterally from the gate electrode. Works. Therefore, it is possible to make T1 thinner than T2 regardless of the demand for the withstand voltage for the gate insulating film. On the other hand, for example, in an EEPROM typified by a flash memory, an insulating film separating a floating gate and a channel region or a well region is sandwiched between a gate electrode (control gate) and a channel region or a well region. The high electric field from directly acts. Therefore, in the EEPROM, the thickness of the insulating film separating the floating gate from the channel region or the well region is limited, and the optimization of the function of the memory element is hindered. As is clear from the above, in the memory element of the present embodiment, the fact that the insulating film separating the charge retaining film and the channel region or the well region is not sandwiched between the gate electrode and the channel region or the well region is free from T1. This is an essential reason for increasing the degree.
[0141]
By making T1 thinner, it becomes easier to inject charges into the memory function body, it is possible to lower the voltage of the write operation and the erase operation, or to increase the speed of the write operation and the erase operation. Since the amount of charges induced in the channel region or the well region when charges are accumulated in the nitride film 242 increases, the memory effect can be increased.
[0142]
By the way, as shown by an arrow 284 in FIG. 13, there are short lines of electric force in the memory function body that do not pass through the silicon nitride film 242. Since the electric field strength is relatively large on such a short line of electric force, the electric field along the line of electric force plays a large role during the rewriting operation. By reducing the thickness of T1, the silicon nitride film 242 moves to the lower side in the figure, and the lines of electric force indicated by arrows 283 pass through the silicon nitride film. Therefore, the effective relative permittivity in the memory function body along the electric flux lines 284 increases, and the potential difference at both ends of the electric flux lines can be further reduced. Therefore, a large part of the voltage applied to the gate electrode 217 is used to increase the electric field in the offset region, and the writing operation and the erasing operation are performed at high speed.
[0143]
As is clear from the above, by setting T1 <T2, the voltage of the writing operation and the erasing operation can be reduced, or the writing operation and the erasing operation can be speeded up without lowering the withstand voltage performance of the memory, and the memory effect can be further improved. It is possible to increase.
[0144]
The thickness T1 of the insulating film is preferably at least 0.8 nm, which is a limit at which uniformity and film quality due to the manufacturing process can be maintained at a certain level and holding characteristics are not extremely deteriorated. preferable.
[0145]
Specifically, in the case of a liquid crystal driver LSI which requires a high withstand voltage having a large design rule, a maximum voltage of 15 to 18 V is required to drive the liquid crystal panel TFT. Therefore, the thickness of the gate oxide film cannot be reduced. When the nonvolatile memory of the present invention is mixedly mounted on the liquid crystal driver LSI for image adjustment, in the memory element of the present invention, the charge holding film (silicon nitride film 242) and the channel region or the well region are independent of the gate insulating film thickness. The thickness of the insulating film that separates the above can be optimally designed. For example, a memory element having a gate electrode length (word line width) of 250 nm can be individually set at T1 = 20 nm and T2 = 10 nm, thereby realizing a memory element with high writing efficiency. (The reason that the short channel effect does not occur even when T1 is thicker than a normal logic transistor is because the source / drain regions are offset with respect to the gate electrode).
[0146]
(Eighth embodiment)
In the memory element of this embodiment, as shown in FIG. 18, in the second embodiment, the thickness (T1) of the insulating film separating the charge holding film (silicon nitride film 242) from the channel region or the well region is equal to the gate. Except that it is thicker than the thickness (T2) of the insulating film, it has substantially the same configuration as the second embodiment.
[0147]
The thickness T2 of the gate insulating film 214 has an upper limit due to a demand for preventing a short channel effect of the device. However, the thickness T1 of the insulating film can be made larger than T2 irrespective of the need to prevent the short channel effect. That is, when the miniaturization scaling advances (when the gate insulating film becomes thinner), the insulation separating the charge holding film (silicon nitride film 242) and the channel region or the well region is independent of the gate insulating film thickness. Since the thickness of the film can be optimally designed, there is an effect that the memory function body does not hinder the scaling.
[0148]
As described above, in the memory element of the present embodiment, the reason for the high degree of freedom in design for T1 is that the insulating film that separates the charge retention film from the channel region or the well region includes the gate electrode and the channel region or the insulating film. It is because it is not sandwiched between the well region. Therefore, T1 can be made thicker than T2 irrespective of the request for preventing the short channel effect on the gate insulating film.
[0149]
By increasing the thickness of T1, it is possible to prevent the charge accumulated in the memory function body from being dissipated, and to improve the retention characteristics of the memory.
[0150]
Therefore, by setting T1> T2, it is possible to improve the holding characteristics without deteriorating the short channel effect of the memory.
[0151]
Note that the thickness T1 of the insulating film is preferably 20 nm or less in consideration of a decrease in the rewriting speed.
[0152]
Specifically, in a conventional nonvolatile memory represented by a flash memory, a select gate electrode forms a write / erase gate electrode, and a gate insulating film (including a floating gate) corresponding to the write / erase gate electrode has a charge. The storage film is also used. For this reason, the demand for miniaturization (it is necessary to reduce the film thickness to suppress the short channel effect) and the securing of reliability (the thickness of the insulating film that separates the floating gate from the channel region or the well region in order to suppress the leakage of the retained charges, Since the requirement of being less than about 7 nm cannot be achieved, miniaturization becomes difficult. In fact, according to the ITRS (International Technology Roadmap for Semiconductors), the miniaturization of the physical gate length has not been remarkable for about 0.2 μm or less. In the memory element of the present invention, T1 and T2 can be individually designed as described above, so that miniaturization becomes possible. For example, in the present invention, a memory element having a gate electrode length (word line width) of 45 nm is individually set at T2 = 4 nm and T1 = 7 nm, thereby realizing a memory element free from a short channel effect. The reason that the short channel effect does not occur even when T2 is set to be thicker than a normal logic transistor is because the source / drain regions are offset with respect to the gate electrode. Further, in the memory element of the present invention, since the source / drain regions are offset with respect to the gate electrode, miniaturization is further facilitated as compared with a normal logic transistor.
[0153]
In summary, since there is no electrode for assisting writing and erasing above the memory function body, the electrode and channel for assisting writing and erasing are formed on the insulating film separating the charge holding film and the channel region or the well region. The high electric field acting between the regions or well regions does not act directly, only the relatively weak electric field spreading laterally from the gate electrode acts. Therefore, it is possible to realize a memory element having a gate length miniaturized to be equal to or more than the gate length of the logic transistor for the same processing generation.
[0154]
(Ninth embodiment)
This embodiment relates to a change in electrical characteristics when a memory element is rewritten.
[0155]
FIG. 19 shows characteristics (actually measured values) of the drain current (Id) versus the gate voltage (Vg) when the amount of charge in the memory function body of the N-channel type memory element changes. The solid line shows the characteristics in the erased state, and the dotted line shows the characteristics in the written state. As is clear from FIG. 19, when the writing operation is performed from the erased state, not only does the threshold value simply rise, but also the slope of the graph is significantly reduced particularly in the sub-threshold region. Therefore, even in a region where the gate voltage (Vg) is relatively high, the drain current ratio between the erased state and the written state is large. For example, even at Vg = 2.5 V, the current ratio maintains two digits or more. This characteristic is significantly different from the case of the flash memory (FIG. 37).
[0156]
The appearance of such characteristics is a peculiar phenomenon that occurs because the gate electrode and the diffusion region are offset and the gate electric field is hard to reach the offset region. When the memory element is in the written state, even if a positive voltage is applied to the gate electrode, it is extremely difficult to form an inversion layer in the offset region below the memory function body. This causes the slope of the Id-Vg curve in the sub-threshold region to decrease in the writing state. On the other hand, when the memory element is in the erased state, high-density electrons are induced in the offset region. When 0 V is applied to the gate electrode (that is, when the gate electrode is off), no electrons are induced in the channel below the gate electrode (therefore, the off-state current is small). This causes a large slope of the Id-Vg curve in the sub-threshold region in the erased state, and a large current increase rate (conductance) even in the region above the threshold.
[0157]
As is clear from the above, the memory element constituting the semiconductor memory element of the present invention can have a particularly large drain current ratio at the time of writing and erasing.
[0158]
(Tenth embodiment)
This embodiment is a semiconductor memory device (memory cell array) configured by arranging the memory elements.
[0159]
20 is a schematic plan view of the memory cell array according to the tenth embodiment, FIG. 21 is a schematic sectional view taken along the line AA ′ of FIG. 20, and FIG. 22 is a sectional line BB of FIG. FIG. However, in FIG. 20, the upper wiring structure (bit lines and contacts) is shown as a connection diagram for simplicity. Although FIGS. 20 to 22 show a memory cell array of 3 rows × 3 columns, the number of rows and the number of columns are arbitrary. Note that the first direction of the present invention corresponds to the row direction, and the second direction corresponds to the column direction. Hereinafter, the same applies to the first and second directions.
[0160]
On the semiconductor substrate 1101, a P-type well region 1102 is formed. An element isolation region 1108 is formed on the surface of the P-type well region 1102. A region on the surface of the semiconductor substrate where the element isolation region 1108 is not formed is an active region. Active regions are arranged on the semiconductor substrate. The word lines WL1, WL2, WL3 (1104) extend in the horizontal direction on the paper and are formed side by side in the vertical direction on the paper. Word lines WL1, WL2, and WL3 pass over each active region via a gate insulating film 1103, and an active layer region is formed on both sides of each word line (an active region that is not covered by the word line). 1107 are formed. A word line (gate electrode) and two active layer regions (source region or drain region) formed on both sides of the word line constitute one field effect transistor. A silicon nitride film 1109 is formed on the side walls and the upper surface of the word lines WL1, WL2, WL3 (1104). Portions of the silicon nitride film 1109 located on the side walls on both sides of the word line are memory function bodies 1105a and 1105b. One of the two active layer regions formed on both sides of the word line is connected to one of the first bit lines BL11, BL12, and BL13, and the other is connected to one of the second bit lines BL21, BL22, and BL31. Have been. In the present embodiment, the first bit line is formed by the first-layer metal wiring 1132, and the second bit line is formed by the second-layer metal wiring 1134, but the wiring method is not limited to this.
[0161]
21 and 22, reference numeral 1131 denotes a contact hole (a hole connecting an active layer or a word line to a first-layer metal wiring) 1133 denotes a via hole (a hole connecting a first-layer metal wiring to a second-layer metal wiring). It is.
[0162]
FIG. 23 shows a circuit diagram of the memory cell array. For simplicity, the memory element is represented by a symbol representing a normal field effect transistor. In the memory element Mij (i = 1, 2, 3, j = 1, 2, 3), the gate electrode is connected to the word line WLi (i = 1, 2, 3), and one of the diffusion regions is set to the first bit line BL1j. (J = 1, 2, 3), and the other of the diffusion regions is connected to the second bit line BL2j (j = 1, 2, 3), respectively.
[0163]
The operation of the memory cell array may be performed by applying a voltage required for the above-described operation method of the memory element to a desired memory element via a specific word line, a first bit line, and a second bit line. For example, when writing to one of the memory functional units of the memory element M11, for example, + 5V is applied to the word line WL1, + 5V is applied to the first bit line BL11, and 0V is applied to the second bit line BL21. Good. Further, when writing to the other of the memory function bodies of the memory element M11, for example, + 5V is applied to the word line WL1, 0V is applied to the first bit line BL11, and + 5V is applied to the second bit line BL21. Good. At this time, for example, 0 V may be applied to other unselected word lines and unselected bit lines.
[0164]
As is clear from the above description, the memory cell array of the present embodiment is configured by arranging the above memory elements. As described above, the memory element can store two bits with one element and can reduce the thickness of the gate insulating film, so that miniaturization is easy. Therefore, the memory cell array according to the present embodiment in which the memory elements are arranged is also easily miniaturized, and the manufacturing cost is reduced.
[0165]
Further, as described above, the process of forming the memory element is very close to a normal CMOS process, and can be manufactured very easily as compared with a conventional nonvolatile memory having a floating gate such as an EEPROM. . Therefore, the memory cell array of the present invention can be easily manufactured, and can be easily mounted together with a logic circuit.
[0166]
As described in the second embodiment, in the memory element used in the present embodiment, the regions (silicon nitride films 242) of the memory function bodies 261 and 262 that hold the charges overlap with the diffusion regions 212 and 213, respectively. Is preferred. If such a memory element is used in the semiconductor memory device of the present embodiment, the reading speed of the semiconductor memory device can be made sufficiently high.
[0167]
Further, in the memory element used in the present embodiment, as described in the second embodiment, it is preferable that the memory function body includes a charge holding film disposed substantially in parallel with the surface of the gate insulating film. When such a memory element is used in the semiconductor memory device of the present embodiment, variation in the memory effect of the memory element can be reduced, so that variation in the read current of the semiconductor memory device can be suppressed. Furthermore, since the change in the characteristics of the memory element during storage can be reduced, the storage characteristics of the semiconductor memory device are improved.
[0168]
Further, in the memory element used in the present embodiment, as described in the third embodiment, the memory function body includes a charge holding film, and the charge holding film includes a portion extending substantially parallel to the surface of the gate insulating film. And a portion extending substantially in parallel with the side surface of the gate electrode. When such a memory element is used in the semiconductor memory device of the present embodiment, the rewriting speed of the memory element increases, so that the rewriting operation of the semiconductor memory device can be made faster.
[0169]
Further, it is preferable to use the memory element of the seventh embodiment as the memory element used in the present embodiment. That is, the thickness (T1) of the insulating film that separates the charge holding film (silicon nitride film 242) from the channel region or the well region is smaller than the thickness (T2) of the gate insulating film and is 0.8 nm or more. Is preferred. When such a memory element is used in the semiconductor memory device of the present embodiment, it is possible to lower the voltage of the write operation and the erase operation or to increase the speed of the write operation and the erase operation. Further, since the memory effect of the memory element increases, the reading speed of the semiconductor memory device can be increased.
[0170]
Further, as the memory element used in the present embodiment, it is preferable to use the memory element of the eighth embodiment. That is, the thickness (T1) of the insulating film that separates the charge holding film (silicon nitride film 242) from the channel region or the well region is preferably larger than the thickness (T2) of the gate insulating film and equal to or less than 20 nm. . When such a memory element is used in the semiconductor memory device of the present embodiment, the holding characteristics can be improved without deteriorating the short channel effect of the memory element. Retention performance can be obtained.
[0171]
The memory element used in the present embodiment preferably includes a memory function body having a structure in which a silicon nitride film is sandwiched between silicon oxide films, for example, as in the second embodiment (FIG. 8). If such a memory element is used in the semiconductor memory device of the present embodiment, the operation speed of the semiconductor memory device can be improved, and the reliability can be improved.
[0172]
It is most preferable that the memory element used in this embodiment use the best-described memory element. Thereby, the performance of the semiconductor memory device can be optimized.
[0173]
(Eleventh embodiment)
An eleventh embodiment of the present invention will be described with reference to FIGS. FIG. 24 is a schematic plan view of the semiconductor memory device (memory cell array) according to the eleventh embodiment, and FIG. 25 is a schematic cross-sectional view taken along the line CC ′ of FIG. However, in FIG. 24, the upper wiring structure (bit lines and contacts) is represented as a connection diagram for simplicity. Although FIGS. 24 and 25 show a memory cell array of 3 rows × 3 columns, the number of rows and the number of columns are arbitrary.
[0174]
The memory cell array of this embodiment differs from the memory cell array of the tenth embodiment in that adjacent memory elements (memory elements arranged in the vertical direction on the paper) share a diffusion region. As described above, by sharing the diffusion region, the area of the diffusion region itself is reduced, and the margin of the element isolation region for separating the diffusion region itself is not required, so that the area of the memory element is significantly reduced. can do.
[0175]
Even when the diffusion region is shared by adjacent memory elements, a voltage for a desired operation can be applied to a desired memory element by a method similar to the operation method described in the first embodiment. The circuit diagram of the memory cell array of the present embodiment is the same as FIG.
[0176]
According to the memory cell array of the present embodiment, the pitch between word lines is smaller than that of the memory cell array of the tenth embodiment, so that the cell area can be significantly reduced and the manufacturing cost can be further reduced.
[0177]
(Twelfth embodiment)
A twelfth embodiment of the present invention will be described with reference to FIGS. FIG. 26 is a schematic plan view of the memory cell array according to the twelfth embodiment, and FIG. 27 is a schematic sectional view taken along section line DD ′ of FIG. FIG. 28 is a circuit diagram of the memory cell array. FIG. 29 is a diagram showing the arrangement of the first-layer metal wiring of this memory cell array. However, in FIG. 26, the upper wiring structure (bit lines and contacts) is shown as a connection diagram for simplicity. Although FIGS. 7 to 10 show a memory cell array of 3 rows × 3 columns, the number of rows and the number of columns are arbitrary. In FIG. 29, an element isolation region 1108 is also drawn to clarify the positional relationship with the lower layer of the first-layer metal wiring.
[0178]
The memory cell array of the present embodiment differs from the memory cell array of the eleventh embodiment in that a pair of a first bit line and a second bit line is shared as one bit line. That is, assuming that the second bit line BL21 and the first bit line BL12 and the second bit line BL22 and the first bit line BL13 in FIG. 24 are shared to form one bit line BL2, BL3, respectively. 26 memory cell arrays are obtained.
[0179]
That is, when two adjacent bit lines 1134 and 1134 are selected, one active region 1107 is specified between the two bit lines 1134 and 1134. The diffusion region belonging to the specified active region 1107 is alternately connected to one of the bit lines 1134 and the other 1134. Since every other diffusion region belonging to the specified active region 1107 is a source region or a drain region, one of the selected two bit lines 1134 is connected to the source region belonging to the specified active region 1107. And the other of the selected two bit lines 1134 is connected to the other of the source / drain regions belonging to the specified active region 1107.
[0180]
Thus, by using the first bit line and the second bit line in common, the number of wirings (bit lines) can be reduced. Accordingly, the area of the memory element can be further greatly reduced and the manufacturing cost can be reduced.
[0181]
Next, the operation of the cell array will be described.
[0182]
First, a reading method will be described. Here, it is assumed that information stored in the memory storage unit (M1) on the bit line BL2 side of the memory element M22 is read. First, the bit lines BL1 and BL2 are precharged to a logic level L, and BL3 and BL4 are precharged to a logic level H. After the precharge is completed, the word line WL2 is set to the logic level H. At the moment when the word line WL2 becomes logic level H, the memory elements M22 and M23 are turned on. At this time, a high voltage (logic level H-logic level L) is applied between the source and the drain of the memory element M22 and a current flows, but the current amount changes depending on the state of the memory storage unit M1. Therefore, the state of the memory storage unit M1 can be known by detecting the amount of current flowing through the bit line BL2 or BL3 or monitoring the potential change of the bit line BL2 or BL3.
[0183]
In the above operation, when the bit line BL1 is not precharged to the logic level L, the memory element M21 is turned on at the moment when the word line WL2 goes to the logic level H, and the bit line BL1 is switched from the bit line BL1 to the bit line BL2. Electric current flows. Such a current hinders detection of a current flowing through the selected memory element M22. Therefore, it is preferable that bit line BL1 be precharged to the same logic level L as bit line BL2. Similarly, it is preferable that the bit line BL4 be precharged to the same logic level H as the bit line BL3.
[0184]
When the storage information of the memory storage unit (M2) on the bit line BL3 side of the memory element M22 is called, the bit lines, BL1 and BL2 are set to the logic level H, BL3 and BL4 are set to the logic level L, and the precharge is performed. Do. After the precharge is completed, the word line WL2 may be set to the logic level H.
[0185]
Table 1 shows an example of a specific voltage in each operation of writing, reading, and erasing of the memory cell array according to the present embodiment. Lbw, Hbw, Lww, and Hww are the low-level potential of the bit line, the high-level potential of the bit line, the low-level potential of the word line, and the high-level potential of the word line at the time of writing, respectively. Lbr, Hbr, Lwr, and Hwr are the low level potential of the bit line, the high level potential of the bit line, the low level potential of the word line, and the high level potential of the word line at the time of reading, respectively. Lbe1, Lbe2, Hbe, Lwe, and Hwe are the low level potential 1 of the bit line, the low level potential 2 of the bit line, the high level potential of the bit line, the low level potential of the word line, and the high level of the word line at the time of erasing, respectively. Potential. In each case, an example of a specific voltage is shown in parentheses.
[0186]
Note that the erasing method described in Table 1 uses the above-described second erasing method. Therefore, at the time of erasing, Lbe2 (+0.8 V in Table 1) is applied to the P-type well region. When erasing the memory function body M1 of the memory element M22, electrons injected by a forward voltage applied to the P-type well region and the bit line BL3 serve as a trigger to perform erasing. Lbe2 is applied to the bit line BL1 in order to prevent erroneous erasure of the memory element M21.
[0187]
[Table 1]

[0188]
As is clear from Table 1, the memory cell array according to the present embodiment is capable of random access (reading and rewriting operation for each bit). For this reason, the access efficiency can be improved as compared with a device that needs to be erased all at once. In addition, there is no need to perform a sequence such as temporary storage of the memory state, batch erasing, and writing, so that the control circuit is simplified.
[0189]
According to the above-described read operation, when two-bit storage of a certain memory element is to be continuously read (for example, the memory function bodies W1 and W2 of the memory element M22 are continuously read), a nearby bit line is read. Must be inverted (in the above example, the potentials of the bit lines BL1 to BL4 are all inverted), which is inefficient. Therefore, as described later, it is preferable to avoid a state in which data is continuously read alternately by devising an address decoder circuit and taking measures such as separating addresses for accessing the left and right memory functional units.
[0190]
(Thirteenth embodiment)
A thirteenth embodiment of the present invention will be described with reference to FIGS. FIG. 30 is a schematic plan view of the memory cell array according to the thirteenth embodiment, and FIG. 31 is a schematic cross-sectional view taken along the line EE ′ of FIG. FIG. 32 is a view for explaining the arrangement of the first-layer metal wiring of the memory cell array. However, in FIG. 30, the upper wiring structure (bit lines and contacts) is shown as a connection diagram for simplicity. Although FIGS. 30 to 32 show a memory cell array of 3 rows × 3 columns, the number of rows and the number of columns are arbitrary. In FIG. 32, an element isolation region 1108 is also drawn in order to clarify the positional relationship with the lower layer of the first-layer metal wiring.
[0191]
The memory cell array according to the present embodiment differs from the memory cell array according to the twelfth embodiment in connection patterns between diffusion regions and bit lines, which will be described below.
[0192]
Here, three adjacent bit lines (for example, BL1, BL2, and BL3) are selected, and are arranged as bit line 1 (BL1), bit line 2 (BL2), and bit line 3 (BL3) in the order of arrangement. Bit line 1 corresponds to a first bit line of the present invention, bit line 2 corresponds to a second bit line of the present invention, and bit line 3 corresponds to a third bit line of the present invention.
[0193]
At this time, the active region existing between the bit line 1 (BL1) and the bit line 2 (BL2) is defined as an active region 1 (A1). Similarly, an active region existing between bit line 2 (BL2) and bit line 3 (BL3) is referred to as an active region 2 (A2). At this time, the bit line 2 (BL2) is connected to one of the source / drain regions belonging to the active region 1 (A1) and the active region 2 (A2). The bit line 1 (BL1) is connected to the other of the source / drain regions belonging to the active region 1 (A1). The bit line 3 (BL3) is connected to the other of the source / drain regions belonging to the active region 2 (A2). That is, the active region 1 corresponds to a first active region of the present invention, and the active region 2 corresponds to a second active region of the present invention.
[0194]
Further, when two adjacent word lines (for example, WL1 and WL2) are selected, a diffusion region belonging to the active region 1 (A1) and sandwiched between the two word lines, The diffusion region that belongs to the active region 2 (A2) and is interposed between the two word lines is connected to the bit line 2 (BL2) or is connected to the bit line 1 (BL1) and the bit line 2 (BL1). 3 (BL3). In other words, if the diffusion region belonging to the active region 1 (A1) and sandwiched between the two selected word lines (WL1 and WL2) is one of the source / drain regions, The diffusion region belonging to the active region 2 (A2) and sandwiched between the selected two word lines also becomes one of the source / drain regions.
[0195]
According to the memory cell array of the present embodiment, as is clear from comparison between FIG. 32 and FIG. 29, it is possible to increase the margin between the first-layer metal wires 1132 even if the pitch in the horizontal direction of the paper is reduced. . This is because the connection pattern between the diffusion region and the bit line is set as described above, so that a part of the first-layer metal wiring 1132 is integrated and the number thereof is reduced. In the examples of FIGS. 29 and 32, there are 12 first-layer metal wires 1132 in FIG. 29, but the number is reduced to 8 in FIG. Accordingly, the area of the memory element can be further greatly reduced and the manufacturing cost can be reduced.
[0196]
The circuit diagram of the memory cell array of the present embodiment is the same as FIG. Therefore, the operation method may be the same as that of the memory cell array of the twelfth embodiment.
[0197]
(14th embodiment)
A semiconductor device can be configured using the memory cell array described above as follows. FIG. 33 shows a hardware block diagram of the semiconductor device of the present embodiment.
[0198]
The semiconductor device 13 of the present embodiment includes the memory cell array 1301 of the tenth to thirteenth embodiments, and includes a column address buffer 1302, a row address buffer 1303, and a column address decoder for specifying a memory element to be accessed. 1304, a row address decoder 1305, a sense amplifier 1306, and a control circuit 1307 for controlling these components.
[0199]
By using the memory cell arrays of the tenth to thirteenth embodiments and configuring various circuits as described above, a large-capacity and low-cost semiconductor device can be provided.
[0200]
By the way, when designing the semiconductor device as described above, considering the efficiency of the read operation of the memory cell array 1301, as described above, it is difficult to continuously read the 2-bit storage of a certain memory element. ineffective. Because, as described above, in order to continuously read 2-bit information of the memory element, the direction of the read current needs to be reversed (the source and the drain are switched), and the potential of the nearby bit line is changed. All must be inverted. Therefore, it is preferable that 2-bit addresses stored in a certain memory element are separated from each other. For example, one of the storage bits of memory elements belonging to the same word line and adjacent to each other may be set to a continuous address, and one and the other addresses of the storage bits in the same memory element may be separated.
[0201]
(Fifteenth embodiment)
In the present embodiment, an example of a portable electronic device using the memory cell array of the tenth to thirteenth embodiments will be described. FIG. 34 shows a block diagram of the portable electronic device of the present embodiment. The portable electronic device 14 includes a central processing unit 1401, a memory unit 1402, a power supply 1403, an input / output unit 1404, and an image output unit 1405. The memory unit 1402 includes the memory cell arrays according to the tenth to thirteenth embodiments.
[0202]
The functions of the memory unit 1402 include a function as a rewritable firmware storage device (for storing a basic sequence of hardware) and a function as a storage device for storing system settings, in addition to the function of the main memory. Can be provided. It is particularly preferable that the memory unit 1402 be used as a storage device of a portable device such as a mobile phone or an electronic organizer, or a game device.
[0203]
Since the memory section 1402 includes the memory cell arrays of the tenth to thirteenth embodiments, high integration is easy and the manufacturing cost of the portable electronic device can be reduced. Further, since it is easy to mount the central processing unit 1401 and the like and the memory unit 1402 on one chip, the manufacturing cost can be further reduced. Note that the memory section 1402 may be configured by a memory cell array of the semiconductor device of the fourteenth embodiment. In the portable electronic device according to the present invention, by mounting the semiconductor device according to the present invention, the number of components can be further reduced, and the manufacturing cost can be further reduced.
[0204]
【The invention's effect】
As is clear from the above, according to the semiconductor memory device of the present invention, an element isolation region and an active region where the element isolation region is not formed are formed on the surface of the semiconductor substrate. A plurality of matrixes are defined in a matrix defined by a first direction and a second direction intersecting the first direction, and each of the active regions has two source / drains serving as a source or a drain. A diffusion region is formed, a channel region is defined between the two source / drain diffusion regions, and a plurality of word lines extending in the second direction are provided on the semiconductor substrate. Is provided on the channel region of the active region arranged in the second direction via an insulator, and on the semiconductor substrate, a plurality of first bit lines extending in the first direction; The first one A plurality of second bit lines extending in the first direction, the first bit line is connected to one of the source / drain diffusion regions formed in the active region arranged in the first direction, and A second bit line connected to the other of the source / drain diffusion regions formed in the active region arranged in the first direction; the word line functioning as a gate electrode on the channel region; With respect to the electrodes, a memory function body having a function of retaining electric charge or a function of retaining polarization is formed on a side wall of one side and the other side of the source / drain diffusion region, respectively. The predetermined word line, the first bit line, and the second bit line are selected depending on the amount of charge or polarization held in the memory function body specified by selecting one bit line and the second bit line. The configuration is such that the amount of charge flowing through the channel region specified by selecting a bit line is changed. Therefore, by selecting a predetermined word line, a first bit line, and a second bit line, It becomes possible to rewrite or read the storage information of a specific memory function body. In addition, since the memory functional body provided on the side wall of the gate electrode is formed separately from the insulator separating the channel region and the word line, the insulator can be easily thinned to reduce the short channel effect. As a result, the element can be miniaturized and the manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a memory device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a modification of the memory element of the first embodiment.
FIG. 3 is a diagram illustrating a write operation of the memory element according to the first embodiment.
FIG. 4 is a diagram illustrating a write operation of the memory element according to the first embodiment.
FIG. 5 is a diagram illustrating an erasing operation of the memory element according to the first embodiment.
FIG. 6 is a diagram illustrating an erasing operation of the memory element according to the first embodiment.
FIG. 7 is a diagram illustrating a read operation of the memory element according to the first embodiment.
FIG. 8 is a schematic sectional view of a memory device according to a second embodiment.
FIG. 9 is a sectional view of a part of the memory element of FIG. 8;
FIG. 10 is a partial cross-sectional view showing a modification of the memory element of the second embodiment.
FIG. 11 is a diagram illustrating electrical characteristics of a memory element according to a second embodiment.
FIG. 12 is a partial cross-sectional view showing a modified example of the memory element of the second embodiment.
FIG. 13 is a partial cross-sectional view of a memory device according to a third embodiment.
FIG. 14 is a partial cross-sectional view of a memory device according to a fourth embodiment.
FIG. 15 is a partial cross-sectional view of a memory device according to a fifth embodiment.
FIG. 16 is a partial cross-sectional view of a memory device according to a sixth embodiment.
FIG. 17 is a partial cross-sectional view of a memory element according to a seventh embodiment.
FIG. 18 is a partial cross-sectional view of a memory device according to an eighth embodiment.
FIG. 19 is a view showing electric characteristics of a memory element according to a ninth embodiment.
FIG. 20 is a plan view showing a semiconductor memory device according to a tenth embodiment.
FIG. 21 is a cross-sectional view taken along the line AA ′ of FIG. 20;
FIG. 22 is a sectional view taken along line BB ′ of FIG. 20;
FIG. 23 is a circuit diagram of a semiconductor memory device according to a tenth embodiment.
FIG. 24 is a plan view of a semiconductor memory device according to an eleventh embodiment.
FIG. 25 is a cross-sectional view taken along the line CC ′ of FIG. 24.
FIG. 26 is a plan view of a semiconductor memory device according to a twelfth embodiment.
FIG. 27 is a cross-sectional view taken along the line DD ′ of FIG. 26.
FIG. 28 is a circuit diagram of a semiconductor memory device according to a twelfth embodiment.
FIG. 29 is a diagram illustrating the layout of the first-layer metal wiring of the semiconductor memory device according to the twelfth embodiment.
FIG. 30 is a plan view of a semiconductor memory device according to a thirteenth embodiment.
FIG. 31 is a cross-sectional view taken along the line EE ′ of FIG. 30;
FIG. 32 is a diagram illustrating the layout of the first-layer metal wiring of the semiconductor memory device according to the thirteenth embodiment.
FIG. 33 is a block diagram illustrating a semiconductor device according to a fourteenth embodiment.
FIG. 34 is a block diagram illustrating a portable electronic device according to a fifteenth embodiment.
FIG. 35 is a schematic plan view of a conventional flash memory cell array.
FIG. 36 is a cross-sectional view taken along the line FF ′ of FIG. 35;
FIG. 37 is a diagram showing electrical characteristics of a conventional flash memory.
[Explanation of symbols]
1 Memory element
101 semiconductor substrate
102 P-type well region
103 Gate insulating film
104 Gate electrode
105a, 105b Memory function body
107a, 107b source / drain diffusion regions
109 silicon nitride film

Claims (15)

An element isolation region and an active region where the element isolation region is not formed are formed on a surface portion of the semiconductor substrate,
A plurality of the active regions are arranged in a matrix defined by a first direction and a second direction intersecting the first direction,
In each of the active regions, two source / drain diffusion regions serving as a source or a drain are formed, and a channel region is defined between the two source / drain diffusion regions.
A plurality of word lines extending in the second direction are provided on the semiconductor substrate, and the word lines are provided on a channel region of the active region arranged in the second direction via an insulator. Yes,
A plurality of first bit lines extending in the first direction and a plurality of second bit lines extending in the first direction are provided on the semiconductor substrate;
The first bit line is connected to one of the source / drain diffusion regions formed in the active region arranged in the first direction;
The second bit line is connected to the other of the source / drain diffusion regions formed in the active region arranged in the first direction;
The word line functions as a gate electrode on the channel region,
With respect to the gate electrode, memory function bodies having a function of retaining charge or a function of retaining polarization are formed on sidewalls on one side and the other side of the source / drain diffusion region, respectively.
The predetermined word line, the first bit line, and the second bit line are selected, and the predetermined word line, the first bit line, A semiconductor memory device configured to change the amount of charge flowing through the channel region specified by selecting a second bit line. An element isolation region and an active region where the element isolation region is not formed are formed on a surface portion of the semiconductor substrate,
The active region extends in a first direction and is arranged in a plurality in a second direction intersecting the first direction.
A plurality of source / drain diffusion regions serving as a source or a drain are formed in the active region, and channel regions are respectively defined between the adjacent source / drain diffusion regions in the same active region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate on channel regions of the plurality of active regions via an insulator,
A plurality of first bit lines extending in the first direction and a plurality of second bit lines extending in the first direction are provided on the semiconductor substrate;
The first bit line is connected to one of the source / drain diffusion regions formed on the same active region;
The second bit line is connected to the other of the source / drain diffusion regions formed on the same active region;
The word line functions as a gate electrode on the channel region,
With respect to the gate electrode, memory function bodies having a function of retaining charge or a function of retaining polarization are formed on sidewalls on one side and the other side of the source / drain diffusion region, respectively.
The predetermined word line, the first bit line, and the second bit line are selected, and the predetermined word line, the first bit line, A semiconductor memory device configured to change the amount of charge flowing through the channel region specified by selecting a second bit line. An element isolation region and an active region where the element isolation region is not formed are formed on a surface portion of the semiconductor substrate,
The active region extends in a first direction and is arranged in a plurality in a second direction intersecting the first direction.
A plurality of source / drain diffusion regions serving as a source or a drain are formed in the active region, and channel regions are respectively defined between the adjacent source / drain diffusion regions in the same active region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate on channel regions of the plurality of active regions via an insulator,
A plurality of bit lines extending in the first direction are provided on the semiconductor substrate;
In the active region connected to two adjacent bit lines, one of the two bit lines is connected to one of the source / drain diffusion regions formed on the active region, and the two bit lines are connected to one another. The other of the bit lines is connected to the other of the source / drain diffusion regions formed in the active region,
The word line functions as a gate electrode on the channel region,
With respect to the gate electrode, memory function bodies having a function of retaining charge or a function of retaining polarization are formed on sidewalls on one side and the other side of the source / drain diffusion region, respectively.
A memory element is constituted by the gate electrode, the memory function body formed on the side walls on both sides of the gate electrode, and the source / drain diffusion regions adjacent to the gate electrode;
The predetermined word line and the two bit lines adjacent to each other are selected, and the predetermined word line and the two adjacent bit lines are determined by the amount of charge or polarization held in the memory function body specified by the selection. A semiconductor memory device configured to change a charge amount flowing through the channel region specified by selecting a bit line. An element isolation region and an active region where the element isolation region is not formed are formed on a surface portion of the semiconductor substrate,
The active region extends in a first direction and is arranged in a plurality in a second direction intersecting the first direction.
A plurality of source / drain diffusion regions serving as a source or a drain are formed in the active region, and channel regions are respectively defined between the adjacent source / drain diffusion regions in the same active region,
A plurality of word lines extending in the second direction are provided on the semiconductor substrate on channel regions of the plurality of active regions via an insulator,
A plurality of bit lines extending in the first direction are provided on the semiconductor substrate;
With respect to a first bit line, a second bit line, and a third bit line, which are sequentially adjacent to each other, the first active region connected to the first bit line and the second bit line; 2 and the second active region connected to the third bit line,
The second bit line is connected to one of the source / drain diffusion regions formed in the first active region, and is connected to one of the source / drain diffusion regions formed in the second active region. Connected to
The first bit line is connected to the other of the source / drain diffusion regions formed in the first active region;
The third bit line is connected to the other of the source / drain diffusion regions formed in the second active region;
The word line functions as a gate electrode on the channel region,
With respect to the gate electrode, memory function bodies having a function of retaining charge or a function of retaining polarization are formed on sidewalls on one side and the other side of the source / drain diffusion region, respectively.
A memory element is constituted by the gate electrode, the memory function body formed on the side walls on both sides of the gate electrode, and the source / drain diffusion regions adjacent to the gate electrode;
The predetermined word line and the two bit lines adjacent to each other are selected, and the predetermined word line and the two adjacent bit lines are determined by the amount of charge or polarization held in the memory function body specified by the selection. A semiconductor memory device configured to change a charge amount flowing through the channel region specified by selecting a bit line. An operation method of the semiconductor memory device according to claim 3, wherein:
Regarding a selected memory element which is a memory element to which a memory function body to be operated belongs, before applying a potential for performing an operation to a word line connected to the selected memory element,
One of the two bit lines connected to the selected memory element is precharged to a first potential and the other is precharged to a second potential;
Precharging a bit line adjacent to the one bit line on the side opposite to the other bit line to the first potential;
A method of operating a semiconductor memory device, characterized in that a bit line adjacent to the other bit line on the side opposite to the one bit line is precharged to the second potential. The semiconductor memory device according to claim 1, wherein
A semiconductor memory device, wherein a rewrite operation and a read operation are performed using the memory function bodies formed on both side walls of the gate electrode as independent storage units. The semiconductor memory device according to claim 1, wherein
A semiconductor memory device, wherein at least a part of the memory function body is formed so as to overlap a part of the source / drain diffusion region. The semiconductor memory device according to claim 1, wherein:
The memory function body includes a charge holding film having a function of holding charge,
The semiconductor memory device, wherein the charge retention film has a portion substantially parallel to a surface of the gate insulating film. 9. The semiconductor memory device according to claim 8,
The semiconductor memory device, wherein the charge holding film has a portion substantially parallel to a side surface of the gate electrode. The semiconductor memory device according to claim 8, wherein
A portion of the charge retention film substantially parallel to the surface of the gate insulating film, and an insulating film separating the semiconductor substrate;
A semiconductor memory device wherein the thickness of the insulating film is smaller than the thickness of the gate insulating film and is 0.8 nm or more. The semiconductor memory device according to claim 8, wherein
A portion of the charge retention film substantially parallel to the surface of the gate insulating film, and an insulating film separating the semiconductor substrate;
A semiconductor memory device, wherein the thickness of the insulating film is larger than the thickness of the gate insulating film and is equal to or less than 20 nm. The semiconductor memory device according to claim 1, wherein:
The above-mentioned memory functional unit has a structure in which a silicon nitride film is sandwiched between silicon oxide films. 13. A semiconductor device, wherein at least one of a column decoder, a sense amplifier, and a row decoder is formed on the same semiconductor substrate as the semiconductor memory device according to claim 1. apparatus. A portable electronic device comprising the semiconductor storage device according to claim 1. A portable electronic device comprising the semiconductor device according to claim 13.

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