JP2004343624A - Image processor, image forming apparatus, image processing method, computer program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of an abnormality at the time of image transfer by adjusting transfer rate, namely, the degree of congestion on a parallel bus. <P>SOLUTION: This image processor is provided with a first MEM 21 which temporarily stores inputted image information and an IPP 5 which processes the image information to data by which image formation is possible, arbitrarily sets a line data reading period from the first MEM 21 in the case of reading the image information stored in the first MEM 21 and storing it in a second MEM 9, reads the image information from the first surface 21 with set period intervals and transmits it to the second MEM 9 via the parallel bus 4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention processes image data of a digital copying machine or an MFP (multifunction machine such as a copy machine, a fax machine, a printer, and a scanner) that reproduces a digital image signal as an image on transfer paper, or handles measurement data of a measuring instrument or the like. The present invention relates to an image processing apparatus, an image forming apparatus using the image processing apparatus, an image processing method for processing the data, a computer program for implementing the image processing method on a computer, and a recording medium on which the computer program is recorded.
[0002]
[Prior art]
The invention described in Patent Document 1 is known as a device for reproducing a digital image signal on a transfer sheet as an image, particularly a device for reading an image from a scanner and reproducing the image on a transfer sheet.
[0003]
FIG. 14 shows the configuration of a system block of the image processing apparatus disclosed in Patent Document 1, which relates to the configuration of an MFP (Multi Function Peripheral-digital multifunction peripheral). Hereinafter, the related art will be described with reference to FIG.
[0004]
The reading unit 1 that optically reads a document condenses reflected light of lamp irradiation on the document on a light receiving element by a mirror and a lens. A light receiving element (for example, a CCD) is mounted on an SBU (sensor board unit) 2, and an image signal converted into an electric signal in the CCD is converted into a digital signal and then output from the SBU 2. The image signal output from the SBU 2 is input to a CDIC (compression / decompression and data interface control unit) 3. The transmission of image data between the functional device and the data bus is entirely controlled by the CDIC 3.
[0005]
The CDIC 3 performs data transfer between the SBU 2, the parallel bus 4, and the IPP (image processing processor) 5, and a communication between the system controller 6 that controls overall control and the process controller 7 for image data. The image signal from the SBU 2 is transferred to the IPP 5 via the CDIC 3, where the signal deterioration due to the quantization into the optical system and the digital signal (referred to as signal deterioration of the scanner system) is corrected, and is output to the CDIC 3 again.
[0006]
The data transferred from the IPP 5 to the CDIC 3 is sent from the CDIC 3 to the IMAC (image memory access control) 8 via the parallel bus 4. Here, under the control of the system controller 6, access control of image data and MEM (memory module) 9, expansion of print data of an external PC (personal computer) 10, and compression / expansion of image data for effective memory utilization are performed.
[0007]
The data sent to the IMAC 8 is stored in the MEM 9 after data compression, and the stored data is read as needed. The read data is decompressed, returned to the original image data, and returned from the IMAC 8 to the CDIC 3 via the parallel bus 4. After the transfer from the CDIC 3 to the IPP 5, image quality processing and pulse control are performed by the VDC 11, and the image forming unit 12 forms a reproduced image on transfer paper. During such a flow of image data, the functions of the MFP are realized by the bus control by the parallel bus 4 and the CDIC 3.
[0008]
In the FAX transmission function, the read image data is subjected to image processing by the IPP 5 and transferred to the FCU (FAX control unit) 13 via the CDIC 3 and the parallel bus 4. The data is converted into a communication network by the FCU 13 and transmitted to the PN (public line) 14 as FAX data. In the FAX reception, the line data from the PN 14 is converted into image data by the FCU 13 and transferred to the IPP 5 via the parallel bus 4 and the CDIC 3. In this case, the VDC 11 performs dot rearrangement and pulse control without performing any special image quality processing, and the image forming unit 12 forms a reproduced image on transfer paper. Note that the system controller 6 implements a function given to itself by executing a program stored in the ROM 16 while using the RAM 15 as a work area. Instructions and inputs required for control are performed from an operation panel (Open Panel) 17. The process controller 7 realizes a function given to itself by executing a program stored in the ROM 19 while using the RAM 18 as a work area.
[0009]
In the MFP configured as described above, when a plurality of jobs, for example, a copy function, a facsimile transmission / reception function, and a printer output function operate in parallel, the assignment of the reading unit 1, the imaging unit 12, and the right to use the parallel bus to the job is performed. It is controlled by a system controller 6 and a process controller 7. The process controller 7 controls the flow of image data, and the system controller 6 controls the entire system and manages activation of each resource. The function of the MFP is selected and input from the operation panel 17, and processing contents such as a copy function and a facsimile function are set. The system controller 6 and the process controller 7 communicate with each other via the parallel bus 4, the CDIC 3, and the serial bus (CPU bus) 20. A data format conversion for a data interface between the parallel bus 4 and the serial bus 20 is performed in the CDIC 3.
[0010]
Also, an invention described in Patent Document 2 is known as related to control when an image memory is arranged on the engine ENU side separately from the memory on the controller CTR side and the image data on the front side and the back side of the double-sided document are simultaneously read.
[0011]
FIG. 15 is a block diagram illustrating an example of an MFP disclosed in Patent Document 2. An image memory (MEM21-following) is stored in the engine separately from a memory (MEM9-hereinafter referred to as a second MEM) on the controller side shown in FIG. , Referred to as a first MEM—indicated by MEM1 in the figure), and sends the original surface data read by the surface reading unit 1a from the SBU1 (2a) to the CDIC3, and further to the first MEM21 via the CDIC3. The data is sent from the SBU2 (2b) to the CDIC3, and is input to the first MEM 21 via the CDIC3. Thereafter, the data is read from the first MEM 21 in the order of the front document data and the back document data, and sent to the controller-side second MEM 9.
[0012]
In the example of FIG. 15, at the time of copying, the image signals read by the reading units 1a and 1b are transferred to the SBUs 1 and 2 (2a and 2b), CDIC3, the first MEM 21, CDIC3, IPP5, and CDIC3. The data is stored in the frame memory (the second MEM 9) via the parallel bus 4 and the IMAC 8. Thereafter, the image signal is sent from the frame memory (second MEM 9) to the CDIC 3 via the IMAC 8 and the parallel bus 4, and is sent to the IPP 5, the VDC 11, and the image forming unit 12 to obtain a transfer image.
[0013]
FIG. 16 is a block diagram showing the internal configuration of the CDIC 3 shown in FIG. The image data input control unit 202 receives the image data of the front and back surfaces of the original from the front image data input control unit 221 and the back image data input control unit 223 from the SBU 2, and the memory I / O control unit 222 performs a write operation to the first MEM 21. Control. Thereafter, the original or back document data read from the first MEM 21 by the memory input / output control unit 222 is sent to the IPP 5 by the image data output control unit 224. Thereafter, the image data subjected to the image processing by the IPP 5 is input by the image data input control unit 202, and is input from the parallel bus 4 via the scaling unit 215, the data compression unit 203, the data conversion unit 206, and the parallel data I / F 205. Will be sent to IMAC8. Other parts that are not particularly described are configured the same as in FIG. 3 described later. See the description of FIG. 3 below for details.
[0014]
[Patent Document 1]
JP 2000-316063 A
[0015]
[Patent Document 2]
JP-A-2002-109527
[0016]
[Problems to be solved by the invention]
FIG. 17 shows a state of zooming, which is one of the functions for realizing copying.
FIG. 17A shows a case where, for example, an A4 size original is read and an A4 size transfer is obtained, that is, a case of a 1: 1 (100%) copy. FIG. 17B shows a case where, for example, an A4-size original is read and an A3-size transfer is obtained, that is, an enlarged copy. To convert from A4 size to A3 size, about 141% enlargement is required. FIG. 17C shows a case where, for example, an A4 size document is read and an A5 size transfer is obtained, that is, a reduced copy. In order to convert from A4 size to A5 size, a reduction of about 71% is required.
[0017]
In the above case, the state of the line data transfer timing of the document image is shown in FIG. FIG. 18A shows a case of the same magnification, and a READ_START signal indicates a read start command from the first MEM 21. The write synchronization signal W_LDSYNC is a synchronization signal for inputting original data from the SBU 2 to the CDIC 3 and writing the original data from the CDIC 3 to the first MEM 21, and W_DATA represents line data of an image to be written. R_DATA indicates the line data read from the first MEM 21, and is transferred from the first MEM 21 to the CDIC3 and the IPP5. T_DATA indicates transfer data after data input from the IPP 5 is input to the CDIC 3 and scaled by a scaling block in the CDIC 3. Thereafter, after this data is compressed, it is sent to the IMAC 8 via the parallel bus 4.
[0018]
FIG. 18A shows an example in which a read command READ_START is issued when line data of the 51st line of the document is written in the first MEM 21. At this time, since image data for 50 lines has already been stored in the first MEM 21, reading is performed one after another as soon as the transfer of the previous line is completed. As a result, the reading speed becomes faster than the writing speed to the first MEM 21. This is good for increasing the transfer rate, but it also has some negative effects. For example, if the line data transfer to the IPP 5 becomes faster, this data processing must be performed at a high speed, and a high-performance image processing module is required as the IPP 5. Further, when image data transfer on the parallel bus 4 becomes frequent, for example, when it is necessary to transfer the transfer paper data from the IMAC 8 to the CDIC 3 in parallel while transmitting the scanner original data from the CDIC 3 to the IMAC 8, When the image transfer speed increases, the data transfer from the IMAC 8 to the CDIC 3 may be interrupted by the image transfer from the CDIC 3 to the IMAC 8 and may not be able to keep up. In this case, the image formed on the transfer paper becomes an abnormal image, which is a serious problem.
[0019]
Also, if the line data read cycle of the original image from the first MEM 21 is shorter than the line cycle stored in the first MEM 21 on the engine side, that is, if the read speed is faster, the memory read will overtake the memory write. , Resulting in abnormal operation.
[0020]
FIG. 18B shows an enlarged case. The meanings of the READ_START signal and the write synchronization signals W_LDSYNC, W_DATA, R_DATA, and T_DATA are the same as those in FIG. 18A. In FIG. 18B, when 50 lines of image data are stored in the first MEM 21, the reading of the first MEM 21 is started, and the first MEM 21 transfers the CDIC 3, the IPP 5, and the CDIC 3 to the first MEM 21. The enlargement / reduction processing is performed by the enlargement / reduction unit 215. Therefore, the line output speed T_DATA of the scaling unit 215 becomes larger than the transfer speed of the memory read R_DATA of the line data, and the read speed from the first MEM 21 is determined by the maximum transfer speed of T_DATA after the enlargement. Will be. In this case, reading from the first MEM 21 is executed one after another as soon as the transfer of T_DATA is completed.
As a result, the read speed from the first MEM 21 is not much different from the write speed to the first MEM 21 as compared with FIG. 18A, and therefore, the line data transfer to the IPP 5 is the same as the IPP 5 It doesn't mean you need speed. However, the transfer of image data on the parallel bus 4 becomes frequent, and the transfer from the CDIC 3 to the IMAC 8 on the parallel bus 4 becomes crowded, causing the same problem as described with reference to FIG.
[0021]
In FIG. 18C, when 50 lines of image data are stored in the first MEM 21, the reading of the first MEM 21 is started, and the first MEM 21 transfers the CDIC 3, the IPP 5, and the CDIC 3 to the first MEM 21. A scaling unit 215 performs a scaling process for reduction. Therefore, the line output speed T_DATA of the scaling unit 215 is smaller than the transfer speed of the memory read R_DATA of the line data, and the transfer on the parallel bus 4 is not crowded. However, reading from the first MEM 21 becomes faster, and thereafter, processing is performed by the IPP 5, so that a high-performance image processing device is required as the IPP 5. In this case, the read speed from the first MEM 21 is determined by the maximum transfer speed of R_DATA, which is the processing speed of IPP5.
[0022]
The present invention has been made in view of such a situation of the related art, and an object of the present invention is to adjust a transfer speed on a parallel bus, that is, a congestion degree, and to prevent occurrence of an abnormality during image transfer. In addition, an image processing apparatus capable of suppressing occurrence of an abnormal image, an image forming apparatus including the image processing apparatus, an occurrence of an abnormality during image transfer can be prevented, and an occurrence of an abnormal image can be suppressed. An object of the present invention is to provide an image processing method capable of performing the image processing method, a computer program for realizing the image processing method by a computer, and a recording medium on which the computer program is recorded.
[0023]
[Means for Solving the Problems]
In order to achieve the above object, the first means includes a first storage means for temporarily storing input image information, an image information read from the first storage means, and a second storage means. In the image processing apparatus provided with control means for storing, the control means arbitrarily sets (changes) a line data read cycle from the first storage means, and sets the first data read cycle at the set cycle interval. It is characterized in that the image information is read from a storage means and transmitted to the second storage means via a parallel bus.
[0024]
The second means is the first means, wherein the control means sets a line data read cycle from the first storage means to the same cycle as a line data write cycle to the first storage means. It is characterized by.
[0025]
A third means is the first means, wherein the control means sets a line data read cycle from the first storage means to a cycle different from a line data write cycle to the first storage means. Features.
[0026]
A fourth means is the first to third means, wherein the control means is configured to perform the first storage so that the number of lines of the image to be read is equal to or less than the number of lines of the image information written in the first storage means. The image information is read from the means.
[0027]
A fifth means is the image processing apparatus according to the first to fourth means, wherein the input image information is image information obtained by optically reading a document by a reading unit.
[0028]
A sixth means is that the image forming apparatus is constituted by the image processing apparatus according to the first to fifth means, and an image forming means for forming an image based on image information accumulated in the image processing apparatus. Features.
[0029]
A seventh means is the sixth means, wherein the first storage means is provided in an engine unit for processing image information and forming an image on a recording medium, and the second storage means is provided with an engine unit. It is characterized in that it is provided in a controller section that controls each section of the apparatus, including:
[0030]
Eighth means temporarily stores the input image information in a first storage means, reads out the image information stored in the first storage means, accumulates the image information in a second storage means, and stores the first image information in the first storage means. Alternatively, in an image processing method for performing a predetermined image processing while storing in the second storage means, a line data read cycle from the first storage means is set, and the first storage is performed at the set cycle interval. The image information is read from the means and transmitted to the second storage means, and the image information is stored in the second storage means.
[0031]
A ninth means is that, in the eighth means, the line data is read from the first storage means at the same cycle as the line data write cycle to the first storage means.
[0032]
According to a tenth aspect, in the eighth aspect, the line data is read from the first storage unit at a cycle different from a cycle of writing the line data to the first storage unit.
[0033]
An eleventh means is the image processing apparatus according to the eighth to tenth means, wherein the image information is read from the first storage means so that the number of lines of the image to be read is equal to or less than the number of lines of the image information written in the first storage means. It is characterized by reading.
[0034]
A twelfth means is characterized in that the data storage method according to the eighth to eleventh means is constructed by a computer program.
[0035]
A thirteenth means is characterized in that the computer program according to the twelfth means is read by a computer and is recorded on a recording medium in an executable manner.
[0036]
In the following description, the first storage means is in the first MEM 21, the second storage means is in the second MEM 9, the control means is in the CDIC 3 and the system controller 6, the parallel bus is in the parallel bus 4, the engine is The unit corresponds to ENU, and the controller corresponds to CTR.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts as those of the above-described conventional example are denoted by the same reference numerals, and duplicate description will be omitted as appropriate.
[0038]
FIG. 1 is a block diagram illustrating an overall configuration of an image processing apparatus according to an embodiment of the present invention. The conventional configuration shown in FIG. 15 is a configuration for simultaneous double-sided reading, but here, a single-sided reading system shown in FIG. 1 is shown. In FIG. 1, the controller CTR connected to the parallel bus 4 having units such as the IMAC 8, the second MEM 9, and the FCU 13, the reading unit 1, the SBU 2, the CDIC 3, the first MEM 21, the IPP 5, the VDC 11, and the imaging unit 12. And an engine-side unit ENU.
[0039]
FIG. 2 is a block diagram showing a schematic configuration of the image processing of the IPP 5 in FIG. The read image is transmitted from the input I / F 101 of the IPP 5 to the scanner image processing unit 102 via the SBU 2 and the CDIC 3. The scanner image processing unit 102 performs shading correction, scanner γ correction, MTF correction, and the like for the purpose of correcting the deterioration of the read image signal. After the correction processing of the read image data is completed, the image data is transferred to the CDIC 3 via the output I / F 103. For output to transfer paper, image data from the CDIC 3 is received from the input I / F 104, and the image quality processing unit 105 performs area gradation processing. The data after the image quality processing is output to the VDC 11 via the output I / F 106.
[0040]
The area gradation processing includes density conversion, dither processing, error diffusion processing, and the like, and the main processing is area approximation of gradation information. Once the image data subjected to the scanner image processing is stored in the memory, various reproduced images can be confirmed by changing the image quality processing. For example, by changing the density of the reproduced image or changing the number of lines of the dither matrix, the atmosphere of the reproduced image can be changed. At this time, it is not necessary to read the image again from the reading unit 1 every time the processing is changed, and if the stored image is read from the second MEM 9, different processing can be performed on the same data any number of times.
[0041]
In the case of a single scanner, scanner image processing and gradation processing are performed together and output to the CDIC 3. The processing content is changed programmably. Switching of processing, change of processing procedure, and the like are managed by the command control unit 107.
[0042]
FIG. 3 is a block diagram showing a schematic configuration of the CDIC 3 in FIG. The image data input / output control unit 201 receives image data from the SBU 2 and outputs the data to the IPP 5.
[0043]
The image data input control unit 202 receives the data after the scanner image correction by the IPP5. The input data is subjected to data compression in the data compression section 203 in order to increase the transfer efficiency on the parallel bus 4. Then, the data is sent to the parallel bus 4 via the parallel data I / F 205.
[0044]
Image data input from the parallel data bus 4 via the parallel data I / F 205 is compressed for bus transfer, and is expanded by the data expansion unit 206. The decompressed image data is transferred from the image data output control unit 207 to the IPP5.
[0045]
The CDIC 3 has a function of converting parallel data and serial data. The system controller 6 transfers data to the parallel bus 4, and the process controller 7 transfers data to the serial bus 20. The data conversion unit 204 performs data conversion for communication between the two controllers 6 and 7. Serial data I / Fs 208 and 209 are further provided for IPP5, and also interface with IPP5. The switching of the processing, the change of the processing procedure, and the like are managed by the command control unit 210.
[0046]
In this embodiment, the image data input control unit 201 receives the document image data from the SBU 2, and the memory write control unit 211 controls a write operation to the first MEM 21 on the engine side. Thereafter, the document data read from the first MEM 21 by the memory read control unit 212 is sent from the image data output control unit 213 to the IPP 5. Thereafter, the image data subjected to the image processing by the IPP 5 is input from the image data input control unit 202, and is passed through a scaling unit (magnification block) 215, a data compression unit 203, a data conversion unit 204, a parallel data I / F 205, and a parallel bus. 4 to the IMAC 8 from above.
[0047]
FIG. 4 is a block diagram showing a schematic configuration of the VDC 11. The VDC 11 performs additional processing on the input image data according to the characteristics of the image forming unit. First, the edge smoothing unit 301 performs a dot rearrangement process, and then the pulse control unit 302 performs pulse control of an image signal for dot formation, and image data is output to the image forming unit 12. The VDC 11 has a parallel data and serial data format conversion function separately from the image data conversion, and the VDC 11 alone can support communication between the system controller 6 and the process controller 7.
For this purpose, a parallel data I / F 303, a serial data I / F 304, and a data conversion unit 305 for performing data conversion between the two are provided.
[0048]
FIG. 5 is a block diagram showing a schematic configuration of the IMAC 8. In the IMAC 8, the parallel data I / F unit 401 manages an interface of image data with the parallel bus 4. Structurally, it controls storage / reading of image data to / from the second MEM 9 and expansion of code data mainly input from the external PC 10 into image data. Code data input from the outside is stored in the line buffer 402 in a local area. The code data stored in the line buffer 402 is expanded into image data in the video control unit 404 based on an expansion processing command from the system controller 6 input via the system controller I / F 403. The expanded image data or the image data input from the parallel bus 4 via the parallel data I / F 401 is stored in the second MEM 9. In this case, the data conversion unit 405 selects image data to be stored, the data compression unit 406 performs secondary compression of the data in order to increase the memory use efficiency, and the memory access control unit 407 uses the address of the second MEM 9. While the image data is stored in the second MEM 9. The read address of the image data stored in the second MEM 9 is controlled by the memory access control unit 407, and the read image data is expanded by the data expansion unit 408. When transferring the decompressed image data to the parallel bus 4, data transfer is performed via the parallel data I / F 401.
[0049]
FIG. 6 is a block diagram showing a schematic configuration of the FCU 13. An FCU (Fax Control Unit-FAX transmission / reception unit) 13 converts image data into a communication format and transmits it to the external line PN14, and converts external data into image data to convert the image data into an external I / F unit 501 and a parallel bus. The image data is output from the image forming unit 12 via the control unit 4. The FAX transmission / reception unit 13 includes a FAX image processing unit 502, an image memory 503, a memory control unit 504, a facsimile control unit 505, an image compression / decompression unit 506, a modem 507, and a network control device 508. Among these, regarding the FAX image processing, the binary smoothing processing on the received image is performed by the edge smoothing processing unit 301 of the VCU 11. As for the image memory 503, part of the output buffer function is transferred to the IMAC 8 and the second MEM 9.
[0050]
In the facsimile transmission / reception unit 13 configured as described above, when transmission of image information is started, the facsimile control unit 505 instructs the memory control unit 504 to transfer the image information stored in the image memory 503 from the image memory 503. Read sequentially. The read image information is restored to the original signal by the FAX image processing unit 502, is subjected to density conversion processing and scaling processing, and is added to the facsimile control unit 505. The image signal applied to the facsimile control unit 505 is code-compressed by the image compression / decompression unit 506, modulated by the modem 507, and transmitted to the destination via the network control device 508. Then, the image information whose transmission has been completed is deleted from the image memory 503.
[0051]
At the time of reception, the received image is temporarily stored in the image memory 503, and if the received image can be recorded and output at that time, it is recorded and output when the reception of one image is completed. When a call is made during the copying operation and reception starts, the usage rate of the image memory 503 is stored in the image memory 503 until the usage rate reaches a predetermined value, for example, 80%, and the usage rate of the image memory 503 is reduced to 80%. If it has reached, the writing operation being executed at that time is forcibly interrupted, and the received image is read from the image memory 503 and recorded and output. At this time, the received image read from the image memory 503 is deleted from the image memory 503, and the writing operation which has been interrupted when the usage rate of the image memory 503 decreases to a predetermined value, for example, 10%, is resumed. At the end of the process, the remaining received images are recorded and output. Further, after the write operation is interrupted, various parameters for the write operation at the time of the interruption are internally saved so that the write operation can be resumed, and the parameters are internally restored at the time of restart.
[0052]
FIG. 7 shows an image path from reading a document image to storing image data in the second MEM 9 on the controller CTR side. The document image data read by the reading unit 1 is temporarily stored in the first MEM 21 on the engine ENU side via the SBU 2 and the CDIC 3. Thereafter, the image data is read from the first MEM 21 on the engine side, and is stored in the second MEM 9 on the controller CTR side via the CDIC 3, IPP 5, CDIC 3, parallel bus 4, and IMAC 8.
[0053]
FIG. 8 shows a state of FAX transmission, and shows an image path from reading a FAX document to storing FAX transmission data in the FAX control unit (FCU) 13. The FAX document image sent to the FCU 13 is temporarily stored in a buffer in the FCU 13, read out, and transmitted to a destination via the external communication line PN. In the case of the facsimile transmission shown in FIG. 8, the speed of the communication line is not faster than the transmission speed of the parallel bus as compared with the transmission to the second MEM 9 on the controller side in FIG.
[0054]
FIG. 9A is a sequencer state diagram for adjusting the reading speed of the first MEM 21 on the engine side, and FIG. 9B is a counter block diagram for adjusting the reading speed. When the read speed of the first MEM 21 on the engine side is adjusted, when the read start signal READ_START of the first MEM 21 is input in FIG. 9A, the state transits from the state S0 to S1 and the counter load signal LD_RCNT. After one cycle is output, the state transits to the state S2.
[0055]
In state S2, a counter decrement signal DEC_RCNT is output, and when the counter value becomes '0', RCNT_0 indicating this is input. After the output, the process returns to the state S1. In the state S1, the counter load signal LD_RCNT is output for one cycle, and then the state transitions to the state S2. This is a repetitive operation, and the memory read synchronization signal R_LDSYNC is periodically output. One line is read from the first MEM 21 on the engine side every time the synchronization signal is generated.
[0056]
In FIG. 9B, the memory read interval register RPER 601 is loaded from the CPU that performs data control by the load signal LD_RPER and stored using the memory read interval as the number of clock cycles. The memory read counter RCNT 602 loads the value of the memory read interval register RPER with the load signal LD_RCNT, and decrements the counter with the decrement signal DEC_RCNT. When the value of the counter becomes '0', the comparator CMP 603 detects that fact and outputs an RCNT_0 signal.
[0057]
With the configuration shown in FIG. 9, it is possible to arbitrarily set (change) or adjust the read cycle from the first MEM 21 on the engine side.
[0058]
FIGS. 10 to 12 show that the read cycle from the first MEM 21 on the engine side is arbitrarily changed and the number of read lines from the first MEM 21 does not exceed the number of write lines to the first MEM 21. 1 shows a circuit for performing the above.
[0059]
FIG. 10 is a diagram showing a circuit for counting the number of lines stored in the first MEM 21.
[0060]
In the sequencer state diagram of FIG. 10A, when the write start signal WRITE_START to the first MEM 21 is input, the state transits from the state S0 to S1, and the reset signal RES_WCNT of the memory write counter WCNT611 is output in the state S1. . When the scanning of the document is started, the line synchronization signal W_LDSYNC is input from SBU2, and the state transits from state S1 to S2. After the increment signal INC_WCNT of the memory write counter WCNT611 is output for one cycle, the state transits to state S3. In state S3, input of the line synchronization signal W_LDSYNC is again waited. When this signal is input, the state transits from state S3 to S2, and after outputting the increment signal INC_WCNT of the memory write counter WCNT611 for one cycle, transits to state S3. Thereafter, the increment signal INC_WCNT of the memory write counter WCNT 611 is output every time the line data of the document is input.
[0061]
FIG. 10B shows a memory write counter WCNT 611 that resets the counter value to an initial value of “0” by a reset signal RES_WCNT, and thereafter, increments the memory write counter WCNT 611 every time an increment signal INC_WCNT is input. I do. Thus, the number of write lines to the first MEM 21 on the engine side is counted.
[0062]
FIG. 11 is a diagram showing a circuit for counting the number of lines read from the first MEM 21.
[0063]
In the sequencer state diagram of FIG. 11A, when a read start signal READ_START from the first MEM 21 is input, a transition is made from state S0 to S1, and a reset signal RES_RCNT of the memory read counter RCNT621 is output in state S1. When the memory read synchronization signal R_LDSYNC is input, the state transits from state S1 to S2, and after outputting the increment signal INC_RCNT of the memory read counter RCNT621 for one cycle, transits to state S3. In state S3, input of the line read synchronizing signal R_LDSYNC is again waited. When this signal is input, the state transits from state S3 to S2, outputs the increment signal INC_RCNT of the memory read counter RCNT621 for one cycle, and then transits to state S3. . Thereafter, every time the line data of the document is read from the memory, the increment signal INC_RCNT of the memory read counter RCNT621 is output.
[0064]
FIG. 11B illustrates a memory read counter RCNT 621 that resets the counter value to an initial value “0” by a reset signal RES_RCNT, and thereafter, increments the read counter RCNT 621 every time an increment signal INC_RCNT is input. Thus, the number of read lines from the first MEM 21 on the engine side is counted.
[0065]
FIG. 12 (a) shows a control for adjusting the read speed of the first MEM 21 on the engine side and controlling the number of read lines from the first MEM 21 not to exceed the number of write lines to the first MEM 21. In the sequencer state diagram, main operations are the same as those in FIG. The difference from FIG. 9A is that the transition condition from the state S2 to S3 is not only RCNT_0 in which the read cycle counter RCNT602 becomes “0”, but also that the value of the memory write line counter WCNT611 is the value of the memory read counter RCNT602. That is, the condition (WCNT ≧ RCNT) is added. The function of the memory read cycle counter in FIG. 12B is exactly the same as that described in FIG. 9B.
[0066]
By configuring and operating in this manner, the read speed of the first MEM 21 on the engine side can be arbitrarily adjusted, and the number of read lines from the first MEM 21 does not exceed the number of write lines to the first MEM 21. Control can be performed as follows.
[0067]
FIG. 13 is a timing chart showing the transfer timing of each data when the line data read timing of the original image from the first MEM 21 on the engine side is adjusted.
[0068]
FIG. 13A shows the case of the same magnification, and the READ_START signal indicates a read start command from the first MEM 21. A write synchronization signal W_LDSYNC is a synchronization signal for inputting original data from the SBU 2 to the CDIC 3 and writing line data from the CDIC 3 to the first MEM 21, and W_DATA represents line data of an image to be written. Both W_LDSYNC and W_DATA are input from SBU2. R_LDSYNC is a line data read synchronization signal generated by the memory read cycle generation circuit shown in FIG. 9 or FIG. 12, and the line data of the document image is read from the first MEM 21 every time this synchronization signal is input. This read interval can be arbitrarily changed by changing the value set in the read cycle register RPER601 in FIG. 9 or FIG. The memory read data R_DATA indicates the line data read from the first MEM 21, and is transferred from the first MEM 21 to the CDIC3 and the IPP5. T_LDSYNC and T_DATA indicate a line transfer synchronization signal and transfer data after data input from the IPP 5 is input to the CDIC 3 and scaled by the scaling unit 215 in the CDIC 3. Thereafter, after the data is compressed, it is sent to the IMAC 8 via the parallel bus 4.
[0069]
FIG. 13A shows an example in which a read command READ_START is issued when the line data of the 51st line of the document is written in the first MEM 21. At this time, image data for 50 lines has already been stored in the first MEM 21, and the line data R_DATA is read each time the line data read synchronization signal R_LDSYNC is input. Since this is the case of the same magnification, the line transfer synchronizing signal T_LDSYNC output from the transformer is the same as the read synchronizing signal R_LDSYNC. As a result, the line cycle for transmitting the read data from the first MEM 21 to the IPP 5 does not become too fast, and can be adjusted. Therefore, there is no need to arrange an image processor IPP for processing line data at high speed. Further, since the data transfer speed on the parallel bus 4, in other words, the transfer cycle of the line data can be adjusted to an optimum value, for example, the scanner paper data is transmitted from the CDIC 3 to the IMAC 8 while the transfer paper data is When it is necessary to transfer the data in parallel, the data transfer from IMAC 8 to CDIC 3 is obstructed by the image transfer from CDIC 3 to IMAC 8 by adjusting the image transfer speed from CDIC 3 to IMAC 8 so as not to be too fast. To prevent data transfer from the IMAC 8 to the CDIC 3 from being made in time. This makes it possible to avoid an image formed on the transfer paper from becoming an abnormal image.
[0070]
In addition, by making the line cycle stored in the first MEM 21 on the engine side, that is, the line data read cycle of the original image from the first MEM 21, that is, the R_LDSYNC interval longer than the W_LDSYNC interval, the memory read can be performed in the memory. It is also possible to prevent the light from overtaking and causing an abnormal operation.
[0071]
Even if the line cycle stored in the first MEM 21 on the engine side, that is, the line data read cycle of the document image from the first MEM 21, that is, the R_LDSYNC interval is set smaller than the W_LDSYNC interval, FIG. ), The number of lines write count value WCNT written to the memory first MEM 21 and the number of lines read count value RCNT read from the first MEM 21) are compared and written. Since control is performed so as not to read more than the number of lines, it is possible to avoid such a problem that a memory read overtakes a memory write.
[0072]
FIG. 13B shows an enlarged case. The meanings of the READ_START signal and the write synchronization signals W_LDSYNC, W_DATA, R_DATA, and T_DATA are the same as those in FIG. 13A.
[0073]
In FIG. 13B, when 50 lines of image data are stored in the first MEM 21, the reading of the first MEM 21 is started, and the first MEM 21 transfers the data to the CDIC 3, the IPP 5, and the CDIC 3. The enlargement / reduction processing is performed by the enlargement / reduction unit 215. Here, the enlargement of the line interval of the pre-enlargement line data R_DATA by the scaling unit can be controlled so as not to reduce the interval of the line data T_DATA after the enlargement processing. Therefore, the image data transfer on the parallel bus 4 is not frequently performed. As a result, it is possible to prevent the transfer from the CDIC 3 to the IMAC 8 from being mixed on the parallel bus 4 and obtain the same effect as in the case of the control at the same magnification in FIG.
[0074]
In FIG. 13C, when 50 lines of image data are stored in the first MEM 21, the reading of the first MEM 21 is started, and the first MEM 21 transfers the data to the CDIC 3, the IPP 5, and the CDIC 3. A scaling unit 215 performs a scaling process for reduction. Therefore, by increasing the transfer speed of the memory read R_DATA of the line data to the maximum processing capability of the image processor IPP, it is possible to prevent the speed of the line data T_DATA after the scaling from being reduced.
[0075]
In this manner, the cycle of the line data read synchronization signal R_LDSYNC from the first MEM 21 can be arbitrarily changed, so that the line cycle for transmitting the read data from the first MEM 21 to the IPP 5 is not too fast. It can be adjusted. Therefore, there is no need to arrange an image processor IPP for processing line data at high speed. Also, since the data transfer speed on the parallel bus 4, in other words, the transfer cycle of the line data can be adjusted to an optimum value, for example, the transfer paper data is transferred from the IMAC 8 to the CDIC 3 while the scanner original data is transmitted from the CDIC 3 to the IMAC 8. If it is necessary to transfer the image data from the CDIC3 to the IMAC8, the data transfer speed is adjusted so as not to be too high, so that the data transfer from the IMAC8 to the CDIC3 is not hindered by the image transfer from the CDIC3 to the IMAC8. , IMAC 8 to CDIC 3 can be prevented from becoming too late. This makes it possible to avoid an image formed on the transfer paper from becoming an abnormal image.
[0076]
When image data cannot be sent from the first MEM 21 on the engine side to the FCU 13 on the parallel bus 4 at a very high speed as in the case of facsimile transmission in FIG. 8, the line data of the first MEM 21 is read. Can be dealt with by increasing the period and reducing the read speed.
[0077]
If an image processor capable of high-speed processing can be arranged, the line read interval from the first MEM 21 is set to be short to maximize the line data output speed to the image processor IPP5, If there is room, the system can be operated with the maximum processing capacity. Further, in the case of the reduction process, by setting the line read interval from the first MEM 21 to be short, it is possible to operate without reducing the line data transfer speed after the reduction.
[0078]
In addition, by making the line cycle stored in the first MEM 21 on the engine side, that is, the line data read cycle of the original image from the first MEM 21, that is, the R_LDSYNC interval longer than the W_LDSYNC interval, the memory read can be performed in the memory. It is possible to prevent the light from overtaking and causing an abnormal operation.
[0079]
Further, even if the line cycle stored in the first MEM 21 on the engine side, that is, the line data read cycle of the original image from the first MEM 21, that is, the R_LDSYNC interval is set to be smaller than the W_LDSYNC interval, the first MEM 21 is set to the first MEM 21. By comparing the number of written lines WCNT with the number of lines read from the memory RCNT and controlling not to read more than the number of written lines, a problem such as memory reading overtaking memory writing can be avoided. Can be avoided.
[0080]
In the present embodiment, the control is executed by the system controller 6, the process controller 7, and the CDIC 3. However, the control can be replaced with a computer program and executed by a computer. In this case, the computer program can be downloaded to a computer from a known recording medium such as an FD, a CD-ROM, or a PC memory card, or can be downloaded from a server to a computer via a network and used.
[0081]
As described above, according to the present embodiment,
{Circle around (1)} Since the cycle of the line data read synchronization signal R_LDSYNC from the first MEM 21 can be arbitrarily changed, the transfer rate of the read data from the memory can be increased to the maximum of the processing capability of the image processor IPP. It becomes.
[0082]
{Circle around (2)} Since the data transfer speed on the parallel bus 4, in other words, the transfer cycle of the line data, can be adjusted to an optimum value, for example, the scanner paper data is transmitted from the CDIC 3 to the IMAC 8 while the transfer paper data is transmitted from the IMAC 8 to the CDIC 3 in parallel. When it is necessary to transfer the data from the CDIC3 to the IMAC8, the data transfer speed from the CDIC3 to the IMAC8 is adjusted so as not to be too fast, so that the data transfer from the IMAC9 to the CDIC3 is prevented from being interrupted by the image transfer from the CDIC3 to the IMAC8. , IMAC 8 to CDIC 3 can be prevented from becoming too late.
[0083]
(3) Since it is possible to prevent data transfer from the IMAC 8 to the CDIC 3 from being performed in time, it is possible to prevent an abnormal image from being formed on transfer paper.
[0084]
{Circle around (4)} When an image processor capable of high-speed processing can be arranged, the line read interval from the first MEM 21 is set to be short so that the line data output speed to the image processor is maximized. If there is room, the system can be operated with the maximum processing capacity.
[0085]
{Circle around (5)} In the case of the reduction processing, by setting the line read interval from the first MEM 21 to be short, the operation can be performed without lowering the line data transfer speed after the reduction.
[0086]
{Circle around (6)} The line read stored in the first MEM 21, that is, the line data read period of the original image from the first MEM 21, that is, the R_LDSYNC interval is made equal to or larger than the W_LDSYNC interval, so that the memory read makes the memory write. It is possible to prevent an overtaking and an abnormal operation.
[0087]
{Circle around (7)} Referring to the line data write cycle to the first MEM 21, the cycle of the line data read synchronization signal R_LDSYNC from the first MEM 21 is arbitrarily changed to be the same as, faster, or later than the line data write cycle. Therefore, occurrence of an abnormal image or an abnormal operation can be prevented.
[0088]
(8) Even if the line cycle stored in the first MEM 21, that is, the line data read cycle of the original image from the memory first MEM, that is, the R_LDSYNC interval, is set smaller than the W_LDSYNC interval, the data is written to the first memory MEM 21. The number of written lines WCNT is compared with the number of lines RCNT read from the memory, and control is performed so as not to read more than the number of written lines. Therefore, it is possible to avoid a problem that a memory read overtakes a memory write. Can be.
[0089]
This has the effect.
[0090]
【The invention's effect】
As described above, according to the present invention, the line data read cycle from the first storage means is arbitrarily set, and the image information is read from the first storage means at the set cycle interval, and the second storage is performed. Since the data is transmitted to the means, the transfer speed on the parallel bus, that is, the degree of congestion can be adjusted to prevent occurrence of an abnormality during image transfer. Further, since the occurrence of an abnormality at the time of image transfer can be prevented, the occurrence of an abnormal image can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an overall configuration of an image processing apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of image processing of IPP in FIG. 1;
FIG. 3 is a block diagram showing an example of an internal configuration of the CDIC of FIG. 1;
FIG. 4 is a block diagram illustrating a schematic configuration of the VDC of FIG. 1;
FIG. 5 is a block diagram illustrating a schematic configuration of the IMAC of FIG. 1;
FIG. 6 is a block diagram illustrating a schematic configuration of an FCU 13 in FIG. 1;
FIG. 7 is a diagram showing an image path from reading a document image to storing image data in a second MEM on the controller side.
FIG. 8 is a diagram illustrating a state of FAX transmission, illustrating an image path from reading a FAX original to storing FAX transmission data in an FCU of a FAX control unit.
FIG. 9 is a diagram showing a sequencer state for adjusting the read speed of the first MEM on the engine side and a counter for adjusting the read speed.
FIG. 10 is a diagram showing a circuit for counting the number of lines stored in a first MEM.
FIG. 11 is a diagram showing a circuit for counting the number of lines read from a first MEM.
FIG. 12 is a diagram showing a sequencer state for adjusting the read speed of a first MEM on the engine side and a counter for adjusting the read speed.
FIG. 13 is a timing chart showing the transfer timing of each data when the line data read timing of the original image from the engine side memory MEM is adjusted.
FIG. 14 is a block diagram illustrating a system configuration of a conventionally implemented image processing apparatus.
FIG. 15 is a block diagram illustrating a system configuration of an image processing apparatus according to another conventional example.
16 is a block diagram showing an internal configuration of the CDIC shown in FIG.
FIG. 17 is a diagram illustrating a relationship between a copy image and a document.
FIG. 18 is a timing chart showing a state of line data transfer timing of a document image according to a conventional example.
[Explanation of symbols]
1 Reading unit
2 SBU
3 CDIC
4 Parallel bus
5 IPP
6 System controller
7 Process controller
8 IMAC
9 Second MEM
10 PC
11 VDC
12 Imaging unit
13 FCU
21 First MEM

Claims (13)

First storage means for temporarily storing input image information;
Control means for reading out the image information stored in the first storage means and storing the image information in the second storage means;
An image processing means for processing the image information into data capable of forming an image,
The control means arbitrarily sets a line data read cycle from the first storage means, reads the image information from the first storage means at the set cycle interval, and stores the read image information in the second storage means. An image processing apparatus for transmitting data via a parallel bus. 2. The image processing apparatus according to claim 1, wherein the control unit sets a line data read period from the first storage unit to a period same as a line data write period to the first storage unit. . 2. The image processing apparatus according to claim 1, wherein the control unit sets a line data read period from the first storage unit to a period different from a line data write period to the first storage unit. 2. The image processing apparatus according to claim 1, wherein the control unit reads the image information from the first storage unit such that the number of lines of the image to be read is equal to or less than the number of lines of the image information written in the first storage unit. 4. The image processing device according to any one of 3. The image processing apparatus according to claim 1, wherein the input image information is image information obtained by optically reading a document by a reading unit. An image processing apparatus comprising: the image processing apparatus according to claim 1; and an image forming unit configured to form an image based on image information stored in the image processing apparatus. Forming equipment. The first storage unit is provided in an engine unit that processes image information and forms an image on a recording medium,
7. The image forming apparatus according to claim 6, wherein the second storage unit is provided in a controller unit that controls each unit of the apparatus including an engine unit. The input image information is temporarily stored in a first storage unit, the image information stored in the first storage unit is read, and stored in a second storage unit, and the first or second storage unit is stored. In the image processing method of performing a predetermined image processing while storing in the
A line data read cycle from the first storage means is set, the image information is read from the first storage means at the set cycle interval and transmitted to the second storage means, and the second An image processing method comprising storing image information in a storage unit. 9. The image processing method according to claim 8, wherein the line data is read from the first storage unit at the same period as the line data writing period to the first storage unit. 9. The image processing method according to claim 8, wherein line data is read from the first storage unit at a period different from a line data writing period to the first storage unit. The image information is read from the first storage means so that the number of lines of the image to be read is equal to or less than the number of lines of the image information written in the first storage means. The image processing method according to the item. A computer program for causing a computer to execute the image processing method according to claim 8. A recording medium on which the computer program according to claim 12 is read by a computer and recorded in an executable manner.

Images