JP2004342197A - Memory cell circuit and data writing and data reading method to be used for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To complete the sensing of the necessary data only by using simple control circuits. <P>SOLUTION: The memory cell circuit includes a first memory cell 32 which is used for storing the nonvolatile first data and outputs a first current to be made correspondent to the first data, a second memory cell 34 which is used for storing the nonvolatile second data and is inputted with a second current to be made correspondent to the second data, a bias circuit 36 which is electrically connected to the first memory cell 32 and the second memory cell 34, is inputted with the first current from the first memory cell 32 and is used to output the second current to the second memory cell 34, and an amplifier circuit 38 which is electrically connected to a load contact of the bias circuit 36 and is used to output an output signal made correspondent to the first data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data write and data read method used in a memory cell circuit, and more particularly, a data write and data read method for sensing a load voltage by charging and discharging a load contact using a difference between two currents. About.
[0002]
[Prior art]
Among various electronic products currently on the market, the memory is a very important and indispensable device. The memory usually includes a memory cell array composed of a plurality of memory cells, and each memory cell is used to store one bit of digital data. Operations such as data writing, data deletion, and data reading are performed according to control signals (for example, control signals from word lines and bit lines). Usually, the memory also includes a sense amplifier, the function of the sense amplifier is to sense digital data stored in the memory cell when the memory reads data into the memory cell therein, and Amplification produces an output signal corresponding to the digital data.
[0003]
Referring to FIG. 1, FIG. 1 is an explanatory diagram illustrating a sense amplifier 10 according to the prior art. As shown in FIG. 1, the sense amplifier 10 is connected to NMOS transistors 12 and 14 used to provide the gain required for the sense amplifier 10 in the form of a current mirror, and serves as an active load for the sense amplifier 10. PMOS transistors 16 and 18 used and the gate electrode is bias voltage V_BAnd an NMOS transistor 20 that is electrically connected to and used to provide the bias current required for the sense amplifier. As described above, the sense amplifier 10 is a differential amplifier and has two input terminals V input from the gate electrodes of the NMOS transistors 12 and 14._in ⁺, V_in ⁻The result of the amplification is an output signal at the output terminal Vout extracted from the drain electrode of the NMOS transistor 14.
[0004]
When the sense amplifier 10 is applied in the memory, the input terminal V_in ⁺Is electrically connected to the memory cell and the input terminal V_in ⁻Is electrically connected to the reference voltage. The operating principle of the sense amplifier 10 is described below. When the memory reads data from the memory cell, the memory cell uses a variety of control signals to control the memory cell, so that the memory cell generates a current corresponding to the stored data, and a special circuit. Through the design, the current is converted into a voltage, and further the input terminal V of the sense amplifier 10_in ⁺The sense amplifier 10 input to the input terminal V_in ⁺, V_in ⁻By performing differential amplification on the voltage input from the reference voltage and the reference voltage, an output signal corresponding to data stored in the memory cell is generated at the output terminal Vout.
In practice, the memory includes more complicated operations when reading data using the sense amplifier 10, and is usually divided into three steps, such as precharging, data sensing and data latching. Pre-charging is performed at the input terminal V of the sense amplifier 10._in ⁺, V_in ⁻In order to avoid that the voltage values above are shifted from each other by the previous read operation and there is a difference, and this difference becomes an error factor for the next data read, the sense amplifier 10 is used each time, and the memory Before amplifying the data stored in the cell, the memory makes use of the precharge function and the input V_in ⁺, V_in ⁻Are charged to the same level (that is, the input terminal V_in ⁺Is charged to the reference voltage). Data sensing is an operation of sensing and amplifying data stored in the memory cell using the sense amplifier 10 and outputting a corresponding output signal. Data latching uses a latch to store this output result after the sense amplifier 10 outputs an output signal corresponding to the data stored in the memory cell, and to avoid losing it by a subsequent operation, The output signal is latched and provided for later circuit use.
[0005]
The circuit operations such as precharging, data sensing, and data latching described above require very accurate time control, thereby controlling the order of front and back and ensuring the accuracy of the output result. In order to achieve this goal, a control circuit is usually required in the memory that generates a control signal in the order of front and back. Most of the control circuit is composed of a logic gate and a delay circuit. Since the delay circuit uses a large amount of capacitors, the delay circuit is one circuit that occupies a large area of the integrated circuit. Since a highly integrated memory includes a large number of memory cells, the memory cell array occupies a very large area in the highly integrated memory. Under this situation, the area occupied by the control circuit is relatively acceptable. Note that the number of memory cells is limited in a low integration memory, and the memory cell array of the low integration memory does not occupy a large area. However, in order for the control circuit to reach the purpose of time control described above, the complexity of the circuit and the occupied area are almost the same as the control circuit in the highly integrated memory. Therefore, the control circuit occupies a large area of the low integration memory.
[0006]
[Problems to be solved by the invention]
It is an object of the present invention to provide a data sensing operation that is required only with a simple control circuit.
[0007]
[Means for Solving the Problems]
Accordingly, as a result of intensive research in view of the drawbacks found in the prior art, the present inventor is used to store nonvolatile first data, and when the memory cell circuit is placed in a read mode, the first A first memory cell that outputs a first current corresponding to one data and a non-volatile second data are stored in the memory cell circuit when the memory cell circuit is placed in the read mode. A second memory cell for inputting a corresponding second current; and electrically connected to the first memory cell and the second memory cell, and when the memory cell circuit is placed in the read mode, the first memory A bias circuit used for inputting the first current from the cell and further outputting the second current to the second memory cell; and electrically connected to a load contact of the bias circuit; When the load voltage is sensed by charging and discharging the load contact with the difference between the current and the second current, the load voltage is amplified with the input, and the output signal corresponding to the first data is The present invention has been completed on the basis of this finding, focusing on the point that the problem can be solved by a structure including an amplifier circuit used for output.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 2, FIG. 2 is an explanatory diagram showing functional blocks of the first embodiment of the memory cell circuit using the data writing and data reading method according to the present invention. The memory cell circuit 30 according to the present invention includes nonvolatile first data D₁And when the memory cell circuit 30 is placed in the read mode, the first data D is stored.₁The first current I corresponding to₁Of the first memory cell 32 and the non-volatile second data D₂And the second data D when the memory cell circuit 30 is placed in the read mode.₂The second current I corresponding to₂Is electrically connected to the first memory cell 32 and the second memory cell 34, and when the memory cell circuit 30 is placed in the read mode, the first memory cell 32 generates a first current I.₁And the second current I₂Is output to the second memory cell 34, and the load contact N of the bias circuit 36_LOADElectrically connected to the first current I (not shown in FIG. 2)₁And second current I₂The difference of load contact N_LOADBy charging / discharging the equivalent capacity of the load voltage V_{L OAD}When sensing the load voltage V_LOADAnd the first data D₁And an amplifier circuit 38 for outputting an output signal Dout corresponding to the.
[0009]
The memory cell circuit 30 further includes a control circuit (not shown in FIG. 2), and the control circuit is electrically connected to the first memory cell 32, the second memory cell 34, and the bias circuit 36, and includes a plurality of control circuits. And providing different logic values to the plurality of control signals when the memory cell circuit 30 is placed in a write mode and a read mode. It should be noted that when the memory cell circuit 30 is placed in the write mode, the first data D₁And second data D₂Are the data written in the first memory cell 32 and the second memory cell 34, respectively, and the first data D₁And second data D₂Are digital data complementary to each other. That is, when the memory cell 32 is placed in the write state (PROGRAM state), the memory cell 34 is placed in the erase state (ERASE state), and when the memory cell 32 is placed in the erase state, the memory cell 34 is written. Put in state.
[0010]
2 and FIG. 3, FIG. 3 is a circuit diagram of the memory cell circuit 30 shown in FIG. In FIG. 3, the first memory cell 32 and the second memory cell 34 are respectively connected to the memory cell X₁And X₂It is. Memory cell X₁And X₂Is a flash memory cell having a stack gate structure, and includes a control gate electrode, a floating gate electrode, and two contacts. The bias circuit 36 includes a memory cell X₁And load contact N_LOADBetween the first current I₁First bias switch S used to control the input of the₁And memory cell X₂And load contact N_LOADElectrically connected to the second current I₂Second bias switch S used to control the output of₂Including. The amplifier circuit 38 is an inverter X_INVAnd load contact N_LOADIs electrically connected to the load voltage V_LOADOutput signal D by amplifying_OUTUsed to produce
[0011]
The memory cell circuit 30 in FIG. 3 also includes a data write input terminal Din, which is connected to the memory cell XX when the memory cell circuit 30 is placed in the write mode.₁Let's memorize the first data D₁Enter. The memory cell circuit 30 in FIG. 3 further includes an inverter INV and a first write switch S._P1And second write switch S_P2including. The data write input terminal Din is electrically connected to the input terminal of the inverter INV (that is, the output terminal of the inverter INV is the second data D₂Is output). First write switch S_P1Is a data write input terminal Din and a memory cell X₁And the first data D₁Used to control the input of. Second write switch S_P2Is the output terminal of the inverter INV and the memory cell X₂And the second data D₂Used to control the input of. The memory cell circuit 30 in FIG. 3 further includes a control circuit (not shown in FIG. 3). The control circuit uses the first write switch S_P1And second write switch S_P2A mode selection signal PGM for controlling opening and closing by being electrically connected to the memory cell X, and a memory cell X₁, X₂Word line signal ZWL electrically connected to the control gate electrode of the first bias switch S₁A first bias signal BIASU which is electrically connected to control the opening and closing thereof, and a second bias switch S₂And a second bias signal BIASD for controlling opening and closing of the second bias signal BIASD.
[0012]
The memory cell circuit 30 in FIG. 3 further includes a power supply device and a bias voltage circuit (not shown in FIG. 3). The power supply device provides a first voltage Vpp, a second voltage Vdd, and a ground voltage Vss. The first voltage Vpp is a pump voltage required when the nonvolatile memory writes data, and when the data is written in FIG. 3, the voltage source VCP and the voltage source VSP are the voltage Vpp. The second voltage Vdd and the ground voltage Vss are system voltages required when reading data, and the level of the first voltage Vpp is usually higher than the second voltage Vdd. In addition, the bias voltage circuit provides a first bias Vbu and a second bias Vbd, and the first bias Vbu is a first bias switch S.₁To control the first bias switch S₁When the memory cell X is turned on, the memory cell X₁Used to avoid the occurrence of read interference. The second bias Vbd is a second bias switch S.₂To control the second bias switch S₂When the memory cell X is turned on, the memory cell X₂Used to avoid the occurrence of read interference. Here, the read interference is a soft program phenomenon caused by the voltage difference Vds in the nonvolatile memory cell being too large in the read mode, that is, a small amount of write operation that occurs in the nonvolatile memory cell in the read mode. .
[0013]
In the memory cell circuit 30 of FIG._P1And second write switch S_P2Is an NMOS transistor and the memory cell X₁, X₂Is a P-type channel flash memory cell and the first bias switch S₁Is a PMOS transistor and the second bias switch S₂Is an NMOS transistor.
[0014]
As shown in FIGS. 2 and 4, FIG. 4 is another circuit diagram of the memory cell circuit 30 in FIG. The circuit layout in FIG. 4 is similar to the circuit layout in FIG. 3 and will not be described again here. However, the control circuit (not shown in FIG. 4) included in the memory cell circuit 30 in FIG.₁, X₂The word line signal WL is electrically connected to the control gate electrode of the inverter, and the amplifier circuit further includes two inverters X_INV1, X_INV2Connected in series. Or the first write switch S_P1And second write switch S_P2Is an NMOS transistor and the memory cell X₁, X₂Is an N-type channel flash memory cell and the first bias switch S₁Is a PMOS transistor and the second bias switch S₂Is an NMOS transistor.
[0015]
Referring to FIGS. 5 and 6, FIGS. 5 and 6 are flowcharts of a method for writing and reading data in the memory cell circuit 30 used in FIGS. 3 and 4. As shown in FIG. 5, the method of writing data is performed in step 40 in the first write switch S._P1And second write switch S_P2And turn on the first bias switch S₁And second bias switch S₂To turn the memory cell circuit 30 into the write mode, and the first data D₁Memory cell X₁To the second data D₂Memory cell X₂Write to. As shown in FIG. 6, the method of reading data is performed in step 42 in the first write switch S._P1And second write switch S_P2And the first bias switch S₁And second bias switch S₂To turn the memory cell circuit 30 into the read mode, and the memory cell X₁To first data D₁The first current I corresponding to₁Is output to the bias circuit 36, or the second data D is output from the bias circuit 36.₂The second current I corresponding to₂Memory cell X₂To the first current I₁And second current I₂Load contact N using the difference between_LOADBy charging / discharging to the load voltage V_LOADSensing.
[0016]
As shown in FIGS. 3, 5 and 6, the steps of performing the data writing and data reading method shown in FIGS. 5 and 6 by the memory cell circuit 30 in FIG. 3 are as follows. It is. As shown in FIG. 5, in the method of writing data, in step 40, the first voltage Vpp is input to the first bias signal BIASU, so that the first bias switch S₁Is turned off and the ground bias voltage Vss is input to the second bias signal BIASD, whereby the second bias switch S₂Turn off. Further, by inputting the ground voltage Vss to the word line signal ZWL, the memory cell X₁, X₂And the first voltage Vpp is input to the mode selection signal PGM, whereby the first write switch S_P1And second write switch S_P2ON, the first data D₁And second data D₂Memory cell X₁, X₂Input to one end of. Further, the first voltage Vpp is applied to the memory cell X₁, X₂To the other end (shown as VCP and VSP in FIG. 3), respectively.₁, X₂Data is stored in the floating gate electrode.
[0017]
As shown in FIG. 6, the method for reading data is performed by inputting the first bias Vbu to the first bias signal BIASU in step 42, as shown in FIG.₁Is turned on, and the second bias switch S is input by inputting the second bias Vbd to the second bias signal BIASD.₂Turn on. Further, by inputting the ground voltage Vss to the word line signal ZWL, the memory cell X₁, X₂The first write switch S is selected by inputting the ground voltage Vss to the mode selection signal PGM._P1And second write switch S_P2Turn off. The second voltage Vdd is applied to the memory cell X₁Is input to one end (shown by VCP in FIG. 3), and the ground voltage Vss is further set to X₂At one end (shown as VSP in FIG. 3),₁, X₂Each of the other ends of the first current I₁And second current I₂Produce.
[0018]
Referring to FIGS. 4, 5 and 6, the steps of performing the data writing and data reading method shown in FIGS. 5 and 6 by the memory cell circuit 30 in FIG. 4 are as follows. . As shown in FIG. 5, in the method of writing data, in step 40, the first voltage Vpp is input to the first bias signal BIASU, so that the first bias switch S₁Is turned off and the ground bias voltage Vss is input to the second bias signal BIASD, whereby the second bias switch S₂Turn off. Further, by inputting the first voltage Vpp to the word line signal WL, the memory cell X₁, X₂And the first voltage Vpp is input to the mode selection signal PGM, whereby the first write switch S_P1And second write switch S_P2ON, the first data D₁And second data D₂Memory cell X₁, X₂Input to one end of. Further, the first voltage Vpp is applied to the memory cell X₁, X₂To the other end (shown as VCP and VSP in FIG. 4), respectively.₁, X₂Data is stored in the floating gate electrode.
[0019]
As shown in FIG. 6, the method for reading data is performed by inputting the first bias Vbu to the first bias signal BIASU in step 42, as shown in FIG.₁Is turned on, and the second bias switch S is input by inputting the second bias Vbd to the second bias signal BIASD.₂Turn on. Further, by inputting the second voltage Vdd to the word line signal WL, the memory cell X₁, X₂The first write switch S is selected by inputting the ground voltage Vss to the mode selection signal PGM._P1And second write switch S_P2Turn off. The second voltage Vdd is applied to the memory cell X₁Is input to one end (shown by VCP in FIG. 4), and the ground voltage Vss is further supplied to the memory cell X₂At one end (shown as VSP in FIG. 4),₁, X₂Each of the other ends of the first current I₁And second current I₂Produce.
[0020]
Referring to FIG. 7, FIG. 7 is an explanatory diagram showing functional blocks of a second embodiment of the memory cell circuit using the data writing and data reading method according to the present invention. The memory cell circuit 50 according to the present invention includes nonvolatile first data D₁'Is used to store the first data D when the memory cell circuit 50 is placed in the read mode.₁The first current I corresponding to '₁When the first memory cell 52 that outputs' and the memory cell circuit 50 are placed in the read mode, the reference current I_REFIs electrically connected to the first memory cell 52 and the reference current unit 54, and when the memory cell circuit 50 is placed in the read mode, the first memory cell 52 to the first current cell Current I₁’And then the reference current I_REFTo the reference current unit 54, and a load contact N of the bias circuit 56_LOAD′ (Not shown in FIG. 7) and connected to the first current I₁'And reference current I_REFThe difference of load contact N_LOADCharge / discharge with respect to the equivalent capacity of the load voltage V_LOADWhen sensing ', load voltage V_LOAD'Is amplified with the input, and the first data D₁And an output circuit 58 for outputting an output signal Dout 'corresponding to'.
[0021]
Memory cell circuit 50 further includes a control circuit (not shown in FIG. 7). The control circuit is electrically connected to the first memory cell 52 and the bias circuit 56 and provides a plurality of control signals, and is different from the plurality of control signals when the memory cell circuit 50 is placed in a write mode and a read mode. Enter a logic value. It should be noted that when the memory cell circuit 50 is placed in the write mode, the first data D₁'Is data written in the first memory cell 52.
[0022]
Referring to FIGS. 7 and 8, FIG. 8 is a circuit diagram of the memory cell circuit 50 shown in FIG. In FIG. 8, the first memory cell 52 is a memory cell X.₁'. Memory cell X₁A flash memory cell having a stack gate includes a control gate electrode, a floating gate electrode, and two contacts. The bias circuit 56 is connected to the memory cell X₁'And load contact N_LOAD'Is electrically connected between the first current I₁The first bias switch S used to control the input of '₁'. The amplifying circuit 58 includes an inverter X_INV′ And load contact N_LOADTo the load voltage V_LOADOutput signal D by amplifying '_OUTUsed to generate '.
[0023]
The memory cell circuit 50 in FIG. 8 also includes a data write input terminal Din ′. The data write input terminal Din ′ is connected to the memory cell XX when the memory cell circuit 50 is placed in the write mode.₁First data D to be stored in₁Enter '. The memory cell circuit 50 in FIG. 8 further includes a first write switch S._P1including. First write switch S_P1Are the data write input terminal Din 'and the memory cell X₁'And the first data D₁Used to control the input of '. The memory cell circuit 50 in FIG. 8 further includes a control circuit (not shown in FIG. 8). The control circuit uses the first write switch S_P1A mode selection signal PGM that is electrically connected to 'and controls its opening and closing; and a memory cell X₁A word line signal ZWL 'electrically connected to the control gate electrode of the first bias switch S₁And a first bias signal BIAS that is electrically connected to 'and controls its opening and closing.
[0024]
The memory cell circuit 50 in FIG. 8 further includes a power supply device and a bias voltage circuit (not shown in FIG. 8). The power supply device provides a first voltage Vpp ′, a second voltage Vdd ′, and a ground voltage Vss. The first voltage Vpp 'is a pump voltage required when the nonvolatile memory writes data, and when the data is written in FIG. 8, the voltage source VCP and the voltage source VSP are the voltage Vpp. The second voltage Vdd 'and the ground voltage Vss are system voltages required when reading data. When the data is read in FIG. 8, the voltage source VCP is the voltage Vdd', and the voltage source VSP is the voltage Vss. The level of the first voltage Vpp 'is usually higher than the second voltage Vdd'. In addition, the bias voltage circuit provides a first bias Vb. The first bias Vb is a first bias switch S.₁Used to control the first bias switch S₁When 'is turned on, it is placed in an ideal bias state and the memory cell X₁Avoid 'reading interference. Here, the read interference is a soft program phenomenon caused by the voltage difference Vds in the nonvolatile memory cell being too large in the read mode, that is, a small amount of write operation that occurs in the nonvolatile memory cell in the read mode. .
[0025]
In the memory cell circuit 50 of FIG._P1'Is an NMOS transistor and the memory cell X₁′ Is a P-type channel flash memory cell, and the first bias switch S₁'Is a PMOS transistor. The reference current unit 54 is an NMOS transistor and further has a gate electrode whose reference voltage V is fixed._REF1To the reference current I_REFProduce.
[0026]
As shown in FIGS. 7 and 9, FIG. 9 is another circuit diagram of the memory cell circuit 50 in FIG. The circuit layout in FIG. 9 is similar to the circuit layout in FIG. 8 and will not be described again here. However, the control circuit (not shown in FIG. 9) included in the memory cell circuit 50 in FIG.₁A word line signal WL 'electrically connected to the control gate electrode of' is provided. Furthermore, the amplifier circuit consists of two inverters X_INV1', X_INV2'Is connected in series. Or the first write switch S_P1'Is an NMOS transistor and the memory cell X₁'Is an N-type channel flash memory cell, and the first bias switch S₁'Is an NMOS transistor. The reference current unit 54 is a PMOS transistor, and its gate electrode is a fixed reference voltage V._REF2To the reference current I_REFProduce. Other, first write switch S_P1By inserting an inverter INV 'between' and the data write input terminal Din ', the logic consistency of the preceding and succeeding data is ensured.
[0027]
As shown in FIGS. 10 and 11, FIGS. 10 and 11 are flowcharts of a method for writing and reading data in the memory cell circuit 50 used in FIGS. As shown in FIG. 10, the method for writing data includes the first write switch S in step 60._P1', And the first bias switch S₁'Is turned off, the memory cell circuit 50 is put into the write mode, and the first data D₁'Is a memory cell X₁Write to '. As shown in FIG. 11, the method of reading data is performed in step 62 by the first write switch S._P1′ Is turned off, and the first bias switch S₁To turn on the memory cell circuit 50 in the read mode, and the memory cell X₁'To the first data D₁The first current I corresponding to '₁'Is output to the bias circuit 56, or the reference current I is output from the bias circuit 56._{R EF}Is output to the reference current unit 54, and the first current I₁'And reference current I_REFLoad contact N_LOADBy charging / discharging to the load voltage V_LOADSensing '.
[0028]
8, 10, and 11, steps for performing the data writing and data reading methods shown in FIGS. 10 and 11 by the memory cell circuit 50 in FIG. 8 will be described below. As shown in FIG. 10, the data writing method is performed by inputting the first voltage Vpp ′ to the first bias signal BIAS in step 60, as shown in FIG. 10.₁Turn off '. Further, by inputting the ground voltage Vss to the word line signal ZWL ', the memory cell X₁′ And the first voltage Vpp ′ is input to the mode selection signal PGM ′, thereby the first write switch S_P1ON, the first data D₁'Is a memory cell X₁Input to one end of '. Further, the first voltage Vpp ′ is applied to the memory cell X₁To the other end (shown as VCP 'in FIG. 8), the memory cell X₁Data is stored in the floating gate electrode of '.
[0029]
As shown in FIG. 11, the method of reading data is performed by inputting the first bias Vb to the first bias signal BIAS in step 62, as shown in FIG.₁Turn on '. Further, by inputting the ground voltage Vss to the word line signal ZWL ', the memory cell X₁And selecting the first write switch S by inputting the ground voltage Vss to the mode selection signal PGM '._P1Turn off '. The second voltage Vdd 'is applied to the memory cell X₁'Is input to one end (shown as VCP' in FIG. 8), and the ground voltage Vss is further input to the source electrode of the reference current unit 54, whereby the memory cell X₁'And another drain electrode of the reference current unit 54 are connected to the first current I₁'And reference current I_REFProduce.
[0030]
Referring to FIGS. 9, 10, and 11, the steps of performing the data writing and data reading method shown in FIGS. 10 and 11 by the memory cell circuit 50 in FIG. 9 are as follows. . As shown in FIG. 10, the data writing method is performed by inputting the ground voltage Vss to the first bias signal BIAS in step 60, as shown in FIG.₁Turn off '. Further, by inputting the first voltage Vpp ′ to the word line signal WL ′, the memory cell X₁And the first voltage Vpp ′ is input to the mode selection signal PGM ′, thereby the first write switch S_P1’Is turned on, the first data D₁'Is a memory cell X₁Input to one end of. Further, the first voltage Vpp ′ is applied to the memory cell X₁To the other end (shown as VSP 'in FIG. 9),₁Data is stored in the floating gate electrode of '.
[0031]
As shown in FIG. 11, the method of reading data is performed by inputting the first bias Vb to the first bias signal BIAS in step 62, as shown in FIG.₁Turn on '. Further, by inputting the second voltage Vdd 'to the word line signal WL', the memory cell X₁And selecting the first write switch S by inputting the ground voltage Vss to the mode selection signal PGM '._P1Turn off '. The second voltage Vdd 'is inputted to the source electrode of the reference current unit 54 (shown by VCP' in FIG. 9), and the ground voltage Vss is further inputted to the memory cell X₁To one end (as indicated by VSP 'in FIG. 8), the memory cell X₁'And another drain electrode of the reference current unit 54 are connected to the first current I₁'And reference current I_REFProduce.
[0032]
The above is a preferred embodiment of the present invention and does not limit the scope of the present invention. Accordingly, any modifications or changes that can be made by those skilled in the art, which are made within the spirit of the present invention and have an equivalent effect on the present invention, belong to the scope of the claims of the present invention. Shall.
[0033]
【The invention's effect】
Compared with the method of sensing data with a sensing amplifier according to the prior art, the method of reading data according to the present invention charges and discharges the load contact with the current generated from the memory cell, and senses the load voltage at the load contact. As a result, the data stored in the memory cell is taken out. The present invention does not require that a method of sensing data with a sensing amplifier according to the prior art generally includes complicated circuit operations such as precharging, data sensing, data latching, etc. Therefore, the necessary operation can be completed with only a simple control circuit.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a sensing amplifier according to the prior art.
FIG. 2 is an explanatory diagram showing functional blocks of a first embodiment of a memory cell circuit according to the present invention.
3 is a circuit diagram of the memory cell circuit in FIG. 2. FIG.
4 is another circuit diagram of the memory cell circuit in FIG. 2. FIG.
5 is a flowchart of a data write method of the memory cell circuit used in FIGS. 3 and 4. FIG.
6 is a flowchart of a data write method of the memory cell circuit used in FIGS. 3 and 4. FIG.
FIG. 7 is an explanatory diagram showing functional blocks of a second embodiment of the memory cell circuit according to the present invention.
8 is a circuit diagram of the memory cell circuit in FIG. 7. FIG.
FIG. 9 is another circuit diagram of the memory cell circuit in FIG. 7;
10 is a flowchart of a data write method of the memory cell circuit used in FIGS. 8 and 9. FIG.
11 is a flowchart of a data write method of the memory cell circuit used in FIGS. 8 and 9. FIG.
[Explanation of symbols]
10 Sensing amplifier
12, 14, 20 NMOS transistor
16, 18 PMOS transistor
30, 50 memory cell circuit
32, 34, 52 memory cells
36, 56 Bias circuit
38, 58 Amplifier circuit
54 Reference current unit

Claims (52)

A memory cell circuit,
A first memory cell that is used to store non-volatile first data and outputs a first current corresponding to the first data when the memory cell circuit is placed in a read mode;
A second memory cell that is used to store non-volatile second data and that inputs a second current corresponding to the second data when the memory cell circuit is placed in the read mode;
When the memory cell circuit is placed in the read mode, the first current is input from the first memory cell, and the second current is electrically connected to the first memory cell and the second memory cell. A bias circuit used to output to the second memory cell;
The load voltage is electrically connected to a load contact of the bias circuit, and when the load voltage is sensed by charging / discharging the load contact with the difference between the first current and the second current, A memory cell circuit comprising: an amplification circuit used for amplifying an input and outputting an output signal corresponding to the first data. The bias circuit is electrically connected between the first memory cell and the load contact, and includes a first bias switch that controls input of the first current, and the second memory cell and the load contact. 2. The memory cell circuit according to claim 1, further comprising a second bias switch electrically connected between the first bias switch and the second bias switch for controlling the output of the second current. The first memory cell and the second memory cell are flash memory cells having a stack gate structure, and the flash memory cell includes a control gate electrode, a floating gate electrode, and two end points. 3. The memory cell circuit according to 2. The memory cell circuit further includes a data write input terminal, and the data write input terminal inputs the first data to be stored in the first memory cell when the memory cell circuit is placed in a write mode. 4. The memory cell circuit according to claim 3, wherein: The memory cell circuit further includes an inverter, a first write switch, and a second write switch, the data write input terminal is electrically connected to an input terminal of the inverter, and the first write switch is connected to the data The input of the first data is controlled by being electrically connected between the write input terminal and the first memory cell, and the second write switch is connected to the output terminal of the inverter and the second memory 5. The memory cell circuit according to claim 4, wherein the second data input is controlled by being electrically connected to a cell, and the first data and the second data are complementary. . The memory cell circuit further includes a power supply device and a bias voltage circuit, and the power supply device provides a first voltage, a second voltage, and a ground voltage, and the level of the first voltage is higher than the second voltage. The bias voltage circuit provides a first bias and a second bias, the first bias is used to control the first bias switch, and when the first bias switch is turned on, When the first bias switch is placed in the ideal bias state, avoiding read interference, the second bias is used to control the second bias switch, and the second bias switch is turned on, 6. The memory cell circuit according to claim 5, wherein the second bias switch is placed in an ideal bias state to avoid occurrence of read interference. The memory cell circuit further includes a control circuit, and the control circuit provides a mode selection signal, a word line signal, a first bias signal, and a second bias signal, and the mode selection signal includes the first write switch, Electrically connected to a second write switch to control opening and closing of the first write switch and the second write switch, and the word line signal is a control gate electrode of the first memory cell and the second memory cell And the first bias signal is electrically connected to the first bias switch to control opening and closing of the first bias switch, and the second bias signal is electrically connected to the second bias switch. The memory cell circuit according to claim 6, wherein the memory cell circuit is connected to the second bias switch to control opening and closing of the second bias switch. The first write switch and the second write switch are NMOS transistors, the first memory cell and the second memory cell are P-type channel flash memory cells, the first bias switch is a PMOS transistor, 8. The memory cell circuit according to claim 7, wherein the second bias switch is an NMOS transistor. When the memory cell circuit is placed in the write mode, the first bias signal turns off the first bias switch by inputting the first voltage to the first bias switch, and the second bias signal is By inputting the ground voltage to the second bias switch, the second bias switch is turned off, and when the word line signal inputs the ground voltage, the first memory cell and the second memory cell are connected. The mode selection signal turns on the first write switch and the second write switch by inputting the first voltage to the first write switch and the second write switch, and the first data and the second write switch are turned on. Second data is input to one end of each of the first memory cell and the second memory cell, and the first voltage is It is inputted to the other end of the first memory cell and the second memory cell, and data is stored in the floating gate electrodes of the first memory cell and the second memory cell, respectively. The memory cell circuit according to claim 8. When the memory cell circuit is placed in the read mode, the first bias signal turns on the first bias switch by inputting the first bias to the first bias switch, and the second bias signal is By inputting the second bias to the second bias switch, the second bias switch is turned on, and when the word line signal inputs the ground voltage, the first memory cell and the second memory cell And the mode selection signal inputs the ground voltage to the first write switch and the second write switch to turn off the first write switch and the second write switch, and the second voltage is Input to one end of the first memory cell, and the ground voltage is input to one end of the second memory cell; Serial first memory cell and the second memory cell circuit according to claim 8, wherein each of the other end of the memory cell, characterized in that to produce the second current and the first current. The first write switch and the second write switch are NMOS transistors, the first memory cell and the second memory cell are N-type channel flash memory cells, the first bias switch is a PMOS transistor, 8. The memory cell circuit according to claim 7, wherein the second bias switch is an NMOS transistor. When the memory cell circuit is placed in the write mode, the first bias signal turns off the first bias switch by inputting the first voltage to the first bias switch, and the second bias signal is By inputting the ground voltage to the second bias switch, the second bias switch is turned off, and when the word line signal inputs the first voltage, the first memory cell and the second memory cell And the mode selection signal turns on the first write switch and the second write switch by inputting the first voltage to the first write switch and the second write switch, and the first data and The second data is input to one end of the first memory cell and the second memory cell, respectively, and the first voltage is It is inputted to the other end of the first memory cell and the second memory cell, and data is stored in the floating gate electrodes of the first memory cell and the second memory cell, respectively. The memory cell circuit according to claim 11. When the memory cell circuit is placed in the read mode, the first bias signal turns on the first bias switch by inputting the first bias to the first bias switch, and the second bias signal is By inputting the second bias to the second bias switch, the second bias switch is turned on, and when the word line signal inputs the second voltage, the first memory cell and the second memory The cell is selected, and the mode selection signal inputs the ground voltage to the first write switch and the second write switch to turn off the first write switch and the second write switch, and the second voltage is Input to one end of the first memory cell, and the ground voltage is input to one end of the second memory cell; Serial first memory cell and the second memory cell circuit according to claim 11, wherein each of the other end of the memory cell, characterized in that to produce the second current and the first current. A memory cell circuit,
A first memory cell that is used to store non-volatile first data and outputs a first current corresponding to the first data when the memory cell circuit is placed in a read mode;
A reference current unit used to input a reference current when the memory cell circuit is placed in the read mode;
Electrically connected to the first memory cell and the reference current unit, and when the memory cell circuit is placed in the read mode, the first current is input from the first memory cell, and the reference current is A bias circuit used to output to the reference current unit;
The load is electrically connected to a load contact of the bias circuit, and when the load voltage is sensed by charging / discharging the load contact of the bias with the difference between the first current and the reference current, the load A memory cell circuit comprising: an amplifier circuit used for amplifying a voltage with an input and outputting an output signal corresponding to the first data. The bias circuit includes a first bias switch, and the first bias switch is electrically connected between the first memory cell and the load contact, and controls the input of the first current. The memory cell circuit according to claim 14. 16. The memory cell circuit according to claim 15, wherein the first memory cell is a flash memory cell having a stack gate structure, and the flash memory cell includes a control gate electrode, a floating gate electrode, and two end points. The memory cell circuit further includes a data write input terminal, and the data write input terminal inputs the first data to be stored in the first memory cell when the memory cell circuit is placed in a write mode. The memory cell circuit according to claim 16. The memory cell circuit further includes a first write switch, and the first write switch is electrically connected between the data write input terminal and the first memory cell to control the input of the first data. 18. The memory cell circuit according to claim 17, wherein: The memory cell circuit further includes a power supply device and a bias voltage circuit, and the power supply device provides a first voltage, a second voltage, and a ground voltage, and the level of the first voltage is higher than the second voltage. The bias voltage circuit provides a first bias, the first bias is used to control the first bias switch, and the first bias switch is turned on when the first bias switch is turned on. 19. The memory cell circuit according to claim 18, wherein occurrence of read interference is avoided by placing the in an ideal bias state. The memory cell circuit further includes a control circuit, and the control circuit provides a mode selection signal, a word line signal, and a first bias signal, and the mode selection signal is electrically connected to the first write switch. Controlling the opening and closing of the first write switch, the word line signal is electrically connected to the control gate electrode of the first memory cell, and the first bias signal is electrically connected to the first bias switch. 20. The memory cell circuit according to claim 19, wherein opening and closing of the first bias switch is controlled. The first write switch is an NMOS transistor, the first memory cell is a P-type channel flash memory cell, the first bias switch is a PMOS transistor, the reference current unit is an NMOS transistor, or 21. The memory cell circuit according to claim 20, wherein the reference current is generated by electrically connecting a gate electrode of a reference current unit to a fixed reference voltage. When the memory cell circuit is placed in the write mode, the first bias signal turns off the first bias switch by inputting the first voltage to the first bias switch, and the word line signal is The first memory cell is selected by inputting a ground voltage, and the mode selection signal turns on the first write switch by inputting the first voltage to the first write switch. Is input to one end of the first memory cell, the first voltage is input to the other end of the first memory cell, and data is stored in the floating gate electrode of the first memory cell. The memory cell circuit according to claim 21. When the memory cell circuit is placed in the read mode, the first bias signal turns on the first bias switch by inputting the first bias to the first bias switch, and the word line signal is The first memory cell is selected by inputting a ground voltage, and the mode selection signal turns off the first write switch by inputting the ground voltage to the first write switch, and the second voltage is 22. The memory cell circuit according to claim 21, wherein the memory cell circuit is input to one end of the first memory cell, and the other end of the first memory cell generates the first current. The first write switch is an NMOS transistor, the first memory cell is an N-type channel flash memory cell, the first bias switch is an NMOS transistor, the reference current unit is a PMOS transistor, or 21. The memory cell circuit according to claim 20, wherein the reference current is generated by electrically connecting a gate electrode of a reference current unit to a fixed reference voltage. When the memory cell circuit is placed in the write mode, the first bias signal inputs the ground voltage to the first bias switch to turn off the first bias switch, and the word line signal is The first memory cell is selected by inputting a voltage, and the mode selection signal turns on the first write switch by inputting the first voltage to the first write switch. Is input to one end of the first memory cell, the first voltage is input to the other end of the first memory cell, and data is stored in the floating gate electrode of the first memory cell. 25. The memory cell circuit according to claim 24. When the memory cell circuit is placed in the read mode, the first bias signal turns on the first bias switch by inputting the first bias to the first bias switch, and the word line signal is By inputting a second voltage, the first memory cell is selected, and when the mode selection signal inputs the ground voltage to the first write switch, the first write switch is turned off, and the ground voltage is 25. The input of the first memory cell, wherein the other end of the first memory cell generates the first current, wherein the first current is a negative value. Memory cell circuit. A data write and data read method used in a memory cell circuit,
The memory cell circuit includes:
A first memory cell used to store non-volatile first data;
A second memory cell used to store non-volatile second data;
A first write switch electrically connected to the first memory cell and used to control input of the first data;
A second write switch electrically connected to the second memory cell and used to control input of the second data;
A first bias switch; a second bias switch; and a load contact, wherein the first bias switch is electrically connected between the first memory cell and the load contact, and the second bias switch is the second memory. Electrically connected between the cell and the load contact;
The method
By turning on the first write switch and the second write switch and further turning off the first bias switch and the second bias switch, the memory cell circuit is placed in a write mode, and Writing one data to the first memory cell, and further writing the second data to the second memory cell;
The memory cell circuit is placed in a read mode by turning off the first write switch and the second write switch, and further turning on the first bias switch and the second bias switch, and Outputting a first current corresponding to the first data from one memory cell to the bias circuit, or outputting a second current corresponding to the second data from the bias circuit to the second memory cell; Data writing used in the memory cell circuit, further comprising charging and discharging the load contact according to a difference between the first current and the second current, and sensing a load voltage; Data reading method. The memory cell circuit further includes an amplifier circuit electrically connected to a load contact of the bias circuit, and the method further includes the load voltage by the amplifier circuit when the memory cell circuit is placed in the read mode. 28. The data writing and data reading method used in the memory cell circuit according to claim 27, further comprising: outputting an output signal corresponding to the first data. 29. The flash memory cell, wherein the first memory cell and the second memory cell have a stack gate structure, and the flash memory cell includes a control gate electrode, a floating gate electrode, and two end points. Data write and data read methods used in the described memory cell circuit. The memory cell circuit further includes a data write input, and the method stores the data in the first memory cell when the memory cell circuit is placed in the write mode by the data write input. 30. The data writing and data reading method used in the memory cell circuit according to claim 29, further comprising inputting one data. The memory cell circuit further includes an inverter, the data write input terminal is electrically connected to the input terminal of the inverter, and the first write switch is connected between the data write input terminal and the first memory cell. The second data switch is electrically connected between the output terminal of the inverter and the second memory cell, and is electrically connected between the second memory cell and the second data switch. 31. The data writing and data reading method used in the memory cell circuit according to claim 30, wherein an input is controlled and the first data and the second data are complementary. The memory cell circuit further includes a power supply device and a bias voltage circuit, and the power supply device provides a first voltage, a second voltage, and a ground voltage, and the level of the first voltage is higher than the second voltage. The bias voltage circuit provides a first bias and a second bias, the first bias is used to control the first bias switch, and when the first bias switch is turned on, By placing the first bias switch in an ideal bias state, the occurrence of read interference is avoided, the second bias is used to control the second bias switch, and the second bias switch is turned on. 32. The method of claim 31, wherein the second bias switch is placed in an ideal bias state to avoid occurrence of read interference. Data writing and data reading methods used to Riseru circuit. The memory cell circuit further includes a control circuit, and the method further provides a mode selection signal, a word line signal, a first bias signal, and a second bias signal by the control circuit, and the mode selection signal is the first selection signal. Electrically connected to one write switch and the second write switch to control opening and closing of the first write switch and the second write switch; and the word line signal is connected to the first memory cell and the second write switch. Electrically connected to a control gate electrode of the memory cell, the first bias signal is electrically connected to the first bias switch, and controls opening and closing of the first bias switch; A second bias signal is electrically connected to the second bias switch and controls opening and closing of the second bias switch; Data writing and data reading method used for the memory cell circuit according to claim 32, wherein that. The first write switch and the second write switch are NMOS transistors, the first memory cell and the second memory cell are P-type channel flash memory cells, the first bias switch is a PMOS transistor, 34. The data writing and data reading method used in the memory cell circuit according to claim 33, wherein the second bias switch is an NMOS transistor. When the memory cell circuit is placed in the write mode, the method further turns off the first bias switch by inputting the first voltage to the first bias signal, or sets the ground voltage to the ground voltage. Selecting the first memory cell and the second memory cell by turning off the second bias switch by inputting to the second bias signal and inputting the ground voltage to the word line signal, By inputting the first voltage to the mode selection signal, the first write switch and the second write switch are turned on, and the first data and the second data are respectively sent to the first memory cell and the second memory cell. Input to one end of the memory cell, and further input the first voltage to the other end of the first memory cell and the second memory cell, Serial data writing and data reading method used for the memory cell circuit of claim 34, characterized in that it comprises to carry out storing the data in the floating gate electrode of the first memory cell and the second memory cell. When the memory cell circuit is placed in the read mode, the method further turns on the first bias switch and inputs the second bias voltage by inputting the first bias to the first bias signal. By selecting the first memory cell and the second memory cell by turning on the second bias switch by inputting the second bias signal and by inputting the ground voltage to the word line signal, By inputting the ground voltage to the mode selection signal, the first write switch and the second write switch are turned off, or the second voltage is input to one end of the first memory cell, and further the ground By inputting a voltage to one end of the second memory cell, the other end of the first memory cell and the second memory cell Data writing and data reading method used for the memory cell circuit of claim 34, characterized in that it comprises a causing said first current and said second current is. The first write switch and the second write switch are NMOS transistors, the first memory cell and the second memory cell are N-type channel flash memory cells, the first bias switch is a PMOS transistor, 34. The data writing and data reading method used in the memory cell circuit according to claim 33, wherein the second bias switch is an NMOS transistor. When the memory cell circuit is placed in the write mode, the method further turns off the first bias switch and inputs the ground voltage to the second voltage by inputting the first voltage to the first bias signal. By selecting the first memory cell and the second memory cell by turning off the second bias switch by inputting the bias signal and by inputting the first voltage to the word line signal, By inputting a first voltage to the mode selection signal, the first write switch and the second write switch are turned on, and the first data and the second data are transferred to the first memory cell and the second memory, respectively. The first voltage is input to one end of the cell, or the first voltage is input to the other end of the first memory cell and the second memory cell. Data writing and data reading method used for the memory cell circuit according to claim 37, wherein the containing and carrying out the store data to the floating electrode and the the cell second memory cell. When the memory cell circuit is placed in the read mode, the method further turns on the first bias switch by inputting the first bias into the first bias signal, or turns on the second bias. By turning on the second bias switch by inputting to the second bias signal, and by inputting the second voltage to the word line signal, the first memory cell and the second memory cell are turned on. By selecting and inputting the ground voltage to the mode selection signal, the first write switch and the second write switch are turned off, the second voltage is input to one end of the first memory cell, and the ground By inputting a voltage to one end of the second memory cell, the other end of the first memory cell and the second memory cell are respectively Data writing and data reading method used to Claim 37 memory cell circuit, wherein the containing and the serial first current and produce the second current. A data write and data read method used in a memory cell circuit,
The memory cell circuit includes:
A first memory cell used to store non-volatile first data;
A reference current unit used to provide a reference current; and
A first write switch electrically connected to the first memory cell and used to control input of the first data;
A first bias switch and a load contact, wherein the first bias switch is electrically connected between the first memory cell and the load contact, and the load contact is electrically connected to a reference current unit;
The method
Turning on the first write switch, and further turning off the first bias switch, causing the memory cell circuit to be placed in a write mode and writing the first data to the first memory cell; ,
Turning the first write switch off and further turning on the first bias switch causes the memory cell circuit to be placed in a read mode and corresponds to the first data from the first memory cell. The first current is output to the bias circuit, or the reference current is output from the bias circuit to the reference current unit, and the load contact is charged by the difference between the first current and the reference current. A method of writing and reading data used in a memory cell circuit, comprising discharging and sensing a load voltage. The memory cell circuit further includes an amplifier circuit electrically connected to a load contact of the bias circuit, and the method further includes the load voltage by the amplifier circuit when the memory cell circuit is placed in the read mode. 41. The data writing and data reading method used in the memory cell circuit according to claim 40, further comprising: outputting an output signal corresponding to the first data. The memory cell circuit of claim 41, wherein the first memory cell is a flash memory cell having a stack gate structure, and the flash memory cell includes a control gate electrode, a floating gate electrode, and two end points. Data writing and data reading methods used. The memory cell circuit further includes a data write input, and the method further stores the data in the first memory cell when the memory cell circuit is placed in the write mode by the data write input. 43. The data writing and data reading method used in the memory cell circuit according to claim 42, further comprising inputting first data. The memory cell circuit further includes a first write switch, and the first write switch is electrically connected between the data write input terminal and the first memory cell to control input of first data. 45. A data writing and data reading method used for a memory cell circuit according to claim 43. The memory cell circuit further includes a power supply device and a bias voltage circuit, and the power supply device provides a first voltage, a second voltage, and a ground voltage, and the level of the first voltage is higher than the second voltage. The bias voltage circuit provides a first bias, the first bias is used to control the first bias switch, and the first bias switch is turned on when the first bias switch is turned on. 45. The data writing and data reading method for use in the memory cell circuit according to claim 44, wherein occurrence of read interference is avoided by placing the signal in an ideal bias state. The memory cell circuit further includes a control circuit, and the method further provides a mode selection signal, a word line signal, and a first bias signal by the control circuit, and the mode selection signal is electrically connected to the first write switch. Connected to the first write switch, the word line signal is electrically connected to the control gate electrode of the first memory cell, and the first bias signal is 46. The data write and data read method used in the memory cell circuit according to claim 45, further comprising: electrically connected to a first bias switch, and controlling opening and closing of the first bias switch. The first write switch is an NMOS transistor, the first memory cell is a P-type channel flash memory cell, the first bias switch is a PMOS transistor, and the reference current unit is an NMOS transistor, or 47. The memory cell circuit according to claim 46, wherein the reference current is generated by electrically connecting a gate electrode to a fixed reference voltage, wherein the reference current is a positive value. Data writing and data reading methods. When the memory cell circuit is placed in the write mode, the method further includes turning off the first bias switch by inputting the first voltage to the first bias signal, and setting the ground voltage. By inputting the word line signal, the first memory cell is selected, and by inputting the first voltage to the mode selection signal, the first write switch is turned on, and the first data is transferred to the first data line. Including inputting to one end of the memory cell, further inputting the first voltage to the other end of the first memory cell, and storing data in a floating gate electrode of the first memory cell. 48. A data write and data read method used for a memory cell circuit according to claim 47. When the memory cell circuit is placed in the read mode, the method further turns on the first bias switch by inputting the first bias to the first bias signal, and sets the ground voltage. The first memory cell is selected by inputting to the word line signal, and the first write switch is turned off by inputting the ground voltage to the mode selection signal, or the second voltage is applied to the first voltage. The data write used in the memory cell circuit according to claim 47, further comprising: generating the first current at the other end of the first memory cell by inputting to one end of the memory cell. Data reading method. The first write switch is an NMOS transistor, the first memory cell is an N-type channel flash memory cell, the first bias switch is an NMOS transistor, and the reference current unit is a PMOS transistor; or The data used in the memory cell circuit according to claim 46, wherein the reference current is generated by electrically connecting a gate electrode to a fixed reference voltage, and the reference current is a negative value. How to write and read data. When the memory cell circuit is placed in the write mode, the method further includes turning off the first bias switch by inputting the ground voltage to the first bias signal; and By inputting the word line signal, the first memory cell is selected, and by inputting the first voltage to the mode selection signal, the first write switch is turned on, and the first data is transferred to the first data line. Input to one end of the memory cell, or input the first voltage to the other end of the first memory cell, and storing data in the floating electrode of the first memory cell. 51. A data write and data read method used in a memory cell circuit according to claim 50. When the memory cell circuit is placed in the read mode, the method further turns on the first bias switch by inputting the first bias to the first bias signal, and the second voltage. Is input to the word line signal to select the first memory cell, and the ground voltage is input to the mode selection signal to turn off the first write switch, or the ground voltage is 51. The data write used in the memory cell circuit according to claim 50, further comprising generating the first current at the other end of the first memory cell by inputting to one end of the memory cell. Data reading method.

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