JP2004341725A - Control method for computer, computer, storage controller, program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently supply a program executed by each processor. <P>SOLUTION: This computer includes: two or more processors; first memories each provided correspondingly to each of the processors, storing the program executed by the processor; and a second memory capable of being accessed by each processor. The two or more processors respectively share division data that are data obtained by dividing the program stored in the first memory to transfer them to the second memory. The processor combines the division data stored in the second memory by the transfer to restore the program. The processor stores the restored program into the first memory. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a computer control method, a computer, a storage control device, a program, and a recording medium.
[0002]
[Prior art]
In a computer system that employs a so-called multiprocessor architecture configured for the purpose of achieving load distribution, high performance, and high reliability, a memory for storing a microprogram executed by the processor is provided for each processor. There is a configuration that takes the configuration described below. For example, in a disk array device whose demand is increasing due to the recent development of IT technology, a communication control unit (channel control unit) for controlling communication with an information processing device to be accessed and a large number of disk drives are required. There is a multiprocessor configuration in which a plurality of disk control devices for performing access are mounted.In such a disk array device, a memory for storing a microprogram is provided for each communication control unit, or It is provided for each disk control unit.
[0003]
In the computer system having the above configuration, for example, at the time of setup, version upgrade, or the like, a process of transferring a microprogram to a memory is performed. Here, since the transfer processing of the microprogram affects other processing of the computer system, it is preferable to perform the processing as efficiently as possible. Therefore, as a mechanism for increasing the efficiency of the transfer processing, for example, Japanese Patent Application Laid-Open Publication No. H11-157572 discloses a method in which a microprogram is transferred to a shared memory accessible by each processor, and each processor reads the microprogram by itself to execute parallel data transfer. A technique has been disclosed in which a load is distributed by performing transfer, and the time for loading a microprogram to a memory corresponding to a processor is reduced.
[0004]
[Patent Document 1]
JP-A-11-250028
[0005]
[Problems to be solved by the invention]
In the technology described in the above publication, a microprogram to be loaded into a memory corresponding to each processor is transferred to a shared memory in advance. However, since this transfer is performed through a specific processor, Concentration of load on the inevitable. Further, in a mechanism in which only a specific processor is involved in writing, the efficiency of the transfer process is determined by the processing capability of the specific processor, so it is difficult to improve the efficiency of the transfer process.
[0006]
The present invention has been made in view of such a background, and in a computer system having a multiprocessor architecture, a computer control method, a computer, and a storage control capable of efficiently supplying a microprogram executed by each processor. It is an object to provide an apparatus, a program, and a recording medium.
[0007]
[Means for Solving the Problems]
Including two or more processors, a first memory provided corresponding to each of the processors and storing a program to be executed by the processors, and a second memory accessible by each of the processors In the computer control method configured, wherein at least two or more of the processors share divided data, which is data obtained by dividing a program stored in the first memory, and transfer the divided data to the second memory. Restoring the program by combining the divided data stored in the second memory by the transfer, and causing the processor to store the restored program in the first memory And
[0008]
The present invention is applied to a computer adopting a multiprocessor architecture having two or more processors. The first memory is, for example, a local memory or a non-volatile memory that stores a microprogram executed by each processor corresponding to each processor of a computer having such an architecture. The second memory is, for example, a shared memory provided to be accessible from each processor in a computer having such an architecture.
The present invention is applied, for example, when a microprogram supplied from the outside is set up in the first memory by each of the processors.
[0009]
In addition, the problems disclosed by the present application and the solution thereof will be clarified by the description of the embodiments of the invention and the drawings.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a block configuration of a control device 100 described as an embodiment of the present invention. The control device 100 is controlled by at least one of the processors 1, 2, 3, and 4, the shared memory 5 accessible from each of the processors 1, 2, 3, and 4, and the processors 1, 2, 3, and 4. A service processor 8 communicably connected to the control target parts 6 and 7, the processors 1, 2, 3, 4, and a shared memory communicably connected between the processors 1, 2, 3, 4 and the shared memory 5 An access bus 9 and a service processor-processor communication bus 10 for communicably connecting the processors 1, 2, 3, 4 and the service processor 8 are included.
[0011]
The processors 1, 2, 3, and 4 respectively include a processor controller 11, 21, 31, 41, a non-volatile memory 12, 22, 32, 42 composed of a flash memory and the like, and a local memory 13 composed of an SRAM and a DRAM. , 23, 33, 43, microprogram storage areas 14, 24, 34, 44, microprogram load areas 15, 25, 35, 45, and the like. In the shared memory 5, a microprogram storage area 51 is secured.
[0012]
In the control device 100, a microprogram executed by the processors 1, 2, 3, and 4 is supplied from the service processor 8 to the processors 1, 2, 3, and 4 via the shared memory 5. The service processor 8 includes a processor control unit 81, a memory 82, and the like. The microprogram supplied to each of the processors 1, 2, 3, and 4 is supplied from an external device 70 such as a computer and stored in a microprogram storage area 83 secured in a storage area of a memory 82. The supply of the microprogram from the external device 70 to the service processor 8 is performed, for example, when the control device 100 is introduced or when the microprogram is upgraded.
[0013]
In the processors 1, 2, 3, and 4, the microprogram supplied from the service processor 8 is stored in the microprogram storage areas 14, 24, 34, and 44, and the microprogram load areas 15, 25, 35, and 45. In each of the processors 1, 2, 3, and 4, for example, when the processors 1, 2, 3, and 4 are activated, the microprograms are stored in the microprogram storage areas 14, 24, 34, and 44 to the microprogram load areas 15, 25, 35, and 45. Is loaded.
[0014]
In the control device 100, the microprogram supplied from the external device 70 and stored in the microprogram storage area 83 is first transferred to the microprogram storage area 51 of the shared memory 5, and thereafter, the respective processors 1, 2, 3, 4 accesses the shared memory 5 via the shared memory access bus 9 and is taken into each of the processors 1, 2, 3, and 4.
[0015]
The transfer of the microprogram from the microprogram storage area 83 to the microprogram storage area 51 of the shared memory 5 is performed by the service processor-processor communication bus 10, at least one of the processors 1, 2, 3, and 4, This is performed via the memory access bus 9. Here, the entire microprogram can be collectively transferred by a specific processor among the processors 1, 2, 3, and 4 (hereinafter, this transfer method is referred to as a collective transfer method). Further, the microprogram can divide the divided data into a plurality of data (hereinafter, referred to as divided data), share the divided data among the plurality of processors 1, 2, 3, and 4, and transfer the divided data to the shared memory 5. (Hereinafter, this transfer method is referred to as a division transfer method). For example, the external device 70 can instruct the service processor 8 whether the transfer method is the batch transfer method or the split transfer method.
[0016]
FIG. 2 shows a processing flow in the case of the batch transfer method. In the batch transfer method, a specific processor collectively transfers the microprogram stored in the microprogram storage area 83 of the service processor 8 to the shared memory 5.
At the time of the transfer, first, the microprogram is transferred from the service processor 8 to the specific processor in charge of the transfer processing of the microprogram via the service processor-processor communication bus 10 (S211), and the specific processor owns itself. Store the microprogram in local memory. Next, the microprogram stored in the specific processor is transferred to the microprogram storage area 51 of the shared memory 5 (S212).
[0017]
On the other hand, FIG. 3 shows a processing flow in the case of the division transfer method. In this method, first, the service processor 8 generates divided data by dividing the microprogram stored in the microprogram storage area 83 into a predetermined data size, and stores the generated divided data in a predetermined area of the memory 82. It is stored (S311). When storing the generated divided data in the memory 82, the processor control unit 81 attaches an identifier to each of the generated divided data and stores it in the memory 82 (S312). As the identifier to be attached to the divided data, an identifier that can specify the combining order, such as a numeral or an alphabet, is adopted so that the combining order when the divided data is combined later to restore the microprogram can be grasped. You. It should be noted that the divided data described in this embodiment is provided with a number (hereinafter, referred to as a divided data number) indicating the connection order at the time of restoring the microprogram as an identifier.
[0018]
Next, the processor control unit 81 assigns a processor in charge of the transfer process to each shared memory 5 to each of the divided data generated as described above (S313). Which processor is in charge of the transfer processing of each divided data, that is, the assignment of the processor that is in charge of each divided data is stored in the transfer data management table 400 shown in FIG. It is registered (S314). As shown in this figure, the correspondence between the identifier assigned to the divided data and the identifier assigned to the processor is registered in the transfer data management table 400. In the column "division data" 410, an identifier of the division data is set.
The “assigned processor” column 420 is set with the identifier of the processor responsible for the process of transferring the divided data to the shared memory 5. In the "head address" column 430, an address on the memory 82 where the divided data is stored is set. In the “data length” column 440, the data length of the divided data is set. A flag indicating whether or not the divided data has already been transferred is set in the “status” column 450. In this example, “transferred” is set when the transfer has been completed, and “untransferred” is set when the transfer has not been performed. The service processor 8 updates the contents of the transfer data management table 400 in real time each time the divided data is allocated or changed.
[0019]
After generating the divided data and determining the processor in charge of the transfer processing of each divided data, the service processor 8 notifies the processor in charge of the transfer processing of the divided data of an instruction to transfer the divided data (S315). Upon receiving the notification, each of the processors 1, 2, 3, and 4 prepares for securing a recording area on the local memories 13, 23, 33, and 43 for storing the divided data sent from the service processor 8. After performing the process, the service processor 8 notifies the service processor 8 that it is in a standby state for receiving the divided data (S316). Upon receiving the notification, the service processor 8 transmits the divided data for which the processor is in charge of the transfer processing to the processor (S317). Note that the service processor 8 attaches the above-described identifier to each divided data to be transmitted. Upon receiving the divided data sent from the service processor 8, each processor stores the received divided data in its own local memory 13, 23, 33, 43 (S318).
[0020]
Next, each of the processors 1, 2, 3, and 4 stores the divided data in the local memories 13, 23, 33, and 43, and stores the stored divided data in the microprogram storage area 51 of the shared memory 5 in the shared memory access bus 9. (S319). FIG. 5 shows the state of the divided data stored in the microprogram storage area 51. A division data number 510 is stored at the head of each division data.
At the end of the divided data, information (EOD (End Of Data)) indicating the end of the divided data is set. As shown in this figure, the divided data is sequentially written from the head address of the microprogram storage area 51. In principle, the next divided data is written following the already written divided data. The storage order of the divided data stored in the microprogram storage area 51 is not always in the order of the divided data numbers. That is, the storage order of the divided data is determined in accordance with, for example, the processing load of each of the processors 1, 2, 3, and 4, and is not necessarily the same as the order in which the divided data is combined when the microprogram is restored. Not necessarily.
[0021]
When the storage of the divided data in the microprogram storage area 51 is completed as described above, the processors 1, 2, 3, and 4 store the divided data in the shared memory 5 with respect to the service processor 8. Is completed (S320). Upon receiving the notification sent from the processor, the service processor 8 sets “transferred” in the “status” column 450 of the corresponding divided data in the transfer data management table 400 (S321).
[0022]
The service processor 8 monitors the contents of the “status” column 450 of the transfer data management table 400 in real time (S322). When the service processor 8 detects that “transferred” is set in the “status” column 450 of all the divided data in the transfer data management table 400 (S322: YES), the micro processor stores the microprogram in the shared memory 5. The completion of (setup) is notified to each of the processors 1, 2, 3, and 4 (S323).
[0023]
Each of the processors 1, 2, 3, and 4 manages a microprogram update flag in each of the local memories 13, 23, 33, and 43, which indicates whether the microprogram needs to be updated. Upon receiving the notification, at least one of the processors 1, 2, 3, and 4 sets the microprogram update flag to an ON state indicating that updating is necessary (S324).
[0024]
As described above, the process of transferring the microprogram from the service processor 8 to the shared memory 5 is performed. When the microprogram is transferred by the division transfer method, the microprogram is divided into a plurality of divided data, and the microprogram is stored in the shared memory 5 by a plurality of processors which are in charge of the transfer processing of each divided data. For this reason, load distribution is achieved in the transfer processing of the microprogram, and the microprogram stored in the service processor 8 is efficiently stored in the shared memory 5 without concentrating the processing load on one processor. Can be.
[0025]
In the above-described embodiment, the service processor 8 notifies the processors 1, 2, 3, and 4 that the microprogram has been stored in the shared memory 5 (S323). Instead of notifying from the processor 8, the processor 1, 2, 3, 4 may spontaneously inquire the service processor 8 whether a new microprogram is stored in the shared memory 5.
[0026]
The number of divided data stored in the shared memory 5 by each of the processors 1, 2, 3, and 4 (hereinafter, referred to as the number of stored data) is determined at a predetermined timing (for example, at regular intervals) by the spontaneous or service processor 8. Is notified to the service processor 8 in response to a request from the processor, and the service processor 8 stores the microprogram in the shared memory 5 when the sum of the storage numbers notified from each processor matches the division number of the microprogram. May be determined. In this case, the number of storages notified to the service processor 8 from each of the processors 1, 2, 3, and 4 is notified to an operator or the like in real time by a user interface, so that the shared memory of the divided data is provided to the operator or the like. It is also possible to grasp the real-time progress status of the transfer processing to the server 5.
[0027]
In the embodiment described above, the divided data downloaded by each processor is different from each other, and the same divided data stored in the memory 82 is not accessed by a plurality of processors. Therefore, it is not necessary to perform exclusive control on the divided data, whereby it is possible to simply configure a program for downloading the divided data from the processor, and to effectively use the memory capacity. In addition, since the exclusive control is not required, there is no processing waiting time caused by the exclusive control, and the processing efficiency is improved accordingly.
[0028]
In the above-described embodiment, as a method of allocating the processor to the divided data, for example, a method of simply allocating the divided data to each of the processors 1, 2, 3, and 4; There is a method of allocating in order from the processor with the smallest processing load according to the load. Also, once the divided data is allocated, at a certain point during the period from the start of the transfer process to the completion of the transfer process, the real-time processing load at that point is measured, and the remaining load is measured according to the measurement result. The processors 1, 2, 3, and 4 that are in charge of the transfer processing of the untransferred divided data to be transferred may be reassigned. In this case, for example, it is possible to cause the processor whose transfer processing has been completed and the processing load has been reduced to participate again in the transfer processing, thereby improving the processing efficiency.
[0029]
In the embodiment described above, the service processor 8 notifies the processors 1, 2, 3, and 4 of a transfer instruction of the divided data (S315). Alternatively, the processors 1, 2, 3, and 4 may spontaneously inquire the service processor 8 about the determination. In this case, the processors 1, 2, 3, and 4 monitor changes in their own processing loads, and when the processing load is small, the processors 1, 2, 3, and 4 determine whether or not there is divided data. Can also be configured. By doing so, the efficiency of the processing related to the supply of the microprocessor can be further improved. In this case, the magnitude of the processing load is determined by comparing the value of a parameter corresponding to the processing load such as the number of tasks per unit time with a threshold.
[0030]
The number of divisions of the microprogram and the data size of the divided data may be fixedly set, or may be changed each time the transfer is performed. Further, the number of divisions and the data size can be changed according to, for example, the processing load of the processors 1, 2, 3, and 4. In this case, the processing load is grasped, for example, by measuring the number of tasks processed per unit time in each processor.
[0031]
As for the number of divisions, for example, if the processing loads of the processors 1, 2, 3, and 4 are not much different, the microprogram is transferred to all of the processors 1, 2, 3, and 4. , The division number is set to 4. For example, when the processing load of the processor 1 is high, the microprogram is transferred only to the processors 2, 3, and 4. In this case, the division number is set to 3. It is also conceivable to do so. In addition, when the number of divisions is set to N, if the difference in the processing load of the processor is smaller than the threshold, the data size of each divided data is set uniformly, and the difference in the processing load of the processor is equal to or larger than the threshold. In such a case, the data size of the divided data assigned to the processor having a large processing load may be set smaller than the data size of the divided data assigned to the processor having a small processing load.
[0032]
=== Load to processor ===
The microprogram stored in the microprogram storage area 51 of the shared memory 5 is taken into the processors 1, 2, 3, and 4 at a predetermined timing. The microprograms captured by the processors 1, 2, 3, and 4 are stored in the microprogram storage areas 14, 24, 34, and 44 secured on the nonvolatile memories 12, 22, 32, and 42. Further, the microprogram stored in the microprogram storage area 51 or the microprogram storage areas 14, 24, 34, 44 is appropriately loaded into the microprogram load areas 15, 25, 35, 45. Further, as described above, the microprogram stored in the microprogram storage area 51 transferred by the divided transfer method is stored in the form of divided data. Is restored at the predetermined timing to restore the original microprogram.
[0033]
=== Load to local memory ===
FIG. 6 is a task generation sequence of the control device 100 to which the present invention is applied. When the processors 1, 2, 3, 4 are started (S601), the root program is transferred from the non-volatile memories 12, 22, 32, 42 inside the processors 1, 2, 3, 4 to the local memories 13, 23, 33, 43. 606 is loaded (S614), and a root task (S602) is generated (S613). The generated root task (S602) loads the microprogram load program 607 from the nonvolatile memories 12, 22, 32, and 42 (S616), and generates the microprogram load task 603 (S615).
The micro program load task (S603) loads any of the main program 608 stored in the nonvolatile memories 12, 22, 32, and 42 and the main program 612 stored in the shared memory 5 (S618), and (S604) is generated (S617).
[0034]
FIG. 7 is a detailed processing flow of the microprogram loading task (S603) in FIG. When activated, the microprogram load task (S603) sets a shared memory access bus (S702) and establishes a shared memory access path (S703). Next, the microprogram load task (S603) determines whether or not the shared memory access bus 9 is usable (S704). If so, the microprogram in the shared memory 5 is valid. Is determined (S705). If valid, it is determined whether or not the microprogram in the shared memory 5 is different from the microprogram in the nonvolatile memories 12, 22, 32, and 42 (S706). Here, if the microprogram is different, the microprogram is loaded from the shared memory 5 to the local memories 13, 23, 33, and 43 (S707). At the time of loading, the processor control units 11, 21, 31, and 41 read a plurality of pieces of divided data stored in the microprogram storage area 51 of the shared memory 5 and sequentially combine the read divided data in the order of identifiers. Restore the original microprogram. Then, the microprogram restored by the above processing is loaded from the shared memory 5 to the local memories 13, 23, 33, 43. Instead of determining whether the microprogram is different in (S706), it may be determined whether to load the microprogram from the shared memory 5 according to the microprogram update flag described above.
[0035]
Next, the processors 1, 2, 3, and 4 determine whether the microprogram has been successfully loaded (S708), and succeeded in loading the microprogram from the shared memory 5 to the local memories 13, 23, 33, and 43. If so, the microprogram valid flag of the shared memory 5 is set to ON (S709). Here, the microprogram valid flag indicates whether or not the microprogram needs to be loaded from the shared memory 5 to the nonvolatile memories 12, 22, 32, and 42, that is, the nonvolatile memories 12, 22, and 32, as described later. , 42 are used to determine whether the contents need to be updated.
[0036]
Next, in (S710), the processors 1, 2, 3, and 4 determine whether the microprogram has been successfully loaded into the local memories 13, 23, 33, and 43 (S710). Then, a main task is generated (S711), and the process ends (S712).
[0037]
In the determination of (S704), when the bus was not available, or in the determination of (S706), the microprogram of the shared memory 5 and the microprogram of the nonvolatile memories 12, 22, 32, and 42 were the same. In this case, the microprogram is loaded not from the shared memory 5 but from the nonvolatile memories 12, 22, 32, and 42 (S714). In the determination of (S705), the microprogram in the shared memory 5 is invalid due to the volatilization of data stored in the shared memory 5 or the occurrence of a failure, or in the determination of (S708), If the loading from the shared memory 5 has not been successful, the microprogram invalid flag stored in the shared memory 5 is set to ON (S713). Further, the microprogram is loaded from the microprogram storage areas 14, 24, 34, 44 of the nonvolatile memories 12, 22, 32, 42 to the local memories 13, 23, 33, 43 (S714). Then, it is determined whether or not the microprogram has been successfully loaded into the local memories 13, 23, 33, and 43 (S710). If the microprogram has been successfully loaded, the processors 1, 2, 3, and 4 generate a main task. (S711), the process ends (S712).
[0038]
=== Loading to nonvolatile memory ===
FIG. 8 is a flowchart illustrating the processing of the main task (S604) in FIG. This figure explains the processing related to the setup of the microprogram in the nonvolatile memories 12, 22, 32, 42 and the shared memory 5. When activated, the main task (S604) performs various initial settings (S802) of the hardware and software of the control device 100. When the microprogram valid flag of the shared memory 5 is set to ON in the microprogram load task (S603) in FIG. 6 (S709), it is determined whether the microvalid flag of the shared memory 5 is ON (S803). ON (S803: YES), and the processors 1, 2, 3, and 4 transfer the microprogram from the shared memory 5 to the microprogram storage areas 14, 24, 34, and 44 of the nonvolatile memories 12, 22, 32, and 42 (see FIG. S804). If the result of the determination in (S803) is not ON (S803: NO), the processing in (S804) is skipped.
[0039]
When the microprogram invalid flag of the shared memory 5 is set to ON in the microprogram load task (S603) (S713), the determination whether the microprogram invalid flag of the shared memory 5 is ON (S805) is ON (S805). S805: YES), the microprograms stored in the microprogram storage areas 14, 24, 34, 44 of the nonvolatile memories 12, 22, 32, 42 are transferred to the shared memory 5, whereby the microprograms are stored in the microprogram storage area 51. The program is stored (S806). In (S807), the processors 1, 2, 3, and 4 determine whether the transfer of the microprogram from the nonvolatile memories 12, 22, 32, and 42 to the shared memory 5 has succeeded, and has determined that the transfer has succeeded. If it is (S807: YES), the microprogram invalidation flag of the shared memory 5 is set to OFF (S808), and the initial setting of the main task ends (S809). If the microprogram invalidation flag of the shared memory 5 is OFF in the determination of (S805) (S805: NO), the processors 1, 2, 3, and 4 terminate the initial setting of the main task as it is (S809). . If the transfer is not successful in the determination of (S807) (S807: NO), the initial setting of the main task is terminated as it is.
[0040]
=== Application Example ===
FIG. 9 illustrates a storage including a disk array device 900 (storage control device) and an information processing device 950 that accesses the disk array device 900 (storage control device) via a communication path 940, which will be described as an application example of the control device 100 described above. 2 shows a block configuration of a system 90. The information processing device 950 is a computer such as a personal computer, a workstation, or a mainframe computer that includes a CPU (Central Processing Unit) and a memory. The communication performed via the communication path 940 includes, for example, a TCP / IP protocol, a fiber channel protocol (Fibre Channel Protocol), a FICON (Fibre Connection) (registered trademark), and an ESCON (Enterprise System Connection) (registered trademark). A communication protocol is employed.
[0041]
The disk array device 900 includes a channel control unit 910 (communication control unit), a disk control unit 920, a cache memory 930, a shared memory 931 and switches 932, a disk drive 933, a service processor 934, and the like for connecting these. You. As the switch 932, for example, a high-speed crossbar switch is used. The disk drive 933 may be housed in a separate housing from other components of the disk array device 900. A management terminal 935 is connected to the service processor 934. The management terminal 935 is a computer operated by an operator or the like. An operator or the like operates the management terminal 935 to perform various settings and operations for the disk array device 900, monitor operation status, monitor a failure, and the like. In addition, the management terminal 935 supplies a microprogram to the channel control unit 910 and the disk control unit 920 for the necessity of version upgrade or the like. It also provides a function of transferring the microprogram recorded and supplied on the medium 936 to the memory of the service processor 934. When a file system operates in the channel control unit 910 or the disk control unit device 920, the microprogram may be provided in a file format.
[0042]
FIG. 10 shows the configuration of the channel control unit 910. The channel control unit 910 includes a communication interface 9101 that provides a function related to communication with the information processing device 950, a non-volatile memory 9103 including a local memory 9102, a flash memory, and a program stored in the local memory 9102. And a I / O processor 9105 for realizing high-speed data transfer between the channel control unit 910 and the cache memory 930. The non-volatile memory 9103 stores a microprogram, which is software for realizing various functions provided by the channel control unit 910. The microprogram is appropriately loaded into the local memory 9102 and executed by the microprocessor 9104. Note that these components are connected to each other by a bus 9109. As the I / O processor 9105, for example, a DMA (Direct Memory Access) processor is used.
[0043]
FIG. 11 shows the configuration of the disk control unit 920. The disk control unit 920 includes an I / O processor 9201 for realizing high-speed data transfer between the cache memory 930 and the channel control unit 910, a local memory 9202, a nonvolatile memory 9203 including a flash memory, and the like, and a local memory. The system includes a microprocessor 9204 that implements various functions of the disk control unit 920 by executing programs stored in the 9202, a disk controller 9205 that writes and reads data to and from the disk drive 933, and the like. The non-volatile memory 9203 stores a microprogram which is software for realizing various functions provided by the disk control unit 920. The microprogram is appropriately loaded into the local memory 9202 and executed by the microprocessor 9204. Note that these components are connected to each other by a bus 9209. As the I / O processor 9201, for example, a DMA (Direct Memory Access) processor is used. The disk controller 9205 also provides a function of controlling the disk drive 933 in a RAID system (for example, RAID 0, 1, 5).
[0044]
The shared memory 931 and the cache memory 930 are used to store, for example, various control information and commands. The cache memory 930 is used to store, for example, data written to the disk drive 933 or data read from the disk drive 933.
[0045]
FIG. 12 shows the configuration of the service processor 934. The service processor 934 includes a microprocessor 9344, a memory 9342, and the like. The service processor 934 is communicably connected to the channel control unit 910 and the disk control unit 920 via the internal communication path 970 by the internal communication interface 9343. As the internal communication path 970, for example, a bus such as PCI or a LAN (Local Area Network) using TCP / IP as a communication protocol is adopted. The service processor 934 is communicably connected to the management terminal 935 via an external communication interface 9344. As a communication means between the service processor 934 and the management terminal 935, a bus or a LAN is employed. Note that the microprocessor 9104, the memory 9102, the internal communication interface 9343, and the external communication interface 9344 are connected by a bus 9349.
[0046]
The service processor 934 sets various operations for the channel control unit 910 and the disk control unit 920, monitors a failure, collects information on an operation state, and the like. The service processor 934 can collect information on the processing load of each channel control unit 910 and each disk control unit 920. The information on the processing load is, for example, the usage rate of the microprocessors 9104 and 9204. These values are provided by a program executed in the channel control unit 910 or the disk control unit 920.
[0047]
In the storage system 90 of this application example, the shared memory 5 in the control device 100 described above corresponds to the shared memory 931 that is a component of the disk array device 900. Further, the processors 1, 2, 3, and 4 in the control device 100 correspond to the channel control unit 910 or the disk control unit 920 that is a component of the disk array device 900.
[0048]
The service processor 8 in the control device 100 described above corresponds to the service processor 934 that is a component of the disk array device 900. The microprogram is stored in the memory 9302 of the service processor 934 from the management terminal 935 as appropriate. The service processor 934 transfers the microprogram stored in the memory to the channel control unit 910 and the disk control unit 920 via the shared memory 931 in the manner described above. When a file system is operating in the channel control unit 910 or the disk control unit 920, the microprogram is handled in a file format. In this case, the above-described divided data is also handled in a file format.
[0049]
The local memories 13, 23, 33, 43 in the control device 100 described above correspond to the local memories 9102, 9202. The non-volatile memories 12, 22, 32, and 42 in the control device 100 correspond to the non-volatile memories 9103, 9203, respectively. The processor control units 11, 21, 31, and 41 in the above-described control device 100 correspond to at least one of the microprocessors 9104 and 9204, the I / O processors 9105 and 9201, the communication interface 9101, the disk controller 9205, and the like. For example, when the processors 1, 2, 3, and 4 are the channel control units 910, the control target units 6 and 7 in the above-described control device 100 include other channel control units 910, disk control units 920, and cache memories 930. , A shared memory 931 and the like. Further, for example, when the processors 1, 2, 3, and 4 are the disk control units 920, they are other disk control units 910, channel control units 910, disk drives 933, cache memories 930, shared memories 931, and the like.
[0050]
A basic operation of the disk array device 900 when a data input / output request such as a data write request or a data read request transmitted from the information processing device 950 is received will be described. First, a case where a data write request is transmitted from the information processing device 950 to the disk array device 900 will be described.
Upon receiving the data write request sent from the information processing device 950, the disk array device 900 writes a data write command to the shared memory 931 and writes the write data received from the information processing device 950 to the cache memory 930. When the data writing to the cache memory 930 is completed, the disk array device 900 transmits a write completion report to the information processing device 950. That is, the completion report to the information processing device 950 is performed asynchronously with the actual data write operation to the disk drive 900. The disk control unit 920 monitors the contents of the shared memory 931 in real time (for example, at fixed time intervals). When the disk control unit 920 detects that a data write command has been written to the shared memory 931 by the above monitoring, the disk control unit 920 reads data to be written (hereinafter, referred to as write data) from the cache memory 930 and writes the read write data. The data is written to the disk drive 933. As described above, data writing to the disk drive 933 corresponding to the data write request is performed.
[0051]
Next, a basic operation of the disk array device 900 when a data write request is transmitted from the information processing device 950 to the disk array device 900 will be described. Upon receiving the data read request sent from the information processing device 950, the disk array device 900 sends a data read command corresponding to the request to the disk control unit 920. The transmission of the data read command from the channel control unit 910 to the disk control unit 920 may be performed via the shared memory 931.
[0052]
When receiving the data read command from the channel control unit 910, the disk control unit 920 reads the data to be read specified in the command from the disk drive 933, and writes the read data to the cache memory 930. When the data transfer to the cache memory 930 is completed, the disk control unit 920 notifies the channel control unit 910 of the completion. Then, the channel control unit 910 that has received the notification transfers the data to be read stored in the cache memory 930 to the information processing device 950.
[0053]
As described above, the present invention has been described based on one embodiment. However, the above embodiment of the present invention is for facilitating understanding of the present invention, and does not limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention naturally includes equivalents thereof.
[0054]
【The invention's effect】
According to the present invention, it is possible to provide a computer control method, a computer, a storage control device, a program, and a recording medium.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a block configuration of a control device described as an embodiment of the present invention.
FIG. 2 is a diagram illustrating a flowchart for explaining a processing flow in the case of a batch transfer method, which is described as one embodiment of the present invention;
FIG. 3 is a diagram illustrating a flowchart for explaining a processing flow in the case of a division transfer method, which is described as one embodiment of the present invention;
FIG. 4 is a diagram showing a transfer data management table described as an embodiment of the present invention.
FIG. 5 is a diagram illustrating a state of divided data stored in a microprogram storage area of a shared memory described as an embodiment of the present invention.
FIG. 6 is a flowchart illustrating a task sequence of a control device to which the present invention is applied, which is described as an embodiment of the present invention.
FIG. 7 is a diagram illustrating a flowchart illustrating processing of a microprogram load task, which is described as one embodiment of the present invention.
FIG. 8 is a diagram illustrating a flowchart illustrating processing of a main task, which is described as one embodiment of the present invention.
FIG. 9 is a diagram showing a block configuration of a storage system described as an embodiment of the present invention.
FIG. 10 is a diagram illustrating a configuration of a channel control unit described as one embodiment of the present invention.
FIG. 11 is a diagram illustrating a configuration of a disk control unit described as an embodiment of the present invention.
FIG. 12 is a diagram illustrating a configuration of a service processor described as an embodiment of the present invention.
[Explanation of symbols]
1-4 processor
5 Shared memory
6,7 Control target site
8 Service processor
9 Shared memory access bus
10 Service processor-processor communication bus
11, 21, 31, 41 Processor control unit
13,23,33,43 Local memory
14, 24, 34, 44 Microprogram storage area
15, 25, 35, 45 Micro program load area
51 Microprogram storage area
70 External device
81 Processor control unit
82 memory
83 Micro program storage area
100 control device
400 transfer data management table
900 disk array device
910 Channel control unit
9102 Local memory
9103 Non-volatile memory
920 Disk control unit
9202 Local memory
9203 Non-volatile memory
930 cache memory
931 Shared memory
932 switch
933 disk drive
935 management terminal
936 Recording medium
940 communication channel
950 Information processing device

Claims (12)

Including two or more processors, a first memory provided corresponding to each of the processors and storing a program to be executed by the processors, and a second memory accessible by each of the processors In the configured computer control method,
A step in which at least two or more processors share the divided data, which is data obtained by dividing a program stored in the first memory, and transfer the divided data to the second memory;
The processor restores the program by combining the divided data stored in the second memory by the transfer;
A step of causing the processor to store the restored program in the first memory. The computer control method according to claim 1,
A control method for a computer, wherein the processor that is in charge of transferring the divided data to the second memory is determined according to the processing load of each processor. The computer control method according to claim 1,
A control method for a computer, wherein a data size of divided data assigned to each processor is changed according to a processing load of the processor. Two or more communication control units for communicating with the information processing apparatus, a disk control unit for inputting / outputting data to / from a disk drive, a shared memory accessible by each of the communication control units, A cache memory accessible by the disk control unit; and
At least two or more of the communication control unit, sharing the divided data, which is data obtained by dividing a program for storing in the communication control unit, and transferring the divided data to the shared memory;
The communication control unit restores the program by combining the divided data stored in the shared memory by the transfer;
The communication control unit stores the restored program in the communication control unit;
A control method for a storage control device, comprising: A communication control unit that communicates with an information processing device; two or more disk control units that input and output data to and from a disk drive; a shared memory accessible by each of the disk control units; A cache memory accessible by each disk control unit; and
A step in which at least two or more of the disk controllers share divided data, which are data obtained by dividing a program to be stored in the disk controller, and transfer the divided data to the shared memory;
The disk controller restores the program by combining the divided data stored in the shared memory by the transfer;
Storing the restored program in the communication control unit, wherein the disk control unit stores the restored program in the communication control unit. A communication control unit that performs communication with the information processing device, a disk control unit that performs data input / output to / from a disk drive, a shared memory that can be accessed by the communication control unit and the disk control unit, the communication control unit, A cache memory accessible by the disk control unit; and
A step in which the communication control unit or the disk control unit transfers divided data, which is data obtained by dividing a program to be stored in the communication control unit or the disk control unit, to the shared memory,
The communication control unit or the disk control unit restores the program by combining the divided data stored in the shared memory by the transfer,
Storing the restored program in the communication control unit or the disk control unit by the communication control unit or the disk control unit. The computer control method according to claim 1, wherein the first memory is a non-volatile memory. 2. The computer control method according to claim 1, wherein the program is a micro program. Including two or more processors, a first memory provided corresponding to each of the processors and storing a program to be executed by the processors, and a second memory accessible by each of the processors Composed,
Means for at least two or more of the processors sharing the divided data, which is data obtained by dividing a program stored in the first memory, and transferring the divided data to the second memory;
Means for the processor to restore the program by combining the divided data stored in the second memory by the transfer,
Means for storing the program restored by the processor in the first memory. A communication control unit that performs communication with the information processing device, a disk control unit that performs data input / output to / from a disk drive, a shared memory that can be accessed by the communication control unit and the disk control unit, the communication control unit, A cache memory accessible by the disk control unit,
Means for the communication control unit or the disk control unit to share the divided data, which is data obtained by dividing a program to be stored in the communication control unit or the disk control unit, and transfer the divided data to the shared memory;
Means for the communication control unit or the disk control unit to restore the program by combining the divided data stored in the shared memory by the transfer,
Means for causing the communication control unit or the disk control unit to store the restored program in the communication control unit or the disk control unit. Including two or more processors, a first memory provided corresponding to each of the processors and storing a program to be executed by the processors, and a second memory accessible by each of the processors On the configured computer,
A function of transferring at least two or more processors to the second memory by respectively sharing divided data that is data obtained by dividing a program stored in the first memory;
A function of restoring the program by combining the divided data stored in the second memory by the transfer,
A function of causing the processor to store the restored program in the first memory. A recording medium on which the program according to claim 11 is recorded.

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