JP2004328869A - Zero cross signal output device, and image forming apparatus - Google Patents

Zero cross signal output device, and image forming apparatus Download PDF

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JP2004328869A
JP2004328869A JP2003118687A JP2003118687A JP2004328869A JP 2004328869 A JP2004328869 A JP 2004328869A JP 2003118687 A JP2003118687 A JP 2003118687A JP 2003118687 A JP2003118687 A JP 2003118687A JP 2004328869 A JP2004328869 A JP 2004328869A
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zero
cross signal
signal
signal output
output device
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JP4338429B2 (en
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Yoshifumi Yonetani
善文 米谷
Kazuya Iwabayashi
一也 岩林
Atsushi Umekage
篤 梅景
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Sharp Corp
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Sharp Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To generate and output a precise zero cross signal by removing the effect of noise when generating and outputting a zero cross signal, based on an AC signal obtained from an AC power source. <P>SOLUTION: This zero cross signal output device is provided with a capacitor 406 on the secondary side of a photocoupler PC3 which outputs a secondary zero cross signal FW, and a control circuit 500 executes interruption with the timing of ON of a secondary zero cross signal FW. Furthermore, this is provided with a constant current element 601 on the power source side of the voltage dividing point between resistor elements R1 and R2 provided in series for dividing the voltage of an AC signal, and this suppresses the effect of an induced noise current while suppressing a current consumption by lowering the impedance at ON of a primary zero cross signal. Or, this gives hysteresis properties and prevents a malfunction due to noise, by providing three or more resistor elements which divide the voltage of an AC signal and connecting the junction between the resistor elements on the grounding side more than the voltage dividing point and the line of a primary zero cross signal with each other via a resistor element or a diode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は,交流電源から得た交流信号に基づいてゼロクロス信号を生成・出力するゼロクロス信号出力装置及びそれを具備する画像形成装置に関するものである。
【0002】
【従来の技術】
画像形成装置では,交流電源から得た全波整流された交流信号に基づいてゼロクロス信号を生成し,このゼロクロス信号を用いて制御CPUに割り込みをかける(割り込み処理を実行する)ことにより,停電監視や定着装置の電力制御,電源周波数(50Hz/60Hz)の検出等が行われている。従って,このゼロクロス信号にノイズが生じると,不必要な割り込み処理が発生して装置が誤動作する。
従来,ゼロクロス信号に発生するノイズによる割り込み処理の誤動作を防止するため,特許文献1には,ゼロクロス信号により割り込みが発生した後,所定時間だけ割り込みを禁止することが示されている。これにより,前記交流信号におけるゼロクロスの検出電圧付近でノイズが発生することにより,ゼロクロス信号が連続してON/OFFして無用な割り込み処理が生じる誤動作を防止できる。
【0003】
【特許文献1】
特開2002−272089号広報
【0004】
【発明が解決しようとする課題】
しかしながら,特許文献1に示されるように,割り込み禁止の時間帯を設けると,比較的短い時間幅であるゼロクロス信号のパルス幅(ONからOFFまでの時間)を検出できないという問題点があった。
交流電源の電圧変動によって前記交流信号の電圧が変動した場合,これがゼロクロスの検出タイミング(前記交流信号の電圧がゼロクロスの検出電圧となるタイミング)を変化させる結果,前記交流信号の位相は変化していないにも関わらずゼロクロス信号の位相が変化してしまう。これに対応するため,従来,ゼロクロス信号のパルス幅を検出し,例えばその中央点(1/2の点)を検出する等により電源電圧の影響を除去することが行われていたが,ゼロクロス信号のパルス幅を検出できないと,電源電圧変化によるゼロクロス信号の位相変化の影響を除去することができない。
一方,交流信号における誘導ノイズ電流による誤動作を防止するため,交流信号経路のインピーダンスを小さくすることが有効であることが知られているが,該インピーダンスを単に小さくすると,流れる電流が大きくなって消費電力が増大するので,現実には前記インピーダンスを小さくしてノイズ(誘導ノイズ)の影響を除去することが難しいという問題点もあった。
従って,本発明は上記事情に鑑みてなされたものであり,その目的とするところは,交流電源から得た交流信号に基づいてゼロクロス信号を生成・出力する際に,ノイズの影響を除去して精度の高いゼロクロス信号の生成・出力を可能とするゼロクロス信号出力装置及びそれを具備する画像形成装置を提供することにある。
【0005】
【課題を解決するための手段】
上記目的を達成するために第1の発明は,交流電源から得た全波整流された交流信号に基づいて1次側ゼロクロス信号を生成するゼロクロス信号生成手段と,前記1次側ゼロクロス信号を入力しフォトカプラを介して2次側ゼロクロス信号を出力するゼロクロス信号出力手段と,を具備するゼロクロス信号出力装置において,前記ゼロクロス信号出力手段が,前記フォトカプラの2次側におけるコレクタ端子からエミッタ端子への経路と並列に接続されたコンデンサを具備してなることを特徴とするゼロクロス信号出力装置として構成されるものである。
これにより,2次側ゼロクロス信号がONするときには,フォトカプラの2次側トランジスタ(フォトトランジスタ)のON抵抗とコンデンサとからなる放電回路が形成され,その時定数は充分に小さいので,HighレベルからLowレベルに瞬時に立ち下がり,同OFFするときには,フォトカプラの2次側トランジスタのコレクタ負荷抵抗とコンデンサとからなる充電回路が形成され,該充電回路の時定数の作用によってLowレベルからHighレベルへの立ち上がりが一次遅れになる。従って,1次側ゼロクロス信号において,ONとOFFとの間で切り替わる際にノイズによって瞬時的に連続したON/OFFの切り替わりが生じた場合,2次側ゼロクロス信号におけるノイズの影響が鈍ることになる。このため,前記コンデンサの容量をノイズの大きさを想定した適切な容量とすれば,ノイズの影響を除去して精度の高いゼロクロス信号の生成・出力が可能となり,この2次側ゼロクロス信号(ON→OFFの切り替わりが鈍る信号)を用いた割り込み制御が,ノイズによって誤動作することを防止できる。
【0006】
また,第2の発明は,交流電源から得た全波整流された交流信号に基づいて1次側ゼロクロス信号を生成するゼロクロス信号生成手段と,前記1次側ゼロクロス信号を入力しフォトカプラを介して2次側ゼロクロス信号を出力するゼロクロス信号出力手段と,を具備するゼロクロス信号出力装置において,前記ゼロクロス信号生成手段が,前記交流信号を分圧するために直列に設けられた複数の抵抗素子からなる分圧回路と,該分圧回路における分圧点の電源側に設けられた定電流素子とを具備してなることを特徴とするゼロクロス信号出力装置として構成されるものである。
これにより,前記定電流素子によって前記分圧回路を流れる電流が制限されるので消費電力の増大を抑え,かつ,ゼロクロス検出タイミング近傍にける前記分圧回路のインピーダンスを小さくして誘導ノイズ電流による誤動作を防止することができる。
【0007】
また,第3の発明は,交流電源から得た全波整流された交流信号に基づいて1次側ゼロクロス信号を生成するゼロクロス信号生成手段と,前記1次側ゼロクロス信号を入力しフォトカプラを介して2次側ゼロクロス信号を出力するゼロクロス信号出力手段と,を具備するゼロクロス信号出力装置において,前記ゼロクロス信号生成手段が,前記交流信号を分圧するために直列に設けられた3つ以上の抵抗素子からなる分圧回路を具備し,前記分圧回路の分圧点に接地側から接続された前記抵抗素子よりもさらに接地側に位置する前記抵抗素子のいずれかにおける電源側の接続点と前記1次側ゼロクロス信号のラインとが抵抗素子又はダイオードを介して接続されてなることを特徴とするゼロクロス信号出力装置として構成されるものである。
これにより,前記分圧点の電圧が所定の基準電圧より下がって前記1次側ゼロクロス信号がONの状態では,接地側の分圧抵抗素子がダイオード或いは抵抗等を介してゼロクロス検出信号のON状態に引き込まれるので,分圧比(分圧点の電圧)は分圧抵抗によって定まる所定の値より小さく設定されることとなる。また,前記分圧点の電圧が所定の基準電圧より上がって前記1次側ゼロクロス信号がOFFの状態では,ダイオードを用いた場合には該ダイオードによって接地側の分圧抵抗素子がゼロクロス検出信号とアイソレートされるので分圧比が分圧抵抗によって定まる所定の分圧比となり,また,抵抗素子を用いた場合にはゼロクロス信号のOFF状態にプルアップされるので分圧比が分圧抵抗によって定まる所定の分圧比より大きく設定されることなる。このようにゼロクロス信号の出力状態に応じて分圧比が切り替わることによりヒステリス特性が得られ,ノイズによる誤動作を防止することができる。
【0008】
また,本発明は,前記第1の発明に係るゼロクロス信号出力装置と,これにより出力された前記2次側ゼロクロス信号がONするタイミングを基準に割り込み処理を行う制御手段と,を具備してなることを特徴とする画像形成装置として捉えたものであってもよい。
同様に,本発明は,前記第2の発明又は第3の発明に係るゼロクロス信号出力装置と,これにより出力された前記2次側ゼロクロス信号を用いて割り込み処理を行う制御手段と,を具備してなることを特徴とする画像形成装置として捉えたものであってもよい。
【0009】
【発明の実施の形態】
以下添付図面を参照しながら,本発明の実施の形態及び実施例について説明し,本発明の理解に供する。尚,以下の実施の形態及び実施例は,本発明を具体化した一例であって,本発明の技術的範囲を限定する性格のものではない。
ここに,図1は本発明の実施の形態に係るゼロクロス信号出力装置Xを具備する画像形成装置の概略構成を表す断面図,図2は本発明の実施の形態に係るゼロクロス信号出力装置Xの構成を表す回路図,図3は本発明の実施の形態に係るゼロクロス信号出力装置Xにおける交流信号及びゼロクロス信号の電圧波形を表す図,図4は本発明の第1の実施例に係るゼロクロス信号出力装置X1の構成を表す回路図,図5は本発明の第1の実施例に係るゼロクロス信号出力装置X1における交流信号及びゼロクロス信号の電圧波形を表す図,図6は本発明の第2の実施例に係るゼロクロス信号出力装置X2の構成を表す回路図,図7は本発明の第3の実施例に係るゼロクロス信号出力装置X3の構成を表す回路図である。
【0010】
まず,図1を用いて,本発明の実施の形態に係るゼロクロス信号出力装置Xを具備する画像形成装置の一例である複写機1の概略構成について説明する。
本複写機1の上部は,原稿読取部110となっている。これは,該原稿読取部110が備える自動原稿搬送装置112により,該自動原稿搬送装置112の上面の原稿セットトレイ上にセットされた複数枚の原稿を1枚ずつ自動的にガラス板で形成された原稿台111上へ給送する装置である。
前記原稿台111上に載置,或いは前記自動原稿搬送装置112により前記原稿台11上に給送された原稿の画像を走査して読み取る前記原稿読取部110の読取光学系は,前記原稿台111の下部に配置され,第1の走査ユニット113,第2の走査ユニット114,原稿からの反射光をCCDラインセンサ116上に結像させる光学レンズ115,光電変換素子であるCCDラインセンサ116等から構成されている。また,前記第1の走査ユニット113は,原稿面上を露光する露光ランプユニット113aと,原稿からの反射光像を所定の方向に反射させる第1ミラー113b等から構成されている。さらに,前記第2の走査ユニット114は,前記第1ミラーから反射されてくる原稿からの反射光を,前記CCDラインセンサ116に導く第2及び第3ミラー114a,114bより構成されている。
そして,前記原稿読取部110によって読み取られた原稿画像は,画像データとして不図示の画像データ入力部へと送られ,その画像データに対して所定の画像処理が施された後に不図示の画像処理部のメモリに一旦記憶され,画像処理終了後或いは外部からの所定の出力指示に応じて前記メモリ内の画像データが読み出されて前記原稿読取部の下方に配置された画像形成部210を構成する書込みユニット227に転送される。
【0011】
前記書込みユニット227は,前記画像処理部から或いは外部の装置から転送されてきた画像データの内容に応じてレーザ光を出射する半導体レーザ光源(不図示),そのレーザ光を等角速度偏向するポリゴンミラー(不図示),等角速度で偏向されたレーザ光が感光体ドラム2上において等速度で偏向されるように補正するf−θレンズ(不図示)等から構成されている。なお,本実施の形態では,前記書込みユニット227としてレーザ書込みユニットを用いているが,LEDやEL等の発光素子アレイを用いた固体走査型の光書込みヘッドユニットを用いてもよい。感光体ドラム2としては,例えばアルミニウム等で製作された導電性基体(金属ドラム)の外周面に,アモルファスシリコン(a−Si),セレン(Se)や有機光半導体(OPC)等の光導電層が薄膜状に形成されてなる構成が挙げられるが,特に限定されるものではない。
さらに,前記画像形成部210は,前記感光体ドラム2の周囲に,該感光体ドラム2を所定の電位に帯電させる帯電器223,前記感光体ドラム2上に形成された静電潜像にトナーを供給して顕像化する現像装置100,前記感光体ドラム2表面に形成されたトナー像を記録シート(用紙,前記被転写材の一例)に転写するコロナ放電方式の転写装置225(前記転写手段の一例),前記感光体ドラム2を除電する除電器229,前記感光体ドラム上の余分なトナーを回収するクリーニング器226等も備えている。この画像形成部210により画像が転写された記録シートは,その後,定着ユニット217に送られ画像が記録シートに定着される。
また,前記画像形成部210の排出側には,前記定着ユニット217の他に,記録シートの裏面に再度画像を形成するために記録シートの方向(前後)を反転させるスイッチバック路221,画像が形成された記録シートに対してステープル処理等を行うとともに昇降トレイ261を有する後処理装置260を備えている。前記定着ユニット217によりトナー像が定着された記録シートは,必要に応じて前記スイッチバック路221を経て排紙ローラ219によって前記後処理装置260へと導かれ,ここで所定の後処理が施された後,前記昇降トレイ261上に排出される。
また,本複写機1は,前記画像形成部210に記録シートを供給するとして,前記画像形成部210の下方に備えられた用紙トレイ251,前記スイッチバック路221に通じており記録シートの両面に画像形成を行う際に記録シートを一時退避させる両面ユニット255,複数の給紙トレイ252,253を備える多段給紙部270に加え,本複写機1の側面側に突出して設けられ手差トレイ254を供える手差しシート給送装置280を具備している。さらに,前記各トレイ251,252,253,254にセットされた記録シートを前記画像形成部210の前記転写装置225による転写位置へと搬送する搬送手段250を具備している。なお,前記両面ユニット255は通常の用紙カセットと交換可能な構成となっており,前記両面ユニット255を通常の用紙カセットに置き換えた構成とすることも可能となっている。
【0012】
次に,図2を用いて,前記複写機1が備えるゼロクロス信号出力装置Xの回路構成について説明する。
ゼロクロス信号出力装置Xは,交流電源301側の1次側回路部Aと,該1次側回路部Aとスイッチングレギュレータ304やフォトカプラPC1,PC2,PC3を介して絶縁された2次側回路部Bとから構成されている。
交流電源301の出力は,1次側回路部Aにおいて,メインスイッチ302(手動スイッチ)を経た後に全波整流回路303により全波整流され,該全波整流後の信号がスイッチングレギュレータ304に出力されるとともに,スイッチング用FET309及び平滑回路310により定電圧化されDCライン311へ出力される。
一方,スイッチングレギュレータ304に出力された信号を介した信号は,2次側回路部Bにおいて,平滑回路404,405により平滑化されて,駆動系定電圧電源出力V,および回路系定電圧電源出力VCCが生成される。駆動系定電圧電源出力Vはドラムモータ等の駆動回路に供給されるものであり,同時に,分圧されて反転シャントレギュレータSRG1に入力される。このシャントレータSRG1は入力電圧と内部の基準電圧とを比較し,入力電圧が高い場合にはその出力はONとなる。この出力がON状態ではフォトカプラPC1を介して1次側に伝わり,スイッチング用FET309のゲートを強制的に接地し,スイッチング発振を停止させる。また入力電圧が低い場合にはシャントレレギュレータSRG1の出力はOFFとなり,スイッチング用FET309のゲートの強制的な接地が解除され,1次側はスイッチング発振を行い,駆動系出力電圧Vは一定電圧となる。また,スイッチングレギュレータ304(トランス)の2次側コイル中間タップより得られた平滑電圧Vは,電圧降下型の定電圧電源素子VRGで安定化され,その出力が回路系定電圧電源出力Vccとして制御回路等に供給される。
また,交流電源301の出力は,1次側回路部Aにおいて,他の全波整流回路307により全波整流され,該全波整流後の信号(以下,交流信号314という)は,電源側から接地側へ順に直列接続された第1の抵抗素子R1及び第2の抵抗素子R2(分圧回路)によって分圧される。その分圧点308は,DCライン311に接続されたシャンド・レギュレータ(SRG2)の入力端子に接続され,分圧点308の電圧(分圧電圧)が所定の基準電圧未満となるとSRG2の出力がON状態となり,DCライン311から抵抗,フォトカプラPC3を介して電流がSRG2へ流れるとともに,フォトカプラPC3を構成するフォトダイオード312aが発光し,同じくフォトカプラPC3を構成し2次側回路部Bに接続されたフォトトランジスタ312bがON状態となる。
これに対し,前記交流信号314の前記分圧電圧が前記基準電圧以上となると,SRG2の出力はOFF状態となり,フォトカプラPC3を構成するフォトダイオード312aの発光が停止(消灯)し,2次側回路部B側の前記フォトトランジスタ312bがOFF状態となる。
これにより,SRG2を流れる信号は,前記交流信号314が所定電圧未満であるときにLowレベルとなるゼロクロス信号(1次側ゼロクロス信号315)となる。ここで,前記全波整流回路307,前記抵抗素子R1,R2及びSRG2等が前記ゼロクロス信号出力手段の一例を構成するものである。
【0013】
一方,2次側回路部Bにおいては,定電圧電源出力Vが抵抗Rを介して前記フォトトランジスタ312b(フォトカプラPC3)のコレクタに供給されており,前記フォトトランジスタ312b(フォトカプラPC2)がON状態となる(即ち,前記交流信号314が分圧された前記分圧点308の電圧が基準電圧未満である)と2次側ゼロクロス信号FWはLowレベルとなり,前記フォトトランジスタ312bがOFF状態となる(前記分圧点308の電圧が基準電圧以上である)と2次側ゼロクロス信号FWはHighレベルとなる。
このような構成により,整流回路307で全波整流された前記交流信号314から前記1次側ゼロクロス信号315が生成され,これが前記フォトカプラPC2を介することにより絶縁された前記2次側ゼロクロス信号FWとして出力される。
図3(a)〜(d)は,当該ゼロクロス信号出力装置Xにより得られる前記交流電源301の出力信号(a),前記交流信号314(b),前記1次側ゼロクロス信号315(c)及び前記2次側ゼロクロス信号FW(d)の各電圧波形を表したものである。
【0014】
また,2次側回路部Bには,パワーセーブ信号PSの入力端子が設けられ,該パワーセーブ信号PSがON(Highレベル)すると,フォトカプラPC1がON状態となり,スイッチング用FET309のスイッチング発振は強制停止させられ,パワーセーブ状態となる。
さらに,2次側回路部Bには,パワーリレー信号PRの入力端子が設けられ,該パワーリレー信号PRがON(Highレベル)すると,リレーコイルRLが動作することによって1次側回路部Aにおけるリレー接点305がOFFとなり,前記交流信号314が停止状態(Lowレベル)となる。
前記パワーセーブ信号PS及び前記パワーリレー信号PRは,所定の制御回路500により,当該複写機1が所定時間以上操作されず,外部装置からの印刷要求も受信されなかった場合に,ONとなるように制御される。
また,2次側回路部Bには,ヒータランプ信号HLの入力端子が設けられ,複写装置1の印刷動作時に,前記制御回路500によって前記ヒータランプ信号HLがON/OFFされ,これによってフォトカプラPC2が動作/停止することで1次側回路部Aに設けられた定着温度制御回路306において位相角によるハロゲンランプ等のヒータランプ306aの定着温度制御が行われる。
また,前記制御回路500はCPUを備え,前記2次側ゼロクロス信号FWを用いて前記CPUに割り込みをかける(割り込み処理を実行する)ことにより,停電監視や定着装置の電力制御,電源周波数(50Hz/60Hz)の検出等を行う。
また,プッシュスイッチ401はユーザーの操作によりコピー動作の要求がなされたことを制御回路500が検知するためのものである。
以上に説明した構成は,一般的な画像形成装置に設けられる従来のゼロクロス信号出力回路と同様の構成である。
【0015】
本発明に係るゼロクロス信号出力装置Xの特徴は,前記フォトカプラPC3の2次側におけるコレクタ端子からエミッタ端子へ(前記フォトトランジスタ312bのコレクタ〜エミッタ)の経路と並列に接続されたコンデンサ406が設けられていることである。
これにより,図3(e)に示すように,前記2次側ゼロクロス信号FWがONするときには,HighレベルからLowレベルに瞬時に立ち下がり,同OFFするときには,前記コンデンサ406の作用によってLowレベルからHighレベルへの立ち上がりが一次遅れ状に鈍ることになる。従って,図3(f)に破線で示すように,前記1次側ゼロクロス信号315において,OFFとONとの間で切り替わる際にノイズによって瞬時的に連続したOFF/ONの切り替わりが生じた場合,図3(f)に実線で示すように,前記2次側ゼロクロス信号FWにおけるノイズの影響も鈍って割込み検出のしきい電圧以下に抑制され,制御回路500は誤動作することなく正常動作することになる。
ここで,前記2次側ゼロクロス信号FWを入力として割り込み処理を行う制御回路500における割り込み検出のしきい電圧をVth,信号FWのOFF時の電圧レベル(Highレベル)をVCC(ON時は0(ゼロ)V),ノイズの時間幅をTn,前記コンデンサ406の容量をC,前記フォトカプラPCのコレクタに接続される抵抗素子407の抵抗値をRとすると,次の(1)式の関係が成立する範囲では,ノイズが前記制御回路500によって検出されず,ノイズによる影響を除去して前記制御回路500の誤動作を防止できる(Lnは低eの自然対数を表す)。
C・R>−Tn/Ln(1−Vth/VCC) …(1)
従って,例えば,前記しきい電圧Vth=VCC/2である場合,次の(2)式が成立するような前記コンデンサ406及び前記抵抗素子407を選定すればノイズによる前記制御回路500の誤動作を防止できる。
C・R=Tn/0.693 …(2)
また,従来技術のように,割り込み禁止の時間帯を設ける必要がないので,前記制御回路500によって前記2次側ゼロクロス信号FWのパルス幅(ONからOFFまでの時間)を検出することが可能である。これにより,電源電圧変化の変化による前記2次側ゼロクロス信号FWの位相変化の影響を除去することができ,精度の高いゼロクロス信号検出が可能となる。ここで,前記2次側ゼロクロス信号FWの立ち上がり(ON→OFF)の時間は,前記抵抗素子407の抵抗値及び前記コンデンサ406の容量により予め想定できるので,前記2次側ゼロクロス信号FWのパルス幅検出時に,その立ち上がり時間分を考慮すればより精度高くパルス幅を求めることができる。
また,前記制御回路500により,前記2次側ゼロクロス信号FWがONするタイミング(High→Low)で割り込み処理を実行すれば,瞬時に立ち下がる信号により遅れのない正確なタイミングでの割り込み処理を実行することができる。
【0016】
【実施例】
(第2の発明)
次に,図4を用いて,前記ゼロクロス信号出力装置Xに,さらにノイズ除去性能を高める構成を加えた第1の実施例(第2の発明の実施例)であるゼロクロス信号出力装置X1について説明する。
ゼロクロス信号出力装置X1は,前記ゼロクロス信号出力装置Xにおいて,前記交流信号314を分圧するために電源側から接地側への順に直列に設けられた前記第1の抵抗素子R1及び第2の抵抗素子R2の分圧点308と前記第1の抵抗素子R1との間に定電流ダイオード601(前記定電流素子の一例)を設けたものである。
図5は,本ゼロクロス信号出力装置X1における前記交流信号314(全波整流された信号),前記分圧点308における信号(分圧回路電流)及び前記2次側ゼロクロス信号FWの各電流波形を表す。
図5に示すように,前記分圧点308における信号の電流波形は,前記定電流ダイオード601が設けられたことにより,該定電流ダイオード601のピンチオフ電流Ipでリミットがかかる。このピンチオフ電流Ipを,前記分圧点308の電圧がSRG2の基準電圧となるときに流れる電流Irefに若干の余裕分を加えた電流とすれば,SRG2を動作(ON/OFF)させるのに必要十分なものとなる。
一般に,交流信号における誘導ノイズ電流による誤動作を防止するために,回路(信号経路)のインピーダンス(ここでは,前記抵抗素子R1,R2の抵抗値)を小さくすることが有効であることが知られている。しかし,回路のインピーダンスを小さくすると,流れる電流が大きくなるので消費電力が増大する。
例えば,図5において,SRG2の前記基準電圧が2.5V,前記第1及び第2の抵抗素子R1,R2の抵抗値がそれぞれ4.7KΩ,47KΩであり,位相各11.2度のタイミングでゼロクロス検出を行う場合,位相各11.2度のときに前記抵抗素子R1,R2(分圧回路)に流れる電流は0.53A,ピーク電流は2.7mA,消費電力は0.193Wとなる。
ここで,ゼロクロス検出の位相角を維持しつつ,ノイズ対策のために前記第1及び第2の抵抗素子R1,R2の抵抗値をそれぞれ470Ω,4.7KΩとして元の1/10倍とすると,位相角11.2度のときに流れる電流は5.3mA,ピーク電流は27mA,消費電力は1.93Wとなり元の10倍となってしまう。しかし,この場合において,前記定電流ダイオード601として,ピンチオフ電流Ipが5.3mAであるものを用いると,前記抵抗素子R1,R2に流れるピーク電流は1/5倍となり,消費電力は0.4753Wと約1/4倍に抑えることができる。
このように,ゼロクロス検出タイミング近傍で定電流素子のピッチオフ電流以下にすることにより,前記分圧回路のインピーダンスを小さくして誘導ノイズ電流による誤動作を防止し,かつ,前記定電流素子によって前記分圧回路を流れる電流がピンチオフ電流に制限されるので消費電力も抑えることができる。
前記定電流素子としては,前記定電流ダイオード601の他,ドレインとゲートの間を短絡させた電界効果トランジスタ(FET)や,カレントミラー回路等を用いてもよい。
【0017】
(第3の発明)
次に,図6を用いて,前記ゼロクロス信号出力装置Xに,さらにノイズ除去性能を高める構成を加えた第2の実施例(第3の発明の実施例)であるゼロクロス信号出力装置X2について説明する。
ゼロクロス信号出力装置X1は,前記ゼロクロス信号出力装置Xにおいて,前記交流信号314を分圧するために電源側から接地側への順に直列に設けられた前記第1及び第2の抵抗素子R1,R2よりもさらに接地側に直列に第3の抵抗素子R3を設けて3つの抵抗素子によって分圧回路を構成し,前記第2及び第3の抵抗素子R2,R3の間の接続点602(前記分圧点308に接地側から接続された前記抵抗素子R2よりもさらに接地側に位置する前記抵抗素子R3の電源側の接続点)と前記1次側ゼロクロス信号315のラインとが第4の抵抗素子R4を介して接続されたものである。
図6では,前記分圧点308と1次側接地(GND)との間にごく小容量のコンデンサC1を設けているが,これは特に本発明の構成をなすものではなく,特に設けなくてもよい。
このような構成により,前記分圧点308の電圧が所定の基準電圧より下がって前記1次側ゼロクロス信号がONの状態では,接地側の分圧抵抗素子R3が抵抗素子R4を介してゼロクロス検出信号のON状態に引き込まれるので,分圧比は分圧抵抗によって定まる所定の値((R2+R3)/(R1+R2+R3))より小さく設定されることとなる。また,前記分圧点308の電圧が所定の基準電圧より上がって前記1次側ゼロクロス信号がOFFの状態では,接地側の分圧抵抗素子R3は前記1次側ゼロクロス信号のOFF状態にプルアップされるので,分圧比が前記所定の分圧比より大きく設定されることなる。このようにゼロクロス信号の出力状態に応じて分圧比が切り替わることによりヒステリス特性が得られ,ノイズによる誤動作を防止することができる。
この効果は,図7に示すように,前記第4の抵抗素子R4をダイオード603に置き換えた実施例であるゼロクロス信号出力装置X3も同様に奏する。
【0018】
【発明の効果】
以上説明したように,第1の発明によれば,交流電源から得た交流信号に基づいてゼロクロス信号を生成・出力する際に,2次側ゼロクロス信号を出力するフォトカプラの2次側にコンデンサを設けることにより,交流信号におけるゼロクロスの検出電圧付近でノイズが発生することにより,ゼロクロス信号が連続してON/OFFして無用な割り込み処理が生じる誤動作を防止できる。このとき,従来のように割り込み禁止の時間帯を設ける必要がないので,ゼロクロス信号(2次側)のパルス幅を検出することも可能であり,電源電圧の変化の影響を受けずに精度の高いゼロクロス信号の検出を行うことが可能である。さらに,2次側ゼロクロス信号がONするタイミングで制御部により割り込み処理を行えば,瞬時に立ち下がる信号により遅れのない正確なタイミングでの割り込み処理を実行することができる。
また,第2の発明によれば,交流信号を分圧するために直列に設けられた抵抗素子の分圧点の電源側に定電流素子を設けることにより,抵抗素子のインピーダンスを下げても消費電流を抑えつつ交流信号における誘導ノイズ電流の影響を抑えることが可能となる。
また,第3の発明によれば,交流信号を分圧するために直列に設けられた3つ以上の抵抗素子のうち,分圧点よりも接地側の抵抗素子の接続点と1次側ゼロクロス信号のラインとを抵抗素子又はダイオードを介して接続することにより,ゼロクロス検出動作がヒステリシス特性を有することとなり,ノイズによる誤動作を防止することができる。
【図面の簡単な説明】
【図1】本発明の実施の形態に係るゼロクロス信号出力装置Xを具備する画像形成装置の概略構成を表す断面図。
【図2】本発明の実施の形態に係るゼロクロス信号出力装置Xの構成を表す回路図。
【図3】本発明の実施の形態に係るゼロクロス信号出力装置Xにおける交流信号及びゼロクロス信号の電圧波形を表す図。
【図4】本発明の第1の実施例に係るゼロクロス信号出力装置X1の構成を表す回路図。
【図5】本発明の第1の実施例に係るゼロクロス信号出力装置X1における交流信号及びゼロクロス信号の電圧波形を表す図。
【図6】本発明の第2の実施例に係るゼロクロス信号出力装置X2の構成を表す回路図。
【図7】本発明の第3の実施例に係るゼロクロス信号出力装置X3の構成を表す回路図。
【符号の説明】
1…画像形成装置
2…感光体ドラム(像担持体)
100…現像装置
110…画像読取部
210…画像形成部
225…転写装置
254…手差しトレイ
280…手差しシート給送装置
301…交流電源
302…メインスイッチ
303,305…全波整流回路
304…スイッチングレギュレータ
305…リレー接点
306…定着温度制御回路
306a…ヒータランプ
308…分圧点
309…スイッチング用FET
310,404,405…平滑回路
311…DCライン
312a…フォトダイオード(フォトカプラ)
312b…フォトトランジスタ(フォトカプラ)
314…交流信号(全波整流信号)
315…1次側ゼロクロス信号
406…コンデンサ
407…抵抗素子
500…制御回路
601…定電流ダイオード(低電流素子)
603…ダイオード
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a zero-cross signal output device that generates and outputs a zero-cross signal based on an AC signal obtained from an AC power supply, and an image forming apparatus including the same.
[0002]
[Prior art]
The image forming apparatus generates a zero-cross signal based on the full-wave rectified AC signal obtained from the AC power supply, and interrupts the control CPU using the zero-cross signal (executes interrupt processing), thereby monitoring the power failure. And power control of the fixing device, detection of a power supply frequency (50 Hz / 60 Hz), and the like. Therefore, when noise occurs in the zero-cross signal, unnecessary interrupt processing occurs and the device malfunctions.
Conventionally, in order to prevent malfunction of interrupt processing due to noise generated in a zero-cross signal, Patent Document 1 discloses that interrupt is prohibited for a predetermined time after an interrupt is generated by a zero-cross signal. Accordingly, it is possible to prevent a malfunction in which a zero-cross signal is continuously turned ON / OFF and an unnecessary interrupt process is generated due to generation of noise near a zero-cross detection voltage in the AC signal.
[0003]
[Patent Document 1]
JP-A-2002-27089
[0004]
[Problems to be solved by the invention]
However, as shown in Patent Literature 1, there is a problem in that when a time zone in which interrupts are prohibited is provided, the pulse width (time from ON to OFF) of the zero-cross signal, which is a relatively short time width, cannot be detected.
When the voltage of the AC signal fluctuates due to the voltage fluctuation of the AC power supply, this changes the zero-cross detection timing (timing at which the voltage of the AC signal becomes the zero-cross detection voltage). As a result, the phase of the AC signal changes. Despite the absence, the phase of the zero-cross signal changes. In order to cope with this, conventionally, the influence of the power supply voltage has been removed by detecting the pulse width of the zero-cross signal and detecting, for example, a center point (a half point) thereof. If the pulse width cannot be detected, the influence of the phase change of the zero-cross signal due to the power supply voltage change cannot be removed.
On the other hand, it is known that it is effective to reduce the impedance of the AC signal path in order to prevent malfunction due to the induced noise current in the AC signal. However, if the impedance is simply reduced, the flowing current increases and the consumption increases. Since the power is increased, there is a problem that it is actually difficult to reduce the impedance and remove the influence of noise (inductive noise).
Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to eliminate the influence of noise when generating and outputting a zero-cross signal based on an AC signal obtained from an AC power supply. An object of the present invention is to provide a zero-cross signal output device capable of generating and outputting a high-precision zero-cross signal and an image forming apparatus including the same.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention provides a zero-cross signal generating means for generating a primary-side zero-cross signal based on a full-wave rectified AC signal obtained from an AC power supply, and an input of the primary-side zero-cross signal. A zero-cross signal output means for outputting a secondary-side zero-cross signal via a photocoupler, wherein the zero-cross signal output means is connected from a collector terminal to an emitter terminal on the secondary side of the photocoupler. And a capacitor connected in parallel with the path.
Thus, when the secondary-side zero-cross signal is turned on, a discharge circuit including the ON resistance of the secondary-side transistor (phototransistor) of the photocoupler and the capacitor is formed, and the time constant is sufficiently small. When the charge level instantaneously falls and turns off, a charging circuit composed of the collector load resistance of the secondary transistor of the photocoupler and a capacitor is formed, and the time constant of the charging circuit changes from the Low level to the High level. The rise is first-order lag. Therefore, in the case of switching between ON and OFF in the primary-side zero-cross signal, when the ON / OFF switching occurs instantaneously continuously due to noise, the influence of the noise in the secondary-side zero-cross signal is reduced. . For this reason, if the capacitance of the capacitor is set to an appropriate value assuming the magnitude of noise, it is possible to generate and output a highly accurate zero-cross signal by eliminating the influence of noise. It is possible to prevent the malfunction of the interrupt control using the signal which makes the switching of OFF slow) due to noise.
[0006]
Further, a second invention provides a zero-cross signal generating means for generating a primary-side zero-cross signal based on a full-wave rectified AC signal obtained from an AC power supply, and a means for inputting the primary-side zero-cross signal and receiving the signal via a photocoupler. And a zero-cross signal output means for outputting a secondary-side zero-cross signal. The zero-cross signal generation means comprises a plurality of resistance elements provided in series to divide the AC signal. A zero-cross signal output device comprising a voltage dividing circuit and a constant current element provided on a power supply side of a voltage dividing point in the voltage dividing circuit.
As a result, the current flowing through the voltage dividing circuit is limited by the constant current element, so that an increase in power consumption is suppressed, and the impedance of the voltage dividing circuit near the zero-crossing detection timing is reduced to cause a malfunction due to an induced noise current. Can be prevented.
[0007]
According to a third aspect of the present invention, there is provided a zero-crossing signal generating means for generating a primary-side zero-crossing signal based on a full-wave rectified AC signal obtained from an AC power supply, and the primary-side zero-crossing signal being input and passed through a photocoupler. A zero-cross signal output means for outputting a secondary-side zero-cross signal, wherein the zero-cross signal generation means comprises three or more resistive elements provided in series for dividing the AC signal. And a power-supply-side connection point of one of the resistive elements further located on the ground side than the resistive element connected from the ground side to the voltage-dividing point of the voltage-divider circuit. It is configured as a zero-cross signal output device, wherein a line of a next-side zero-cross signal is connected via a resistance element or a diode.
Thus, when the voltage at the voltage dividing point falls below a predetermined reference voltage and the primary-side zero-crossing signal is ON, the ground-side voltage dividing resistor element is turned on by a diode or a resistor. Therefore, the voltage dividing ratio (voltage at the voltage dividing point) is set to be smaller than a predetermined value determined by the voltage dividing resistor. When the voltage at the voltage dividing point is higher than a predetermined reference voltage and the primary-side zero-cross signal is OFF, when a diode is used, the diode causes the ground-side voltage-dividing resistance element to generate a zero-cross detection signal. Since the isolation is performed, the voltage dividing ratio becomes a predetermined voltage dividing ratio determined by the voltage dividing resistor. If a resistance element is used, the voltage is pulled up to an OFF state of the zero cross signal, so that the voltage dividing ratio is the predetermined voltage dividing determined by the voltage dividing resistor. It will be set larger than the partial pressure ratio. By switching the voltage division ratio in accordance with the output state of the zero-cross signal in this manner, a hysteresis characteristic is obtained, and malfunction due to noise can be prevented.
[0008]
Further, the present invention includes the zero-cross signal output device according to the first invention, and control means for performing an interrupt process based on the timing at which the secondary-side zero-cross signal output thereby is turned on. The image forming apparatus may be regarded as an image forming apparatus characterized by the above.
Similarly, the present invention includes the zero-cross signal output device according to the second or third invention, and control means for performing interrupt processing using the secondary-side zero-cross signal output thereby. Alternatively, the image forming apparatus may be regarded as an image forming apparatus.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments and examples of the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention. The following embodiments and examples are mere examples embodying the present invention, and do not limit the technical scope of the present invention.
Here, FIG. 1 is a cross-sectional view showing a schematic configuration of an image forming apparatus provided with a zero-cross signal output device X according to an embodiment of the present invention, and FIG. 2 is a sectional view of the zero-cross signal output device X according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration, FIG. 3 is a diagram showing voltage waveforms of an AC signal and a zero-cross signal in a zero-cross signal output device X according to an embodiment of the present invention, and FIG. 4 is a zero-cross signal according to a first embodiment of the present invention. FIG. 5 is a circuit diagram illustrating a configuration of the output device X1, FIG. 5 is a diagram illustrating voltage waveforms of an AC signal and a zero-cross signal in the zero-cross signal output device X1 according to the first embodiment of the present invention, and FIG. FIG. 7 is a circuit diagram illustrating a configuration of a zero-cross signal output device X2 according to an embodiment. FIG. 7 is a circuit diagram illustrating a configuration of a zero-cross signal output device X3 according to a third embodiment of the present invention.
[0010]
First, a schematic configuration of a copying machine 1 which is an example of an image forming apparatus including a zero-cross signal output device X according to an embodiment of the present invention will be described with reference to FIG.
The upper part of the copying machine 1 is a document reading unit 110. The automatic document feeder 112 provided in the document reading unit 110 automatically forms a plurality of documents set on a document set tray on the upper surface of the automatic document feeder 112 one by one on a glass plate. This is a device that feeds the original onto a document table 111.
The reading optical system of the document reading unit 110 scans an image of a document placed on the document table 111 or fed by the automatic document feeder 112 onto the document table 11 to read the image. , A first scanning unit 113, a second scanning unit 114, an optical lens 115 for forming reflected light from a document on a CCD line sensor 116, a CCD line sensor 116 as a photoelectric conversion element, and the like. It is configured. The first scanning unit 113 includes an exposure lamp unit 113a for exposing the surface of the original, a first mirror 113b for reflecting a reflected light image from the original in a predetermined direction, and the like. Further, the second scanning unit 114 includes second and third mirrors 114a and 114b for guiding the reflected light from the document reflected from the first mirror to the CCD line sensor 116.
The document image read by the document reading unit 110 is sent as image data to an image data input unit (not shown), and after the image data is subjected to predetermined image processing, the image processing The image forming unit 210 is temporarily stored in a memory of the image forming unit, and the image data in the memory is read out after the image processing is completed or in response to a predetermined output instruction from the outside to constitute an image forming unit 210 disposed below the document reading unit. Is transferred to the writing unit 227.
[0011]
The writing unit 227 includes a semiconductor laser light source (not shown) that emits a laser beam in accordance with the content of image data transferred from the image processing unit or an external device, and a polygon mirror that deflects the laser beam at an equal angular velocity. (Not shown), and comprises an f-θ lens (not shown) that corrects the laser beam deflected at a constant angular velocity on the photosensitive drum 2 so as to be deflected at a constant velocity. In the present embodiment, a laser writing unit is used as the writing unit 227, but a solid-scanning optical writing head unit using a light emitting element array such as an LED or an EL may be used. As the photosensitive drum 2, for example, a photoconductive layer such as amorphous silicon (a-Si), selenium (Se), or an organic optical semiconductor (OPC) is formed on an outer peripheral surface of a conductive substrate (metal drum) made of aluminum or the like. Is formed in the form of a thin film, but is not particularly limited.
Further, the image forming unit 210 includes a charger 223 around the photosensitive drum 2 for charging the photosensitive drum 2 to a predetermined potential, and a toner on the electrostatic latent image formed on the photosensitive drum 2. And a corona discharge type transfer device 225 (the transfer device) for transferring a toner image formed on the surface of the photosensitive drum 2 to a recording sheet (paper, an example of the material to be transferred). An example of the means), a static eliminator 229 for neutralizing the photosensitive drum 2, a cleaning device 226 for collecting excess toner on the photosensitive drum, and the like are also provided. The recording sheet on which the image has been transferred by the image forming unit 210 is then sent to the fixing unit 217, where the image is fixed on the recording sheet.
On the discharge side of the image forming unit 210, in addition to the fixing unit 217, a switchback path 221 for reversing the direction (front and rear) of the recording sheet in order to form an image again on the back surface of the recording sheet is provided. A post-processing device 260 that performs a stapling process and the like on the formed recording sheet and has a lifting tray 261 is provided. The recording sheet on which the toner image is fixed by the fixing unit 217 is guided to the post-processing device 260 by the discharge roller 219 through the switchback path 221 as necessary, where a predetermined post-processing is performed. After that, it is discharged onto the elevating tray 261.
The copier 1 supplies the recording sheet to the image forming unit 210 and communicates with the paper tray 251 and the switchback path 221 provided below the image forming unit 210 to supply the recording sheet to both sides of the recording sheet. In addition to a double-sided unit 255 for temporarily retreating recording sheets when performing image formation, a multi-stage paper feed unit 270 having a plurality of paper feed trays 252 and 253, a manual feed tray 254 protruding from the side of the copying machine 1 is provided. Is provided. The image forming apparatus further includes a conveying unit 250 that conveys the recording sheets set on each of the trays 251, 252, 253, and 254 to a transfer position of the image forming unit 210 by the transfer device 225. The duplex unit 255 can be replaced with a normal paper cassette, and the duplex unit 255 can be replaced with a normal paper cassette.
[0012]
Next, the circuit configuration of the zero-cross signal output device X provided in the copying machine 1 will be described with reference to FIG.
The zero-cross signal output device X includes a primary circuit section A on the AC power supply 301 side, and a secondary circuit section insulated from the primary circuit section A via the switching regulator 304 and the photocouplers PC1, PC2, and PC3. B.
The output of the AC power supply 301 is subjected to full-wave rectification by the full-wave rectifier circuit 303 after passing through the main switch 302 (manual switch) in the primary circuit section A, and the signal after the full-wave rectification is output to the switching regulator 304. At the same time, the voltage is made constant by the switching FET 309 and the smoothing circuit 310 and output to the DC line 311.
On the other hand, the signal via the signal output to the switching regulator 304 is smoothed by the smoothing circuits 404 and 405 in the secondary side circuit section B, and the driving system constant voltage power supply output V M , And circuit system constant voltage power supply output V CC Is generated. Drive system constant voltage power supply output V M Is supplied to a drive circuit such as a drum motor, and at the same time, is divided and input to an inversion shunt regulator SRG1. The shuntator SRG1 compares an input voltage with an internal reference voltage, and when the input voltage is high, its output is turned on. When this output is in the ON state, it is transmitted to the primary side via the photocoupler PC1, forcibly grounding the gate of the switching FET 309, and stopping the switching oscillation. When the input voltage is low, the output of the shunt regulator SRG1 is turned off, the forcible grounding of the gate of the switching FET 309 is released, the primary side performs switching oscillation, and the driving system output voltage V M Is a constant voltage. Also, the smoothed voltage V obtained from the secondary coil middle tap of the switching regulator 304 (transformer) L Is stabilized by a voltage drop type constant voltage power supply element VRG, and its output is cc Is supplied to a control circuit or the like.
The output of the AC power supply 301 is subjected to full-wave rectification by another full-wave rectification circuit 307 in the primary side circuit section A, and a signal after the full-wave rectification (hereinafter referred to as an AC signal 314) is supplied from the power supply side. The voltage is divided by a first resistance element R1 and a second resistance element R2 (voltage dividing circuit) connected in series to the ground side. The voltage dividing point 308 is connected to the input terminal of the shunt regulator (SRG2) connected to the DC line 311. When the voltage at the voltage dividing point 308 (divided voltage) becomes lower than a predetermined reference voltage, the output of the SRG2 is output. In the ON state, a current flows from the DC line 311 through the resistor and the photocoupler PC3 to the SRG2, and the photodiode 312a constituting the photocoupler PC3 emits light. The connected phototransistor 312b is turned on.
On the other hand, when the divided voltage of the AC signal 314 becomes higher than the reference voltage, the output of the SRG2 is turned off, the light emission of the photodiode 312a constituting the photocoupler PC3 stops (turns off), and the secondary side The phototransistor 312b on the circuit section B side is turned off.
As a result, the signal flowing through the SRG2 becomes a zero-cross signal (primary-side zero-cross signal 315) which becomes a low level when the AC signal 314 is lower than a predetermined voltage. Here, the full-wave rectifier circuit 307, the resistance elements R1, R2, SRG2, etc. constitute an example of the zero-cross signal output means.
[0013]
On the other hand, in the secondary side circuit section B, the constant voltage power supply output V M Is supplied to the collector of the phototransistor 312b (photocoupler PC3) via the resistor R, and the phototransistor 312b (photocoupler PC2) is turned on (that is, the AC signal 314 is divided). When the voltage at the voltage dividing point 308 is lower than the reference voltage), the secondary-side zero-cross signal FW becomes Low level, and the phototransistor 312b is turned off (the voltage at the voltage dividing point 308 is higher than the reference voltage). The secondary-side zero-cross signal FW becomes a high level.
With such a configuration, the primary-side zero-cross signal 315 is generated from the AC signal 314 that has been full-wave rectified by the rectifier circuit 307, and is isolated through the photocoupler PC2. Is output as
3A to 3D show the output signal (a) of the AC power supply 301 obtained by the zero-cross signal output device X, the AC signal 314 (b), the primary-side zero-cross signal 315 (c), FIG. 6 shows voltage waveforms of the secondary-side zero-cross signal FW (d).
[0014]
The secondary side circuit section B is provided with an input terminal for a power save signal PS. When the power save signal PS is turned on (High level), the photocoupler PC1 is turned on, and the switching oscillation of the switching FET 309 is stopped. It is forcibly stopped and enters the power save state.
Further, an input terminal of a power relay signal PR is provided in the secondary circuit section B, and when the power relay signal PR is turned on (High level), the relay coil RL is operated, thereby causing the primary circuit section A to operate. The relay contact 305 is turned off, and the AC signal 314 is stopped (Low level).
The power save signal PS and the power relay signal PR are turned on by the predetermined control circuit 500 when the copier 1 has not been operated for a predetermined time or longer and a print request from an external device has not been received. Is controlled.
The secondary circuit section B is provided with an input terminal for a heater lamp signal HL, and the control circuit 500 turns on / off the heater lamp signal HL during the printing operation of the copying apparatus 1, whereby the photocoupler is operated. When the PC 2 is operated / stopped, the fixing temperature of the heater lamp 306a such as a halogen lamp is controlled by the phase angle in the fixing temperature control circuit 306 provided in the primary circuit section A.
The control circuit 500 includes a CPU, and interrupts the CPU using the secondary-side zero-cross signal FW (performs interrupt processing) to monitor a power failure, control the power of the fixing device, and control the power frequency (50 Hz). / 60 Hz).
The push switch 401 is for the control circuit 500 to detect that a request for a copy operation has been made by a user operation.
The configuration described above is the same as the configuration of a conventional zero-cross signal output circuit provided in a general image forming apparatus.
[0015]
A feature of the zero cross signal output device X according to the present invention is that a capacitor 406 connected in parallel with a path from the collector terminal to the emitter terminal (collector to emitter of the phototransistor 312b) on the secondary side of the photocoupler PC3 is provided. It is being done.
As a result, as shown in FIG. 3E, when the secondary-side zero-cross signal FW is turned on, it instantaneously falls from a high level to a low level, and when it is turned off, the capacitor 406 operates from the low level. The rise to the High level becomes dull like a first-order lag. Therefore, as shown by a broken line in FIG. 3F, when the primary zero-cross signal 315 is switched between OFF and ON, a continuous OFF / ON switching occurs instantaneously due to noise. As shown by the solid line in FIG. 3 (f), the influence of noise on the secondary-side zero-cross signal FW also becomes dull and is suppressed below the threshold voltage for interrupt detection, so that the control circuit 500 operates normally without malfunction. Become.
Here, the threshold voltage of the interruption detection in the control circuit 500 which performs the interruption processing by using the secondary side zero cross signal FW as an input is V. th , The voltage level (High level) when the signal FW is OFF is V CC (When ON, 0 (zero) V), the time width of the noise is Tn, the capacitance of the capacitor 406 is C, and the photocoupler PC 3 Assuming that the resistance value of the resistance element 407 connected to the collector is R, noise is not detected by the control circuit 500 in a range where the following equation (1) is satisfied, and the influence of noise is removed. Malfunction of the control circuit 500 can be prevented (Ln represents a natural logarithm of low e).
C · R> -Tn / Ln (1-V th / V CC …… (1)
Therefore, for example, the threshold voltage V th = V CC In the case of / 2, by selecting the capacitor 406 and the resistance element 407 such that the following equation (2) is satisfied, malfunction of the control circuit 500 due to noise can be prevented.
C · R = Tn / 0.693 (2)
Also, unlike the prior art, there is no need to provide a time zone in which interrupts are prohibited, so that the control circuit 500 can detect the pulse width (time from ON to OFF) of the secondary-side zero-cross signal FW. is there. As a result, the influence of the phase change of the secondary-side zero-cross signal FW due to the change of the power supply voltage can be removed, and the highly accurate zero-cross signal can be detected. Here, the rise time (ON → OFF) of the secondary-side zero-cross signal FW can be estimated in advance by the resistance value of the resistance element 407 and the capacitance of the capacitor 406, so that the pulse width of the secondary-side zero-cross signal FW At the time of detection, if the rise time is taken into consideration, the pulse width can be obtained with higher accuracy.
Further, if the control circuit 500 executes the interrupt processing at the timing when the secondary-side zero-cross signal FW is turned on (High → Low), the interrupt processing is executed at an accurate timing with no delay due to the instantaneous falling signal. can do.
[0016]
【Example】
(Second invention)
Next, with reference to FIG. 4, a description will be given of a zero-cross signal output device X1 according to a first embodiment (an embodiment of the second invention) in which a configuration for further improving noise removal performance is added to the zero-cross signal output device X. I do.
The zero-cross signal output device X1 is different from the zero-cross signal output device X in that the first resistance element R1 and the second resistance element are provided in series from the power supply side to the ground side in order to divide the AC signal 314. A constant current diode 601 (an example of the constant current element) is provided between a voltage dividing point 308 of R2 and the first resistance element R1.
FIG. 5 shows the respective current waveforms of the AC signal 314 (full-wave rectified signal), the signal at the voltage dividing point 308 (voltage dividing circuit current), and the secondary zero-cross signal FW in the zero-cross signal output device X1. Represent.
As shown in FIG. 5, the current waveform of the signal at the voltage dividing point 308 is limited by the pinch-off current Ip of the constant current diode 601 due to the provision of the constant current diode 601. If this pinch-off current Ip is a current obtained by adding a margin to the current Iref flowing when the voltage at the voltage dividing point 308 becomes the reference voltage of the SRG2, it is necessary to operate (ON / OFF) the SRG2. Will be enough.
Generally, it is known that it is effective to reduce the impedance of the circuit (signal path) (here, the resistance values of the resistance elements R1 and R2) in order to prevent a malfunction due to an induced noise current in an AC signal. I have. However, when the impedance of the circuit is reduced, the flowing current increases, so that the power consumption increases.
For example, in FIG. 5, the reference voltage of SRG2 is 2.5 V, the resistance values of the first and second resistance elements R1 and R2 are 4.7 KΩ and 47 KΩ, respectively, and the timing is 11.2 degrees in each phase. When zero-cross detection is performed, the current flowing through the resistance elements R1 and R2 (voltage dividing circuit) at each phase of 11.2 degrees is 0.53 A, the peak current is 2.7 mA, and the power consumption is 0.193 W.
Here, assuming that the resistance values of the first and second resistance elements R1 and R2 are 470Ω and 4.7KΩ, respectively, which are 1/10 times the original values, while maintaining the phase angle of the zero-cross detection while taking measures against noise. The current flowing at the phase angle of 11.2 degrees is 5.3 mA, the peak current is 27 mA, and the power consumption is 1.93 W, which is ten times the original value. However, in this case, if a pinch-off current Ip of 5.3 mA is used as the constant current diode 601, the peak current flowing through the resistance elements R1 and R2 becomes 1/5 times, and the power consumption is 0.4753W. And about 1/4 times.
As described above, by making the pitch off current of the constant current element or less near the zero-cross detection timing, the impedance of the voltage dividing circuit is reduced to prevent a malfunction due to an induced noise current, and the voltage dividing circuit is controlled by the constant current element. Since the current flowing through the circuit is limited to the pinch-off current, power consumption can be suppressed.
As the constant current element, in addition to the constant current diode 601, a field effect transistor (FET) in which the drain and the gate are short-circuited, a current mirror circuit, or the like may be used.
[0017]
(Third invention)
Next, referring to FIG. 6, a description will be given of a zero-cross signal output device X2 which is a second embodiment (embodiment of the third invention) in which a configuration for further improving the noise removal performance is added to the zero-cross signal output device X. I do.
The zero-cross signal output device X1 is different from the zero-cross signal output device X in that the first and second resistance elements R1 and R2 are provided in series from the power supply side to the ground side in order to divide the AC signal 314. In addition, a third resistor R3 is provided in series on the ground side to form a voltage divider circuit with three resistors, and a connection point 602 (the voltage divider) between the second and third resistors R2 and R3 is provided. The power supply side connection point of the resistance element R3 further located on the ground side than the resistance element R2 connected from the ground side to the point 308) and the line of the primary side zero cross signal 315 are connected to the fourth resistance element R4. Are connected through a.
In FIG. 6, a very small-capacity capacitor C1 is provided between the voltage dividing point 308 and the primary side ground (GND). However, this does not particularly constitute the present invention, and is not particularly provided. Is also good.
With such a configuration, when the voltage at the voltage dividing point 308 falls below a predetermined reference voltage and the primary-side zero-cross signal is ON, the ground-side voltage dividing resistor R3 detects the zero-cross through the resistor R4. Since the signal is pulled into the ON state, the voltage dividing ratio is set to be smaller than a predetermined value ((R2 + R3) / (R1 + R2 + R3)) determined by the voltage dividing resistor. When the voltage at the voltage dividing point 308 rises above a predetermined reference voltage and the primary-side zero-crossing signal is OFF, the ground-side voltage-dividing resistor R3 is pulled up to the primary-side zero-crossing signal OFF state. Therefore, the partial pressure ratio is set to be larger than the predetermined partial pressure ratio. By switching the voltage division ratio in accordance with the output state of the zero-cross signal in this manner, a hysteresis characteristic is obtained, and malfunction due to noise can be prevented.
This effect is similarly exerted by the zero-cross signal output device X3 which is an embodiment in which the fourth resistance element R4 is replaced with a diode 603, as shown in FIG.
[0018]
【The invention's effect】
As described above, according to the first aspect, when generating and outputting a zero-cross signal based on an AC signal obtained from an AC power supply, a capacitor is provided on the secondary side of a photocoupler that outputs a secondary-side zero-cross signal. Is provided, noise is generated in the vicinity of the zero-cross detection voltage of the AC signal, whereby a malfunction in which the zero-cross signal is continuously turned on / off and unnecessary interrupt processing can be prevented can be prevented. At this time, since it is not necessary to provide a time zone in which interrupts are prohibited unlike the conventional case, it is possible to detect the pulse width of the zero-cross signal (secondary side), and the accuracy is improved without being affected by the power supply voltage change. It is possible to detect a high zero-cross signal. Furthermore, if an interrupt process is performed by the control unit at the timing when the secondary-side zero-cross signal is turned on, it is possible to execute the interrupt process at an accurate timing with no delay due to the instantaneously falling signal.
According to the second aspect of the present invention, the constant current element is provided on the power supply side of the voltage dividing point of the resistance element provided in series to divide the AC signal, so that the current consumption can be reduced even if the impedance of the resistance element is reduced. And the effect of the induced noise current on the AC signal can be suppressed.
Further, according to the third aspect, of the three or more resistive elements provided in series to divide the AC signal, the connection point of the resistive element on the ground side with respect to the voltage dividing point and the primary-side zero-cross signal Is connected via a resistance element or a diode, the zero-cross detection operation has a hysteresis characteristic, and malfunction due to noise can be prevented.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a schematic configuration of an image forming apparatus including a zero-cross signal output device X according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a configuration of a zero-cross signal output device X according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating voltage waveforms of an AC signal and a zero-cross signal in the zero-cross signal output device X according to the embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating a configuration of a zero-cross signal output device X1 according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating voltage waveforms of an AC signal and a zero-cross signal in the zero-cross signal output device X1 according to the first embodiment of the present invention.
FIG. 6 is a circuit diagram illustrating a configuration of a zero-cross signal output device X2 according to a second embodiment of the present invention.
FIG. 7 is a circuit diagram illustrating a configuration of a zero-cross signal output device X3 according to a third embodiment of the present invention.
[Explanation of symbols]
1. Image forming apparatus
2. Photoconductor drum (image carrier)
100: developing device
110 ... Image reading unit
210: Image forming unit
225 ... Transfer device
254: manual feed tray
280: Manual sheet feeding device
301 ... AC power supply
302: Main switch
303, 305: Full-wave rectifier circuit
304 Switching regulator
305… Relay contact
306: Fixing temperature control circuit
306a: heater lamp
308: partial pressure point
309 ... Switching FET
310,404,405 ... Smoothing circuit
311 ... DC line
312a ... photodiode (photocoupler)
312b: Phototransistor (photocoupler)
314 ... AC signal (full-wave rectified signal)
315: Primary zero-cross signal
406… Capacitor
407 ... resistance element
500 ... Control circuit
601 ... constant current diode (low current element)
603 ... diode

Claims (5)

交流電源から得た全波整流された交流信号に基づいて1次側ゼロクロス信号を生成するゼロクロス信号生成手段と,前記1次側ゼロクロス信号を入力しフォトカプラを介して2次側ゼロクロス信号を出力するゼロクロス信号出力手段と,を具備するゼロクロス信号出力装置において,
前記ゼロクロス信号出力手段が,前記フォトカプラの2次側におけるコレクタ端子からエミッタ端子への経路と並列に接続されたコンデンサを具備してなることを特徴とするゼロクロス信号出力装置。
Zero-cross signal generating means for generating a primary-side zero-cross signal based on a full-wave rectified AC signal obtained from an AC power supply; and inputting the primary-side zero-cross signal and outputting a secondary-side zero-cross signal via a photocoupler A zero-cross signal output device comprising:
The zero cross signal output device, wherein the zero cross signal output means includes a capacitor connected in parallel with a path from a collector terminal to an emitter terminal on the secondary side of the photocoupler.
交流電源から得た全波整流された交流信号に基づいて1次側ゼロクロス信号を生成するゼロクロス信号生成手段と,前記1次側ゼロクロス信号を入力しフォトカプラを介して2次側ゼロクロス信号を出力するゼロクロス信号出力手段と,を具備するゼロクロス信号出力装置において,
前記ゼロクロス信号生成手段が,前記交流信号を分圧するために直列に設けられた複数の抵抗素子からなる分圧回路と,該分圧回路における分圧点の電源側に設けられた定電流素子とを具備してなることを特徴とするゼロクロス信号出力装置。
Zero-cross signal generating means for generating a primary-side zero-cross signal based on a full-wave rectified AC signal obtained from an AC power supply; and inputting the primary-side zero-cross signal and outputting a secondary-side zero-cross signal via a photocoupler A zero-cross signal output device comprising:
The zero-cross signal generating means includes a voltage dividing circuit including a plurality of resistance elements provided in series to divide the AC signal, and a constant current element provided on a power supply side of a voltage dividing point in the voltage dividing circuit. A zero-cross signal output device comprising:
交流電源から得た全波整流された交流信号に基づいて1次側ゼロクロス信号を生成するゼロクロス信号生成手段と,前記1次側ゼロクロス信号を入力しフォトカプラを介して2次側ゼロクロス信号を出力するゼロクロス信号出力手段と,を具備するゼロクロス信号出力装置において,
前記ゼロクロス信号生成手段が,前記交流信号を分圧するために直列に設けられた3つ以上の抵抗素子からなる分圧回路を具備し,
前記分圧回路の分圧点に接地側から接続された前記抵抗素子よりもさらに接地側に位置する前記抵抗素子のいずれかにおける電源側の接続点と前記1次側ゼロクロス信号のラインとが抵抗素子又はダイオードを介して接続されてなることを特徴とするゼロクロス信号出力装置。
Zero-cross signal generating means for generating a primary-side zero-cross signal based on a full-wave rectified AC signal obtained from an AC power supply; and inputting the primary-side zero-cross signal and outputting a secondary-side zero-cross signal via a photocoupler A zero-cross signal output device comprising:
The zero-cross signal generating means includes a voltage dividing circuit including three or more resistive elements provided in series to divide the AC signal;
The connection point on the power supply side and the line of the primary-side zero-crossing signal in any one of the resistance elements located on the ground side more than the resistance element connected from the ground side to the voltage dividing point of the voltage divider circuit has a resistance. A zero-cross signal output device, which is connected via an element or a diode.
請求項1に記載のゼロクロス信号出力装置と,これにより出力された前記2次側ゼロクロス信号がONするタイミングを基準に割り込み処理を行う制御手段と,を具備してなることを特徴とする画像形成装置。2. An image forming apparatus comprising: the zero-cross signal output device according to claim 1; and control means for performing an interrupt process based on a timing at which the secondary-side zero-cross signal output thereby is turned on. apparatus. 請求項2又は3のいずれかに記載のゼロクロス信号出力装置と,これにより出力された前記2次側ゼロクロス信号を用いて割り込み処理を行う制御手段と,を具備してなることを特徴とする画像形成装置。4. An image, comprising: the zero-cross signal output device according to claim 2; and control means for performing interrupt processing using the secondary-side zero-cross signal output thereby. Forming equipment.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010239774A (en) * 2009-03-31 2010-10-21 Brother Ind Ltd Zero-cross detection device
CN105092948A (en) * 2015-08-25 2015-11-25 南京工程学院 High-precision alternating-current signal zero crossing detection device and method
US9405261B2 (en) 2014-08-26 2016-08-02 Samsung Electronics Co., Ltd. Method and apparatus for detecting phase of input power
CN111796140A (en) * 2020-06-30 2020-10-20 上海宏力达信息技术股份有限公司 Detection circuit for simultaneously detecting zero crossing point and stopping power recovery

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010239774A (en) * 2009-03-31 2010-10-21 Brother Ind Ltd Zero-cross detection device
US9405261B2 (en) 2014-08-26 2016-08-02 Samsung Electronics Co., Ltd. Method and apparatus for detecting phase of input power
CN105092948A (en) * 2015-08-25 2015-11-25 南京工程学院 High-precision alternating-current signal zero crossing detection device and method
CN111796140A (en) * 2020-06-30 2020-10-20 上海宏力达信息技术股份有限公司 Detection circuit for simultaneously detecting zero crossing point and stopping power recovery
CN111796140B (en) * 2020-06-30 2023-06-30 上海宏力达信息技术股份有限公司 Detection circuit for simultaneously detecting zero crossing point and stopping and restoring electricity

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