JP2004327810A - Information processor and method for manufacturing lsi chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To evaluate processing result in a process for a short time in a design stage. <P>SOLUTION: According to the hierarchical structure of a circuit function block shown by the wiring design data of an LSI chip, a two-dimensional shape information on wiring or wiring interlayer film included in the circuit function block is acquired from the wiring design data by each of layers corresponding to a photo mask (101), and a layer relating to the two-dimensional shape of wiring or the like to be processed in a process included in a process flow is corresponded to the process (102), and then the setting of dimensional change quantity of the wiring or the like in the process is received (103), and the two-dimensional shape information, a film thickness specified for the process or the like are corrected on the basis of the dimensional change quantity and the corrected data is used to calculate a three-dimensional shape information showing a three-dimensional shape of the wiring or the like (104). The feature variables of the three-dimensional shape shown by the three-dimensional shape information are output corresponding to the dimensional change quantities (105). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technique for estimating a surface shape of a thin film product before starting manufacturing based on CAD data of the thin film product and process data of the thin film product.
[0002]
[Prior art]
Conventionally, a production system described in Patent Document 1 is known as a system capable of determining a process flow before starting construction. In this production system, various simulations (process simulation, shape simulation, device simulation, and the like) are performed by inputting initial conditions of the process flow, mask information (length of a design drawing (pattern), etc.) and a recipe (processing sequence information of the apparatus). (Circuit simulation, layout simulation) are performed, and the best simulation results are obtained by feeding back the simulation results to the process flow generator. Further, in this production system, the calculation procedure and conditions of the simulation are modified based on the actual construction start result, and the process flow information is optimized.
[Patent Document 1]
JP-A-6-260380
[0003]
[Problems to be solved by the invention]
However, in the above-described conventional semiconductor production system, only an ideal recipe is set based on a simulation result, and no evaluation of process variation due to one-time process variation or repetition of construction is performed. For this reason, the accuracy of the process cannot be determined. Further, process flow information or recipes are optimized by modifying simulation conditions based on the start-up results. However, if the simulation time is longer than the start-up cycle, it is difficult to provide feedback to the process. For this reason, it is difficult to use it for the start of each run-to-run product lot.
[0004]
Therefore, an object of the present invention is to make it possible to evaluate a processing result in a process in a short time in a design stage.
[0005]
[Means for Solving the Problems]
The present invention
An information processing apparatus for analyzing a shape of each circuit functional block included in the LSI chip based on wiring design data of the LSI chip manufactured according to a process flow,
The wiring design data represents, according to the hierarchical structure of the circuit function block, the two-dimensional shape information of the wiring or wiring interlayer film included in the circuit function block, from the wiring design data for each layer corresponding to the photomask Wiring shape acquisition means to acquire;
Correlation means for associating a layer related to a two-dimensional shape of a wiring or a wiring interlayer film to be processed in a process included in the process flow with the process,
In the process, a variation amount setting means for receiving a setting of a dimensional variation amount of the wiring or the wiring interlayer film,
The two-dimensional shape information obtained by the wiring shape obtaining means and the film thickness or the engraving amount determined for the process are corrected based on the dimensional variation amount, and the wiring or the wiring interlayer film is corrected based on the corrected information. Three-dimensional means for calculating three-dimensional shape information representing the three-dimensional shape of,
Means for outputting a feature amount of the three-dimensional shape represented by the three-dimensional shape information in association with the dimensional variation amount,
An information processing apparatus characterized by having:
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0007]
First, the configuration of the system according to the present embodiment will be described. Here, a case where an LSI chip is a product to be manufactured will be described as an example.
[0008]
As shown in FIG. 2, a system according to the present embodiment includes a production system 251 for controlling production equipment and inspection equipment for products, and a production parameter determination system for supporting a user who determines production parameters used in the production system 251. 205, a network interconnecting these systems 205 and 251 is included.
[0009]
The production system 251 includes a production facility controller 241 for controlling various production facilities on a production line or a production shop, an inspection facility controller 242 for controlling various inspection facilities, and each controller 241 based on production parameters from the production parameter determination system 205. , 242, a facility group control system 212 for instructing the start of construction, a start instruction system 211 for instructing each of the controllers 241, 242 to commence a construction in response to an input from an operator, and a data totaling system for totalizing the processing contents of the manufacturing equipment and the inspection equipment. 213, and a network for interconnecting these systems 211 to 213, 241, and 242 are included. The data totaling system 213 has a storage device in which databases (a processing result database 231, an inspection result database 232, and a device management database 234) are stored. Then, the processing result data of each facility, inspection result data (such as measurement dimensions of a predetermined portion of the wafer) and equipment management data (such as the use history of the facility and equipment) are stored in the databases 231 to 233 corresponding to the respective information. .
[0010]
Here, the configuration in the case where the equipment group control system 306 is connected to each of the controllers 241 and 242 via the network is shown, but the equipment group control system 306 is connected to each of the controllers 241 and 242 via the network. If not, the worker may give an instruction to the controllers 241 and 242 to start construction to the construction start instruction system 211 while referring to the recipe.
[0011]
On the other hand, the manufacturing parameter determination system 205 includes a wiring CAD system 201 used by a designer to generate wiring design data (for example, mask data stored in a GDSII file format), and wiring design data created by the wiring CAD system 201. A wiring design database 221 to be stored, an LSI surface shape analysis system 202 for analyzing and evaluating the surface shape of the LSI, and a process simulator for simulating a post-process shape based on simulation conditions (pre-process shape) given from the LSI surface shape analysis system 202 203, a process control model setting system 204 for setting a process control model 223 based on the process parameters designated by the LSI surface shape analysis system 202, and a process set in the process control model setting system 204. And a process condition calculation system 205, for calculating the production parameters on the basis of the control model 223. When the output of the process simulator 203 is a process condition, the process condition calculation system 205 calculates a manufacturing parameter based on the output of the process simulator 203.
[0012]
As shown in FIG. 3, the LSI surface shape analysis system 202 includes an information storage unit 3226 in which various data are stored, and an arithmetic processing unit 3227 that performs analysis and evaluation processing of the surface shape of the LSI chip.
[0013]
The information storage unit 3226 stores five types of databases 3221 to 225 in which various data generated in the analysis and evaluation processing executed by the arithmetic processing unit 3227 are stored. Specifically, a circuit function block tree database 3221, a layer-process correspondence information database 3222, a two-dimensional wiring shape database 3223, a process flow / process module (dimensional information) database 3224, and a three-dimensional wiring shape database 3225 are stored. I have.
[0014]
On the other hand, the arithmetic processing unit 3227 includes the following functional components 3201 to 208.
[0015]
The circuit function block tree structure acquisition function unit 3201 extracts the hierarchical structure of the circuit function block from the wiring design data of the wiring design database 221 from the wiring design data, and outputs information representing the extraction result (circuit function block hierarchical structure information). It is stored in the circuit function block tree database 3221.
[0016]
The layer-process (process module) associating function unit 3203 assigns a process or a plurality of continuous processes (process modules) to each layer corresponding to the photomask of the wiring design data, and information (layer-process correspondence) indicating the assignment result. Attached information) is stored in the layer-process correspondence information database 3222.
[0017]
The circuit function block-specific wiring shape acquisition function 3202 extracts or specifies a circuit function block to be analyzed from the circuit function block hierarchical structure information of the circuit function block tree database 3221, and specifies a process to be analyzed. Then, the layer of the target wiring layer is acquired from the layer-process correspondence information. Further, the wiring shape of the designated layer in the target circuit function block is extracted from the wiring design data, and the extraction result (wiring shape information that is a part of the mask data) is stored in the two-dimensional wiring shape database 3223.
[0018]
The process / process module dimension setting function unit 3204 sets dimension values (wiring thickness, film thickness, etc.) defined as process specifications, and uses the set data as process flow specification information in a process flow / process module (dimension information) database. 3224.
[0019]
The dimension variation setting function unit 3205 accepts the setting of the dimension variation of each process or process module on the process flow, and stores the dimension variation information in the process flow / process module (dimension information) database 3224.
[0020]
The wiring shape three-dimensionalizing function unit 3206 obtains the wiring shape of the circuit function block to be analyzed (a part of the mask data for the specified process) from the two-dimensional wiring shape database 3223, as well as the dimensions of the specified process and the amount of variation thereof. Information is acquired from the process flow / process module (dimensional information) database 3224, and three-dimensional shape information of the wiring or the wiring interlayer film is generated based on the two-dimensional wiring shape and the dimension information in the height direction. Then, the three-dimensional shape information is stored in the three-dimensional wiring shape database 3225. Note that a plurality of three-dimensional information is generated based on the amount of dimensional change.
[0021]
The LSI surface shape analysis / evaluation function unit 3207 performs a shape feature (film thickness, step, step) based on the three-dimensional shape information of the three-dimensional wiring shape database 3225 and the process flow information of the process flow / process module (dimensional information) database 222. And the area / volume occupied by the steps) are calculated, and the variation of the shape feature amount is evaluated. Alternatively, the simulation condition (pre-process shape) is passed to the process simulator 203, and the variation of the shape feature is evaluated based on the simulation result of the process simulator 203.
[0022]
The process parameter calculation function unit 3208 includes a parameter for determining a manufacturing parameter (for example, the influence of a wiring step) based on the shape feature amount calculated by the LSI surface shape analysis / evaluation function unit 3207 or the simulation result of the process simulator 203. And the rate of received CMP and etch). The process parameters calculated at this time are passed to the process control model setting system 204 for setting the process control model 3122.
[0023]
Next, an on-LSI chip shape analysis process executed in such a system will be described with reference to FIG.
[0024]
First, the circuit function block tree structure acquisition function unit 3201 reads wiring design data from the wiring design database 221 and, based on the wiring design data, circuit function block hierarchical structure information indicating the hierarchical structure of the circuit function blocks and cells of the LSI chip. Generate Then, the circuit function block hierarchical structure information is stored in the circuit function block tree database 3221 (S101). Here, the generation of the circuit function block hierarchical structure information is specifically performed as follows.
[0025]
As shown in FIG. 4, the wiring design data has a hierarchical data structure in which the layout information of the entire chip is the top 411. Specifically, the layout information in the entire chip area is included as the data of the first hierarchy 410, and the layout information in each of the circuit function blocks 421 to 424 configuring the entire chip area is included as the data of the second hierarchy 420. It has a hierarchical structure that is expanded to include pattern information in a cell that represents an element element, which is the minimum unit, so that it is included. However, cells and circuit function blocks may be mixed in the circuit function block.
[0026]
Since the amount of wiring data (the number of wirings) of the entire wiring design data is enormous, it is difficult to make all wiring shapes three-dimensional at once. Therefore, here, a circuit function block to be analyzed is selected. For example, a circuit function block to be analyzed is selected by searching for a circuit function block in the maximum hierarchy within a range in which the number of wires in the circuit function block is equal to or less than a predetermined number. Alternatively, a search may be made for a circuit functional block that fits within a region of a predetermined area (eg, within a 1 mm section).
[0027]
Then, the circuit-function-block-specific wiring shape acquisition function unit 3202 acquires the wiring shape information in the circuit function block selected as the analysis target. Here, when the circuit function block selected as the analysis target further includes a circuit function block, the wiring shape is obtained from the lowest hierarchical cell (see FIG. 4) of each branch derived from the circuit function block selected as the analysis target. Get information. In order to extract a wiring shape by associating a process with a layer, the wiring shape needs to be acquired for each layer.
[0028]
Next, the layer-process (process module) associating function unit 3203 performs a process or a process of forming the wiring or the wiring interlayer film on the wiring design data layer related to the wiring shape or the wiring interlayer film shape on the LSI surface. The module is allocated, and layer-process association information representing the allocation result is stored in the layer-process association information database 3222. Alternatively, a process or a process module affected by the shape is allocated to a layer of wiring design data related to the wiring shape on the LSI surface or the shape of the wiring interlayer film, and layer-process correspondence information representing the allocation result is obtained. Is stored in the layer-process correspondence information database 3222 (S102). Specifically, it is as follows.
[0029]
The wirings 511 to 512 shown in FIG. 5B are formed by the following procedure using the photomask of each layer shown in FIG.
[0030]
Al is sputtered on a film serving as a base of the M1 wiring 511, and a resist pattern is formed on the AL film thus formed by photolithography using an M1 mask 501. Further, an M1 wiring 511 is formed by performing a metal etching process.
[0031]
After forming the M1 wiring, a wiring interlayer film is deposited by an oxide film CVD, and the wiring interlayer film is planarized by CMP (chemical mechanical polishing). Then, a resist pattern is formed on the wiring interlayer film by photolithography using a V1 mask 502, and a via hole is formed by performing an oxide film etching process. Furthermore, V1 plugs 512 are formed by embedding Al in the via holes by Al sputtering and etching back the Al.
[0032]
After the formation of the V1 plug, Al is sputtered, and a resist pattern is formed on the AL film thus formed by photolithography using an M2 mask 503. Further, an M2 wiring 513 is formed by performing a metal etching process.
[0033]
As described above, the layer of the M1 mask 501 relates to Al sputtering, photolithography, and metal etching, and the layer of the V1 mask 502 relates to oxide film CVD, CMP, photolithography, oxide film etching, Al sputtering, and Al etch back. However, it can be seen that the layer of the M2 mask 503 relates to Al sputtering, photolithography, and metal etching. According to this relationship, each layer is associated with a process on the process flow. As an example of the relationship between the photomask of FIG. 5B and the wirings 511 to 512 of FIG. 5A, as shown in FIG. 6, the Al sputtering 621, the resist coating 622, the metal etch 623, and the resist removal 624 are formed. The layer of the V1 mask 502 is associated with the layer of the M1 mask 501, the layer of the V1 mask 502 is associated with the oxide film CVD, the CMP, the photolithography, the oxide film etching, the Al sputtering and the Al etch back, and the M2 is associated with the Al sputtering, the photolithography and the metal etching. The layer of the mask 503 is associated.
[0034]
When associating a layer with a process module, the process from Al sputtering to metal etching is a wiring layer forming module, from oxide film CVD to CMP is a wiring interlayer film forming module, and from photolithography to oxide film etching is a via hole forming module. , From the Al sputtering to the Al etch back is defined as a plug forming module, and is associated as follows. Specifically, the M1 wiring layer forming module is associated with the M1 mask layer, the V1 wiring interlayer film forming module, the V1 via hole forming module, and the V1 plug forming module are associated with the V1 mask layer, and the M2 wiring layer forming module is associated with the M1 wiring layer forming module. What is necessary is just to correspond to the layer of the M2 mask.
[0035]
Next, the dimensional variation setting function unit 3205 receives from the engineer the setting of the variation by the process of the wiring shape or the wiring interlayer film shape to be analyzed (S103). Specifically, it is as follows.
[0036]
The wiring shape or the shape of the wiring interlayer film varies depending on the process. This will be described with reference to an example of a wiring shape formed by the above-described procedure using the photomask of FIG. FIG. 7A shows wiring design data and wiring shapes 511 to 513 when formed according to the process dimension specifications (process target dimensions) using the photomask of FIG. 5A. If excessive metal etching is performed in the process of forming the M2 wiring 513, the size 724 of the M2 wiring 513 changes as shown in FIG. 7B. Further, if excessive polishing is performed in the process of forming the V1 interlayer film (plug) 512, the thickness of the wiring interlayer film becomes thin, so that the dimension 734 of the plug shape 532 varies as shown in FIG. 7C. .
[0037]
Therefore, in order to reflect the variation of the process in the wiring design data and the dimension specification of the process, an input of the variation in the process is accepted. For example, when the shape of the M2 wiring 513 changes to become the M2 wiring 513 ′ having the shape shown in FIG. 7B, the width 811 and the length 812 of the wiring are used as shown in FIG. 821 and 822 (or the offset 823 of the offset shape 813 around the ridge line (the boundary line of the wiring)) and the variation 824 of the layout sizes 814 and 815 are specified. When the film thickness of the wiring interlayer film 512 fluctuates to become the wiring interlayer film 512 'having the film thickness shown in FIG. 7C, the dimensions determined by the process specifications as shown in FIG. A variation 841 of (thickness, height) 831 is designated. The variation may be specified as, for example, a numerical value of the variation itself (+50 nm), a ratio of the variation to the original dimension (± 10%), or the like.
[0038]
After that, the wiring shape three-dimensionalizing function unit 3206 reflects the variation amount on the two-dimensional wiring shape of the circuit function block to be analyzed and the dimension specification of the process. The variation in the two-dimensional wiring shape can be reflected by the method described in S103 by modifying the two-dimensional wiring shape. The variation in the process specification dimension is reflected in the dimension specification value when the three-dimensional structure is formed. You can add Then, based on the two-dimensional wiring shape after the variation is reflected, the process dimension specification, and the layer-process correspondence information, the wiring or the wiring interlayer film shape is made three-dimensional (S104). Specifically, by offsetting the two-dimensional wiring shape or the planar shape covering the entire area including the two-dimensional wiring shape in the height direction by a dimension determined by the process specification, the three-dimensional shape of the wiring or the wiring interlayer film is reduced. obtain. For example, as shown in FIG. 9A, the three-dimensional shape of the Al film formed by the Al sputtering 911 is such that the upper surface of the oxide film has a thickness 912 of the Al film with respect to a plane including the upper surface of the oxide film. By offsetting by a dimension corresponding to Further, as shown in FIG. 9B, the three-dimensional shape of the wiring formed by the Al sputtering to the metal etching 921 is obtained by offsetting the two-dimensional wiring shape by a dimension corresponding to the Al film thickness 922. can get. As shown in FIG. 9C, the three-dimensional shape of the oxide film formed by the oxide film CVD 931 is obtained by changing the two-dimensional wiring shape to the dimension corresponding to the thickness 933 of Al and the thickness 932 of the oxide film. This is obtained by offsetting the negative region of the two-dimensional wiring shape by the dimension corresponding to the thickness 932 of the oxide film. As shown in FIG. 9D, the three-dimensional shape of the oxide film polished by the oxide film polishing 941 is such that the planar region including the upper surface of the wiring-shaped base film (oxide film) is polished to the polished oxide film. Is obtained by offsetting by a dimension corresponding to the film thickness 942.
[0039]
Then, the LSI surface shape analysis / evaluation function unit 3207 outputs the three-dimensional shape of the wiring or the wiring interlayer film for each variation of the designated circuit function block. Based on this, the engineer can compare and evaluate the variation of the three-dimensional shape with respect to the variation (S105). Note that a comparative evaluation may be performed between a plurality of circuit function blocks.
[0040]
The evaluation items for the evaluation performed here include the film thickness, the step, the distribution of the step (film thickness), the area and the volume of the step, and the like. The comparative evaluation of the area of the step portion and the volume of the step portion is performed, for example, in order to evaluate the variation in the polishing amount of the step portion in CMP, the variation amount of the wiring step in metal etching, and the like. Further, the comparative evaluation of the film thickness, the step, and the step distribution is performed, for example, in order to evaluate the influence of a change in each process on the wiring shape when a plurality of processes are performed to form one wiring. In addition, the evaluation performed on the film thickness and the like among a plurality of circuit function blocks is based on a case where a certain circuit function block is covered with a resist mask and there is a part that is not actually processed. Perform to evaluate.
[0041]
With reference to FIGS. 10, 11 and 12, the above-described LSI chip shape analysis processing will be further described with a specific example.
[0042]
FIG. 10 shows the data structure of the wiring design data.
[0043]
The wiring design data is managed for each LSI chip. Therefore, a wiring shape information design name 1012 is set in the wiring design data. In the wiring design data, wiring shape information is defined for each cell or circuit functional block. The wiring shape information of each cell or each circuit functional block includes definition information of a shape associated with a layer, and reference information for a cell or a circuit functional block included therein.
[0044]
The shape definition information includes, as information for defining the shape, contour (point sequence) data representing a boundary of the shape. In FIG. 10, the shape definition information corresponding to the circuit function block name “FF003” 1021 includes the boundaries 1023 and 1025 of layer 1, the boundary 1024 of layer 3, the circuit function block CMOS01 “1026”, and the like.
[0045]
FIG. 11A shows a tree structure represented by the shape included in the circuit function block “FF003” and the reference information to the circuit function block CMOS01. One level below the circuit function block “FF003” 1101 includes boundary shapes 1102, 1103, and 1104 and a circuit function block “CMOS01” 1105 at the end of the tree structure. One level lower than the circuit function block “CMOS01” 1105 includes boundary shapes 1106 and 1107. By converting the position and orientation of the shape based on such a tree structure, it is possible to acquire the wiring shapes all included in the circuit function block. FIG. 11B shows an example of a wiring shape acquired based on such a tree structure. Layer 1 and layer 2 represent wiring shapes of different wiring layers. The FF003 area includes the CMOS01 area. The CMOS01 wiring 1131 and the FF003 wiring 1132 are connected.
[0046]
Thus, a wiring shape serving as mask data is generated. Further, in order to treat the image as three-dimensional, three-dimensionalization is performed based on dimensional information included in the process flow. Hereinafter, a specific example of three-dimensionalization will be described. According to the process flow of FIG. 12A, a wiring layer and a wiring interlayer film are formed in the order of AL sputter 1201, photo 1202, metal etch 1203, CVD 1204, and CMP 1205. The dimension information of each process includes one of the predetermined dimensions 1211, 1215, and 1216 and the accuracy 1212, 1213, and 1214 that must be compensated for by the device or the process phenomenon. Based on this dimensional information, three-dimensionalization is performed by the three-dimensionalization method described above (see FIG. 9). According to the dimensional information 1211, 1212, 1213, 1214, 1215, 1216 included in the process flow, the AL film thickness 1231, the wiring position ± error 1232 determined by the photo process, the wiring dimension ± error determined by the photo process and the metal etch process. With 1233 and 1234, each dimension of the wiring 1221 can be set. The post-CMP oxide film thickness (interlayer wiring film) 1235 can be set by the oxide film thickness 1216 defined in the CMP 1205 step.
[0047]
By making it three-dimensional in this way, it is possible to obtain a three-dimensional wiring shape or a wiring interlayer film shape of an LSI (circuit function block) after the process processing. As a state, a shape after the process processing can be generated by performing a simulation with a process simulator. Commercially available process simulators perform simulation by setting thickness information (thickness etc.) for two-dimensional wiring shapes and giving process conditions. Can be obtained for each coordinate. For this reason, the simulation can be efficiently performed for each circuit function block.
[0048]
Then, the process parameter calculation function 3208 uses the shape feature amounts (area and volume, etc.) calculated in S105 or the simulation results (processed shape) of the process simulator 3102 to determine the process parameters used to determine the manufacturing parameters. Is calculated, the process control model setting system 204 sets the process parameters in the process control model 3122, and the process condition calculation system 205 calculates the manufacturing parameters using the process control model 3122. Hereinafter, a specific example of a process parameter determination method when CMP is an analysis target will be described.
[0049]
The object to be polished by CMP is an LSI surface in which Al sputtering, metal etching, and oxide film CVD are performed on the oxide film surface. Then, the three-dimensional shape information of the LSI surface is obtained by the three-dimensional method described above. From this three-dimensional shape information, a height distribution 1301 before polishing, a density distribution (distribution of a step portion) 1302 before polishing, and a cross-sectional shape 1303 before polishing are obtained as shown in FIG. The purpose of the CMP is to planarize the inside of the LSI chip by polishing until the film thickness before polishing (initial uneven surface state) 1304 reaches a target film thickness (film thickness after polishing) 1305. In an actual manufacturing site, the process is controlled using the thickness after polishing as a control value, and therefore, a fluctuation analysis of the thickness after polishing is required.
[0050]
When a simulation is performed, a polishing rate 1313 serving as a reference, which is determined by a polishing pressure 1311, a pad hardness 1312, such conditions and a chemical action such as a slurry composition, is set in the process simulator 203 as simulation conditions. . Then, a simulation is performed on the LSI surface shape before polishing until a predetermined polishing time elapses or a predetermined post-polishing film thickness is obtained. As a result, a height distribution 1321 after polishing, a density distribution 1322 after polishing, and a cross-sectional shape 1323 after polishing are obtained as simulation results.
[0051]
From the film thicknesses 1304 and 1324 before and after polishing shown in FIG. 13A, the polishing rate 1332 at each position on the LSI surface as shown in FIG. 13B can be obtained by the following equation (1).
[0052]
Polishing rate = (Film thickness before polishing−Film thickness after polishing) ÷ Polishing time (1)
This makes it possible to determine the polishing rate of the LSI chip, which is affected by the unevenness formed on the surface of the wiring interlayer film due to the wiring shape of each circuit functional block. Then, from the polishing rate determined at this time, a polishing time (manufacturing parameter) at the time of commencement of the lot of each type of LSI can be obtained by the following equation (2).
[0053]
Polishing time = (Film thickness before polishing-Target film thickness after polishing) / Polishing rate ... (2)
Next, a run-to-run construction method, that is, a method of manufacturing a workpiece using the system of FIG. 1 will be described with reference to FIG. Here, it is assumed that the layer-process correspondence information database and the process flow / process module (size information) database 3224 already store the layer-process correspondence information and the process flow specification information, respectively. .
[0054]
The LSI surface shape analysis system 202 receives designation of a layer related to a pre-process shape to be processed (S1401).
[0055]
The wiring design data of the LSI to be analyzed is read from the wiring design database 211, and circuit function block hierarchical structure information representing the hierarchical structure of the blocks and cells of the variable chip in the LSI chip is generated from the wiring design data. The two-dimensional layout information and the two-dimensional wiring shape information of the element / wiring in the specified layer are obtained for the entire chip or for each circuit functional block (S1402). Note that the above-described method may be used to obtain the wiring shape.
[0056]
Thereafter, the LSI surface shape analysis system 202 determines the width and length of the two-dimensional wiring shape, the offset around the ridge line, and the like based on the size of the shape of the wiring or wiring interlayer film formed in the process before the target process. The thickness and the step depth determined by the process are set (S1403). The setting at this time may be performed according to the above-described variation amount setting method. However, here, the purpose is not to perform the fluctuation analysis by setting the fluctuation amount a plurality of times, but to set the dimension value for obtaining the process conditions. The original value (default) of the dimension setting may be determined by referring to the process / process module (dimension information) 3224.
[0057]
Then, the process simulator executes a simulation using the three-dimensional shape generated for the entire chip or for each circuit function block as a simulation condition, and the LSI surface shape analysis system 202 calculates a polishing rate based on the simulation result (S1405). Note that the polishing rate may be determined according to the above-described process parameter calculation method or the like.
[0058]
Then, the LSI surface shape analysis system 202 determines an initial condition or a process control model 223 for calculating a manufacturing parameter using the polishing rate (S1406). For example, when the average in the LSI chip of the polishing rate (the polishing rate obtained from the simulation result of the simulator) 1331 shown in FIG. 13 is used as the initial condition, the polishing time of the LSI lot start is set as the following process control model. Can be defined.
[0059]
Polishing rate [0] = Polishing rate of simulation result ... (3)
Polishing time [i] = (Film thickness before polishing [i] −Target film thickness after polishing) ÷ Polishing rate [i−1] (4)
Polishing rate [i] = (film thickness before polishing [i] −film thickness after polishing [i]) ÷ polishing time [i] (5)
Or
Polishing rate [I] = Polishing rate [I-1]
− (Film thickness after polishing [I] −Target value of film thickness after polishing) ÷ Polishing time [I] (6)
The suffix “0” indicates an initial condition, and the suffix “1” indicates a lot to be started first (starting). Since the film thickness before polishing can be measured before polishing, it is used as a parameter when calculating the polishing time.
[0060]
The process condition calculation system 205 determines the manufacturing parameters based on the measured values of the shape before the process, the dimensions of the target shape, and the state values of the apparatus based on the initial conditions or the process control model determined in S1406. After the contents are confirmed by the engineer, the equipment group control system 212 starts construction using the manufacturing parameters obtained at this time (S1407). The construction method at this time is as follows.
[0061]
The process initial conditions 1512 and the process control model 221 are determined by S1406, and the initial conditions 1512 and the process control model 221 are read into the process condition calculation system 205. At the start of the first (initial) product lot 1521, first, the film thickness before polishing [1] is measured, and the polishing time [1] is calculated assuming that i = 1 in Expression (4). Then, the polishing is started by the polishing apparatus 1503 using the polishing time [1]. Since the reference polishing rate, which is a condition of the simulation, differs according to the state value of the apparatus, if the reference polishing rate is prepared at a plurality of levels, and the initial conditions are prepared for each, the polishing rate of the apparatus is An appropriate initial condition can be obtained according to the state value of.
[0062]
Then, the products of the second lot 1522 and subsequent products are continuously started as follows. That is, based on the difference between the measured value of the dimension of the shape after construction and the dimension of the target shape, the process condition or the process control model of the LSI is updated, and the production parameters of the next construction lot are newly determined. Then, the construction is repeated using the new manufacturing parameters (S1408). Specifically, in FIG. 15, first, after the start of the first lot 1521, the post-polishing film thickness [1] is measured, and the polishing rate [1] of the LSI is calculated using Expression (5) or Expression (6). I do. Expression (6) is an example of an expression for updating a process condition in accordance with a difference between a target value of a film thickness after polishing and a target value. Then, at the time of the start of the second lot 1521, the thickness before polishing [2] of the second lot 1521 is measured, and the polishing time [2] of the LSI is calculated by the equation (4). Then, the second lot 1521 is started using the polishing time. For the subsequent lots as well, the polishing time is determined by the same processing, and the construction is started according to the polishing time.
[0063]
When a lot is started (manufacturing, inspection), the database data totaling system 213 corrects the manufacturing parameters used for the subsequent lot starting, so that the processing contents include processing result data and inspection result data. Then, it is stored in the databases 231, 232, and 234 as device management data.
[0064]
According to the processing described above, the wiring design data has a huge amount of data. However, when the wiring design data and dimensional information determined as the process specifications are correlated with each process in the process flow, the circuit function block is used. In order to separately obtain element / wiring shapes, manufacturability of shapes requiring analysis can be evaluated in a short time in a partial circuit design stage. For example, in the wiring design of an LSI chip, a circuit function block is configured from the bottom up by combining cells. However, according to the processing according to the present embodiment, the design department in the stage of designing each circuit function block Manufacturability can be confirmed.
[0065]
In addition, by integrating the variation in the dimensions of the wiring and the film determined by each process in the process flow in the process module, the variation in the three-dimensional shape in the process module can be easily specified. The fluctuation of the processing result constituted by the above can be collectively evaluated.
[0066]
In addition, since the manufacturing parameters can be obtained using the wiring design data, it is possible to eliminate the need for an experiment for determining the conditions of various LSI chips having different wiring shapes.
[0067]
By the way, since the wiring design data handled by the design department is enormous in size, the terminal of the manufacturing department obtains the wiring design data from the computer of the design department and processes it when starting the construction of all products. It may not be appropriate for manufacturing departments with limited resources. When the design department and the manufacturing department are independent companies such as a fabless company and a foundry, the design department sometimes wants to avoid leakage of design data, which is a design asset, to the outside.
[0068]
Therefore, the terminal of the manufacturing department requests the computer system of the design department to execute the above-described process simulation, and the execution result (process conditions required for the start of construction) is returned from the host computer of the design department to the terminal of the manufacturing department. You may. Hereinafter, such a mode of processing will be described.
[0069]
FIG. 16 shows a configuration of a network system suitable for a processing mode in which the terminal of the manufacturing department requests the computer system of the design department to execute the above-described process simulation.
[0070]
In the design section 1601, the above-described wiring CAD system 201, LSI surface shape analysis system 202 ′, and the above-described process simulator 203 are installed. These systems are interconnected by a network.
[0071]
On the other hand, the manufacturing section 1602 includes the above-described process control model setting system 204, the above-described process condition calculation system 205, the above-described data totaling system (here, an online start analysis system such as an SPC (Statistical Process Control)) 213, A process specification management system 1625 that manages the flow and the dimensional specification of each process is installed. These systems are interconnected by a network. Further, the manufacturing section 1602 includes manufacturing equipment (not shown) for manufacturing a product, inspection equipment (not shown) for inspecting the product, a controller (not shown) for controlling the manufacturing equipment and the inspection equipment, and the above-described equipment group. A control system 212 is also provided.
[0072]
The network of the manufacturing department 1602 and the network of the design department 1602 are connected to each other via a network 1603 such as the Internet. In such a network system, each of the systems 1611 to 1613 of the design department 1601 and each of the systems 1621 to 1625 of the manufacturing department 1602 have the following functions.
[0073]
The wiring CAD system 201 and the LSI surface shape analysis system 202 ′ provide the wiring section information 1631, the layer information 1632, and the circuit function block information 1633 to the manufacturing section 1602.
[0074]
The process simulator 203 provides a simulation condition 1634 and a simulation result 1635 relating to the process condition to the manufacturing section 1602. However, the simulation conditions pertaining to the process conditions are determined by instructions from the manufacturing section 1602.
[0075]
The process control model setting system 204, the process condition calculation system 205, and the start analysis system 213 provide the process section management information 1641, the device processing result information 1642, the inspection result information 1643, and the maintenance information 1644 to the design department 1601.
[0076]
The process specification management system 1625 performs the same processing as the circuit function block tree structure acquisition function unit 3201 and the layer-process (process module) association function unit 3203 in FIG. 3, and the process-layer association information 1645 obtained as a result. And the process-circuit functional block association information 1646 is exchanged with the design department 1601.
[0077]
Since the systems 1611 to 1613 of the design department 1601 and the systems 1621 to 1625 of the manufacturing department 1602 have such functions, a large amount of wiring design data may be exchanged between the design department and the manufacturing department. Disappears. For example, data related to wiring is exchanged in the form of a circuit function block name, layer configuration, specific cell and circuit function block, and enormous construction result data accumulated in the manufacturing section 1603 is exchanged for a totaled result. . Further, it is not necessary for the manufacturing section 1602 to process a huge amount of wiring design data.
[0078]
Next, a procedure in which the manufacturing department starts to manufacture an LSI chip using the system of FIG. 16 will be described with reference to FIG. The content of the processing executed by each computer is the same as the above-described processing (S1401 to S1407 in FIG. 14).
[0079]
At a terminal of a manufacturing department (a construction start terminal or a terminal used by an engineer), a layer to be processed in each process constituting a manufacturing process of an LSI chip to be manufactured (hereinafter referred to as a manufacturing target) is specified for wiring design data. (S1701), the computer (host computer) of the design department obtains the hierarchical structure of the circuit function blocks and cells to be manufactured, and based on the obtained information, determines the two-dimensional wiring shape of the designated layer by the terminal of the manufacturing department. It is acquired (S1702).
[0080]
Further, the process dimension caused by the process is checked on the terminal of the manufacturing section based on the dimension specification, and if a change is necessary, the dimension of the wiring shape is set (S1703).
[0081]
The host computer three-dimensionalizes the shape before performing the process (S1704) and performs a process simulation (S1705).
[0082]
At the terminal of the manufacturing department, the engineer checks the rate calculated from the simulation result, and determines an initial condition or a process control model for calculating a manufacturing parameter (S1706). The terminal of the manufacturing section determines the manufacturing parameters based on the initial conditions of the process or the process control model (S1707). Thereafter, in the manufacturing section, LSI chip manufacturing is started using the manufacturing parameters.
[0083]
According to such processing, the terminal of the manufacturing department can specify the layer of the wiring design data to be associated with the process information or the process, so that the high-speed host computer of the design department that performs the processing such as the design rule design and the wiring design can be provided. Calculation processing (wiring design data acquisition, simulation, etc.) is executed, and the simulation result is acquired. For this reason, the manufacturing department can easily acquire only necessary evaluation result data without handling a huge amount of wiring design data. Further, since it is not necessary to transmit and receive a huge amount of design data, conditions can be set in a short time. Further, the design department does not need to disclose design assets to the outside.
In addition, a pre-processing shape of the process to be started is generated, a process simulation is performed based on the shape, manufacturing parameters are obtained from the simulation results, the product is started, and the manufacturing parameters are corrected based on the process control model from the processing results. By doing so, it is not necessary to perform a condition setting experiment for determining a manufacturing parameter. In addition, by compensating for fluctuations caused by the apparatus in continuous start-up with Run-to-Run, stable continuous start-up is realized, so that occurrence of defects can be prevented.
[0084]
【The invention's effect】
According to the present invention, in the design stage, the processing result in the process can be evaluated in a short time.
[Brief description of the drawings]
FIG. 1 is a flowchart of an on-LSI chip shape analysis process according to an embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of a system according to the first embodiment of the present invention.
FIG. 3 is a schematic configuration diagram of the LSI surface shape analysis system of FIG. 2;
FIG. 4 is a diagram for explaining a data structure of wiring design data.
FIG. 5 is a diagram for explaining the correspondence between layers of wiring design data and processes.
FIG. 6 is a diagram for explaining a method of assigning each process of a process flow to a layer of wiring design data.
FIG. 7 is a diagram for explaining a change that occurs in a three-dimensional shape of a wiring or a wiring interlayer film due to a change in a process.
FIG. 8 is a diagram for explaining a method of reflecting variations in wiring design data and process dimension specifications.
FIG. 9 is a diagram for explaining a method of three-dimensionalizing a wiring shape or a wiring interlayer film shape.
FIG. 10 is a diagram conceptually showing a data structure of wiring design data.
11A is a diagram illustrating a tree representing a hierarchical structure of circuit function blocks, and FIG. 11B is a diagram illustrating a wiring shape.
12A is a diagram conceptually showing a data structure of process flow information, and FIG. 12B is a diagram in which dimensions are given to a three-dimensional shape between wirings or wiring layers.
FIG. 13 is a diagram for explaining a process parameter determination method when CMP is an analysis target.
FIG. 14 is a flowchart of an on-LSI chip shape analysis process and a run-to-run construction process according to the embodiment of the present invention.
FIG. 15 is a diagram for describing a run-to-run construction method.
FIG. 16 is a configuration diagram of a system according to a second embodiment of the present invention.
FIG. 17 is a flowchart of an on-LSI chip shape analysis process executed in the system of FIG. 16;
[Explanation of symbols]
201: Wiring CAD system 202: LSI surface shape analysis system, 203: Process simulator 204: Process control model setting system 205: Process condition calculation system 211: Start instruction system 212: Facility group control system 213: Data aggregation system 222: Process flow / Process module (dimension information) database 223 ... Process control model 241 ... Manufacturing equipment controller 242 ... Inspection equipment controller 3201 ... Circuit function block tree structure acquisition function part 3202 ... Wiring shape acquisition function part for each circuit function block 3203 ... Layer-process (Process module) Correlation function unit 3204: Process-process module (dimension information) setting function unit 3205: Dimension variation amount setting function unit 3206: Three-dimensional wiring shape Functional unit 3207 ... LSI surface shape analysis and evaluation function unit 3208 ... process parameter calculating function unit 3221 ... circuit function block tree database 1625 ... process specification management system

Claims (6)

An information processing apparatus for analyzing a shape of each circuit functional block included in the LSI chip based on wiring design data of the LSI chip manufactured according to a process flow,
The wiring design data represents, according to the hierarchical structure of the circuit function block, the two-dimensional shape information of the wiring or wiring interlayer film included in the circuit function block, from the wiring design data for each layer corresponding to the photomask Wiring shape acquisition means to acquire;
Correlation means for associating a layer related to a two-dimensional shape of a wiring or a wiring interlayer film to be processed in a process included in the process flow with the process,
In the process, a variation amount setting means for receiving a setting of a dimensional variation amount of the wiring or the wiring interlayer film,
The two-dimensional shape information obtained by the wiring shape obtaining means and the film thickness or the engraving amount determined for the process are corrected based on the dimensional variation amount, and the wiring or the wiring interlayer film is corrected based on the corrected information. Three-dimensional means for calculating three-dimensional shape information representing the three-dimensional shape of,
Means for outputting a feature amount of the three-dimensional shape represented by the three-dimensional shape information in association with the dimensional variation amount,
An information processing apparatus comprising: The information processing device according to claim 1,
The three-dimensionalizing means,
Information representing a shape corresponding to the two-dimensional shape at a position apart from the two-dimensional shape represented by the corrected two-dimensional shape information by an interval corresponding to the corrected film thickness or the corrected engraving amount. An information processing apparatus, wherein the three-dimensional shape information is calculated based on the information. A shape analysis method for analyzing a shape of each circuit functional block included in the LSI chip by an information processing device based on design data of a workpiece manufactured according to a process flow,
The information processing device,
Input receiving means;
Arithmetic means;
Has,
The shape analysis method,
The arithmetic means, according to the hierarchical design of the circuit function block, represented by the wiring design data, converts the two-dimensional shape information of the wiring or wiring interlayer film included in the circuit function block into layers associated with a photomask. Processing to obtain from the wiring design data;
A process in which the arithmetic unit associates a layer related to a two-dimensional shape of a wiring or a wiring interlayer film to be processed in a process included in the process flow with a process corresponding to the process;
The input means, in the process, a process of accepting the setting of the dimensional variation of the wiring or the wiring interlayer film,
The arithmetic means corrects the two-dimensional shape information and the film thickness or the engraving amount determined for the process based on the dimensional variation amount, and based on the corrected information, determines the tertiary of the wiring or the wiring interlayer film. A process of calculating three-dimensional shape information representing the original shape, and outputting a feature amount of the three-dimensional shape represented by the three-dimensional shape information in association with the dimensional variation amount;
A shape analysis method comprising: The shape analysis method according to claim 1,
The calculating means includes:
Information representing a shape corresponding to the two-dimensional shape at a position apart from the two-dimensional shape represented by the corrected two-dimensional shape information by an interval corresponding to the corrected film thickness or the corrected engraving amount. A shape analysis method, wherein the three-dimensional shape information is calculated based on the following. An LSI chip manufacturing method for manufacturing an LSI chip by controlling a manufacturing apparatus using manufacturing parameters calculated by an information processing system,
The information processing system,
Input receiving means;
Arithmetic means;
Has,
The manufacturing method is
A process in which the input receiving unit receives designation of a layer related to the formation of the first pre-process shape to be subjected to the first process in the wiring design data of the LSI chip;
The arithmetic means acquires two-dimensional shape information of a wiring or a wiring interlayer film included in the circuit function block in the LSI chip according to the hierarchical structure of the circuit function block in the LSI chip for the specified layer. Processing,
In the second process before the first process, the input receiving unit receives the setting of the dimensional variation amount of the wiring or the wiring interlayer film, and the arithmetic unit performs the two-dimensional shape information and the second process. The determined film thickness or the engraved amount is corrected based on the dimensional variation amount, and based on the corrected information, three-dimensional shape information representing the three-dimensional shape of the wiring or the wiring interlayer film before the first process is calculated. Processing,
The calculation means simulates three-dimensional shape information representing a three-dimensional shape of the wiring or the wiring interlayer film after the first process from the three-dimensional shape information, and calculates the manufacturing parameter based on the simulation result. A process of generating the process control model, and calculating the manufacturing parameters based on the process control model, the measured dimensions of the shape before construction, the dimensions of the target shape, and the state values of the manufacturing apparatus,
A process for starting the manufacture of the LSI chip using the manufacturing parameters, wherein the calculating means updates the process control model based on a difference between a measured size of the shape after the start and a size of the target shape;
The arithmetic unit updates the manufacturing parameter based on the updated process control model, a difference between a dimension measurement value of the shape after construction and a dimension of the target shape, and a value correlated with the manufacturing parameter. Processing,
A process of repeating the start process and the update process,
A method of manufacturing an LSI chip, comprising: A method of manufacturing a workpiece using wiring design data,
The host computer and terminal are connected via a network,
The manufacturing method is
A process in which the terminal receives designation of a layer related to formation of a first pre-process shape to be subjected to a first process in wiring design data of an LSI chip;
The host computer, according to the hierarchical structure of the circuit function blocks in the LSI chip, stores the two-dimensional shape information of the wiring or the wiring interlayer film included in the circuit function blocks in the LSI chip for the layer specified in the terminal. Processing to obtain,
From an engineer, the terminal, in a second process before the first process, a process of receiving the setting of the amount of dimensional variation of the wiring or the wiring interlayer film,
The host computer, the two-dimensional shape information, the film thickness or the amount of engraving determined for the second process, based on the amount of dimensional variation set in the terminal, based on the information after the correction, A process of calculating three-dimensional shape information representing the three-dimensional shape of the wiring or the wiring interlayer film before the first process;
The host computer, from the three-dimensional shape information, a process of simulating three-dimensional shape information representing the three-dimensional shape of the wiring or wiring interlayer film after the first process,
An engineer checks a simulation result of the host computer at the terminal, determines a process control model for calculating the manufacturing parameter based on the simulation result, and the terminal determines the process control model and the shape before the start of construction. A process of calculating the manufacturing parameters based on the measured size of the target shape and the state value of the manufacturing apparatus,
A process of starting the manufacture of the LSI chip using the manufacturing parameters, wherein the terminal updates the process control model based on a difference between a measured size of the shape after the start and a size of the target shape;
An update process in which the terminal updates the production parameter based on the updated process control model, a difference between a dimension measurement value of the shape after the start of construction and a dimension of the target shape, and a value correlated with the production parameter. When,
A process of repeating the start process and the update process,
A method for producing a workpiece, comprising:

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