JP2004327804A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory having interchangeability with a CMOS (complementary metal oxide semiconductor) process, low consumption energy, high writing efficiency, high data storing capability and a high integration degree. <P>SOLUTION: This semiconductor memory is provided with a P type substrate 1000, an N type well 110 formed in the P type substrate 1000, a PMOS (p-channel MOS) selection transistor 101 including a selection gate 301, a first P<SP>+</SP>source doping area 201 and a first P<SP>+</SP>drain doping area 202, which is formed on the N type well 110 and a PMOS floating gate transistor 102 including a P<SP>+</SP>doping floating gate 302, a second P<SP>+</SP>source doping area 202 and a second P<SP>+</SP>drain doping area 203, which is formed on the N type well 110, and serially connected to the PMOS selection transistor 101. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly, to a single-layer polycrystalline nonvolatile memory.
[0002]
[Prior art]
Non-volatile memory is a device that is already required in many information, communication and consumer electronics products, with the advantage of keeping the data in the memory even when the power is turned off. As the demand for mobile electronic products such as personal digital assistants and mobile phones has increased, so has the demand for embedded chips and system-on-chips with erasable programmable read only memory, flash memory and logic circuits. Therefore, the erasable programmable read only memory is compatible with the CMOS process, and is developed in the direction of low power consumption, high writing rate, low cost, high data holding capacity, and high integration. It will meet product requirements. Above all, as for the data retention capability of the nonvolatile memory, as the size of the device becomes smaller, the thickness of the oxide film of the floating gate also becomes smaller, and carriers (for example, holes or E) are easily lost.
[0003]
FIG. 1 is a sectional view of a single-layer polycrystalline silicon memory cell 10 according to the prior art. As shown in FIG. 1, a single-layer polycrystalline silicon memory cell 10 according to the prior art includes an NMOS structure 28 and a PMOS structure 30, both of which are separated via an insulating oxide film 24. The NMOS structure 28 is formed on the P-type substrate 12 and includes a first floating gate 32, an N ⁺ source doping region 14, and an N ⁺ drain doping region 16. The PMOS structure 30 is formed on the N-type well 18 and includes a second floating gate 34, a P ⁺ source doping region 20, and a P ⁺ drain doping region 22. In addition, a high concentration N-type channel stop region 38 is implanted on one side adjacent to the P ⁺ source doping region 20, and the N-type channel stop region 38 is provided below the second floating gate 34. The first floating gate 32 and the second floating gate 34 are connected to each other via a floating gate conductive line 36, thereby maintaining the first floating gate 32 and the second floating gate 34 at the same potential. When the first floating gate 32 generates a potential corresponding to the voltage of the control gate, the second floating gate 34 becomes the same potential as the first floating gate 32 due to the connection with the floating gate conductor 36, and the P ⁺ source The electrons are bound into the second floating gate 34 by attracting accelerated electrons resulting from passing through the depletion layer of the doping region 20 and the N-type channel stop region 38.
[0004]
The conventional single-layer polycrystalline silicon memory cell 10 has the following disadvantages. First, the single-layer polycrystalline silicon memory cell 10 according to the prior art includes a PMOS transistor 30 and an NMOS transistor 28, and has a large unit area of a chip. Next, the single-layer polycrystalline silicon memory cell 10 according to the prior art requires an N-type channel stop region 38. Furthermore, the single-layer polycrystalline silicon memory cell 10 according to the prior art requires that the first floating gate 32 and the second floating gate 34 be electrically connected by the floating gate conductor 36. In addition, it is necessary to isolate the NMOS transistor 28 and the PMOS transistor 30 by the field oxide layer 24. As can be seen from the foregoing, prior art single-layer polycrystalline silicon memory cells 10 increase manufacturing costs and manufacturing difficulties and further improve due to the large area of the chip and the complexity of the structure. It is necessary.
[0005]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device which is compatible with a CMOS process and has low energy consumption, high writing efficiency, high data holding capability, and high integration.
[0006]
[Means for Solving the Problems]
The inventor of the present invention has conducted intensive studies in view of the drawbacks of the prior art, and as a result, has found that a P-type substrate, an N-type well provided in the P-type substrate, and a selection gate for applying a word line voltage. A PMOS selection transistor including a first P ⁺ source doping region for applying a source line voltage, a first P ⁺ drain doping region, and formed on the N-type well; a P ⁺ -doped floating gate; a second P ⁺ source doping region electrically connected to the first P ⁺ drain doping region, and a second P ⁺ drain doping region for applying a bit line voltage, and said second P ⁺ source doping region the second P ⁺ drain doping region defining a floating gate P-type channel, is formed on the N-type well, the PMOS election It focuses on the point that can solve the problems by a structure comprising a PMOS floating gate transistor being serially connected to the transistor, and completed the present invention based on this finding.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 2 is a cross-sectional view of the electrically programmable logic device 100 according to the present invention, and FIG. 3 is a plan view of the electrically programmable logic device 100 of FIG. 2 and 3, the electrically programmable logic device 100 includes a PMOS transistor 101 and a PMOS transistor 102 connected in series to the PMOS transistor 101 via a shared P ⁺ doping region 202. A PMOS transistor 101 and a PMOS transistor 102 are formed on the N-type well 110. An N-type well 110 is formed on a P-type semiconductor substrate 1000. The PMOS transistor 101 includes a select gate 301, a P ⁺ source doping region 201, and a P ⁺ doping region 202 shared with the PMOS transistor 102. The PMOS transistor 102 is a floating gate transistor and includes a P ⁺ -doped polysilicon floating gate 302, a P ⁺ drain doping region 203, and a P ⁺ doping region 202 shared with the PMOS transistor 101. The P ⁺ doping region 202 is simultaneously used as the drain of the PMOS transistor 101 and the source of the PMOS transistor 102, thereby forming two transistors in series. The P ⁺ -doped polysilicon floating gate 302 of the present invention is formed from single-layer polysilicon and has no or need for a control gate thereon.
[0008]
As shown in FIG. 2, the PMOS transistor 101 further includes a gate oxide film 301a provided below the select gate 301, and the PMOS transistor 102 further includes a floating gate oxide film 302a provided below the floating gate 302. The P ⁺ drain doping region 203 of the PMOS transistor 102 is electrically connected to a bit line (not shown) to provide a bit line signal to the electrically programmable logic device 100. The electrically programmable logic device 100 according to the present invention is operated under low voltage, and the floating gate oxide 302a and the gate oxide 301a are the same as the thickness of the gate oxide in the logic circuit, or if necessary. Increases the thickness. Either way, the electrically programmable logic device 100 according to the present invention is compatible with standard CMOS semiconductor processing.
[0009]
FIG. 4 is an explanatory diagram when a write operation is performed on the electrically programmable logic device 100 according to the present invention. In FIG. 4, when a write operation is performed, a word line voltage V _SG is applied to the select gate 301 of the PMOS transistor 101, and the P channel below the select gate 301 is opened. A source line voltage _VSL is applied to the P ⁺ source doping region 201 of the PMOS transistor 101. A well voltage V _NW is applied to the N-type well 110. A bit line voltage _VBL is applied to the P ⁺ drain doping region 203 of the PMOS transistor 102. The floating gate 302 of the PMOS transistor 102 is in a floating state. In the floating gate 302, a low voltage is obtained by the effect of capacitive coupling, a P-type channel below the floating gate 302 is opened, and hot electrons are generated by collision with holes of the channel. Hot electrons are accelerated by the electric field of the depletion layer, cross the floating gate oxide film 302a, and are trapped in the floating gate 302.
[0010]
Figure 5 is a PMOS transistor 102, under the conditions of the various bias voltages for N-type well 110 of the drain _{203 (V d = V BL -V} NW), is a diagram showing the relationship between the floating gate voltage and gate current . As shown in FIG. 5, under the condition of the bias voltage V _d = −5 V, the floating gate 302 has a low voltage V _FG of −1 to −2 V due to the effect of capacitive coupling (V _FG is equal to the bit line voltage V _BL . , N-type well voltage V _NW and the voltage applied to P + source doping region 202 of PMOS transistor 102). At this time, the channel of the PMOS transistor 102 has just opened, and the gate current has already approached the maximum value. In other words, in the operation mode according to the present invention, since the value ( _Ig / _Id ) of the gate current with respect to the drain current is large, a better effect can be obtained when performing the write operation.
[0011]
FIG. 7 is an explanatory diagram showing an energy band of electron injection of the P ⁺ polycrystalline silicon gate according to the present invention. Another feature according to the present invention is that the floating gate 302 of the PMOS transistor 102 is P ⁺ doped, and the doping concentration is from 1.0 × 10 ¹⁹ cm ⁻³ to 1.5 × 10 ¹⁹ cm ⁻³ (dopant is boron). ) Is preferable. Since the P ⁺ doping the polysilicon floating gate 302 has a number of free holes, after the hot electrons are injected into the P ⁺ doping the polysilicon floating gate 302, and re-coupling the previous free holes, the ionized The acceptor generates a negative ionic charge. Since these negative ion charges are different from free electrons, they cannot move freely, and are hardly lost because the distance between the polycrystalline silicon and the oxide film interface is long. Then, since the data storage is prolonged, the purpose of increasing the data holding ability of the memory can be achieved.
[0012]
FIG. 6 is a cross-sectional view of another preferred embodiment according to the present invention. As shown in FIG. 6, the electrically programmable logic device 600 includes an NMOS transistor 801 and an NMOS transistor 802 connected in series to the NMOS transistor 801 by a shared N + doping region 602. An NMOS transistor 801 and an NMOS transistor 802 are formed on the P-type well 610. P-type well 610 is formed on N-type semiconductor substrate 700. The NMOS transistor 801 includes an N ⁺ doping region 602 which is shared with the select gate 901, the N ⁺ source doping region 601 and the NMOS transistor 802, and serves as a drain. The NMOS transistor 802 is a floating gate transistor, and includes an N ⁺ -doped polysilicon floating gate 902, an N ⁺ -doped region 603, and an N ⁺ -doped region 602 shared with the NMOS transistor 801. The N ⁺ doping region 602 is simultaneously the drain of the NMOS transistor 801 and the source of the NMOS transistor 802, thereby forming two series transistors. The floating gate 902 according to the present invention is formed from single-layer polycrystalline silicon, and has no or need for a control gate above. The floating gate 902 of the NMOS transistor 802 is N ⁺ doped. Since the N ⁺ -doped polysilicon floating gate 902 has a large number of free electrons, hot free holes are injected into the N ⁺ -doped polysilicon floating gate 902 and then recombined with the free electrons first. This produces a positive ion charge. Since these positive ion charges are different from free holes, they cannot move freely, and the distance from the polycrystalline silicon-oxide film interface is long, so that they are not easily lost. Then, since the data storage is prolonged, the purpose of increasing the data holding ability of the memory can be achieved.
[0013]
The above is a preferred embodiment of the present invention, and does not limit the scope of the present invention. Therefore, any modification or alteration that can be made by those skilled in the art and that is made in the spirit of the present invention and that has an equivalent effect on the present invention shall fall within the scope of the claims of the present invention. I do.
[0014]
【The invention's effect】
Compared to the prior art electrically programmable logic device, the electrically programmable logic device according to the present invention can be operated under low voltage, or due to the unique design, the PMOS transistor 102 will have a floating gate current when the channel is just opened. Is already approaching the maximum. Under the operation mode according to the present invention, the value of the ratio of the gate current to the drain current ( _Ig / _Id ) is relatively large, so that it has the advantage of energy saving, and also provides better efficiency when writing. Reduce writing time. Since the present invention uses two PMOS transistors connected in series, the area of the chip can be significantly reduced and the present invention can be used in the field of highly integrated memories. Alternatively, the present invention has a simple structure, is compatible with a conventional CMOS process, has a low manufacturing cost, and is suitable for a system-on-a-chip. If channel hot electron injection is used in the write operation, a P ⁺ -doped polysilicon floating gate is used, and if channel hole injection is used in the write operation, an N ⁺ -doped polysilicon floating gate is used. In addition, the time for which the ionic charges store data is relatively long, and the data retention capability of the memory can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a conventional single-layer polycrystalline silicon memory cell.
FIG. 2 is a cross-sectional view of an electrically programmable logic device according to the present invention.
FIG. 3 is a plan view of the electrically programmable logic device of FIG. 2;
FIG. 4 is an explanatory diagram in which an electrically programmable logic device performs a write operation.
In Figure 5 PMOS transistor, under different conditions having a drain bias to the N-type well _{(V d = V BL -V NW} ), which is a diagram of the relationship between the floating gate voltage and gate current.
FIG. 6 is a sectional view of another preferred embodiment according to the present invention.
FIG. 7 is an explanatory diagram showing an energy band of electron injection of a P ⁺ polycrystalline silicon gate according to the present invention.
[Explanation of symbols]
Reference Signs List 10 single-layer polycrystalline silicon memory cell 12 P-type substrate 14, 601 N ⁺ source doping region 16, 603 N ⁺ drain doping region 18 N-type ion well 20, 201 P ⁺ source doping region 22, 203 P ⁺ drain doping region 24 Field oxide film 28,801,802 NMOS transistor 30,101,102 PMOS transistor 32 First floating gate 34 Second floating gate 36 Floating gate conductor 38 N-type channel blocking region 100,600 Electrically programmable logic device 110 N-type well 202 P ⁺ doped region 301,901 select gate 302 ^{P +} doped polysilicon floating gate 602 ^{N +} doped region 610 P-type well 902 ^{N +} doping Grayed polysilicon floating gate 700 N-type semiconductor substrate 1000 P-type semiconductor substrate

Claims (8)

An electrically programmable logic device,
A P-type substrate;
An N-type well provided in the P-type substrate;
A PMOS select transistor formed on the N-type well, including a select gate for applying a word line voltage, a first P ⁺ source doping region for applying a source line voltage, and a first P ⁺ drain doping region; ,
A P ⁺ -doped floating gate, a second P ⁺ source doping region electrically connected to the first P ⁺ drain doping region, and a second P ⁺ drain doping region for applying a bit line voltage; A second P ⁺ source doping region and the second P ⁺ drain doping region define a floating gate P-type channel, and a PMOS floating formed on the N-type well and serially connected to the PMOS selection transistor. An electrically programmable logic device, comprising: a gate transistor. 2. The electrically programmable logic device according to claim 1, wherein said PMOS select transistor further includes a gate oxide film provided below said select gate electrode. The electrically programmable logic device of claim 1, wherein said PMOS floating gate transistor further comprises a floating gate oxide film provided below said P ⁺ doped floating gate. When performing a write operation, hot electrons are injected into the P ⁺ doping the floating gates, the free holes and recombination is in the P ⁺ doping the floating gates, by producing the negative ionic charge of fixing, the electrical 2. The electrically programmable logic device according to claim 1, wherein the data retention capability of the programmable logic device is improved. A non-volatile memory cell,
A MOS selection transistor including a select gate electrically connected to the word line, a first source doping region electrically connected to the source line, and a first drain doping region;
A floating gate, a second source doping region electrically connected to the first drain doping region, and a second drain doping region electrically connected to a bit line; and The second drain doping region defines a floating gate channel, and includes a MOS floating gate transistor connected in series to the MOS selection transistor;
When the MOS floating gate transistor is written in channel hot electron mode, the floating gate of the MOS floating gate transistor is doped with a P-type dopant, and when the MOS floating gate transistor is written in channel hot hole mode, the MOS floating gate transistor is A nonvolatile memory cell, wherein a floating gate of a gate transistor is doped with an N-type dopant. 6. The nonvolatile memory cell according to claim 5, wherein said MOS selection transistor further includes a gate oxide film provided below said selection gate electrode. 6. The nonvolatile memory cell according to claim 5, wherein said MOS floating gate transistor further includes a floating gate oxide film provided below said floating gate. The non-volatile memory cell according to claim 5, wherein the non-volatile memory cell can be manufactured by a standard CMOS process.

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