JP2004319890A - Semiconductor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor circuit wherein there are made possible the corrections of the delaying differences among its signal lines, the dealing with its circuit alterations performed without any layout alteration of its buses, the reduction of its designing load, and the prevention of its malfunctions caused by the delaying differences of its signal lines, by controlling properly the driving abilities of the buffers of its bus driving circuit in response to the delaying differences of its signal lines. <P>SOLUTION: In the semiconductor circuit, after transmitting data by a transmitting portion 12 via buses 20, the data received by a receiving portion 32 are so converted into serial data as to send back the serial data to a data transmitting portion 10 via a serial-signal line 50. Then, after comparing the transmitted data and the sent-back data with each other by a delay deciding portion 14, there are sensed the bits of signals according to the compared results whose delays are so larger than other signals in a plurality of signal lines of the buses 20 that errors are generated thereby in their transferring data. According to the sensed results, the delaying differences among the signal lines are so corrected by controlling properly the driving abilities of buffers as to be able to prevent the errors of the transferring data caused by the delaying differences. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention detects a delay difference of each bit of data transferred to a data transfer destination in a semiconductor circuit that transfers data via a bus, and controls a driving capability of a bus drive circuit in accordance with the detection result. And a semiconductor circuit for correcting a delay difference between bits.
[0002]
[Prior art]
In a semiconductor circuit that transmits data consisting of a plurality of bits via a bus, different delay characteristics may occur between adjacent signal lines due to the arrangement of each signal line of the bus or capacitive coupling between the signal lines. There is. The delay difference between the signal lines of the bus may cause an error in the transfer signal, which may cause a malfunction of the semiconductor device.
[0003]
Conventionally, in order to eliminate a signal delay difference due to a difference in capacitance between adjacent wirings of a bus, a method of adjusting wiring dimensions of each signal line of the bus or a method of providing a delay circuit in the bus has been adopted. ing.
FIG. 3 is a conceptual diagram showing an example of a layout of a bus signal line. As shown in the figure, in order to cancel the influence of the capacitive coupling between the signal lines, of the n signal lines corresponding to the n-bit transfer data, the signal lines on both sides are arranged slightly longer than the other signal lines. I have. This is because the wirings on both sides, that is, the signal lines corresponding to the 0-bit and the (n-1) -th bits shown in FIG. This is because the coupling is smaller than the other signal lines, and therefore, the propagation delay of the 0-bit and the (n-1) -bit is smaller than the other bits.
[0004]
As shown in FIG. 3, by arranging the signal lines on both sides slightly longer than the other signal lines, the delay time of these signal lines becomes slightly longer. Thereby, the difference from the delay time of the other signal lines is corrected.
[0005]
[Patent Document 1]
JP-A-2002-246557 [Patent Document 2]
Japanese Patent Application Laid-Open No. 2002-033457
[Problems to be solved by the invention]
By the way, in the above-described conventional semiconductor circuit, when the layout of the bus wiring changes due to a change in the circuit configuration or the like, the capacitive coupling between the signal lines changes, and the delay characteristics of the signal lines change. For this reason, in order to correct the delay difference between the signal lines, it is necessary to recalculate the propagation delay of each signal line and redesign the layout. For this reason, the work load increases in the design stage, and even a slight change in the circuit configuration may affect the layout of the bus signal lines, and the wiring layout becomes unstable.
[0007]
The present invention has been made in view of such circumstances, and an object of the present invention is to appropriately control the driving capability of a signal line driving circuit provided in a signal line of a bus according to a delay time difference between signal lines. To provide a semiconductor circuit capable of correcting a delay difference between signal lines, adapting to a circuit change without changing a bus layout, reducing a design load, and preventing a malfunction due to a signal line delay difference. It is in.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor circuit of the present invention is a semiconductor circuit including a transmitting unit that outputs transmission data to a bus via a driving circuit, and a receiving unit that receives data transmitted through the bus. A semiconductor circuit that corrects a propagation delay of the bus, converts a reception data received by the reception unit to serial data, and transmits the serial data to the transmission unit via a serial signal line; Receiving the serial data transmitted by the transmitting unit, comparing the received data with the transmission data output to the bus, and determining a delay difference of the signal line of the bus according to a result of the comparison; A delay control unit that controls the driving capability of the drive circuit to correct the delay difference.
[0009]
In the present invention, preferably, the delay control unit compares the received serial data and the transmission data bit by bit, and corresponds to each bit of the transmission data according to a result of the comparison. The driving capability of the driving circuit is controlled.
[0010]
In the present invention, preferably, the delay control unit compares the received serial data and the transmission data bit by bit, and according to the comparison result, compares the received serial data with the transmission data. The driving capability of the driving circuit corresponding to the bit having a different value is controlled to be larger than usual.
[0011]
In the present invention, preferably, the drive circuit is connected to a first buffer that amplifies the transmission data and outputs the amplified data to a signal line configuring the bus, and is connected in parallel with the first buffer. A second buffer is provided for each signal line of the bus, the second buffer being controlled to operate or not operate in response to a control signal from the delay control unit, and amplifying the transmission data during operation and outputting the amplified signal to the signal line. Have been.
[0012]
Further, in the present invention, preferably, the control unit compares the received serial data and the transmission data bit by bit, and according to a result of the comparison, among the received serial data and the transmission data, , The second buffer of the drive circuit corresponding to the bit having a different value is controlled to an operating state.
[0013]
According to the present invention, transmission data is output to the bus via the drive circuit by the transmission unit, and transmission data transferred via the bus is received by the reception unit. The received data is returned to the transmission unit via a serial signal line. In the transmission unit, the received serial data is compared with the transmission data, and a delay difference between the signal lines of the bus can be determined according to the comparison result. Based on the determination result, the driving of the buffer configuring the driving circuit is performed. By appropriately controlling the capability, the delay difference between the signal lines of the bus is corrected, and the transfer data error caused by the signal line delay difference can be prevented.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a configuration diagram showing one embodiment of a semiconductor circuit according to the present invention.
As illustrated, the semiconductor circuit of the present embodiment includes a data transmission unit 10, a bus 20, a data reception unit 30, a bus driving circuit 40 for driving each signal line of the bus 20, and a serial signal line 50.
[0015]
The data transmitting unit 10 is, for example, a processing circuit such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor), and the data receiving unit 30 performs processing in response to, for example, a control command or data from the CPU or the DSP. Peripheral circuit for performing the above. The bus 20 includes signal lines for transferring control commands or data from the CPU or DSP to the data receiving unit 30, and a plurality of signal lines are provided according to the number of bits of data to be transferred.
[0016]
Hereinafter, each component of the semiconductor circuit of the present embodiment will be described with reference to FIG.
First, each component of the data transmission unit 10 will be described.
As shown in FIG. 1, the data transmission unit 10 includes a transmission unit 12, a delay control unit 14, a register 16, and a serial reception unit 18. The data reception unit 30 includes a reception unit 32 and a serial transfer unit 34. Have.
[0017]
The transmission unit 12 outputs a control command or data to the bus 20 via the bus driving circuit 40. The control command or data output by the transmission unit 12 is transferred to the data reception unit 30 via the bus 20.
[0018]
The delay control unit 14 compares the data transmitted to the bus 20 by the transmission unit 12 with the data received by the serial reception unit 18, and, based on the result of the comparison, transmits the data of the plurality of bits transferred to the data reception unit 30. Of the data, a bit having a longer delay than the other bits and thereby causing an error in the received data is determined. According to the result of the determination, the delay control data D14 is generated and output to the register 16.
[0019]
The register 16 holds the delay correction data D14 input from the delay control unit 14, and outputs the held data to each buffer of the bus drive circuit 40. In response to this, the driving capability of each buffer of the bus driving circuit 40 is controlled, so that the delay time is longer than that of the other signal lines. By largely controlling the driving capability of the buffer corresponding to the signal line, a delay difference from another signal line can be corrected, and a propagation error due to the delay difference is avoided.
[0020]
The serial receiving section 18 receives the serial data transferred via the serial signal line 50 and outputs the received data to the delay control section 14.
[0021]
The bus 20 includes n signal lines for transferring data of n bits (n is an integer, n ≧ 1).
[0022]
Next, each component of the data receiving unit 30 will be described.
As shown in FIG. 1, the data receiving unit 30 includes a receiving unit 32 and a serial transfer unit 34.
[0023]
The receiving unit 32 receives data input via the bus 20. Then, the receiving unit 32 outputs the received data to the serial transfer unit 34.
The serial transfer unit 34 converts the data received by the reception unit 32 into serial data, and transmits the serial data to the data transmission unit 10 via the serial signal line 50.
[0024]
In the delay control circuit of the present embodiment, the data receiving unit 30 converts the data received by the receiving unit 32 into serial data and transmits the serial data to the data transmitting unit 10 via the serial signal line 50. As compared with the data transfer of the above, an error caused by the difference in the delay characteristics of the signal lines can be avoided. For this reason, the delay control unit 14 of the data transmission unit 10 can determine the delay difference between the signal lines of the bus 20 using the same data as the data that has reached the data reception unit 30, and according to the result of the determination, The delay correction data D14 is generated and output to the register 16. Thus, the delay difference between the signal lines of the bus 20 can be correctly determined, the influence of the delay difference between the bus signal lines can be avoided based on the determination result, and the reliability of data transfer by the bus 20 can be improved.
[0025]
Next, the configuration of the bus drive circuit 40 will be described.
The bus drive circuit 40 includes n buffers 40-1, 40-2,..., 40-n provided on each signal line of the bus 20 as shown. Each of the buffers provided in the bus drive circuit 40 has its drive capability controlled by control data DC-1, DC-2,..., DC-n from the register 16 of the data transmission unit 10.
[0026]
Since the buffers 40-1, 40-2,..., 40-n that constitute the bus drive circuit 40 have the same configuration, the configuration will be described in further detail with the buffer 40-1 as an example.
[0027]
FIG. 2 is a circuit diagram showing a configuration example of the buffer 40-1.
As shown in the drawing, the buffer 40-1 includes an inverter 42, an inverter 44 that is controlled to be in an operation state or a non-operation state by the control data DC-1, and an inverter 46 that supplies logically inverted data of the control data DC-1 to the inverter 44. have.
[0028]
The inverter 42 is a MOS inverter configured by a pMOS transistor P1 and an nMOS transistor N1, as shown in FIG. The input terminal of the inverter 42 is connected to the output terminal of the transmission unit 12 shown in FIG. 1, and the output terminal is connected to the signal line 20-1 of the bus 20.
[0029]
The inverter 44 includes pMOS transistors P2 and P3 and nMOS transistors N2 and N3 as shown. The gates of the pMOS transistor P2 and the nMOS transistor N2 are commonly connected, and the connection point forms an input terminal of the inverter 44. The drains of the pMOS transistor P2 and the nMOS transistor N2 are commonly connected, and the connection point forms an output terminal of the inverter 44.
As shown in FIG. 2, the input terminal of the inverter 44 is connected to the input terminal of the inverter 42, and the output terminal of the inverter 44 is connected to the output terminal of the inverter 42. That is, the inverters 44 and 42 are connected in parallel.
[0030]
The pMOS transistor P3 is connected between the pMOS transistor P2 and a supply terminal of the power supply voltage _VDD , and the nMOS transistor N3 is connected between the nMOS transistor N2 and the ground potential. The gate of the pMOS transistor P3 is connected to the register 16, the gate of the nMOS transistor N3 is connected to the output terminal of the inverter 46, and the input terminal of the inverter 46 is connected to the register 16.
[0031]
Therefore, the transistors P3 and N3 are controlled to be conductive or cut-off by the control data DC-1 stored in the register 16. For example, when the control data DC-1 held in the register 16 is 0, the gate of the transistor P3 is held at a low level and the gate of the transistor N3 is held at a high level, so that both the transistors P3 and N3 are conductive. State, and the inverter 44 is controlled to the operating state. Conversely, when the control data DC-1 held in the register 16 is 1, the gate of the transistor P3 is held at a high level and the gate of the transistor N3 is held at a low level. In the cutoff state, the inverter 44 is controlled to be in a non-operation state.
[0032]
When the inverter 44 is in operation, the buffer 40-1 is formed by two inverters 42 and 44 connected in parallel, the driving capability of which is largely controlled and transferred to the signal line 20-1 of the bus 20. Data delay is controlled to be small. On the other hand, when inverter 44 is in a non-operating state, buffer 40-1 is formed of only inverter 42, its driving capability is controlled to be small, and the delay of data transferred to signal line 20-1 increases.
[0033]
As described above, the drive capability of the buffer 40-1 is controlled according to the control data DC-1 held in the register 16.
In the delay control circuit of the present embodiment, the bus drive circuit 40 is configured by n buffers 40-1, 40-2,..., 40-n provided according to the number of signal lines of the bus 20. I have. Therefore, all buffers of the bus drive circuit 40 can be independently controlled by storing, for example, n-bit control data DC-1, DC-2,..., DC-n in the register 16.
[0034]
Next, the operation of the semiconductor circuit of the present embodiment having the above-described configuration will be described.
In the semiconductor circuit, transmission data output by the transmission unit 12 of the data transmission unit 10 is output to the bus 20 via the bus drive circuit 40. Then, the transmission data is transferred to the data receiving unit 30 by the bus 20. The data receiving unit 30 receives the data transferred by the receiving unit 32 via the bus 20, and outputs the received data to the serial transfer unit 34.
[0035]
In the serial transfer unit 34, the data received by the receiving unit 32 is converted into serial data, and is returned to the data transmitting unit 10 via the serial signal line 50. In the data transmission unit 10, the serial data transferred by the serial signal line 50 is received by the serial reception unit 18, converted into parallel data, and output to the delay control unit 14.
[0036]
In the delay control unit 14, the data transmitted to the bus 20 by the transmission unit 12 is compared with the data input from the serial reception unit 18. As a result of the comparison, when both data match, the propagation delay characteristics of each signal line of the bus 20 substantially match, and the data transmitted by the data transmitting unit 10 is correctly transmitted to the data receiving unit 30 via the bus 20. It can be seen that it has been propagated. In this case, the delay control data D14 is generated so that all the buffers of the bus drive circuit 40 have the normal driving capability, and the delay control data D14 is written into the register 16. At this time, all bits of the buffer 16 are set to, for example, 1. In response, only the inverter 42 shown in FIG. 2 among the buffers 40-1, 40-2,..., 40-n operates, and the inverter 44 is controlled to a non-operating state.
[0037]
On the other hand, as a result of the comparison by the delay control circuit 14, when the data transmitted by the transmission unit 12 and the data received by the serial reception unit 18 do not match, both data are transferred by the bus 20 by detecting different bits. Of the n-bit data, a bit in which an error has occurred due to the delay difference of the signal line can be determined. Based on this determination result, it is possible to determine which of the n signal lines of the bus 20 has a longer propagation delay than the other signal lines. Therefore, by largely controlling the driving capability of the buffer that outputs data to these signal lines, the delay difference between the signal lines of the bus 20 can be corrected, and errors occurring in the data reaching the data receiving unit 30 can be corrected. Can be prevented.
[0038]
Specifically, for example, when the delay control circuit 14 detects a different bit between the transmission data of the transmission unit 12 and the reception data of the serial reception unit 18 as a result of the comparison, the delay control circuit 14 The bit of the data D14 is set to 0, and the other bits are set to 1. The control data D14 is output to the register 16, and is held in the register 16. Then, the n buffers of the bus drive circuit 40 are controlled in accordance with the delay control data D14 held in the register 16, respectively. For example, in the buffer corresponding to the bit of 1 in the delay control data D14, only one inverter (corresponding to the inverter 42 shown in FIG. 2) operates, while, in the delay control data D14, 0 Since both the inverters (corresponding to the inverters 42 and 44 shown in FIG. 2) operate in the buffer corresponding to the following bit, the driving capability is controlled to be larger than that of the buffer in which only one inverter operates. For this reason, the delay difference between the signal lines is maintained, and transfer data errors caused by the delay difference can be prevented.
[0039]
As described above, in the semiconductor circuit of the present embodiment, the data is transmitted by the transmission unit 12 of the data transmission unit 10 via the bus 20 and the data received by the reception unit 32 of the data reception unit 30 is converted into serial data. Then, the data is returned to the data transmission unit 10 via the serial signal line 50. The transmission data of the transmission unit 12 and the returned data are compared by the delay determination unit 14 of the data transmission unit 10, and the delay is larger than other signals among the plurality of signal lines of the bus 20 according to the comparison result. As a result, an erroneous bit is detected in the transmitted data. By appropriately controlling the driving capability of each buffer of the bus driving circuit 40 according to the result of the detection, the delay difference between the signal lines of the bus 20 can be corrected, and the transfer data error caused by the delay difference can be corrected. Can be prevented.
[0040]
It should be noted that the above-described delay determination and delay correction processing according to the determination result are performed for all buses at predetermined time intervals, or when a predetermined operation time of the circuit, for example, after power-on and initialization. In this way, the change in the delay characteristic of the bus can be grasped one by one according to the operation state of the circuit, and the driving capability of each buffer of the bus drive circuit is appropriately controlled in accordance with the change, whereby the delay between the signal lines of the bus is controlled. The difference can always be controlled to be minimized, and errors in transfer data caused by the delay difference can be prevented.
[0041]
【The invention's effect】
As described above, according to the semiconductor circuit of the present invention, the delay difference of the signal line of the bus is detected, and the driving capability of the buffer of the bus drive circuit is appropriately controlled based on the result of the detection. There is an advantage that the difference can be corrected and the resulting data error can be prevented.
Further, according to the semiconductor circuit of the present invention, it is possible to cope with the temporal change of the delay difference of the bus, and even if the delay characteristic of the bus changes due to the use condition of the semiconductor circuit, etc., the change of the delay characteristic is judged one by one. By appropriately controlling the driving capability of the buffer of the bus drive circuit in response to the change, the change in the delay characteristic can be corrected, and the data error caused by the change in the bus delay characteristic can be prevented.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing one embodiment of a semiconductor circuit according to the present invention.
FIG. 2 is a circuit diagram illustrating an example of a buffer included in the semiconductor circuit according to the embodiment;
FIG. 3 is a diagram showing a layout of a conventional bus.
[Explanation of symbols]
10 data transmission unit, 12 transmission unit, 14 delay control unit, 16 register, 18 serial reception unit,
20, a bus, 20-1, 20-2,..., 20-n a bus signal line 30 a data receiving section, 32 a receiving section, 34 a serial transfer section,
40 bus drive circuits, 40-1, 40-2, ..., 40-n buffers
50 ... Serial signal line.

Claims (5)

A semiconductor circuit including a transmission unit that outputs transmission data to a bus via a driving circuit and a reception unit that receives data transmitted through the bus, wherein the semiconductor circuit corrects a propagation delay of the bus. ,
A serial transmission unit that converts reception data received by the reception unit into serial data and transmits the serial data to the transmission unit via a serial signal line,
Receiving the serial data transmitted by the serial transmission unit, comparing the received data with the transmission data output to the bus, and determining a delay difference between signal lines of the bus according to a result of the comparison; And a delay control unit for controlling the drive capability of the drive circuit to correct the delay difference. The delay control unit compares the received serial data and the transmission data bit by bit, and controls a driving capability of the driving circuit corresponding to each bit of the transmission data according to a result of the comparison. Item 2. The semiconductor circuit according to item 1. The delay control unit compares the received serial data and the transmission data bit by bit, and according to a result of the comparison, among the received serial data and the transmission data, a bit corresponding to a bit having a different value. 3. The semiconductor circuit according to claim 2, wherein the driving capability of the driving circuit is controlled to be larger than usual. A first buffer configured to amplify the transmission data and output the amplified signal to a signal line configuring the bus;
A second buffer that is connected in parallel with the first buffer, is controlled to operate or not operate according to a control signal from the delay control unit, and amplifies the transmission data during operation and outputs the amplified data to the signal line; 2. The semiconductor circuit according to claim 1, wherein the circuit is provided for each signal line of the bus. The control unit compares the received serial data and the transmission data bit by bit, and, according to a result of the comparison, among the received serial data and the transmission data, the drive corresponding to a bit having a different value. 5. The semiconductor circuit according to claim 4, wherein said second buffer of said circuit is controlled to an operating state.

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