JP2004318970A - Static semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide SRAM of which the layout area is small, the soft error resistance is high, and the write/read-out speed is high. <P>SOLUTION: The memory cell 2 of this SRAM includes an inverter 16 and an N-channel MOS transistor 12 for outputting an inverted signal of a memory node N2 to a first read-out bit line BLRA in response to the fact that a first read-out word line WLRA is made to "H" level, and an inverter 17 and an N-channel MOS transistor 13 for outputting an inverted signal of a memory node N1 to a second read-out bit line BLRB in response to the fact that a second read-out word line WLRB is made to "H" level. As a result, since the memory cell 2 eliminates the need for a sense amplifier, the layout area can be made small, and since the capacitance values of the memory nodes N1, N2 are large and equal to each other, the soft error resistance and the write/read-out speed are improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a static semiconductor memory device, and more particularly to a static semiconductor memory device having a plurality of read ports.
[0002]
[Prior art]
FIG. 6 is a circuit diagram showing a main part of a conventional static random access memory (hereinafter, referred to as SRAM). 6, this SRAM includes a memory cell 70 arranged at the intersection of a word line WL and a pair of bit lines BL and / BL. Memory cell 70 includes N-channel MOS transistors 71 and 72, inverters 73 and 74, and storage nodes N71 and N72. N-channel MOS transistor 71 is connected between bit line BL and storage node N71, and has its gate connected to word line WL. N-channel MOS transistor 72 is connected between bit line / BL and storage node N72, and has its gate connected to word line WL. Inverter 73 is connected between storage nodes N1 and N2, and inverter 74 is connected between storage nodes N72 and N71. Inverters 73 and 74 constitute a latch circuit.
[0003]
Inverter 73 includes a P-channel MOS transistor 75 and an N-channel MOS transistor 76 as shown in FIG. P-channel MOS transistor 75 is connected between a power supply potential VCC line and an output node (storage node N72), and has a gate connected to an input node (storage node N71). N-channel MOS transistor 76 is connected between the output node and the ground potential GND line, and has its gate connected to the input node.
[0004]
When the input node is at "H" level, P-channel MOS transistor 75 is turned off and N-channel MOS transistor 76 is turned on, and the output node is set to "L" level. When the input node is at "L" level, P-channel MOS transistor 75 is turned on, N-channel MOS transistor 76 is turned off, and the output node is turned to "H" level. Inverter 74 has the same configuration as inverter 73.
[0005]
Next, the operation of the SRAM shown in FIGS. 6 and 7 will be described. In a write operation, word line WL is raised to the selected level "H", N channel MOS transistors 71 and 72 are turned on, and memory cell MC is activated. Further, one of bit lines BL and / BL is set to "H" level and the other bit line is set to "L" level in response to the write data signal. The storage nodes N71 and N72 have the same potential as the bit lines BL and / BL, respectively. When word line WL falls to the "L" level of the non-selection level, N-channel MOS transistors 71 and 72 are rendered non-conductive, and the potentials of storage nodes N1 and N2 are latched by inverters 73 and 74.
[0006]
During a read operation, bit lines BL and / BL are charged to "H" level (power supply potential VCC) via a bit line load (not shown), and word line WL is set to a selected level of "H" level. When activated, N-channel MOS transistors 71 and 72 conduct. When storage nodes N71 and N72 are at "L" level and "H" level, respectively, the potential of bit line BL decreases. When storage nodes N71 and 72 are at "H" level and "L" level, respectively, bit line / is low. The potential of BL decreases. The potential difference between bit lines BL and / BL is amplified by a sense amplifier (not shown) and output to the outside as a read data signal.
[0007]
FIG. 8 is a circuit diagram showing a main part of another conventional SRAM. Referring to FIG. 8, this SRAM differs from the SRAMs of FIGS. 6 and 7 in that each of inverters 73 and 74 is replaced with an inverter 77. Inverter 77 divides N-channel MOS transistor 76 of inverter 73 into two N-channel MOS transistors 76a and 76b, and arranges two N-channel MOS transistors 76a and 76b on one side and the other side of P-channel MOS transistor 75. Things. In this SRAM, the probability of the α particles simultaneously colliding with the two N-channel MOS transistors 76a and 76b is extremely small, so that the occurrence of soft errors can be reduced (for example, see Patent Document 1).
[0008]
FIG. 9 is a circuit diagram showing a main part of a conventional 1 write port / 2 read port SRAM. 9, this SRAM includes a write word line WLWA, a first read word line WLRA and a second read word line WLRB, a pair of write bit lines BLWA and / BLWA, a first read bit line BLRA and a second read bit line. A memory cell 80 is provided at an intersection with the BLRB.
[0009]
Memory cell 80 includes N-channel MOS transistors 81 to 84, inverters 85 and 86, and storage nodes N81 and N82. N-channel MOS transistor 81 is connected between write bit line BLWA and storage node N81, and has its gate connected to write word line WLWA. N-channel MOS transistor 82 is connected between write bit line / BLWA and storage node N82, and has its gate connected to write word line WLWA.
[0010]
Inverter 85 is connected between storage nodes N81 and N82, and inverter 86 is connected between storage nodes N82 and N81. Inverters 85 and 86 constitute a latch circuit. N-channel MOS transistor 83 is connected between storage node N81 and first read bit line BLRA, and has its gate connected to first read word line WLRA. N-channel MOS transistor 84 is connected between storage node N81 and second read bit line BLRB, and has its gate connected to second read word line WLRB.
[0011]
At the time of the write operation, similarly to the SRAM shown in FIG. 6, write word line WLWA is set to the "H" level of the selected level, N channel MOS transistors 81 and 82 are turned on, and write bit lines BLWA and / BLWA are turned on. One of the write bit lines is set to "H" level and the other write bit line / BLWA is set to "L" level, and a logical level corresponding to the data signal is written to storage nodes N81 and N82.
[0012]
In a read operation, when first read word line WLRA is set to the selected level of "H" level, N-channel MOS transistor 83 is turned on, and the potential of storage node N81 is read through N-channel MOS transistor 83 for the first read. Applied to bit line BLRA. When second read word line WLRB is set to the selected level “H”, N-channel MOS transistor 84 is turned on, and the potential of storage node N81 is changed to the second read bit line BLRB via N-channel MOS transistor 84. Given to. The potentials of first read bit line BLRA and second read bit line BLRB are converted to a read data signal and output to the outside.
[0013]
[Patent Document 1]
JP-A-7-7089
[0014]
[Problems to be solved by the invention]
However, the conventional SRAM has the following problems. That is, in the SRAMs of FIGS. 6 and 7, a sense amplifier for amplifying the potential difference between bit lines BL and / BL and a control circuit therefor are required, so that the configuration of the readout circuit is complicated and the layout area is large. There was a problem. Further, as the memory cell 70 is miniaturized, the capacitance values of the storage nodes N71 and N72 become smaller, and there is a problem that a soft error in which a data signal is inverted due to collision of α particles easily occurs.
[0015]
Although the occurrence of soft errors is reduced in the SRAM of FIG. 8, since the N-channel MOS transistor 76 is divided into two, there is a problem that the layout of the memory cell becomes complicated and the layout area becomes large. Was.
[0016]
Further, in the SRAM of FIG. 9, since N-channel MOS transistors 83 and 84 are connected to only one storage node N81, the capacitance value of storage node N81 becomes larger than the capacitance value of storage node N82, and storage node N81. , N82 are difficult to invert and the writing operation is delayed. Further, since the two read bit lines BLRA and BLRB are driven only by the inverter 86, there is a problem that the potential change speed of the read bit lines BLRA and BLRB becomes slow and the read operation becomes slow.
[0017]
SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a static semiconductor memory device having a small layout area, high soft error resistance, and high writing / reading speed.
[0018]
[Means for Solving the Problems]
A static semiconductor memory device according to the present invention includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a write word line, a first read word line, and a second read word provided corresponding to each row. And a first write bit line, a second write bit line, a first read bit line, and a second read bit line provided corresponding to each column. Here, the memory cell connects the corresponding first write bit line and the first storage node in response to the corresponding write word line being set to the selected level, and connects the corresponding second write bit line. A switching circuit for connecting the write bit line to the second storage node, a first inverter connected between the first and second storage nodes, and a connection between the second and first storage nodes A latch circuit including a second inverter, for latching a data signal and an inverted data signal respectively applied to the first and second storage nodes from the corresponding first and second write bit lines; The logic circuit is provided between the storage node and the corresponding first read bit line, and the logic of the data signal latched in the first storage node in response to the corresponding first read word line being set to the selected level. The potential corresponding to the potential is set to the first read bit. A first drive circuit for outputting a signal to a corresponding line and a second storage node provided between the second storage node and a corresponding second read bit line. And a second drive circuit for outputting a potential corresponding to the logical potential of the inverted data signal latched by the second storage node to the second read bit line.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
FIG. 1 is a block diagram showing an overall configuration of a one-write-port / 2-read-port SRAM according to the first embodiment of the present invention. In FIG. 1, the SRAM includes a memory cell array 1, a row decoder 3, and a write / read circuit 4.
[0020]
The memory cell array 1 includes a plurality of memory cells 2 arranged in a plurality of rows and a plurality of columns (n + 1; n is an integer of 0 or more), a write word line WLWA provided for each row, and a first read word. Line WLRA and second read word line WLRB, write bit line pair BLWA, / BLWA provided corresponding to each column, first read bit line BLRA and second read bit line BLRB.
[0021]
The row decoder 3 selects one of the plurality of write word lines WLWA according to the write address signals AWA0 to AWAm (where m is an integer of 0 or more), and selects the selected write word line. The write word line WLWA is set to the "H" level of the selected level, and each memory cell 2 corresponding to the write word line WLWA is set in a writable state.
[0022]
The row decoder 3 selects one of the plurality of first read word lines WLRA according to the first read address signals ARA0 to ARAm, and sets the selected first read word line WLRA to a selection level. Of the memory cell 2 corresponding to the first read word line WLRA in the first readable state.
[0023]
The row decoder 3 selects one of the plurality of second read word lines WLRB from the plurality of second read word lines WLRB according to the second read address signals ARB0 to ARBm, and sets the selected second read word line WLRB to a selection level. Of the memory cell 2 corresponding to the second read word line WLRB in the second readable state.
[0024]
The write / read circuit 4 writes the (n + 1) data signals DA0 to DAn to the (n + 1) memory cells 2 which are made writable via the (n + 1) pairs of write bit lines BLWA and / BLWA. Write / read circuit 4 externally outputs first read data signals QA0 to QAn read from n + 1 memory cells 2 in the first readable state via first read bit line BLRA. Write / read circuit 4 externally outputs second read data signals QB0 to QBn read from n + 1 memory cells 2 in the second readable state via second read bit line BLRB.
[0025]
FIG. 2 is a circuit block diagram showing a main part of the SRAM shown in FIG. In FIG. 2, memory cell 2 includes N-channel MOS transistors 10 to 13, inverters 14 to 17, and storage nodes N1 and N2. N-channel MOS transistor 10 is connected between write bit line / BLWA and storage node N1, and has its gate connected to corresponding write word line WLWA. N-channel MOS transistor 11 is connected between write bit line BLWA and storage node N2, and has its gate connected to corresponding write word line WLWA. Inverter 14 is connected between storage nodes N1 and N2, and inverter 15 is connected between storage nodes N2 and N1. Inverters 14 and 15 form a latch circuit.
[0026]
Inverter 16 and N-channel MOS transistor 12 are connected in series between storage node N2 and first read bit line BLRA, and the gate of N-channel MOS transistor 12 is connected to corresponding first read word line WLWA. Inverter 17 and N-channel MOS transistor 13 are connected in series between storage node N1 and second read bit line BLRB, and the gate of N-channel MOS transistor 13 is connected to corresponding second read word line WLRB. The current driving force of inverters 16 and 17 is set to be larger than the current driving force of inverters 14 and 15.
[0027]
When write word line WLWA is raised to the selected level "H" level, N-channel MOS transistors 10 and 11 are rendered conductive, and memory cell 2 is set in a writable state. Storage nodes N1 and N2 are set to the same logic level as write bit lines / BLWA and BLWA, respectively. When write word line WLWA falls to the "L" level of the non-selection level, N-channel MOS transistors 10 and 11 are turned off, and the logic levels of storage nodes N1 and N2 are latched by inverters 14 and 15. You.
[0028]
When first read word line WLRA is raised to the selected level "H" level, N-channel MOS transistor 12 is turned on, and memory cell 2 is set to the first readable state. The logic level of storage node N2 is inverted by inverter 16 and applied to first read bit line BLRA. When first read word line WLRA falls to the non-selection level “L” level, N-channel MOS transistor 12 is turned off, and memory cell 2 is inactivated.
[0029]
When second read word line WLRB is raised to the selected level "H" level, N-channel MOS transistor 13 is turned on, and memory cell 2 is set to the second readable state. The logic level of storage node N1 is inverted by inverter 17 and applied to second read bit line BLRB. When the second read word line WLRB is raised to the “L” level of the non-selection level, the N-channel MOS transistor 13 is turned off, and the memory cell 2 is inactivated.
[0030]
The row decoder 3 includes predecoders 20 to 22, a word driver 23 provided for each write word line WLWA, a word driver 24 provided for each first read word line WLRA, And a word driver 25 provided corresponding to second read word line WLRB.
[0031]
A unique predecode signal XWA0 to XWAi (where i is an integer of 0 or more) is assigned to each write word line WLWA in advance. Each of the first read word lines WLRA is assigned a unique predecode signal XRA0 to XRAi in advance. To each second read word line WLRB, a unique predecode signal XRB0 to XRBi is assigned in advance.
[0032]
Predecoder 20 generates predecode signals XWA0 to XWAi corresponding to any one of a plurality of write word lines WLWA according to write address signals AWA0 to AWAm, and generates the generated predecode signals. XWA0 to XWAi are given to each word driver 23. Word driver 23 includes a NAND gate 26 and an inverter 27, and sets a corresponding write word line WLWA to a selected level "H" level in response to the application of corresponding predecode signals XWA0 to XWAi.
[0033]
The predecoder 21 generates and generates predecode signals XRA0 to XRAi corresponding to any one of the plurality of first read word lines WLRA according to the first read address signals ARA0 to ARAm. Predecode signals XRA0 to XRAi are applied to each word driver 24. Word driver 24 includes a NAND gate 26 and an inverter 27, and sets the corresponding first read word line WLRA to the "H" level of the selected level in response to the application of corresponding predecode signals XRA0 to XRAi.
[0034]
The predecoder 22 generates and generates the predecode signals XRB0 to XRBi corresponding to any of the second read word lines WLRB among the plurality of second read word lines WLRB according to the second read address signals ARB0 to ARBm. Predecode signals XRB0 to XRBi are applied to each word driver 25. Word driver 25 includes a NAND gate 26 and an inverter 27, and sets the corresponding second read word line WLRB to the selected level "H" in response to the application of corresponding predecode signals XRB0 to XRBi.
[0035]
Write / read circuit 4 includes inverters 30 to 33 and buffers 34 and 35 provided corresponding to each column. FIG. 2 shows the (n + 1) -th column. Write data signal DAn is inverted by inverter 30 and applied to corresponding write bit line / BLWA, and is also applied to corresponding write bit line BLWA via inverters 31 and 32. The signal appearing on first read bit line BLRA is inverted by inverter 33 and buffer 34 to become first read data signal QAn. The signal appearing on second read bit line BLRB is delayed by buffer 35 to become second read data signal QBn.
[0036]
Next, the operation of the SRAM shown in FIGS. 1 and 2 will be described. When write address signals AWA0-AWAm are applied to row decoder 3, word driver 23 of row decoder 3 raises write word line WLWA corresponding to write address signals AWA0-AWAm to the selected level "H" level. Then, N channel MOS transistors 10 and 11 of each memory cell 2 corresponding to the write word line WLWA are turned on.
[0037]
Write data signals DA0-DAn are applied to write / read circuit 4, and each of n + 1 sets of write bit lines BLWA, / BLWA is handled by inverters 30, 31 and buffer 32 of write / read circuit 4. Of the data signal. The potential of each write data line pair BLWA, / BLWA is transmitted to storage nodes N1, N2 of memory cell 2 in the selected row. When write word line WLWA falls to the "L" level of the non-selection level, N-channel MOS transistors 10 and 11 of each memory cell 2 become non-conductive, and the potentials of storage nodes N1 and N2 become inverters 14 and 15 respectively. Latched by
[0038]
When the first read address signals ARA0 to ARAm are applied to the row decoder 3, the word driver 24 of the row decoder 3 sets the first read word line WLRA corresponding to the first read address signals ARA0 to ARAm to the selected level "H". "Level. Thereby, N-channel MOS transistor 12 of each memory cell 2 corresponding to the first read word line WLRA is turned on, and the signal latched at storage node N2 is applied to inverter 16, N-channel MOS transistor 12, and first read bit line. The data is output to the outside as a read data signal QA via the BLRA, the inverter 33, and the buffer. When the first read word line WLRA falls to the "L" level of the non-selection level, the N-channel MOS transistor 12 of each memory cell 2 becomes non-conductive, and the potentials of the storage nodes N1 and N2 are changed by the inverters 14 and 15. Latched.
[0039]
When the second read address signals ARB0 to ARBm are applied to the row decoder 3, the word driver 25 of the row decoder 3 sets the second read word lines WLRB corresponding to the second read address signals ARB0 to ARBm to the selected level “H”. "Level. Thereby, N-channel MOS transistor 13 of each memory cell 2 corresponding to the second read word line WLRB is turned on, and the signal latched at storage node N1 is applied to inverter 17, N-channel MOS transistor 13, and second read bit line. The signal is output to the outside as a read data signal QB via the BLRB and the buffer 35. When the second read word line WLRB falls to the "L" level of the non-selection level, the N-channel MOS transistor 13 of each memory cell 2 becomes non-conductive, and the potentials of the storage nodes N1 and N2 are changed by the inverters 14 and 15. Latched.
[0040]
In this SRAM, write data signals DA0 to DAn are written into memory cells 2 for one row, and data signals QA0 to QAn are read from those memory cells 2, and write data signals DA0 to DAn are written for one row. And reading data signals QB0-QBn from these memory cells 2 can be performed simultaneously.
[0041]
In the first embodiment, since inverters 16 and 17 for providing inverted signals of the signals latched at storage nodes N2 and N2 to read bit lines BLRA and BLRB are provided, the potential difference between a pair of bit lines BL and / BL is amplified. There is no need to separately provide a sense amplifier and its control circuit. Therefore, the read circuit is simplified, the proportion of the memory cell 2 in the entire SRAM is increased, and a small-capacity SRAM can be realized with a smaller area than a sense amplifier type SRAM.
[0042]
Further, since the input nodes of the inverters 17 and 16 are connected to the storage nodes N1 and N2, respectively, the capacitance values of the storage nodes N1 and N2 increase and the soft error resistance increases.
[0043]
Further, since the capacitance values of the storage nodes N1 and N2 are made equal, the writing speed is increased as compared with the related art in which the capacitance values of the storage nodes N81 and N82 are not equal.
[0044]
Since the signals latched in storage nodes N2 and N1 are inverted by inverters 16 and 17 and applied to read bit lines BLRA and BLRB, the read speed can be increased as compared with the conventional SRAM of FIG. .
[0045]
FIG. 3 is a circuit block diagram showing a main part of a one-write-port / 4-read-port SRAM according to a modification of the first embodiment. 3, in this SRAM, a write word line WLWA and first to fourth read word lines WLRA to WLRD are provided corresponding to each memory cell row, and first to fourth write word lines WLRA to WLRD are provided corresponding to each memory cell column. Read bit lines BLRA to BLRD are provided. The memory cell 40 is obtained by adding inverters 41 and 42 and N-channel MOS transistors 43 and 44 to the memory cell 2 of FIG. Inverter 41 and N-channel MOS transistor 43 are connected in series between storage node N2 and third read bit line BLRC, and the gate of N-channel MOS transistor 43 is connected to third read word line WLRC. Inverter 42 and N-channel MOS transistor 44 are connected in series between storage node N1 and fourth read bit line BLRD, and the gate of N-channel MOS transistor 44 is connected to fourth read word line WLRD.
[0046]
When third read word line WLRC is set to the “H” level of the selected level, N-channel MOS transistor 43 is turned on, and the signal latched at storage node N 2 is passed through inverter 41 and N-channel MOS transistor 43 to the third level. This is applied to read bit line BLRC. When fourth read word line WLRD is set to the “H” level of the selected level, N-channel MOS transistor 44 is turned on, and the signal latched at storage node N 1 is output to fourth terminal via inverter 41 and N-channel MOS transistor 44. This is applied to read bit line BLRD.
[0047]
Also in this modified example, the same effect as the SRAM of FIGS. 1 and 2 can be obtained.
[Embodiment 2]
FIG. 4 is a circuit block diagram showing a main part of a two-write port / 2-read port SRAM according to a second embodiment of the present invention, which is compared with FIG. 4, in this SRAM, first and second write word lines WLWA, WLWB and first and second read word lines WLRA, WLRB are provided corresponding to each memory cell row, and each memory cell column is provided. Correspondingly, first and second write bit line pairs BLWA, / BLWA; BLWB, / BLWB and first and second read bit lines BLRA, BLRB are provided.
[0048]
The memory cell 50 is obtained by adding N-channel MOS transistors 51 and 52 to the memory cell 2 of FIG. N channel MOS transistor 51 is connected between storage node N1 and second write bit line BLWB, and has its gate connected to second write word line WLWB. N channel MOS transistor 52 is connected between storage node N2 and second write bit line / BLWB, and has its gate connected to second write word line WLWB.
[0049]
When second write word line WLWB is raised to the selected level "H" level, N-channel MOS transistors 51 and 52 are rendered conductive, and memory cell 50 is set to the second writable state. Storage nodes N1 and N2 are set to the same logic level as second write bit lines BLWB and / BLWB, respectively. When second write word line WLWB is lowered to the non-selection level "L" level, N-channel MOS transistors 51 and 52 are turned off, and the logic levels of storage nodes N1 and N2 are latched by inverters 14 and 15. Is done.
[0050]
The row decoder 53 is obtained by adding a predecoder 54 and a word driver 55 provided corresponding to each second write word line WLWB to the row decoder 3 of FIG. Each of the second write word lines WLWB is assigned a unique predecode signal XWB0 to XWBi in advance. Predecoder 54 generates predecode signals XWB0 to XWBi corresponding to any one of a plurality of second write word lines WLWB according to second write address signals AWB0 to AWBm. , And applies the generated predecode signals XWB0 to XWBi to each word driver 55. Word driver 55 includes a NAND gate 26 and an inverter 27, and raises the corresponding second write word line WLWB to the selected level of "H" in response to the application of corresponding predecode signals XWB0 to XWBi. .
[0051]
Write / read circuit 56 is obtained by adding inverters 57 to 59 to write / read circuit 4 of FIG. Second write data signal DBn is applied to second write bit line BLWB via inverters 57 and 58, and is also inverted by inverter 59 and applied to second write bit line / BLWB.
[0052]
Next, the operation of this SRAM will be described. When second write address signals AWB0 to AWBm are applied to row decoder 53, word driver 55 sets second write word line WLWB corresponding to second write address signals AWB0 to AWBm to the selected level of "H" level. Then, N channel MOS transistors 51 and 52 of each memory cell 50 corresponding to the second write word line WLWB are turned on.
[0053]
Further, second write data signals DB0 to DBn are applied to write / read circuit 56, and n + 1 sets of second write data lines BLWB and / BLWB are respectively connected to inverters 57 to 59 of write / read circuit 56. The potential is set according to the corresponding data signal. The potential of each write data line pair BLWB, / BLWB is transmitted to storage nodes N1, N2 of memory cell 2 in the selected row. When the second write word line WLWB is lowered to the "L" level of the non-selection level, N-channel MOS transistors 51 and 52 of each memory cell 50 become non-conductive, and the potentials of storage nodes N1 and N2 are inverted by inverter 14 , 15.
[0054]
In this SRAM, write data signals DA0 to DAn of the first port are written to memory cells 2 for one row, and data signals QA0 to QAn of the first port are read from these memory cells 2; And writing data signals QB0 to QBn of the second port from those memory cells 2 at the same time. Other configurations and operations are the same as those of the first embodiment, and therefore description thereof will not be repeated.
[0055]
Also in the second embodiment, the same effect as in the first embodiment can be obtained.
[Embodiment 3]
FIG. 5 is a circuit block diagram showing a main part of a one-write-port / 2-read-port SRAM according to a third embodiment of the present invention, which is compared with FIG.
[0056]
Referring to FIG. 5, this SRAM differs from the SRAM of FIG. 2 in that memory cell 2 is replaced by memory cell 60 and P-channel MOS transistors 64 and 65 are added.
[0057]
Memory cell 60 is obtained by replacing inverters 16 and 17 of memory cell 2 with N-channel MOS transistors 61 and 62, respectively. N-channel MOS transistor 61 is connected between the source of N-channel MOS transistor 12 and the line of ground potential GND, and has its gate connected to storage node N2. N-channel MOS transistor 62 is connected between the source of N-channel MOS transistor 13 and the line of ground potential GND, and has its gate connected to storage node N1.
[0058]
P-channel MOS transistor 64 is connected between a line of power supply potential VCC and first read bit line BLRA, and has a gate receiving first precharge signal PCA. P-channel MOS transistor 65 is connected between a line of power supply potential VCC and second read bit line BLRB, and has a gate receiving second precharge signal PCB.
[0059]
When reading data signal QAn of the first port, first, first precharge signal PCA is raised from "L" level to "H" level, and P-channel MOS transistor 64 is turned off. First read bit line BLRA is charged to “H” level (power supply potential VCC) while P-channel MOS transistor 64 is conducting. Next, first read word line WLRA is raised to the selected level "H" level, and N-channel MOS transistor 12 is turned on. When storage node N2 is at "H" level, N-channel MOS transistor 61 is rendered conductive, first read bit line BLRA attains "L" level, and first read data signal QAn attains "H" level. When storage node N2 is at "L" level, N-channel MOS transistor 61 is rendered non-conductive, first read bit line BLRA remains at "H" level, and first read data signal QAn is at "L" level. Be leveled.
[0060]
When reading data signal QBn of the second port, first, second precharge signal PCA is raised from "L" level to "H" level, and P-channel MOS transistor 65 is turned off. Second read bit line BLRB is charged to “H” level while P-channel MOS transistor 65 is conducting. Next, second read word line WLRB is raised to the selected level "H" level, and N-channel MOS transistor 13 is turned on. When storage node N1 is at "H" level, N-channel MOS transistor 62 is turned on, second read bit line BLRB is at "L" level, and second read data signal QBn is at "L" level. When storage node N1 is at "L" level, N-channel MOS transistor 32 is rendered non-conductive, second read bit line BLRB remains at "H" level, and second read data signal QBn is at "H" level. Be leveled. Other configurations and operations are the same as those of the first embodiment, and therefore description thereof will not be repeated.
[0061]
In the third embodiment, the same effect as in the first embodiment can be obtained.
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0062]
【The invention's effect】
As described above, in the static semiconductor memory device according to the present invention, the memory cell is connected to the corresponding first write bit line and the first write bit line in response to the corresponding write word line being set to the selected level. A switching circuit connecting the storage node and connecting the corresponding second write bit line and the second storage node, a first inverter connected between the first and second storage nodes, A second inverter connected between the second and first storage nodes, and a data signal provided from the corresponding first and second write bit lines to the first and second storage nodes, respectively. A latch circuit for latching an inverted data signal is provided between a first storage node and a corresponding first read bit line, and in response to a corresponding first read word line being set to a selected level, Latch to first storage node A first drive circuit for outputting a potential corresponding to the logical potential of the received data signal to the first read bit line, and a second drive node provided between the second storage node and the corresponding second read bit line; Output to the second read bit line a potential corresponding to the logical potential of the inverted data signal latched in the second storage node in response to the second read word line being set to the selected level. A driving circuit. Therefore, since the first and second drive circuits are provided for each memory cell, there is no need to separately provide a sense amplifier and its control circuit, and the layout area can be reduced. Further, since the first and second drive circuits are connected to the first and second storage nodes, respectively, the capacitance value of each of the first and second storage nodes increases, and the soft error resistance increases. Further, since the capacitance values of the first and second storage nodes are equalized, the data writing speed is increased, and the data reading speed is increased since the first and second driving circuits are provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a 1-write port / 2-read port SRAM according to a first embodiment of the present invention.
FIG. 2 is a circuit block diagram showing a main part of the SRAM shown in FIG.
FIG. 3 is a circuit diagram showing a modification of the first embodiment.
FIG. 4 is a circuit block diagram showing a main part of a two write port / 2 read port SRAM according to a second embodiment of the present invention;
FIG. 5 is a circuit block diagram showing a main part of a 1 write port / 2 read port SRAM according to a third embodiment of the present invention.
FIG. 6 is a circuit diagram showing a main part of a conventional SRAM.
FIG. 7 is a circuit diagram showing a configuration of the inverter shown in FIG.
FIG. 8 is a circuit diagram showing a main part of another conventional SRAM.
FIG. 9 is a circuit diagram showing a main part of a conventional 1 write port / 2 read port SRAM.
[Explanation of symbols]
1 memory cell array, 2, 40, 50, 60, 70, 80 memory cells, 3, 53 row decoder, 4, 56 write / read circuit, 10 to 13, 43, 44, 51, 52, 61, 62, 71 , 72, 76, 81 to 84 N-channel MOS transistors, 14 to 17, 27, 30 to 33, 41, 42, 57 to 59, 73, 74, 77, 85, 86 inverters, 20 to 22, 54 predecoders, 23 to 25, 55 word driver, 26 NAND gate, 34, 35 buffer, 64, 65 P channel MOS transistor, WLW write word line, WLR read word line, BLW, / BLW write bit line pair, BLR read bit line , WL word line, BL, / BL bit line pair.

Claims (5)

A static semiconductor memory device,
A plurality of memory cells arranged in a plurality of rows and a plurality of columns;
A write word line, a first read word line, and a second read word line provided corresponding to each row;
A first write bit line, a second write bit line, a first read bit line, and a second read bit line provided corresponding to each column;
The memory cell comprises:
In response to the corresponding write word line being set to the selected level, the corresponding first write bit line is connected to the first storage node, and the corresponding second write bit line is connected to the second storage bit line. A switching circuit for connecting to the storage node of
A first inverter connected between the first and second storage nodes, and a second inverter connected between the second and first storage nodes, the corresponding first and second A latch circuit for latching a data signal and an inverted data signal respectively applied to the first and second storage nodes from a write bit line;
Provided between the first storage node and a corresponding first read bit line, and latched by the first storage node in response to the corresponding first read word line being set to a selected level; A first drive circuit for outputting a potential corresponding to the logic potential of the data signal to the first read bit line, and between the second storage node and a corresponding second read bit line; In response to the corresponding second read word line being set to the selected level, a potential corresponding to the logical potential of the inverted data signal latched in the second storage node is output to the second read bit line. A static semiconductor memory device including a second drive circuit. The first drive circuit includes:
A third inverter whose input node is connected to the first storage node, and a third inverter connected between an output node of the third inverter and a corresponding first read bit line; A first transistor that is turned on in response to the word line being set to a selected level,
The second driving circuit includes:
A fourth inverter whose input node is connected to the second storage node, and a fourth inverter connected between an output node of the fourth inverter and a corresponding second read bit line; 2. The static semiconductor memory device according to claim 1, further comprising a second transistor that is turned on in response to the word line being set to a selected level. The first drive circuit includes:
Its gate is connected to the first storage node, its first electrode receives a first logic potential, and is conductive when the data signal latched at the first storage node is at a second logic potential. A first transistor, and a corresponding first read bit line connected between a corresponding first read bit line precharged to the second logic potential and a second electrode of the first transistor. A second transistor that is turned on in response to the word line being set to a selected level,
The second driving circuit includes:
Its gate is connected to the second storage node, its first electrode receives the first logic potential, and the inverted data signal latched at the second storage node is the second logic potential. A third transistor that is turned on in a case, and is connected between a corresponding second read bit line precharged to the second logic potential and a second electrode of the third transistor; 2. The static semiconductor memory device according to claim 1, further comprising a fourth transistor that is turned on in response to the two read word lines being set to a selected level. A plurality of sets of the first read word line, the second read word line, the first read bit line, the second read bit line, the first drive circuit, and the second drive circuit are provided. The static semiconductor memory device according to claim 1, wherein 5. The static memory according to claim 1, wherein a plurality of sets of the write word line, the first write bit line, the second write bit line, and the switching circuit are provided. 6. Type semiconductor storage device.

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