JP2004318717A - Disk array controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disk array controller which improves access performance, from a host computer to a cache memory and a disk unit, by relieving the load on an internal interface in the disk array controller. <P>SOLUTION: The disk array controller includes a data pattern identifying logic unit 30 for identifying a write data pattern from the host computer and read data patterns, from the cache memory and the disk unit, a command generator 31 for commanding, based on the data pattern identified by the data pattern identifying logic unit 30, and a command analyzer 32 for analyzing the command, to generate an original data pattern. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a disk array control device, and more particularly to a technique that is effective when applied to increase the speed of an internal interface.
[0002]
[Prior art]
With the spread of networks such as the Internet and the increase in the amount of information handled by companies, the demand for storage has become increasingly diversified. The capacity of disk systems has also increased, and external networks connected to the disk systems also support high-speed, large-capacity data transfer.
[0003]
Although the data transfer through the high-speed interface is also supported inside the disk system, the latency is long because the line is thinner than the external network connected to the disk system due to the limitation of the number of pins of the package, the connector, and the LSI.
[0004]
Therefore, conventionally, as a technique for accelerating the internal interface in the disk array control device, when a plurality of commands from the host are commands requesting access to one continuous area, these commands are grouped into one. In some cases, processing as one command reduces the load on the internal interface and speeds up the processing (for example, see Patent Document 1). There is also a technique for providing a buffer in a data transfer path to take measures such as hiding an increase in latency.
[0005]
[Patent Document 1]
JP-A-5-289818
[0006]
[Problems to be solved by the invention]
As a processing of the disk array controller, in response to a write request from the host computer, the write data sent from the host computer is received by the channel interface unit, and the data is transmitted to the data via the internal interface in the disk array controller. Transfer and write to cache memory and disk device. At this time, if the amount of write data is large, the load on the internal interface increases, and the latency increases.
[0007]
In response to a read request from the host computer, the corresponding data is read from the cache memory and the disk device in the disk array controller based on the information sent from the host computer, and is read via the internal interface in the disk array controller. To transfer data and send read data to the host computer. At this time, when the read data amount is large, the load on the internal interface increases, and the latency increases.
[0008]
Also, if the performance of the external network connecting the host computer and the disk array controller is faster and larger than the internal interface, a large-capacity buffer must be provided in the disk array controller to prevent waiting for requests from the host computer. It has to be provided, which has been a problem in terms of cost and the like.
[0009]
In addition, as a method of suppressing the influence on other processes sharing the internal interface, a method of dividing data transfer has conventionally been used. This is a method in which, for example, when transferring 4 kilobytes of data, the data is divided into 256-byte units, and an internal interface is opened for data for other processing.
[0010]
However, in order to reduce the latency, it is necessary to increase the speed of the internal interface and increase the number of internal interfaces. However, it is difficult to increase the speed as compared with the external network, and the package and LSI connectors are increased by increasing the number of interfaces. In addition, there are restrictions on the number of pins and it is difficult to reduce the latency.
[0011]
Further, in the technique described in Patent Document 1, when a plurality of commands are commands that require access to one continuous area, the command amount is reduced by grouping and processing the plurality of commands. Therefore, it is impossible to reduce the amount of commands unless the access is to a continuous area, and the load on the internal interface increases when the amount of write and read data handled by the commands is large. there were.
[0012]
Therefore, an object of the present invention is to provide a disk array control device capable of reducing the load on an internal interface in the disk array control device and improving the performance of accessing a cache memory and a disk device from a host computer. is there.
[0013]
[Means for Solving the Problems]
A disk array control device according to the present invention includes a channel interface unit connected to a host computer, a disk interface unit connected to a disk device, and a cache memory for temporarily storing data read or written to the disk device. , A first interconnection network connecting the channel interface unit and the cache memory unit, and a second interconnection network connecting the disk interface unit and the cache memory unit. A data pattern identification logic for identifying a pattern of write data and a pattern of data read from the cache memory unit and the disk device; and a command for commanding based on the data pattern identified by the data pattern identification logic. And command generation means, analyzes the command, in which a command analysis unit for generating the original data pattern.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0015]
(Embodiment 1)
FIG. 1 is a configuration diagram showing a configuration of the disk array control device according to the first embodiment of the present invention.
[0016]
In FIG. 1, a disk array control device 2 is connected to a disk device 4 composed of a number of magnetic disk devices, and controls the disk device 4 according to an instruction from a host computer 1 connected via an external network 2. The disk array control device 2 and the disk device 4 constitute a disk array device.
[0017]
The disk array control device 2 is connected to the host computer 1 via the external network 3 to perform data transfer, a channel interface unit 10 for performing data transfer, a disk interface unit 60 for performing data transfer with the disk device 4, and a disk device 4. A cache memory unit 40 having a cache memory 50 for temporarily storing data to be read / written from / to the disk unit 4, control of data transfer between the channel interface unit 10 and the disk interface unit 60 and the cache memory unit 40, and It comprises a shared memory unit 20 for storing management information.
[0018]
The channel interface unit 10, the disk interface unit 60, and the shared memory unit 20 are connected by an interconnection network 70, which is a first interconnection network and a second interconnection network, respectively. The cache memory unit 60 and the cache memory unit 40 are connected by an interconnection network 80.
[0019]
Further, the channel interface unit 10 includes a host data transmitting / receiving unit 34 for performing data transfer with the host computer 1, a data pattern identification logic unit 30 as data pattern identification logic unit, a command generation unit 31 as command generation unit, It is composed of a command analysis unit 32 as analysis means and a processor 33 for controlling the channel interface unit 10.
[0020]
The presence / absence of data that can be converted into special commands in the write data to the cache memory unit 40 in response to a write request from the host computer 1 by the data pattern identification logic unit 30, command generation unit 31, and command analysis unit 32 of the channel interface unit 10. And the generation of transmission data to the host computer 1 when the read data from the cache memory unit 40 in the read request processing from the host computer 1 is converted into a special command.
[0021]
The cache memory unit 40 includes a data pattern identification logic unit 30, a command generation unit 31, a command analysis unit 32, and a disk interface unit 60 provided between the cache memory 50, the channel interface unit 10, and the cache memory 50. It comprises a data pattern identification logic unit 30, a command generation unit 31, and a command analysis unit 32 provided between the cache memory 50 and the cache memory 50.
[0022]
A channel interface associated with a write request from the host computer 1 is provided by a data pattern identification logic unit 30, a command generation unit 31, and a command analysis unit 32 provided between the channel interface unit 10 and the cache memory 50 of the cache memory unit 40. When the write data from the unit 10 has been converted into a special command, generation of write data to the cache memory 50, identification of presence / absence of data that can be converted into a special command in data read from the cache memory 50, and conversion to a special command are performed. ing.
[0023]
The data pattern identification logic unit 30, command generation unit 31, and command analysis unit 32 provided between the disk interface unit 60 and the cache memory 50 of the cache memory unit 40 make special commands in the data read from the cache memory 50. The identification of the presence / absence of possible data and the conversion into a special command are performed, and the data generation when the data transmitted from the disk interface unit 60 to the cache memory unit 40 is converted into a special command is performed.
[0024]
The disk interface unit 60 controls the disk data transmission / reception unit 35 that performs data transfer with the disk device 4, the data pattern identification logic unit 30, the command generation unit 31, the command analysis unit 32, and the disk interface unit 60. Processor 33.
[0025]
The data pattern identification logic unit 30, the command generation unit 31, and the command analysis unit 32 of the disk interface unit 60 identify the presence / absence of data that can be converted into special commands in the data transmitted to the cache memory unit 40, and convert the data into special commands. The transmission data to the disk device 4 is generated when the transmission data from the cache memory unit 40 is converted into a special command.
[0026]
The processor 33 of the channel interface unit 10 and the processor 33 of the disk interface unit 60 are connected to the service processor 100 via a service processor connection network 90.
[0027]
Next, the operation of this embodiment will be described.
[0028]
FIG. 2 is a flowchart showing an operation of processing a request from a host computer according to the first embodiment, FIG. 3 is a flowchart showing an operation of reading from a cache memory according to the first embodiment, and FIG. 4 is a cache according to the first embodiment. 6 is a flowchart illustrating an operation of a write-back process from a memory to a disk device.
[0029]
First, in the operation of processing a request from the host computer 1, when a request from the host computer 1 arrives at the channel interface unit 10 (S100), the command analysis unit 32 analyzes the command / address (S101).
[0030]
Then, it is determined whether the request is a write request or a read request by analyzing the command in S101 (S102).
[0031]
When it is determined in S102 that the request is a read request, the command / address is sent to the cache memory unit 40 (S106). When it is determined in S102 that the request is a write request, the data pattern identification logic unit 30 determines whether a specific pattern exists. It is identified (S103).
[0032]
If it is determined in S103 that there is no specific pattern, the command / address / write data is sent to the cache memory unit 40 (S106). It is determined whether special command conversion is necessary (S104).
[0033]
Then, if it is determined in S104 that special command conversion is not necessary, the command / address / write data is sent to the cache memory unit 40 (S106). At 31 the data is converted into a special command (S105), and the command / address / write data / special command is sent to the cache memory unit 40 (S106).
[0034]
If all data can be converted into special commands in S105, it is not necessary to send out write data in S106. If only a part of the data is converted into a special command in S105, the remaining write data needs to be transmitted.
[0035]
By using the special commands, the load on the interconnection network 80 can be reduced without occupying the interconnection network 80 spanning the channel interface unit 10 and the cache memory unit 40 with a large amount of data transfer, and the performance of the write processing can be reduced. Will be improved. The processing up to this point is the processing in the channel interface unit 10.
[0036]
Subsequently, the process proceeds to the processing in the cache memory unit 40. When the request arrives at the cache memory unit 40 from the channel interface unit 10 (S107), the command analysis unit 32 analyzes the command / address (S108).
[0037]
Then, a write request or a read request is determined by the command analysis in S108 (S109).
[0038]
If it is determined in S109 that the request is a read request, data is read from the cache memory 50 (S113). If it is determined in S109 that the request is a write request, the presence or absence of a special command is determined (S110).
[0039]
If it is determined in S110 that there is no special command, data is written to the cache memory 50 (S112). If it is determined in S110 that there is a special command, the command analyzing unit 32 analyzes the special command, and Returns the data to the original data pattern sent from the host computer 1 to generate write data (S111), and writes the data to the cache memory 50 (S112).
[0040]
Here, the special command is determined, write data is generated, and the same data pattern as the data transmitted from the host computer 1 is written to the cache memory 50, and then the special command is written to the cache memory 50 as it is. It is also possible to reduce the cache memory usage capacity.
[0041]
Next, in the operation of the reading process from the cache memory 50, data is read from the cache memory 50 (S120), and the presence / absence of a specific pattern is identified by the data pattern identification logic unit 30 (S121).
[0042]
If it is determined in S121 that there is no specific pattern, the command / address / read data is sent to the channel interface unit 10 (S124). It is determined whether special command conversion is necessary (S122).
[0043]
If it is determined in S122 that the special command is not required, the command / address / read data is sent to the channel interface unit 10 (S124). If it is determined in S122 that the special command is required, the command generation unit is used. At 31 the data is converted into a special command (S123), and the command / address / read data / special command is sent to the channel interface unit 10 (S124).
[0044]
If all data can be converted into a special command in S123, there is no need to transmit read data in S124. If only a part of the data is converted into a special command in S123, the remaining read data needs to be transmitted.
[0045]
By converting the command into a special command, the load on the interconnection network 80 is reduced without occupying the interconnection network 80 spanning the channel interface unit 10 and the cache memory unit 40 by a large-capacity data transfer, and the performance of the read processing is improved. Will be improved. The processing up to here has been the processing in the cache memory unit 40.
[0046]
Subsequently, the process proceeds to the processing in the channel interface unit 10. When the read data from the cache memory unit 40 reaches the channel interface unit 10 (S125), the command analysis unit 32 analyzes the command / address (S126).
[0047]
Then, the presence or absence of a special command is determined (S127). If it is determined in S127 that there is no special command, data is sent to the host computer 1 (S129). If it is determined in S127 that there is a special command, command analysis is performed. The special command is analyzed by the unit 32, the data is returned to the original data pattern read from the cache memory 50 from the special command to generate transmission data (S128), and the data is transmitted to the host computer 1 (S129).
[0048]
Next, in the operation of the write-back processing from the cache memory 50 to the disk device 4, data is read from the cache memory 50 (S130), and the presence / absence of a specific pattern is identified by the data pattern identification logic unit 30 (S131).
[0049]
If it is determined in S131 that there is no specific pattern, the command / address / write-back data is sent to the disk interface unit 60 (S134). It is determined whether special command conversion is necessary (S132).
[0050]
If it is determined in S132 that specialization is not necessary, command / address / write-back data is sent to the disk interface unit 60 (S134). If it is determined in S132 that specialization is necessary, command generation is performed. The unit 31 converts the data into a special command (S133), and sends the command / address / write-back data / special command to the disk interface unit 60 (S134).
[0051]
If all data can be converted into special commands in S133, there is no need to send out write-back data in S134. If only a part of the data is converted into a special command in S133, the remaining write-back data needs to be transmitted.
[0052]
By using special commands, the load on the interconnection network 80 can be reduced without occupying the interconnection network 80 extending between the disk interface unit 60 and the cache memory unit 40 by large-capacity data transfer, and the performance of the write-back processing can be reduced. Will be improved. The processing up to here has been the processing in the cache memory unit 40.
[0053]
Subsequently, the process proceeds to the processing in the disk interface unit 60, and when the write-back data arrives from the cache memory unit 40 to the disk interface unit 60 (S135), the command analysis unit 32 analyzes the command / address (S136).
[0054]
Then, it is determined whether or not there is a special command (S137). If it is determined in S137 that there is no special command, data is sent to the disk device 4 (S139). If it is determined in S137 that there is a special command, command analysis is performed. The special command is analyzed by the unit 32, the data is returned to the original data pattern read from the cache memory 50 from the special command, transmission data is generated (S138), and the data is transmitted to the disk device 4 (S139).
[0055]
Here, the special command is determined, transmission data is generated, the data is sent to the disk device 4 after making the same data pattern as the data read from the cache memory 50, but the special command is transmitted to the disk device 4 as it is. It is also possible to send.
[0056]
Similarly, when data is read from the disk device 4, data is transmitted between the disk interface unit 60 and the cache memory unit 40 using a special command.
[0057]
Next, the conversion of data into a special command in this embodiment will be described.
[0058]
FIG. 5 is a diagram illustrating an example of write data according to the first embodiment, FIG. 6 is a diagram illustrating a timing chart of data processing according to the first embodiment, and a process A in FIG. 6 is a process when the present invention is not used. The process B is an example using the present invention, and the process C is another example using the present invention.
[0059]
FIG. 6 is a timing chart focusing on the occupation time of the interconnection network 80 extending between the channel interface unit 10 and the cache memory unit 40 when the data shown in FIG. 5 is written into the cache memory 50. The interconnection network 80 is designed to be capable of transferring data of 8 bytes in one clock.
[0060]
In FIG. 6, C in the timing chart is a command / address transfer phase, D indicates a data transfer phase, B is a branch phase, and when the processing is divided into the processing B and the processing C, the branch phase is set. It does not matter if it is provided. In addition, “0” in FIG. 6 is a data phase for transmitting the data of ALL “0”.
[0061]
Here, a case where a write request of 4 kilobytes is requested from the host computer 1 is considered.
[0062]
As shown in FIG. 5, the data pattern of the write data from the host computer 1 is 4 kilobytes of write data in which 512 bytes of normal data, 3328 bytes of ALL'0 'data, and 256 bytes of normal data are continuous. ing.
[0063]
First, in the processing A of FIG. 6, the occupation time of the interconnection network 80 in the processing of the write data part excluding the processing of the command / address is because the ALL '0' data of 3328 bytes is not treated as special data. Since a 4-kilobyte data transfer is simply transmitted at 8 bytes / clock, a total of 512 clocks are required.
[0064]
In the process B of FIG. 6, the first 512 bytes are normal processing, the 3328 byte ALL '0' data is one special command (eg, 3328 byte '0' write command), and the second 256 bytes are normal again. Treated as processing.
[0065]
In this processing, the processing of 512 bytes of the first half is 64 clocks, the processing of ALL '0' data of 3328 bytes is converted into a special command, so that 4 clocks and the 256 bytes of the latter half are processed by 32 clocks with a total of 100 clocks. .
[0066]
In the process C of FIG. 6, the first 512 bytes of the normal process are processed, the 3328-byte ALL'0 'data is treated as if the 256-byte ALL'0' data is continuous 13 times, and 13 special commands (for example, , 256 byte '0' write command), and the latter 256 bytes are treated as normal processing again.
[0067]
In this processing, the processing of 512 bytes of the first half is 64 clocks, the processing of ALL '0' data of 3328 bytes is converted into 13 special commands, so that 28 clocks and the latter 256 bytes are processed with a total of 124 clocks of 32 clocks are doing.
[0068]
As shown in FIG. 6, the occupation time of the interconnection network 80 is significantly reduced in both the processing B and the processing C as compared with the processing A, and the processing time for writing to the cache memory 50 is also reduced. .
[0069]
The reason why the data pattern is divided into 256 bytes by the process C is that when the data pattern is determined, the shorter the data length, the shorter the time required for the determination and the smaller the logical scale. The shorter the time required for the determination, the smaller the logical scale. Also, the smaller the number of data patterns to be converted into special commands, the smaller the number of special commands and the corresponding logical scale.
[0070]
Therefore, in the process C of FIG. 6, the processing clock is larger than that in the process B, but the overall processing time can be reduced depending on the type of data and the processing content.
[0071]
In the process C of FIG. 6, the data is divided into 256 bytes. However, the data length does not have to be 256 bytes. The data length can be selected according to the logical scale, the past history, etc., such as ALL'0 'or ALL'1'. The most suitable data length is selected from the length, the impact on performance, the line length of the cache memory, the transfer unit with the cache memory, and the transfer unit with the disk device, which are likely to cause the following.
[0072]
It is also possible to make the data length arbitrarily changeable or selectable by the user.
[0073]
Next, details of the data pattern identification logic unit 30 in this embodiment will be described.
[0074]
FIG. 7 is a block diagram illustrating a configuration of the data pattern identification logic unit according to the first embodiment, and illustrates a configuration of the data pattern identification logic unit 30 that performs the processes B and C of FIG.
[0075]
In FIG. 7, the data pattern identification logic unit 30 has an ALL'0 'data pattern identification logic unit 101 and an ALL'1' data pattern identification logic unit 102, and has an ALL'0 'data pattern in data and an ALL in data. '1' data pattern is identified.
[0076]
The data pattern identification logic unit 101 of the data pattern identification logic unit 30 that performs the process B of FIG. 6 includes a data length identification logic unit 103, and has an 8-byte "0" determination logic inside. The unit 104 has a 16-byte '0' decision logic unit 105 and a decision logic unit in units of 8 bytes, and up to a 4-kilobyte '0' decision logic unit 106. Further, the data pattern identification logic unit 102 of the data pattern identification logic unit 30 that performs the process B of FIG. 6 has a data length identification logic unit 103, and has an 8-byte "1" determination logic inside. The unit 107 has a 16-byte '1' decision logic unit 108 and a decision logic unit in units of 8 bytes, and up to a 4-kilobyte '1' decision logic unit 109.
[0077]
As described above, the data pattern identification logic unit 30 that performs the processing of the processing B in FIG. 6 has a determination processing unit of “0” or “1” in units of 8 bytes, and has many determination logic units. , Which is advantageous in terms of performance.
[0078]
Further, the data pattern identification logic section 101 of the data pattern identification logic section 30 that performs the processing of the processing C in FIG. 6 has a data length identification logic section 103 in the data pattern identification logic section 101, and has 256 bytes of “0” determination logic therein. It has a unit 110. Further, the data pattern identification logic unit 102 of the data pattern identification logic unit 30 that performs the process C of FIG. 6 has a data length identification logic unit 103 in the data pattern identification logic unit 102, and has a 256 byte “1” determination logic inside. It has a part 111.
[0079]
As described above, the data pattern identification logic unit 30 that performs the processing of the processing C of FIG. 6 has a determination processing unit of “0” or “1” in units of 256 bytes. The number of logic units is small and the logic scale can be reduced.
[0080]
In this embodiment, the command generation unit 31 in the channel interface unit 10, the cache memory unit 40, and the disk interface unit 60 uses the special command based on the determination result in each determination processing unit in the data pattern identification logic unit 30. Is generated, and data of '0' or '1' determined by each determination processing unit in the data pattern identification logic unit 30 can be processed only by this special command.
[0081]
Also, in this embodiment, the special command is the same as the command for controlling the operation of each unit in the normal disk array control device. Therefore, it is necessary to use a circuit or a program that expands the compressed data. Instead, it is possible to generate the write data and the transmission data by processing the special command in the same manner as the normal command analysis.
[0082]
In this embodiment, an example has been described in which a specific pattern is identified for each data and converted into a special command. However, even if a check code is added to a command or data, the same processing is performed. Is possible.
[0083]
Here, an outline of the check code will be described.
[0084]
In a disk array device such as a RAID system, various check codes are provided in the system in order to meet required reliability.
[0085]
For example, memory units such as the shared memory unit 20 and the cache memory unit 40 are duplicated and ECC is added, so that a 1-bit error can be automatically corrected by hardware, and a 2-bit error Element errors can also be detected.
[0086]
Paths connecting the resources, such as the interconnection network 80, are also duplicated and have parity, and this parity is also determined by the parity added to the data transmitted with the same clock and the next cycle and thereafter. It has parity including the data to be sent.
[0087]
Parity added to the data portion is added at the entrance of a disk array device such as a RAID system, and the same parity is rotated until writing to memory / disk. Parity is also added to the address part / command part, which is added at the front of the path.
[0088]
In this embodiment, even when such a check code is added, it is possible to perform processing using a special command regardless of the state of addition of the check code.
[0089]
(Embodiment 2)
This embodiment is different from the first embodiment in that the configuration of the cache memory unit 40 is configured only by the cache memory 50, and the processing of the special command is not performed in the cache memory unit 40.
[0090]
FIG. 8 is a configuration diagram showing a configuration of the disk array control device according to the second embodiment of the present invention.
[0091]
In the figure, a cache memory unit 40 is constituted only by a cache memory 50, and a data pattern identification logic unit 30, a command generation unit 31, and a command analysis unit 32 are removed from the configuration of the cache memory unit 40 in the first embodiment. It has a configuration. Other configurations are the same as in the first embodiment.
[0092]
In this embodiment, since the cache memory unit 40 does not have the data pattern identification logic 30, the command generation unit 31, and the command analysis unit 32, the specific data pattern is converted into a special command to reduce the load on the interconnection network 80. In this case, after returning the special command to the original data pattern in the cache memory unit 40, the process of writing to the cache memory 50 becomes unnecessary, and the special command is written to the cache memory 50 as it is.
[0093]
Since a read request from the host computer 1 that uses data stored in the cache memory 50 always passes through the channel interface unit 10, the data pattern identification logic 30, the command generation unit 31, Even if a special command is sent from the cache memory unit 40, the command analysis unit 32 can restore the original data pattern.
[0094]
Also, when writing back from the cache memory unit 40 to the disk device 4, the data pattern identification logic 30, the command generation unit 31, and the command analysis unit 32 in the disk interface unit 60 always pass through the disk interface unit 60. Since the special command can be converted into the original data pattern, the process of writing the special command in the cache memory 50 is closed in the disk array controller 2 and the resources connected to the external network such as the host computer 1 are stored in the cache memory. It is not necessary to be aware that a special command is written in the disk array controller, and processing can be performed without affecting external resources of the disk array controller.
[0095]
Advantages of this embodiment include an improvement in the access performance of the cache memory unit 40, a reduction in the logical scale in the cache memory unit 40, simplification of the processing, a reduction in the used capacity of the cache memory 50, and the like.
[0096]
Next, the operation of this embodiment will be described.
[0097]
FIG. 9 is a flowchart showing the operation of processing a request from a host computer according to the second embodiment, FIG. 10 is a flowchart showing the operation of reading from a cache memory according to the second embodiment, and FIG. 11 is a cache according to the second embodiment. 6 is a flowchart illustrating an operation of a write-back process from a memory to a disk device.
[0098]
First, in the operation of processing a request from the host computer 1, when a request from the host computer 1 arrives at the channel interface unit 10 (S140), the command analysis unit 32 analyzes the command / address (S141).
[0099]
Then, it is determined whether the request is a write request or a read request by analyzing the command in S141 (S142).
[0100]
If it is determined in S142 that the request is a read request, the command / address is sent to the cache memory unit 40 (S146). If it is determined in S142 that the request is a write request, the data pattern identification logic unit 30 determines whether a specific pattern exists. It is identified (S143).
[0101]
If it is determined in S143 that there is no specific pattern, the command / address / write data is sent to the cache memory unit 40 (S146). It is determined whether special command conversion is necessary (S144).
[0102]
If it is determined in S144 that special command conversion is not necessary, command / address / write data is sent to the cache memory unit 40 (S146). If it is determined in S144 that special command conversion is necessary, the command generation unit At 31 the data is converted into a special command (S145), and the command / address / write data / special command is sent to the cache memory unit 40 (S146).
[0103]
If all data can be converted into special commands in S145, it is not necessary to send out write data in S146. If only a part of the data is converted into a special command in S145, the remaining write data needs to be transmitted.
[0104]
By using the special commands, the load on the interconnection network 80 can be reduced without occupying the interconnection network 80 spanning the channel interface unit 10 and the cache memory unit 40 with a large amount of data transfer, and the performance of the write processing can be reduced. Will be improved. The processing up to this point is the processing in the channel interface unit 10.
[0105]
Subsequently, the process proceeds to the processing in the cache memory unit 40. When the request arrives at the cache memory unit 40 from the channel interface unit 10 (S147), the command analysis unit 32 analyzes the command / address (S148).
[0106]
Then, a write request or a read request is determined by the command analysis in S148 (S149).
[0107]
If it is determined in S149 that the request is a read request, data is read from the cache memory 50 (S151). If it is determined in S149 that the request is a write request, data and special commands are written to the cache memory 50 regardless of the presence or absence of the special command. (S150).
[0108]
Next, in the operation of the reading process from the cache memory 50, data and a special command are read from the cache memory 50 (S160), and a command / address / data / special command is transmitted to the channel interface unit 10 (S161).
[0109]
By transmitting the special command written in the cache memory 50, the load on the interconnection network 80 can be reduced without occupying the interconnection network 80 extending between the channel interface unit 10 and the cache memory unit 40 by large-capacity data transfer. At the same time, the performance of the reading process is improved. The processing up to here has been the processing in the cache memory unit 40.
[0110]
Subsequently, the process proceeds to the processing in the channel interface unit 10. When the read data from the cache memory unit 40 arrives at the channel interface unit 10 (S162), the command analysis unit 32 analyzes the command / address (S163).
[0111]
Then, it is determined whether or not there is a special command (S164). If it is determined in S164 that there is no special command, data is sent to the host computer 1 (S166). If it is determined in S164 that there is a special command, command analysis is performed. The special command is analyzed by the unit 32, the data is returned to the original data pattern from the special command to generate transmission data (S165), and the data is transmitted to the host computer 1 (S166).
[0112]
Next, in the operation of the write-back process from the cache memory 50 to the disk device 4, the data and the special command are read from the cache memory 50 (S170), and the command / address / write-back data / special command is sent to the disk interface unit 60. (S171).
[0113]
By transmitting the special command written in the cache memory 50, the load on the interconnection network 80 can be reduced without occupying the interconnection network 80 extending between the disk interface unit 60 and the cache memory unit 40 by large-capacity data transfer. At the same time, the performance of the write-back process is improved. The processing up to here has been the processing in the cache memory unit 40.
[0114]
Subsequently, the process proceeds to the processing in the disk interface unit 60. When the write-back data arrives from the cache memory unit 40 to the disk interface unit 60 (S172), the command analysis unit 32 analyzes the command / address (S173).
[0115]
Then, it is determined whether or not there is a special command (S174). If it is determined in S174 that there is no special command, data is sent to the disk device 4 (S176). If it is determined in S174 that there is a special command, command analysis is performed. The special command is analyzed by the unit 32, the data is returned to the original data pattern from the special command to generate transmission data (S175), and the data is transmitted to the disk device 4 (S176).
[0116]
In this embodiment, the special command is determined, the transmission data is generated, and the data is transmitted to the disk device 4. However, the special command can be transmitted to the disk device 4 as it is.
[0117]
Similarly, when data is read from the disk device 4, data is transmitted between the disk interface unit 60 and the cache memory unit 40 using a special command.
[0118]
Next, the configuration of the cache memory 50 in this embodiment will be described.
[0119]
FIG. 12 is a diagram illustrating an example of the configuration of the cache memory 50 according to the second embodiment, and FIG. 13 is a diagram illustrating another example of the configuration of the cache memory 50 according to the second embodiment. In this embodiment, the line size of the cache memory 50 is 256 bytes.
[0120]
First, in the configuration shown in FIG. 12, when writing the data pattern shown in FIG. 5 to the cache memory 50, first, 512-byte data is written in the data pattern sent from the host computer 1, followed by 3328-byte data ALL'0 'data is recognized as 13 256-byte ALL'0' data, and 13 special commands are written.
[0121]
Similarly, the latter 256 bytes of data are written with the data pattern sent from the host computer 1 as it is.
[0122]
As shown in FIG. 12, an identification bit 51 is provided corresponding to a line of the cache memory 50, and it is possible to identify whether or not a special command exists in the line by this bit.
[0123]
For example, if the identification bit is “1”, it indicates that a special command exists in the line. If the identification bit is “0”, there is no special command in the line. Is shown. The identification bit 51 does not need to exist in the cache memory 50, and may be stored in another management area or the like.
[0124]
In addition, it has pattern information 52 as information of the special command, and can identify ALL'0 'pattern or ALL'1' patterning.
[0125]
For example, if the pattern information 52 is '00', it indicates an ALL'0 'pattern, and if the pattern information 52 is' 11 ', it indicates an ALL'1' pattern. Subsequently, it has order information 53, and indicates the order of the data length of the line as a special command. Subsequently, data length information 54 is stored. This indicates the data length of the special command.
[0126]
In addition, as shown in FIG. 13, the usage of the cache memory 50 and the processing may be reduced by indicating ALL “0” data of 3328 bytes by one special command. However, in this case, in order to reduce the used capacity of the cache memory 50, a process of re-addressing the cache memory 50 is required.
[0127]
Therefore, according to the disk array control device of the present embodiment, since data is converted into a special command instead of compressing the data, there is no need for a circuit or a program for compressing and expanding all the data. Even when the read data amount is large, it is possible to reduce the load on the internal interface.
[0128]
【The invention's effect】
As described above, according to the present invention, the data pattern identification logic unit identifies the pattern of the write data from the host computer and the pattern of the read data from the cache memory unit and the disk device. A command is formed based on the data pattern identified by the pattern identification logic means, and the command analysis means analyzes the command to generate the original data pattern, thereby reducing the load on the internal interface and improving the access performance. It is possible to improve. Further, it is possible to further improve the performance by writing a command in the cache memory unit.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a configuration of a disk array control device according to a first embodiment of the present invention.
FIG. 2 is a flowchart showing an operation of processing a request from a host computer according to the first embodiment of the present invention.
FIG. 3 is a flowchart illustrating an operation of a reading process from a cache memory according to the first embodiment of the present invention;
FIG. 4 is a flowchart showing an operation of a write-back process from the cache memory to the disk device according to the first embodiment of the present invention.
FIG. 5 is a diagram showing an example of write data according to the first embodiment of the present invention.
FIG. 6 is a diagram showing a timing chart of data processing according to the first embodiment of the present invention.
FIG. 7 is a block diagram illustrating a configuration of a data pattern identification logic unit according to the first embodiment of the present invention.
FIG. 8 is a configuration diagram showing a configuration of a disk array control device according to a second embodiment of the present invention.
FIG. 9 is a flowchart showing an operation of processing a request from a host computer according to the second embodiment of the present invention.
FIG. 10 is a flowchart showing an operation of a reading process from a cache memory according to the second embodiment of the present invention;
FIG. 11 is a flowchart showing an operation of a write-back process from the cache memory to the disk device according to the second embodiment of the present invention.
FIG. 12 is a diagram showing an example of a configuration of a cache memory 50 according to a second embodiment of the present invention.
FIG. 13 is a diagram showing another example of the configuration of the cache memory 50 according to the second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Host computer, 2 ... Disk array control device, 3 ... External network, 4 ... Disk device, 10 ... Channel interface part, 20 ... Shared memory part, 30 ... Data pattern identification logic part (data pattern identification logic means), 31 .. Command generating unit (command generating unit), 32 command analyzing unit (command analyzing unit), 33 processor, 34 host data transmitting / receiving unit, 40 cache memory unit, 50 cache memory, 60 disk interface unit, 70 .. Interconnection network (first interconnection network, second interconnection network), 80 interconnection network, 51 identification bit, 52 pattern information, 53 sequence information, 54 data length information, 90 service Processor connection network, 100: service processor, 101: ALL'0 'data pattern identification logic , 102... ALL '1' data pattern identification logic section, 103... Data length identification logic section, 104... 8 bytes '0' determination logic section, 105... 16 bytes '0' determination logic section, 106... Decision logic, 107 ... 8 bytes "1" decision logic, 108 ... 16 bytes "1" decision logic, 109 ... 4 kilobytes "1" decision logic, 110 ... 256 bytes "0" decision logic, 111 ... 256 byte '1' decision logic.

Claims (5)

A channel interface unit connected to a host computer, a disk interface unit connected to a disk device, a cache memory unit for temporarily storing data read or written to the disk device, and the channel interface unit. A disk array control device comprising: a first interconnection network connecting the cache memory unit; and a second interconnection network connecting the disk interface unit and the cache memory unit.
Data pattern identification logic means for identifying a pattern of write data from the host computer, and a pattern of read data from the cache memory unit and the disk device;
Command generation means for commanding based on the data pattern identified by the data pattern identification logic means,
A disk array control device comprising: a command analysis unit configured to analyze the command and generate an original data pattern. The disk array control device according to claim 1,
Said data pattern identification logic means for identifying patterns of write data and read data using said first interconnection network;
The command generation means converts a part or all of write data and read data using the first interconnection network into a command based on a data pattern identified by the data pattern identification logic means. Disk array control device. The disk array control device according to claim 1,
Said data pattern identification logic means for identifying patterns of write data and read data using said second interconnection network;
The command generation means converts a part or all of write data and read data using the second interconnection network into a command based on a data pattern identified by the data pattern identification logic means. Disk array control device. The disk array control device according to claim 1,
The data pattern identification logic unit identifies a pattern of write data to the cache memory unit,
The disk array control device according to claim 1, wherein said command generation means converts a part or all of the data written in said cache memory unit into a command based on the data pattern identified by said data pattern identification logic means. The disk array control device according to claim 1,
A disk array control device comprising means for selecting whether or not to use a data pattern by said data pattern identification logic means, to make a command by said command generation means, and to use said command analysis by a command analysis means.

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