JP2004311512A - Multilevel information storage element, its using method, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilevel information storage element which can be processed easily and on which writing and reading-out can be performed highly reliably without causing any malfunction by suppressing the number of processing steps. <P>SOLUTION: This multilevel information storage element which stores multilevel information has a laminated dielectric structure constituted by laminating a first ferrorelectric layer 2 having a first coercive voltage and a second ferroelectric layer 3 having a second coercive voltage which is different from the first coercive voltage upon another, between two voltage adding sections 1 and 4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multi-valued information storage element, a method of using the same, and a method of manufacturing the same, and more specifically, to a multi-valued information storage element having high reliability and easy to be miniaturized, a method of using the same, and a method of manufacturing the same. .
[0002]
[Prior art]
In a conventional multilevel information storage element, two capacitors including a ferroelectric layer are arranged in parallel in a memory cell (for example, see Patent Document 1). In this multi-valued information storage element, the applied voltage for controlling the polarization state of each ferroelectric portion of the capacitors arranged in parallel is made common, and the two values of the positive and negative polarization directions in the ferroelectric portions of each capacitor are provided. Is stored. Then, by combining the data of the ferroelectric portions of the parallel capacitors, the multi-value information, that is, the ternary information in the above disclosure, is stored as the whole parallel capacitor.
[0003]
In another multivalued information storage element, a plurality of gate regions having a laminated structure of an insulating layer / a lower electrode layer / a ferroelectric layer / an upper electrode layer are formed on a substrate. The thickness of the ferroelectric layer is changed for each gate region by making the thickness of the lower electrode layer of each gate region different and forming a step structure (see Patent Document 2). Due to the step structure of the lower electrode layer, the thickness of the ferroelectric layer differs for each gate region, and a circuit configuration in which ferroelectric capacitors having different capacities are coupled in parallel can be obtained. This multi-valued information storage element exhibits a combined hysteresis characteristic having a shape having a number of polarization stable points corresponding to the number of gate regions. This makes it possible to multi-value the amount of information without increasing the cell area.
[0004]
[Patent Document 1]
JP 2001-24074 A
[0005]
[Patent Document 2]
JP 2001-94065 A
[0006]
[Problems to be solved by the invention]
The above-described conventional multilevel information storage element has a structure in which a parallel-connected capacitor in which ferroelectric layers are arranged in parallel is provided in a memory cell. When an element having such a structure is formed, a transfer and processing process for forming a step structure on the lower electrode is required, and there has been a problem that the number of steps in the entire process increases. In addition, there is a problem that it is difficult to process platinum as a material of a lower electrode used in a ferroelectric capacitor. Further, in the structure of the conventional multi-valued information storage element, there is a problem that the amount of remanent polarization decreases as the area of the capacitor decreases, and the possibility that the element malfunctions due to slight voltage fluctuation increases.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-valued information storage element that is easy to process, suppresses the number of process steps, and is less likely to malfunction in operation control, a method of using the same, and a method of manufacturing the same.
[0008]
[Means for Solving the Problems]
A multi-valued information storage element of the present invention is a multi-valued information storage element that stores multi-valued information, wherein a first ferroelectric layer having a first coercive voltage is provided between two voltage applying units; A stacked ferroelectric structure in which a second ferroelectric layer having a second coercive voltage different from the first coercive voltage is stacked.
[0009]
With this configuration, by applying a pulse voltage (signal) of an appropriate shape to the laminated dielectric structure, a hysteresis characteristic having four stable points (stable polarization state) of remanent polarization is realized, and the multi-valued memory (4 Value) can be realized. In the above-mentioned multi-valued information storage element, complicated process steps such as step processing of a lower electrode and parallel formation of ferroelectric layers are not required, and the configuration is realized by stacking ferroelectric films having different coercive voltages. be able to.
[0010]
Further, it is not necessary to divide the region including the dielectric, and the area of the dielectric region is not reduced, so that the amount of residual polarization does not decrease. For this reason, the fluctuation of the polarization amount at the stable point is small, and the possibility that the element malfunctions even when the device is miniaturized is reduced.
[0011]
The above-mentioned two voltage applying units are such that one is a unit for applying a reference voltage, for example, a ground voltage, and the other is a unit for applying a predetermined driving voltage. The electrode need not always be a conductive electrode, and may be, for example, a semiconductor.
[0012]
In the above-described method of using the multi-valued information storage element, (a1) the voltage α having such a magnitude that both the polarization in the first and second ferroelectric layers is saturated in one direction is applied to the two voltage applying sections. (A2) After the application of the voltage α, a voltage β (> 0) having a magnitude such that the polarization of only one of the first and second ferroelectric layers is saturated and the other is not saturated in the direction opposite to the first direction. (A3) applying a voltage α in a direction opposite to the one direction so as to saturate both polarizations in the first and second ferroelectric layers; and (a4) applying a voltage in a direction opposite to the one direction. After the application of α, a voltage β is applied in a direction opposite to the one direction in which the polarization of only one of the first and second ferroelectric layers is saturated and the other is not saturated. (a1), (a1) a2), (a3) and (a4) any one of the voltage patterns is added, and then a zero potential When, (a1), (a2), (a3) and the four residual polarization remaining in correspondence with four kinds of voltage patterns addition of (a4), in matching 4 values.
[0013]
According to the above usage method, writing and reading of quaternary information can be performed with high reliability, despite the fact that a multi-level information storage element manufactured by a manufacturing method in which the number of manufacturing steps is suppressed without requiring complicated processing.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0015]
(Embodiment 1)
FIG. 1 is a cross-sectional view showing a capacitor part in the multi-valued information storage element according to the first embodiment of the present invention. The capacitor 5 has a configuration in which a ferroelectric layer 2, an intermediate electrode 15, and a ferroelectric layer 3 are sequentially stacked on the electrode 1, and the electrode 4 is disposed on the ferroelectric layer 3. . That is, the capacitor 5 shown in FIG. 1 is equivalent to a circuit in which two capacitors having different capacities are connected in series as shown in FIG. Ferroelectric layers 2 and 3 are electrically connected in series.
[0016]
In FIG. 4, Va represents the potential at the intermediate point between the ferroelectric layers 2 and 3, and Vb represents the potential of the electrode 4. Here, when a voltage Vb (= V2) is applied between the electrodes 1 and 4, the true charges appearing on the electrode surfaces facing the ferroelectric layers 2 and 3 have the same absolute value. The sign of the true charge on the upper surface is opposite to that of the true charge on the lower surface so that the neutral condition at the intermediate electrode is maintained.
[0017]
Next, the materials of the ferroelectric layer and the electrode will be described.
As the ferroelectric layers 2 and 3, a material thin film having a hysteresis characteristic in the relationship between the applied voltage and the amount of charge induced by the voltage as shown in FIGS. 2 and 3 is applied. Further, it is necessary to use materials having different coercive voltages for the ferroelectric layer 2 and the ferroelectric layer 3. As such a ferroelectric layer, Pb (Zr) from which ferroelectricity can be obtained relatively easily. _x Ti _1-x ) O ₃ (0 ≦ x ≦ 1), Pb _x La _1-x Zr _y Ti _1-y O ₃ (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), BaTiO ₃ , PbTiO ₃ Barium titanate-type material such as LiNbO ₃ , KTaO ₃ , NaNb ₅ O _Fifteen , SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ , (Ba, Sr) Nb ₂ O ₆ , SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ and so on. Platinum (Pt), iridium (Ir), and iridium oxide (IrO 2) were used as materials for the upper and lower electrodes 1 and 4 and the intermediate electrode 15. ₂ ), Ruthenium (Ru), ruthenium oxide (RuO) ₂ ) Is appropriate.
[0018]
Next, a method of forming multi-value information by combining the above-described hysteresis characteristics will be described.
[0019]
FIG. 5 is a diagram for obtaining the amount of charge generated by applying a voltage to the capacitor 5 shown in FIG. 1 and a divided voltage. In FIG. 5, the vertical axis (Y axis) is the true electric charge at the electrode, that is, the electric flux density, and the horizontal axis (X axis) corresponds to the potential Va at the midpoint between the ferroelectric layers 2 and 3. In FIG. 5, the hysteresis characteristic 6 of the ferroelectric layer 2 and the hysteresis characteristic 7 of the ferroelectric layer 3 are drawn based on the potential Va of the intermediate electrode. Here, the voltage applied to both ends of the ferroelectric layer 3 corresponds to Vb−Va, and when Va is used as the base point, the hysteresis characteristic 7 of the ferroelectric layer 3 is shown as being inverted left and right.
[0020]
In FIG. 5, when the potential of the electrode 1 in contact with the ferroelectric layer 2 is set to 0 (zero), an intersection 8 between the X axis and the center line of the hysteresis characteristic 7 indicates a potential difference between the electrodes 1 and 4. become. Therefore, when the applied voltage Vb to the entire capacitor is changed, the hysteresis characteristic 7 of the ferroelectric layer 2 moves horizontally in the X-axis direction. The X coordinate of the intersection 9 between the two hysteresis characteristics 6 and 7 represents the potential Va at the boundary between the ferroelectric layers 2 and 3 (that is, the voltage acting on the ferroelectric layer 2), and the Y coordinate of the intersection. Means the true charge amount appearing on the electrodes 1 and 4 at that time.
[0021]
By applying a pulse voltage of an appropriate shape, which will be described later, to both ends of the capacitor shown in FIG. 1, a combined hysteresis characteristic as shown in FIG. 6 can be realized. 6, the horizontal axis corresponds to the voltage applied to the capacitor 5 in FIG. 1 (the potential of the electrode 4), and the vertical axis corresponds to the amount of charge appearing on the electrodes 1 and 4. The hysteresis characteristic shown in FIG. 6 has four paths, and has four polarization stable points P11, P01, P10, and P00 when the applied voltage Vb is 0 (zero) V. As described above, in order to have four polarization stable points, it is necessary that two ferroelectric layers having hysteresis in a voltage-charge relationship have different coercive voltages.
[0022]
Next, a method of writing quaternary information to the above-described capacitor will be described.
First, when writing in the P11 state, a relatively large positive voltage α (α> 0) as shown in FIG. 7C is applied between the electrodes 1 and 4. In this case, as shown in FIG. 7A, the hysteresis 7 of the ferroelectric layer 3 is located in the X-axis direction by the applied voltage from the origin. In this state, as can be seen from FIG. 7A, both the hysteresis 6 and the hysteresis 7 are saturated. Here, when the voltage applied between the electrodes 1 and 4 is set to 0 V (zero volt) as shown in FIG. 7D, the hysteresis 7 moves to the origin position as shown in FIG. 7B. Thus, when the applied voltage is 0 (zero) V, an amount of charge Q (= P11) corresponding to the intersection 11 is accumulated between the electrodes 1 and 4. That is, writing of P11 is performed. As described above, in FIGS. 7A and 7B, the abscissa indicates the midpoint potential Va at the boundary between the ferroelectric layers 2 and 3.
[0023]
8A and 8B, the charge amount Q generated between the electrodes 1 and 4 when the above-described pulse voltage application operation is performed is plotted again with the applied voltage Vb as the horizontal axis. become that way. That is, it can be seen that one path and one polarization stable point are formed out of the four paths and four polarization stable points shown in FIG.
[0024]
Next, writing in the P01 state will be described. As shown in FIG. 9C, after applying a relatively large positive voltage α (α> 0), a negative voltage −β (β> 0) is applied. Here, β is a value in a range where the midpoint potential Va which is a voltage applied to the ferroelectric layer 2 does not exceed a coercive voltage in the hysteresis 6 of the ferroelectric layer 2. However, the difference between β and the intermediate point potential Va, that is, the voltage applied to the ferroelectric layer 3 is set to a value exceeding the coercive voltage in the hysteresis 7 of the ferroelectric layer 3. That is, a voltage that does not saturate the hysteresis of the ferroelectric layer 2 but saturates the hysteresis 7 of the ferroelectric layer 3 is applied.
[0025]
By applying the above-mentioned voltage −β, as shown in FIG. 9A, the hysteresis 7 is shifted by −β in the negative direction of X. As described above, as shown in FIG. 9A, in this state, the hysteresis 6 does not reach saturation, and only the hysteresis 7 is saturated. From this state, when the voltage applied between the electrodes 1 and 4 is set to 0 (zero) V as shown in FIG. 9D, the hysteresis 7 moves to the origin position, and the amount of charge corresponding to the intersection 12 is increased. Q (= P01) is accumulated between the electrodes 1 and 4 (FIG. 9B). That is, writing of P01 is performed. In this case, a voltage large enough to saturate the hysteresis 6 is not applied to the ferroelectric layer 2. Therefore, as shown in FIG. 9B, in the hysteresis 6, the same path follows when the voltage -β is applied and when the voltage -β is changed to zero volt.
[0026]
When the pulse voltage application operation shown in FIGS. 9C and 9D is performed, the charge amount Q accumulated between the electrodes 1 and 4 is plotted again with the applied voltage Vb as the horizontal axis. The results are as shown in FIGS. That is, it can be seen that one of the four paths and the four stable polarization points shown in FIG. 6 and the path leading therethrough are obtained.
[0027]
Next, a procedure for writing in the P00 state will be described. First, as shown in FIG. 11C, a relatively large negative voltage -α (α> 0) is applied between the electrodes 1 and 4. As a result, the hysteresis 7 moves in the X-axis direction from the origin by the amount of applied voltage -α as shown in FIG. Next, as shown in FIG. 11D, when the voltage between the electrodes 1 and 4 is set to 0 (zero) V, the hysteresis 7 moves to the origin position as shown in FIG. At 13, writing of P00 is performed.
[0028]
When the charge amount Q accumulated between the electrodes 1 and 4 when the above-described pulse voltage applying operation is performed is plotted again with the applied voltage Vb as the horizontal axis, FIG. 12A and FIG. Become like That is, it can be seen that one of the four paths and the four polarization stable points shown in FIG. 6 and the path leading to the polarization stable point P00 are obtained.
[0029]
Next, writing in the P10 state will be described. First, as shown in FIG. 13C, after applying a relatively large negative voltage −α (α> 0) between the electrodes 1 and 4, a positive voltage + β (β> 0) is applied. Here, β is a value within a range in which the potential Va at the intermediate point, which is the voltage applied to the ferroelectric layer 2, does not exceed the coercive voltage of the hysteresis 6. Further, the difference between the voltage β applied to the ferroelectric layer 3 and the voltage at the intermediate point is set to a value exceeding the coercive voltage of the hysteresis 7.
[0030]
By applying the voltage + β in the above range, the hysteresis 7 is shifted by + β in the positive X direction as shown in FIG. In this state, since the voltage range is set as described above, as shown in FIG. 13A, the hysteresis 6 does not reach saturation and only the hysteresis 7 is saturated. From this state, as shown in FIG. 13D, when the voltage applied between the electrodes 1 and 4 is set to 0 (zero) V, the hysteresis 7 moves to the origin position, and P10 is written at the intersection 14. (FIG. 13 (b)).
[0031]
In the above case, a voltage large enough to saturate the hysteresis 6 is not applied to the ferroelectric layer 2. For this reason, as shown in FIG. 13B, in the hysteresis 6, when the voltage is changed from the voltage + β to 0 (zero) V, the same path as when the voltage + β is applied follows.
[0032]
When the amount of charge Q accumulated between the electrodes 1 and 4 when the pulse voltage application operation is performed is plotted again with the applied voltage Vb as the horizontal axis, FIG. 14A and FIG. Become like That is, it can be seen that one of the four paths and the four polarization stable points shown in FIG. 6 and the polarization stable point P10 and the path leading to it are obtained.
[0033]
As can be seen from the above four-value information writing and reading methods, the two ferroelectric layers have a hysteresis curve in which a voltage range in which one ferroelectric layer is saturated and the other ferroelectric layer is not saturated. Needs to be present. For this reason, the coercive voltages of the two ferroelectric layers are different.
[0034]
According to the above-described method, four states P11, P01, P10, and P00 can be written by applying two voltage pulses having different magnitudes to the ferroelectric layers 2 and 3 singly or in combination. Become. That is, four-level information can be stored in one memory cell.
[0035]
In the above configuration, the voltage pattern writing unit includes the electrodes 1 and 4 and a control circuit unit (not shown) that applies a voltage pattern to the electrodes. In addition, a remnant polarization reading unit (not shown) can use a mechanism that can read a current or a resistance that is sensitively fluctuated by electric charges induced in the upper lower electrode.
[0036]
By using a structure in which ferroelectric layers are stacked as shown in this embodiment, the formation process of a stacked ferroelectric layer structure can be simplified and the number of steps can be reduced as compared with a conventional multilevel memory. Can be. In addition, since it is not necessary to reduce the area of the laminated ferroelectric structure with the increase in the number of values, the possibility of malfunction of the element can be reduced. Therefore, it is also suitable for miniaturization.
[0037]
(Embodiment 2)
FIG. 15 is a diagram showing an MFSFET-type memory cell to which the multilevel information storage element according to the second embodiment of the present invention is applied. FIG. 16 is an equivalent circuit diagram in which the memory cells of FIG. 15 are arranged on word lines and bit lines. Referring to FIG. 15, on a channel layer 53 between a pair of source / drain regions 52 formed on the surface of a silicon substrate 51, a gate electrode 56 is positioned with ferroelectric layers 54 and 55 interposed therebetween. I do. In FIG. 15, the silicon substrate is of p conductivity type, and the source and drain regions are of n conductivity type.
[0038]
In the above configuration, a pulse voltage pattern corresponding to the various pulse voltages of the first embodiment is applied to the gate electrode 56. By this voltage application, four types of charge amounts P00, P01, P10, and P11 are accumulated at the interface between the ferroelectric layer 54 and the channel layer 53, and quaternary information is stored. The threshold voltage of the transistor changes depending on the polarity and magnitude of the accumulated charge Q.
[0039]
Next, a writing method and a reading method will be specifically described. As described above, when the silicon substrate is of p conductivity type and the source and drain regions are of n conductivity type in FIG. 15, a voltage pattern corresponding to the pulse voltage shown in FIG. As shown in FIG. 17, positive charges 57 are accumulated at the interface between the ferroelectric layer 54 and the channel layer 53. As shown in FIG. 18, the charge amount Q of the positive charges 57 corresponds to P11. In the case of FIG. 15, accumulating charges at the interface means inducing negative charges on the surface of the channel layer 53 facing the ferroelectric layer 54. In addition, a positive charge is induced on the surface of the ferroelectric layer facing the channel layer. In this state, the threshold voltage of the transistor decreases, and the channel layer 53 is inverted and a drain current flows even without applying a voltage to the gate electrode.
[0040]
In addition, when a voltage pattern corresponding to FIG. 9D is applied to the gate voltage, the charges 58 accumulated at the interface are smaller than the charges 57 in FIG. 17 as shown in FIG. This corresponds to the polarization stable point P01 as shown in FIG.
[0041]
When a voltage pattern corresponding to FIG. 11D is applied to the gate voltage, the charge 59 accumulated at the interface becomes a large negative charge as shown in FIG. 21 and a polarization stable point as shown in FIG. Corresponds to P00.
[0042]
Further, when a voltage pattern corresponding to FIG. 13D is applied to the gate voltage, the electric charge 60 accumulated at the interface becomes a large negative electric charge as shown in FIG. 23, and becomes polarized as shown in FIG. Corresponds to stable point P10.
[0043]
The charge amount has a magnitude relationship of P11>P01>P10> P00. As described above, on the surface of the channel layer 53 facing the ferroelectric layer 54, charges having a polarity opposite to that of the accumulated charges are induced. Since the channel layer is of the p-conductivity type as described above, when a voltage is applied to the gate electrode to invert the channel layer, it is easier to invert when a negative charge is induced. Therefore, of the four polarization stable points, the channel inversion is most likely to occur at the polarization stable point P11, and then P01, P10, and P00 in that order. The fact that the channel is easily inverted means that the threshold voltage is low. Therefore, the threshold voltages increase in the order of P11 <P01 <P10 <P00, with P00 being the largest.
[0044]
Therefore, the (drain current Id / gate voltage Vg) characteristic changes as shown in FIG. 25 depending on the polarity and magnitude of the charge appearing at the interface between the ferroelectric layer and the channel region. As shown in FIG. 25, by applying a certain voltage value 65 to the gate electrode and detecting the difference between the drain current values flowing at that time, the four-value information can be read out separately.
[0045]
In the present embodiment, referring to FIG. 16, the voltage pattern writing unit includes a gate electrode 56, a word line, a word line control peripheral circuit unit (not shown) that sends a voltage pattern to the word line, and the like. . Further, the remanent polarization read section includes a source / channel / drain formed on the main surface of the silicon substrate, a bit line connected to the drain, a bit line control peripheral circuit section, and the like.
[0046]
As shown in this embodiment, by using a structure in which a ferroelectric layer is stacked on a silicon substrate, the formation process of the stacked ferroelectric layer structure is simplified and the number of steps is reduced as compared with a conventional multilevel memory. Can be achieved. In addition, since it is not necessary to divide the region of the laminated ferroelectric structure in accordance with the increase in the number of values, the possibility of a malfunction of the element can be reduced. Therefore, it is suitable for miniaturization.
[0047]
(Embodiment 3)
In order to realize the first and second embodiments of the present invention, different materials may be applied to the ferroelectric layers 2 and 3 having different coercive voltages in hysteresis. It is also possible to use the same type of material. In a third embodiment of the present invention, a method of forming ferroelectric layers having different coercive voltages using the same type of material will be described.
[0048]
For example, as a ferroelectric material, Pb (Zr _x Ti _1-x ) O ₃ When a thin film is used, the crystal orientation of the film can be controlled and the coercive voltage can be changed by adjusting the rate of temperature rise in annealing under the crystallization annealing conditions after film formation. In FIG. 26, Pb (Zr) formed under the same film forming conditions for forming the ferroelectric layer and changing only the temperature increase rate in the annealing process after film formation. _0.5 , Ti _0.5 ) O ₃ 3 shows an X-ray diffraction spectrum of the film. As shown in FIG. 26, by increasing the rate of temperature rise during annealing from 0.05 ° C./sec to 25 ° C./sec, Pb (Zr _0.5 , Ti _0.5 ) O ₃ It can be seen that the crystal orientation of the film has changed from the (100) orientation to the (111) orientation. As described above, by adjusting only the annealing process conditions when forming the ferroelectric layers 2 and 3, two ferroelectrics having different coercive voltages required for realizing the first and second embodiments are provided. A layered structure of layers can be easily manufactured. As a result, by stacking the same type of ferroelectric material, it is possible to increase the number of values, so that the number of types of ferroelectric material can be reduced. Further, since it is not necessary to change the film forming conditions of the ferroelectric layer between the first layer and the second layer, the number of steps can be reduced.
[0049]
(Embodiment 4)
In the fourth embodiment of the present invention, as shown in FIG. 27, by applying a film having a different crystal orientation from the lower electrode 1 to the intermediate electrode, the crystal orientation of the ferroelectric layers 2 and 3 can be reduced. Can be changed automatically. Pb (Zr) formed under the same process conditions on a Pt substrate strongly oriented in the (111) direction and a non-oriented Pt substrate, respectively. _0.5 , Ti _0.5 ) O ₃ FIG. 28 shows the X-ray diffraction spectrum of the film. From FIG. 28, Pb (Zr) on Pt oriented to (111) _0.5 , Ti _0.5 ) O ₃ The film is strongly oriented to (111) and Pb (Zr on unoriented Pt _0.5 , Ti _0.5 ) O ₃ It can be seen that the film is non-oriented. That is, Pb (Zr _0.5 , Ti _0.5 ) O ₃ The crystal orientation of the film is the same as that of the underlying substrate.
[0050]
As described above, in realizing the first and second embodiments, even if a thin film in which the same kind of material is formed on the ferroelectric layers 2 and 3 under the same process conditions is applied, the crystal orientations are different. It is possible to make the coercive voltage different. According to this manufacturing method, the same type of ferroelectric material is laminated under the same conditions, so that the number of types of ferroelectric material can be reduced and cost can be reduced.
[0051]
(Remarks to the embodiment)
1. In the above-described embodiment, it has been described that the two ferroelectric layers have different coercive voltages. However, a ferroelectric layer with a very strange hysteresis curve appears, and even with the same coercive voltage, there is a voltage range where one ferroelectric layer is saturated and the other ferroelectric layer is not saturated If two ferroelectric layers having such a hysteresis curve are obtained, the two ferroelectric layers included in the present invention are targeted.
2. In the above-described embodiment, an example has been described in which the two ferroelectric layers have the same composition and have different coercive voltages by different orientations. However, needless to say, by forming the two ferroelectric layers with different compositions, the coercive voltage may be different regardless of the orientation.
[0052]
Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is limited to these embodiments. Never. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.
[0053]
【The invention's effect】
By using the multi-valued information storage element of the present invention, it is possible to obtain a multi-valued information storage element that is easy to process, suppresses an increase in the number of process steps, and is less likely to malfunction in operation control.
[Brief description of the drawings]
FIG. 1 is a diagram showing a capacitor in a multilevel information storage element according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a hysteresis characteristic of one ferroelectric layer of the capacitor of FIG.
FIG. 3 is a diagram showing a hysteresis characteristic of the other ferroelectric layer of the capacitor of FIG.
FIG. 4 is an equivalent circuit diagram of the capacitor of FIG.
FIG. 5 is a diagram for obtaining a charge amount and a divided voltage generated by applying a voltage to a capacitor 5 shown in FIG. 1;
FIG. 6 is a diagram showing a combined hysteresis obtained by combining hysteresis of two ferroelectric layers of the capacitor shown in FIG. 1;
7A is a diagram showing a state where a voltage α is applied to a capacitor, with the horizontal axis representing a voltage between two ferroelectric layers, and FIG. (C) is a diagram showing a waveform of the voltage α, and (d) is a diagram showing a waveform after which the potential is set to zero potential.
8A is a diagram showing a state in which a voltage α is applied on the horizontal axis as a voltage applied to a capacitor, and FIG. 8B is a diagram showing a state in which the voltage α is thereafter set to zero potential.
9A is a diagram showing a state where a voltage α is applied to a capacitor and then a voltage −β is applied, with the horizontal axis representing a voltage between two ferroelectric layers, and FIG. It is a figure which shows the state which made zero electric potential, (c) is a figure which shows the waveform which applies voltage-(beta) after application of voltage (alpha), and (d) is a figure which shows the waveform which makes zero electric potential after that.
10A is a diagram showing a state where a voltage α is applied to a capacitor on the horizontal axis, and then a voltage α and then −β are applied, and FIG. 10B is a diagram showing a state where the voltage is then set to zero potential. .
11A is a diagram showing a state where a voltage -α is applied to a capacitor, with the horizontal axis representing a voltage between two ferroelectric layers, and FIG. It is a figure, (c) is a figure which shows the waveform which applies voltage-(alpha), and (d) is a figure which shows the waveform which makes zero electric potential after that.
12A is a diagram illustrating a state where a voltage −α is applied on the horizontal axis as a voltage applied to a capacitor, and FIG. 12B is a diagram illustrating a state where the potential is then set to zero potential.
13A is a diagram showing a state where a voltage −α is applied to a capacitor, and then a voltage β is applied, with the axis being a voltage between two ferroelectric layers, and FIG. It is a figure which shows the state made into electric potential, (c) is a figure which shows the waveform which applies voltage (beta) after voltage- (alpha) application, and (d) is a figure which shows the waveform which makes zero electric potential after that.
14A is a diagram showing a state in which a voltage -α and then β are applied on the horizontal axis as a voltage applied to a capacitor, and FIG. 14B is a diagram showing a state in which the potential is then set to zero potential; .
FIG. 15 is a diagram showing an MFSFET-type memory cell to which a multilevel information storage element according to a second embodiment of the present invention is applied.
FIG. 16 is an equivalent circuit diagram in which the memory cells of FIG. 15 are arranged on word lines and bit lines.
17 is a diagram showing electric charges accumulated between a channel region and a ferroelectric layer of the MFSFET type memory cell of FIG.
18 is a diagram showing polarization stable points corresponding to the polarization state in FIG.
19 is a diagram showing electric charges accumulated between the channel region and the ferroelectric layer of the MFSFET type memory cell of FIG.
20 is a diagram showing polarization stable points corresponding to the polarization state in FIG.
21 is a diagram showing electric charges stored between a channel region and a ferroelectric layer of the MFSFET type memory cell of FIG.
FIG. 22 is a diagram showing a polarization stable point corresponding to the polarization state in FIG. 21;
23 is a diagram showing electric charges accumulated between the channel region and the ferroelectric layer of the MFSFET type memory cell of FIG.
24 is a diagram showing polarization stable points corresponding to the polarization state in FIG.
FIG. 25 is a diagram showing a relationship between a gate voltage and a drain current corresponding to each polarization state.
FIG. 26 is a diagram showing an X-ray diffraction pattern showing an orientation characteristic of a ferroelectric layer used in Embodiment 3 of the present invention.
FIG. 27 is a diagram showing a configuration of a capacitor used in a fourth embodiment of the present invention.
FIG. 28 is an X-ray diffraction pattern showing the orientation characteristics of a ferroelectric layer used in Embodiment 4 of the present invention.
[Explanation of symbols]
1 lower electrode, 2,3 ferroelectric layer, 4 upper electrode, 6,7 hysteresis, 11, 12, 13, 14 stable polarization point, 15 intermediate electrode, 51 silicon substrate, 52 source / drain region, 53 channel region, 54, 55 ferroelectric layer, 56 gate electrode, 57, 58, 59, 60 charge, 61, 62, 63, 64 drain current-gate voltage relationship, 66, 68 ferroelectric layer, 67 intermediate electrode of different orientation .

Claims (10)

A multi-valued information storage element that stores multi-valued information,
A first ferroelectric layer having a first coercive voltage and a second ferroelectric layer having a second coercive voltage different from the first coercive voltage are laminated between the two voltage applying units. Multi-valued information storage element having a laminated ferroelectric structure. The multi-valued information storage device according to claim 1, further comprising an intermediate electrode sandwiched between the first ferroelectric layer and the second ferroelectric layer. The laminated ferroelectric structure is formed on a semiconductor substrate, one of the two voltage applying portions is a gate electrode, and the other is formed on a main surface of the semiconductor substrate, and is located between a source region and a drain region. 3. The multi-valued information storage device according to claim 1, which is a channel region. (A1) applying, to the two voltage applying units, a voltage α (> 0) having a magnitude that saturates both the polarization in the first and second ferroelectric layers in one direction; After applying the voltage α in the direction of the first direction, the polarization of only one of the first and second ferroelectric layers is saturated in the direction opposite to the one direction, and the voltage β (> 0 (A3) applying the voltage α in the reverse direction, and (a4) applying the voltage α in the reverse direction, and then applying the voltage β in the one direction. ), (A2), (a3) and (a4), and when the potential is set to zero potential, the voltage pattern of (a1), (a2), (a3) and (a4) Of the four types of remanent polarization that correspond to the addition of the four types of voltage patterns, respectively. And a pattern writing portion and the residual polarization reading unit, multi-level information storage device according to claim 1. The voltage pattern writing unit includes a word line connected to the gate electrode, and a word line control peripheral circuit unit that applies a voltage pattern to the word line, and the remnant polarization reading unit includes a bit connected to the drain region. 5. The multi-valued information storage element according to claim 4, further comprising a bit line, and a bit line control peripheral circuit for detecting a drain current flowing through the bit line. 6. The multi-valued information storage device according to claim 1, wherein said first and second ferroelectric layers have the same composition and different orientation characteristics. A first ferroelectric layer having a first coercive voltage and a second ferroelectric layer having a second coercive voltage different from the first coercive voltage are stacked between the two voltage applying units. A method of using a multi-valued information storage element having a laminated ferroelectric structure,
(A1) applying, to the two voltage applying units, a voltage α (> 0) having a magnitude that saturates both the polarization in the first and second ferroelectric layers in one direction; After applying the voltage α in the direction of the first direction, the polarization of only one of the first and second ferroelectric layers is saturated in the direction opposite to the one direction, and the voltage β (> 0 (A3) applying the voltage α in the reverse direction, and (a4) applying the voltage α in the reverse direction, and then applying the voltage β in the one direction. ), (A2), (a3) and (a4), and when the potential is set to zero potential, the voltage pattern of (a1), (a2), (a3) and (a4) The remaining four types of remanent polarization corresponding to each type of voltage pattern addition are That, using the multi-value information storage element. A channel formed between the source region and the drain region, wherein the stacked ferroelectric structure is disposed on a semiconductor substrate, one of the two voltage applying portions is a gate electrode, and the other is formed on a main surface of the semiconductor substrate; A drain current whose magnitude changes in response to the four types of remanent polarization by inducing charges corresponding to the four types of remanent polarization in the channel region and applying a constant gate voltage to the channel region; The method of using the multi-valued information storage element according to claim 7, wherein the multi-valued information storage element is read out as quaternary information. A first ferroelectric layer having a first coercive voltage and a second ferroelectric layer having a second coercive voltage different from the first coercive voltage are stacked between the two voltage applying units. A method for manufacturing a multi-valued information storage element having a laminated ferroelectric structure,
After forming the first ferroelectric layer, when annealing, heating at a first temperature increasing rate;
After forming the second ferroelectric layer with the same composition as the first ferroelectric layer, when annealing, heating at a second temperature increasing rate;
A method for manufacturing a multi-valued information storage element, wherein the first temperature raising rate and the second temperature raising rate are different. A first ferroelectric layer having a first coercive voltage and a second ferroelectric layer having a second coercive voltage different from the first coercive voltage between the two voltage applying units; A method for manufacturing a multi-valued information storage element having a laminated ferroelectric structure laminated with electrodes interposed therebetween,
Forming a first ferroelectric layer on one of the voltage applying portions;
Forming the intermediate electrode having an orientation characteristic different from one of the voltage applying portions;
Forming a second ferroelectric layer in contact with the intermediate electrode.

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